?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
sh: Fix the offset from P1SEG/P2SEG where we map RAM
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / e100.c
blob679965c2bb8600f42ba0c44fb99c68ea84472600
1 /*******************************************************************************
2
3 Intel PRO/100 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * e100.c: Intel(R) PRO/100 ethernet driver
31 *
32 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on
33 * original e100 driver, but better described as a munging of
34 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
35 *
36 * References:
37 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
38 * Open Source Software Developers Manual,
39 * http://sourceforge.net/projects/e1000
40 *
41 *
42 * Theory of Operation
43 *
44 * I. General
45 *
46 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
47 * controller family, which includes the 82557, 82558, 82559, 82550,
48 * 82551, and 82562 devices. 82558 and greater controllers
49 * integrate the Intel 82555 PHY. The controllers are used in
50 * server and client network interface cards, as well as in
51 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
52 * configurations. 8255x supports a 32-bit linear addressing
53 * mode and operates at 33Mhz PCI clock rate.
54 *
55 * II. Driver Operation
56 *
57 * Memory-mapped mode is used exclusively to access the device's
58 * shared-memory structure, the Control/Status Registers (CSR). All
59 * setup, configuration, and control of the device, including queuing
60 * of Tx, Rx, and configuration commands is through the CSR.
61 * cmd_lock serializes accesses to the CSR command register. cb_lock
62 * protects the shared Command Block List (CBL).
63 *
64 * 8255x is highly MII-compliant and all access to the PHY go
65 * through the Management Data Interface (MDI). Consequently, the
66 * driver leverages the mii.c library shared with other MII-compliant
67 * devices.
68 *
69 * Big- and Little-Endian byte order as well as 32- and 64-bit
70 * archs are supported. Weak-ordered memory and non-cache-coherent
71 * archs are supported.
72 *
73 * III. Transmit
74 *
75 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
76 * together in a fixed-size ring (CBL) thus forming the flexible mode
77 * memory structure. A TCB marked with the suspend-bit indicates
78 * the end of the ring. The last TCB processed suspends the
79 * controller, and the controller can be restarted by issue a CU
80 * resume command to continue from the suspend point, or a CU start
81 * command to start at a given position in the ring.
82 *
83 * Non-Tx commands (config, multicast setup, etc) are linked
84 * into the CBL ring along with Tx commands. The common structure
85 * used for both Tx and non-Tx commands is the Command Block (CB).
86 *
87 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
88 * is the next CB to check for completion; cb_to_send is the first
89 * CB to start on in case of a previous failure to resume. CB clean
90 * up happens in interrupt context in response to a CU interrupt.
91 * cbs_avail keeps track of number of free CB resources available.
92 *
93 * Hardware padding of short packets to minimum packet size is
94 * enabled. 82557 pads with 7Eh, while the later controllers pad
95 * with 00h.
96 *
97 * IV. Receive
98 *
99 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
100 * Descriptors (RFD) + data buffer, thus forming the simplified mode
101 * memory structure. Rx skbs are allocated to contain both the RFD
102 * and the data buffer, but the RFD is pulled off before the skb is
103 * indicated. The data buffer is aligned such that encapsulated
104 * protocol headers are u32-aligned. Since the RFD is part of the
105 * mapped shared memory, and completion status is contained within
106 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
107 * view from software and hardware.
108 *
109 * In order to keep updates to the RFD link field from colliding with
110 * hardware writes to mark packets complete, we use the feature that
111 * hardware will not write to a size 0 descriptor and mark the previous
112 * packet as end-of-list (EL). After updating the link, we remove EL
113 * and only then restore the size such that hardware may use the
114 * previous-to-end RFD.
115 *
116 * Under typical operation, the receive unit (RU) is start once,
117 * and the controller happily fills RFDs as frames arrive. If
118 * replacement RFDs cannot be allocated, or the RU goes non-active,
119 * the RU must be restarted. Frame arrival generates an interrupt,
120 * and Rx indication and re-allocation happen in the same context,
121 * therefore no locking is required. A software-generated interrupt
122 * is generated from the watchdog to recover from a failed allocation
123 * scenario where all Rx resources have been indicated and none re-
124 * placed.
125 *
126 * V. Miscellaneous
127 *
128 * VLAN offloading of tagging, stripping and filtering is not
129 * supported, but driver will accommodate the extra 4-byte VLAN tag
130 * for processing by upper layers. Tx/Rx Checksum offloading is not
131 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
132 * not supported (hardware limitation).
133 *
134 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
135 *
136 * Thanks to JC (jchapman@katalix.com) for helping with
137 * testing/troubleshooting the development driver.
138 *
139 * TODO:
140 * o several entry points race with dev->close
141 * o check for tx-no-resources/stop Q races with tx clean/wake Q
142 *
143 * FIXES:
144 * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com>
145 * - Stratus87247: protect MDI control register manipulations
146 * 2009/06/01 - Andreas Mohr <andi at lisas dot de>
147 * - add clean lowlevel I/O emulation for cards with MII-lacking PHYs
148 */
149
150 #include <linux/module.h>
151 #include <linux/moduleparam.h>
152 #include <linux/kernel.h>
153 #include <linux/types.h>
154 #include <linux/slab.h>
155 #include <linux/delay.h>
156 #include <linux/init.h>
157 #include <linux/pci.h>
158 #include <linux/dma-mapping.h>
159 #include <linux/netdevice.h>
160 #include <linux/etherdevice.h>
161 #include <linux/mii.h>
162 #include <linux/if_vlan.h>
163 #include <linux/skbuff.h>
164 #include <linux/ethtool.h>
165 #include <linux/string.h>
166 #include <linux/firmware.h>
167 #include <asm/unaligned.h>
168
169
170 #define DRV_NAME "e100"
171 #define DRV_EXT "-NAPI"
172 #define DRV_VERSION "3.5.24-k2"DRV_EXT
173 #define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
174 #define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation"
175 #define PFX DRV_NAME ": "
176
177 #define E100_WATCHDOG_PERIOD (2 * HZ)
178 #define E100_NAPI_WEIGHT 16
179
180 #define FIRMWARE_D101M "e100/d101m_ucode.bin"
181 #define FIRMWARE_D101S "e100/d101s_ucode.bin"
182 #define FIRMWARE_D102E "e100/d102e_ucode.bin"
183
184 MODULE_DESCRIPTION(DRV_DESCRIPTION);
185 MODULE_AUTHOR(DRV_COPYRIGHT);
186 MODULE_LICENSE("GPL");
187 MODULE_VERSION(DRV_VERSION);
188 MODULE_FIRMWARE(FIRMWARE_D101M);
189 MODULE_FIRMWARE(FIRMWARE_D101S);
190 MODULE_FIRMWARE(FIRMWARE_D102E);
191
192 static int debug = 3;
193 static int eeprom_bad_csum_allow = 0;
194 static int use_io = 0;
195 module_param(debug, int, 0);
196 module_param(eeprom_bad_csum_allow, int, 0);
197 module_param(use_io, int, 0);
198 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
199 MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums");
200 MODULE_PARM_DESC(use_io, "Force use of i/o access mode");
201 #define DPRINTK(nlevel, klevel, fmt, args...) \
202 (void)((NETIF_MSG_##nlevel & nic->msg_enable) && \
203 printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \
204 __func__ , ## args))
205
206 #define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
207 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
208 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
209 static struct pci_device_id e100_id_table[] = {
210 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
211 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
212 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
213 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
214 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
215 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
216 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
217 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
218 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
219 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
220 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
221 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
222 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
223 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
224 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
225 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
226 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
227 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
228 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
229 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
230 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
231 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
232 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
233 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
234 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
235 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
236 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
237 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
238 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
239 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
240 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),
241 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),
242 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),
243 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),
244 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),
245 INTEL_8255X_ETHERNET_DEVICE(0x10fe, 7),
246 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
247 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
248 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
249 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
250 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
251 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),
252 { 0, }
253 };
254 MODULE_DEVICE_TABLE(pci, e100_id_table);
255
256 enum mac {
257 mac_82557_D100_A = 0,
258 mac_82557_D100_B = 1,
259 mac_82557_D100_C = 2,
260 mac_82558_D101_A4 = 4,
261 mac_82558_D101_B0 = 5,
262 mac_82559_D101M = 8,
263 mac_82559_D101S = 9,
264 mac_82550_D102 = 12,
265 mac_82550_D102_C = 13,
266 mac_82551_E = 14,
267 mac_82551_F = 15,
268 mac_82551_10 = 16,
269 mac_unknown = 0xFF,
270 };
271
272 enum phy {
273 phy_100a = 0x000003E0,
274 phy_100c = 0x035002A8,
275 phy_82555_tx = 0x015002A8,
276 phy_nsc_tx = 0x5C002000,
277 phy_82562_et = 0x033002A8,
278 phy_82562_em = 0x032002A8,
279 phy_82562_ek = 0x031002A8,
280 phy_82562_eh = 0x017002A8,
281 phy_82552_v = 0xd061004d,
282 phy_unknown = 0xFFFFFFFF,
283 };
284
285 /* CSR (Control/Status Registers) */
286 struct csr {
287 struct {
288 u8 status;
289 u8 stat_ack;
290 u8 cmd_lo;
291 u8 cmd_hi;
292 u32 gen_ptr;
293 } scb;
294 u32 port;
295 u16 flash_ctrl;
296 u8 eeprom_ctrl_lo;
297 u8 eeprom_ctrl_hi;
298 u32 mdi_ctrl;
299 u32 rx_dma_count;
300 };
301
302 enum scb_status {
303 rus_no_res = 0x08,
304 rus_ready = 0x10,
305 rus_mask = 0x3C,
306 };
307
308 enum ru_state {
309 RU_SUSPENDED = 0,
310 RU_RUNNING = 1,
311 RU_UNINITIALIZED = -1,
312 };
313
314 enum scb_stat_ack {
315 stat_ack_not_ours = 0x00,
316 stat_ack_sw_gen = 0x04,
317 stat_ack_rnr = 0x10,
318 stat_ack_cu_idle = 0x20,
319 stat_ack_frame_rx = 0x40,
320 stat_ack_cu_cmd_done = 0x80,
321 stat_ack_not_present = 0xFF,
322 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
323 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
324 };
325
326 enum scb_cmd_hi {
327 irq_mask_none = 0x00,
328 irq_mask_all = 0x01,
329 irq_sw_gen = 0x02,
330 };
331
332 enum scb_cmd_lo {
333 cuc_nop = 0x00,
334 ruc_start = 0x01,
335 ruc_load_base = 0x06,
336 cuc_start = 0x10,
337 cuc_resume = 0x20,
338 cuc_dump_addr = 0x40,
339 cuc_dump_stats = 0x50,
340 cuc_load_base = 0x60,
341 cuc_dump_reset = 0x70,
342 };
343
344 enum cuc_dump {
345 cuc_dump_complete = 0x0000A005,
346 cuc_dump_reset_complete = 0x0000A007,
347 };
348
349 enum port {
350 software_reset = 0x0000,
351 selftest = 0x0001,
352 selective_reset = 0x0002,
353 };
354
355 enum eeprom_ctrl_lo {
356 eesk = 0x01,
357 eecs = 0x02,
358 eedi = 0x04,
359 eedo = 0x08,
360 };
361
362 enum mdi_ctrl {
363 mdi_write = 0x04000000,
364 mdi_read = 0x08000000,
365 mdi_ready = 0x10000000,
366 };
367
368 enum eeprom_op {
369 op_write = 0x05,
370 op_read = 0x06,
371 op_ewds = 0x10,
372 op_ewen = 0x13,
373 };
374
375 enum eeprom_offsets {
376 eeprom_cnfg_mdix = 0x03,
377 eeprom_phy_iface = 0x06,
378 eeprom_id = 0x0A,
379 eeprom_config_asf = 0x0D,
380 eeprom_smbus_addr = 0x90,
381 };
382
383 enum eeprom_cnfg_mdix {
384 eeprom_mdix_enabled = 0x0080,
385 };
386
387 enum eeprom_phy_iface {
388 NoSuchPhy = 0,
389 I82553AB,
390 I82553C,
391 I82503,
392 DP83840,
393 S80C240,
394 S80C24,
395 I82555,
396 DP83840A = 10,
397 };
398
399 enum eeprom_id {
400 eeprom_id_wol = 0x0020,
401 };
402
403 enum eeprom_config_asf {
404 eeprom_asf = 0x8000,
405 eeprom_gcl = 0x4000,
406 };
407
408 enum cb_status {
409 cb_complete = 0x8000,
410 cb_ok = 0x2000,
411 };
412
413 enum cb_command {
414 cb_nop = 0x0000,
415 cb_iaaddr = 0x0001,
416 cb_config = 0x0002,
417 cb_multi = 0x0003,
418 cb_tx = 0x0004,
419 cb_ucode = 0x0005,
420 cb_dump = 0x0006,
421 cb_tx_sf = 0x0008,
422 cb_cid = 0x1f00,
423 cb_i = 0x2000,
424 cb_s = 0x4000,
425 cb_el = 0x8000,
426 };
427
428 struct rfd {
429 __le16 status;
430 __le16 command;
431 __le32 link;
432 __le32 rbd;
433 __le16 actual_size;
434 __le16 size;
435 };
436
437 struct rx {
438 struct rx *next, *prev;
439 struct sk_buff *skb;
440 dma_addr_t dma_addr;
441 };
442
443 #if defined(__BIG_ENDIAN_BITFIELD)
444 #define X(a,b) b,a
445 #else
446 #define X(a,b) a,b
447 #endif
448 struct config {
449 /*0*/ u8 X(byte_count:6, pad0:2);
450 /*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
451 /*2*/ u8 adaptive_ifs;
452 /*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
453 term_write_cache_line:1), pad3:4);
454 /*4*/ u8 X(rx_dma_max_count:7, pad4:1);
455 /*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
456 /*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
457 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
458 rx_discard_overruns:1), rx_save_bad_frames:1);
459 /*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
460 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
461 tx_dynamic_tbd:1);
462 /*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
463 /*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
464 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
465 /*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
466 loopback:2);
467 /*11*/ u8 X(linear_priority:3, pad11:5);
468 /*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
469 /*13*/ u8 ip_addr_lo;
470 /*14*/ u8 ip_addr_hi;
471 /*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
472 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
473 pad15_2:1), crs_or_cdt:1);
474 /*16*/ u8 fc_delay_lo;
475 /*17*/ u8 fc_delay_hi;
476 /*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
477 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
478 /*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
479 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
480 full_duplex_force:1), full_duplex_pin:1);
481 /*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
482 /*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
483 /*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
484 u8 pad_d102[9];
485 };
486
487 #define E100_MAX_MULTICAST_ADDRS 64
488 struct multi {
489 __le16 count;
490 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
491 };
492
493 /* Important: keep total struct u32-aligned */
494 #define UCODE_SIZE 134
495 struct cb {
496 __le16 status;
497 __le16 command;
498 __le32 link;
499 union {
500 u8 iaaddr[ETH_ALEN];
501 __le32 ucode[UCODE_SIZE];
502 struct config config;
503 struct multi multi;
504 struct {
505 u32 tbd_array;
506 u16 tcb_byte_count;
507 u8 threshold;
508 u8 tbd_count;
509 struct {
510 __le32 buf_addr;
511 __le16 size;
512 u16 eol;
513 } tbd;
514 } tcb;
515 __le32 dump_buffer_addr;
516 } u;
517 struct cb *next, *prev;
518 dma_addr_t dma_addr;
519 struct sk_buff *skb;
520 };
521
522 enum loopback {
523 lb_none = 0, lb_mac = 1, lb_phy = 3,
524 };
525
526 struct stats {
527 __le32 tx_good_frames, tx_max_collisions, tx_late_collisions,
528 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
529 tx_multiple_collisions, tx_total_collisions;
530 __le32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
531 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
532 rx_short_frame_errors;
533 __le32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
534 __le16 xmt_tco_frames, rcv_tco_frames;
535 __le32 complete;
536 };
537
538 struct mem {
539 struct {
540 u32 signature;
541 u32 result;
542 } selftest;
543 struct stats stats;
544 u8 dump_buf[596];
545 };
546
547 struct param_range {
548 u32 min;
549 u32 max;
550 u32 count;
551 };
552
553 struct params {
554 struct param_range rfds;
555 struct param_range cbs;
556 };
557
558 struct nic {
559 /* Begin: frequently used values: keep adjacent for cache effect */
560 u32 msg_enable ____cacheline_aligned;
561 struct net_device *netdev;
562 struct pci_dev *pdev;
563 u16 (*mdio_ctrl)(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data);
564
565 struct rx *rxs ____cacheline_aligned;
566 struct rx *rx_to_use;
567 struct rx *rx_to_clean;
568 struct rfd blank_rfd;
569 enum ru_state ru_running;
570
571 spinlock_t cb_lock ____cacheline_aligned;
572 spinlock_t cmd_lock;
573 struct csr __iomem *csr;
574 enum scb_cmd_lo cuc_cmd;
575 unsigned int cbs_avail;
576 struct napi_struct napi;
577 struct cb *cbs;
578 struct cb *cb_to_use;
579 struct cb *cb_to_send;
580 struct cb *cb_to_clean;
581 __le16 tx_command;
582 /* End: frequently used values: keep adjacent for cache effect */
583
584 enum {
585 ich = (1 << 0),
586 promiscuous = (1 << 1),
587 multicast_all = (1 << 2),
588 wol_magic = (1 << 3),
589 ich_10h_workaround = (1 << 4),
590 } flags ____cacheline_aligned;
591
592 enum mac mac;
593 enum phy phy;
594 struct params params;
595 struct timer_list watchdog;
596 struct timer_list blink_timer;
597 struct mii_if_info mii;
598 struct work_struct tx_timeout_task;
599 enum loopback loopback;
600
601 struct mem *mem;
602 dma_addr_t dma_addr;
603
604 dma_addr_t cbs_dma_addr;
605 u8 adaptive_ifs;
606 u8 tx_threshold;
607 u32 tx_frames;
608 u32 tx_collisions;
609 u32 tx_deferred;
610 u32 tx_single_collisions;
611 u32 tx_multiple_collisions;
612 u32 tx_fc_pause;
613 u32 tx_tco_frames;
614
615 u32 rx_fc_pause;
616 u32 rx_fc_unsupported;
617 u32 rx_tco_frames;
618 u32 rx_over_length_errors;
619
620 u16 leds;
621 u16 eeprom_wc;
622 __le16 eeprom[256];
623 spinlock_t mdio_lock;
624 };
625
626 static inline void e100_write_flush(struct nic *nic)
627 {
628 /* Flush previous PCI writes through intermediate bridges
629 * by doing a benign read */
630 (void)ioread8(&nic->csr->scb.status);
631 }
632
633 static void e100_enable_irq(struct nic *nic)
634 {
635 unsigned long flags;
636
637 spin_lock_irqsave(&nic->cmd_lock, flags);
638 iowrite8(irq_mask_none, &nic->csr->scb.cmd_hi);
639 e100_write_flush(nic);
640 spin_unlock_irqrestore(&nic->cmd_lock, flags);
641 }
642
643 static void e100_disable_irq(struct nic *nic)
644 {
645 unsigned long flags;
646
647 spin_lock_irqsave(&nic->cmd_lock, flags);
648 iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi);
649 e100_write_flush(nic);
650 spin_unlock_irqrestore(&nic->cmd_lock, flags);
651 }
652
653 static void e100_hw_reset(struct nic *nic)
654 {
655 /* Put CU and RU into idle with a selective reset to get
656 * device off of PCI bus */
657 iowrite32(selective_reset, &nic->csr->port);
658 e100_write_flush(nic); udelay(20);
659
660 /* Now fully reset device */
661 iowrite32(software_reset, &nic->csr->port);
662 e100_write_flush(nic); udelay(20);
663
664 /* Mask off our interrupt line - it's unmasked after reset */
665 e100_disable_irq(nic);
666 }
667
668 static int e100_self_test(struct nic *nic)
669 {
670 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
671
672 /* Passing the self-test is a pretty good indication
673 * that the device can DMA to/from host memory */
674
675 nic->mem->selftest.signature = 0;
676 nic->mem->selftest.result = 0xFFFFFFFF;
677
678 iowrite32(selftest | dma_addr, &nic->csr->port);
679 e100_write_flush(nic);
680 /* Wait 10 msec for self-test to complete */
681 msleep(10);
682
683 /* Interrupts are enabled after self-test */
684 e100_disable_irq(nic);
685
686 /* Check results of self-test */
687 if (nic->mem->selftest.result != 0) {
688 DPRINTK(HW, ERR, "Self-test failed: result=0x%08X\n",
689 nic->mem->selftest.result);
690 return -ETIMEDOUT;
691 }
692 if (nic->mem->selftest.signature == 0) {
693 DPRINTK(HW, ERR, "Self-test failed: timed out\n");
694 return -ETIMEDOUT;
695 }
696
697 return 0;
698 }
699
700 static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, __le16 data)
701 {
702 u32 cmd_addr_data[3];
703 u8 ctrl;
704 int i, j;
705
706 /* Three cmds: write/erase enable, write data, write/erase disable */
707 cmd_addr_data[0] = op_ewen << (addr_len - 2);
708 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
709 le16_to_cpu(data);
710 cmd_addr_data[2] = op_ewds << (addr_len - 2);
711
712 /* Bit-bang cmds to write word to eeprom */
713 for (j = 0; j < 3; j++) {
714
715 /* Chip select */
716 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
717 e100_write_flush(nic); udelay(4);
718
719 for (i = 31; i >= 0; i--) {
720 ctrl = (cmd_addr_data[j] & (1 << i)) ?
721 eecs | eedi : eecs;
722 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
723 e100_write_flush(nic); udelay(4);
724
725 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
726 e100_write_flush(nic); udelay(4);
727 }
728 /* Wait 10 msec for cmd to complete */
729 msleep(10);
730
731 /* Chip deselect */
732 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
733 e100_write_flush(nic); udelay(4);
734 }
735 };
736
737 /* General technique stolen from the eepro100 driver - very clever */
738 static __le16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
739 {
740 u32 cmd_addr_data;
741 u16 data = 0;
742 u8 ctrl;
743 int i;
744
745 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
746
747 /* Chip select */
748 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
749 e100_write_flush(nic); udelay(4);
750
751 /* Bit-bang to read word from eeprom */
752 for (i = 31; i >= 0; i--) {
753 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
754 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
755 e100_write_flush(nic); udelay(4);
756
757 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
758 e100_write_flush(nic); udelay(4);
759
760 /* Eeprom drives a dummy zero to EEDO after receiving
761 * complete address. Use this to adjust addr_len. */
762 ctrl = ioread8(&nic->csr->eeprom_ctrl_lo);
763 if (!(ctrl & eedo) && i > 16) {
764 *addr_len -= (i - 16);
765 i = 17;
766 }
767
768 data = (data << 1) | (ctrl & eedo ? 1 : 0);
769 }
770
771 /* Chip deselect */
772 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
773 e100_write_flush(nic); udelay(4);
774
775 return cpu_to_le16(data);
776 };
777
778 /* Load entire EEPROM image into driver cache and validate checksum */
779 static int e100_eeprom_load(struct nic *nic)
780 {
781 u16 addr, addr_len = 8, checksum = 0;
782
783 /* Try reading with an 8-bit addr len to discover actual addr len */
784 e100_eeprom_read(nic, &addr_len, 0);
785 nic->eeprom_wc = 1 << addr_len;
786
787 for (addr = 0; addr < nic->eeprom_wc; addr++) {
788 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
789 if (addr < nic->eeprom_wc - 1)
790 checksum += le16_to_cpu(nic->eeprom[addr]);
791 }
792
793 /* The checksum, stored in the last word, is calculated such that
794 * the sum of words should be 0xBABA */
795 if (cpu_to_le16(0xBABA - checksum) != nic->eeprom[nic->eeprom_wc - 1]) {
796 DPRINTK(PROBE, ERR, "EEPROM corrupted\n");
797 if (!eeprom_bad_csum_allow)
798 return -EAGAIN;
799 }
800
801 return 0;
802 }
803
804 /* Save (portion of) driver EEPROM cache to device and update checksum */
805 static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
806 {
807 u16 addr, addr_len = 8, checksum = 0;
808
809 /* Try reading with an 8-bit addr len to discover actual addr len */
810 e100_eeprom_read(nic, &addr_len, 0);
811 nic->eeprom_wc = 1 << addr_len;
812
813 if (start + count >= nic->eeprom_wc)
814 return -EINVAL;
815
816 for (addr = start; addr < start + count; addr++)
817 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
818
819 /* The checksum, stored in the last word, is calculated such that
820 * the sum of words should be 0xBABA */
821 for (addr = 0; addr < nic->eeprom_wc - 1; addr++)
822 checksum += le16_to_cpu(nic->eeprom[addr]);
823 nic->eeprom[nic->eeprom_wc - 1] = cpu_to_le16(0xBABA - checksum);
824 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
825 nic->eeprom[nic->eeprom_wc - 1]);
826
827 return 0;
828 }
829
830 #define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */
831 #define E100_WAIT_SCB_FAST 20 /* delay like the old code */
832 static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
833 {
834 unsigned long flags;
835 unsigned int i;
836 int err = 0;
837
838 spin_lock_irqsave(&nic->cmd_lock, flags);
839
840 /* Previous command is accepted when SCB clears */
841 for (i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
842 if (likely(!ioread8(&nic->csr->scb.cmd_lo)))
843 break;
844 cpu_relax();
845 if (unlikely(i > E100_WAIT_SCB_FAST))
846 udelay(5);
847 }
848 if (unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
849 err = -EAGAIN;
850 goto err_unlock;
851 }
852
853 if (unlikely(cmd != cuc_resume))
854 iowrite32(dma_addr, &nic->csr->scb.gen_ptr);
855 iowrite8(cmd, &nic->csr->scb.cmd_lo);
856
857 err_unlock:
858 spin_unlock_irqrestore(&nic->cmd_lock, flags);
859
860 return err;
861 }
862
863 static int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
864 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
865 {
866 struct cb *cb;
867 unsigned long flags;
868 int err = 0;
869
870 spin_lock_irqsave(&nic->cb_lock, flags);
871
872 if (unlikely(!nic->cbs_avail)) {
873 err = -ENOMEM;
874 goto err_unlock;
875 }
876
877 cb = nic->cb_to_use;
878 nic->cb_to_use = cb->next;
879 nic->cbs_avail--;
880 cb->skb = skb;
881
882 if (unlikely(!nic->cbs_avail))
883 err = -ENOSPC;
884
885 cb_prepare(nic, cb, skb);
886
887 /* Order is important otherwise we'll be in a race with h/w:
888 * set S-bit in current first, then clear S-bit in previous. */
889 cb->command |= cpu_to_le16(cb_s);
890 wmb();
891 cb->prev->command &= cpu_to_le16(~cb_s);
892
893 while (nic->cb_to_send != nic->cb_to_use) {
894 if (unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
895 nic->cb_to_send->dma_addr))) {
896 /* Ok, here's where things get sticky. It's
897 * possible that we can't schedule the command
898 * because the controller is too busy, so
899 * let's just queue the command and try again
900 * when another command is scheduled. */
901 if (err == -ENOSPC) {
902 //request a reset
903 schedule_work(&nic->tx_timeout_task);
904 }
905 break;
906 } else {
907 nic->cuc_cmd = cuc_resume;
908 nic->cb_to_send = nic->cb_to_send->next;
909 }
910 }
911
912 err_unlock:
913 spin_unlock_irqrestore(&nic->cb_lock, flags);
914
915 return err;
916 }
917
918 static int mdio_read(struct net_device *netdev, int addr, int reg)
919 {
920 struct nic *nic = netdev_priv(netdev);
921 return nic->mdio_ctrl(nic, addr, mdi_read, reg, 0);
922 }
923
924 static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
925 {
926 struct nic *nic = netdev_priv(netdev);
927
928 nic->mdio_ctrl(nic, addr, mdi_write, reg, data);
929 }
930
931 /* the standard mdio_ctrl() function for usual MII-compliant hardware */
932 static u16 mdio_ctrl_hw(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
933 {
934 u32 data_out = 0;
935 unsigned int i;
936 unsigned long flags;
937
938
939 /*
940 * Stratus87247: we shouldn't be writing the MDI control
941 * register until the Ready bit shows True. Also, since
942 * manipulation of the MDI control registers is a multi-step
943 * procedure it should be done under lock.
944 */
945 spin_lock_irqsave(&nic->mdio_lock, flags);
946 for (i = 100; i; --i) {
947 if (ioread32(&nic->csr->mdi_ctrl) & mdi_ready)
948 break;
949 udelay(20);
950 }
951 if (unlikely(!i)) {
952 printk("e100.mdio_ctrl(%s) won't go Ready\n",
953 nic->netdev->name );
954 spin_unlock_irqrestore(&nic->mdio_lock, flags);
955 return 0; /* No way to indicate timeout error */
956 }
957 iowrite32((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
958
959 for (i = 0; i < 100; i++) {
960 udelay(20);
961 if ((data_out = ioread32(&nic->csr->mdi_ctrl)) & mdi_ready)
962 break;
963 }
964 spin_unlock_irqrestore(&nic->mdio_lock, flags);
965 DPRINTK(HW, DEBUG,
966 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
967 dir == mdi_read ? "READ" : "WRITE", addr, reg, data, data_out);
968 return (u16)data_out;
969 }
970
971 /* slightly tweaked mdio_ctrl() function for phy_82552_v specifics */
972 static u16 mdio_ctrl_phy_82552_v(struct nic *nic,
973 u32 addr,
974 u32 dir,
975 u32 reg,
976 u16 data)
977 {
978 if ((reg == MII_BMCR) && (dir == mdi_write)) {
979 if (data & (BMCR_ANRESTART | BMCR_ANENABLE)) {
980 u16 advert = mdio_read(nic->netdev, nic->mii.phy_id,
981 MII_ADVERTISE);
982
983 /*
984 * Workaround Si issue where sometimes the part will not
985 * autoneg to 100Mbps even when advertised.
986 */
987 if (advert & ADVERTISE_100FULL)
988 data |= BMCR_SPEED100 | BMCR_FULLDPLX;
989 else if (advert & ADVERTISE_100HALF)
990 data |= BMCR_SPEED100;
991 }
992 }
993 return mdio_ctrl_hw(nic, addr, dir, reg, data);
994 }
995
996 /* Fully software-emulated mdio_ctrl() function for cards without
997 * MII-compliant PHYs.
998 * For now, this is mainly geared towards 80c24 support; in case of further
999 * requirements for other types (i82503, ...?) either extend this mechanism
1000 * or split it, whichever is cleaner.
1001 */
1002 static u16 mdio_ctrl_phy_mii_emulated(struct nic *nic,
1003 u32 addr,
1004 u32 dir,
1005 u32 reg,
1006 u16 data)
1007 {
1008 /* might need to allocate a netdev_priv'ed register array eventually
1009 * to be able to record state changes, but for now
1010 * some fully hardcoded register handling ought to be ok I guess. */
1011
1012 if (dir == mdi_read) {
1013 switch (reg) {
1014 case MII_BMCR:
1015 /* Auto-negotiation, right? */
1016 return BMCR_ANENABLE |
1017 BMCR_FULLDPLX;
1018 case MII_BMSR:
1019 return BMSR_LSTATUS /* for mii_link_ok() */ |
1020 BMSR_ANEGCAPABLE |
1021 BMSR_10FULL;
1022 case MII_ADVERTISE:
1023 /* 80c24 is a "combo card" PHY, right? */
1024 return ADVERTISE_10HALF |
1025 ADVERTISE_10FULL;
1026 default:
1027 DPRINTK(HW, DEBUG,
1028 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1029 dir == mdi_read ? "READ" : "WRITE", addr, reg, data);
1030 return 0xFFFF;
1031 }
1032 } else {
1033 switch (reg) {
1034 default:
1035 DPRINTK(HW, DEBUG,
1036 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1037 dir == mdi_read ? "READ" : "WRITE", addr, reg, data);
1038 return 0xFFFF;
1039 }
1040 }
1041 }
1042 static inline int e100_phy_supports_mii(struct nic *nic)
1043 {
1044 /* for now, just check it by comparing whether we
1045 are using MII software emulation.
1046 */
1047 return (nic->mdio_ctrl != mdio_ctrl_phy_mii_emulated);
1048 }
1049
1050 static void e100_get_defaults(struct nic *nic)
1051 {
1052 struct param_range rfds = { .min = 16, .max = 256, .count = 256 };
1053 struct param_range cbs = { .min = 64, .max = 256, .count = 128 };
1054
1055 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
1056 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->pdev->revision;
1057 if (nic->mac == mac_unknown)
1058 nic->mac = mac_82557_D100_A;
1059
1060 nic->params.rfds = rfds;
1061 nic->params.cbs = cbs;
1062
1063 /* Quadwords to DMA into FIFO before starting frame transmit */
1064 nic->tx_threshold = 0xE0;
1065
1066 /* no interrupt for every tx completion, delay = 256us if not 557 */
1067 nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |
1068 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));
1069
1070 /* Template for a freshly allocated RFD */
1071 nic->blank_rfd.command = 0;
1072 nic->blank_rfd.rbd = cpu_to_le32(0xFFFFFFFF);
1073 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
1074
1075 /* MII setup */
1076 nic->mii.phy_id_mask = 0x1F;
1077 nic->mii.reg_num_mask = 0x1F;
1078 nic->mii.dev = nic->netdev;
1079 nic->mii.mdio_read = mdio_read;
1080 nic->mii.mdio_write = mdio_write;
1081 }
1082
1083 static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1084 {
1085 struct config *config = &cb->u.config;
1086 u8 *c = (u8 *)config;
1087
1088 cb->command = cpu_to_le16(cb_config);
1089
1090 memset(config, 0, sizeof(struct config));
1091
1092 config->byte_count = 0x16; /* bytes in this struct */
1093 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
1094 config->direct_rx_dma = 0x1; /* reserved */
1095 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
1096 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
1097 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
1098 config->tx_underrun_retry = 0x3; /* # of underrun retries */
1099 if (e100_phy_supports_mii(nic))
1100 config->mii_mode = 1; /* 1=MII mode, 0=i82503 mode */
1101 config->pad10 = 0x6;
1102 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
1103 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
1104 config->ifs = 0x6; /* x16 = inter frame spacing */
1105 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
1106 config->pad15_1 = 0x1;
1107 config->pad15_2 = 0x1;
1108 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
1109 config->fc_delay_hi = 0x40; /* time delay for fc frame */
1110 config->tx_padding = 0x1; /* 1=pad short frames */
1111 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
1112 config->pad18 = 0x1;
1113 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
1114 config->pad20_1 = 0x1F;
1115 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
1116 config->pad21_1 = 0x5;
1117
1118 config->adaptive_ifs = nic->adaptive_ifs;
1119 config->loopback = nic->loopback;
1120
1121 if (nic->mii.force_media && nic->mii.full_duplex)
1122 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
1123
1124 if (nic->flags & promiscuous || nic->loopback) {
1125 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
1126 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
1127 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
1128 }
1129
1130 if (nic->flags & multicast_all)
1131 config->multicast_all = 0x1; /* 1=accept, 0=no */
1132
1133 /* disable WoL when up */
1134 if (netif_running(nic->netdev) || !(nic->flags & wol_magic))
1135 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
1136
1137 if (nic->mac >= mac_82558_D101_A4) {
1138 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
1139 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
1140 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
1141 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
1142 if (nic->mac >= mac_82559_D101M) {
1143 config->tno_intr = 0x1; /* TCO stats enable */
1144 /* Enable TCO in extended config */
1145 if (nic->mac >= mac_82551_10) {
1146 config->byte_count = 0x20; /* extended bytes */
1147 config->rx_d102_mode = 0x1; /* GMRC for TCO */
1148 }
1149 } else {
1150 config->standard_stat_counter = 0x0;
1151 }
1152 }
1153
1154 DPRINTK(HW, DEBUG, "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1155 c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
1156 DPRINTK(HW, DEBUG, "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1157 c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);
1158 DPRINTK(HW, DEBUG, "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1159 c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
1160 }
1161
1162 /*************************************************************************
1163 * CPUSaver parameters
1164 *
1165 * All CPUSaver parameters are 16-bit literals that are part of a
1166 * "move immediate value" instruction. By changing the value of
1167 * the literal in the instruction before the code is loaded, the
1168 * driver can change the algorithm.
1169 *
1170 * INTDELAY - This loads the dead-man timer with its initial value.
1171 * When this timer expires the interrupt is asserted, and the
1172 * timer is reset each time a new packet is received. (see
1173 * BUNDLEMAX below to set the limit on number of chained packets)
1174 * The current default is 0x600 or 1536. Experiments show that
1175 * the value should probably stay within the 0x200 - 0x1000.
1176 *
1177 * BUNDLEMAX -
1178 * This sets the maximum number of frames that will be bundled. In
1179 * some situations, such as the TCP windowing algorithm, it may be
1180 * better to limit the growth of the bundle size than let it go as
1181 * high as it can, because that could cause too much added latency.
1182 * The default is six, because this is the number of packets in the
1183 * default TCP window size. A value of 1 would make CPUSaver indicate
1184 * an interrupt for every frame received. If you do not want to put
1185 * a limit on the bundle size, set this value to xFFFF.
1186 *
1187 * BUNDLESMALL -
1188 * This contains a bit-mask describing the minimum size frame that
1189 * will be bundled. The default masks the lower 7 bits, which means
1190 * that any frame less than 128 bytes in length will not be bundled,
1191 * but will instead immediately generate an interrupt. This does
1192 * not affect the current bundle in any way. Any frame that is 128
1193 * bytes or large will be bundled normally. This feature is meant
1194 * to provide immediate indication of ACK frames in a TCP environment.
1195 * Customers were seeing poor performance when a machine with CPUSaver
1196 * enabled was sending but not receiving. The delay introduced when
1197 * the ACKs were received was enough to reduce total throughput, because
1198 * the sender would sit idle until the ACK was finally seen.
1199 *
1200 * The current default is 0xFF80, which masks out the lower 7 bits.
1201 * This means that any frame which is x7F (127) bytes or smaller
1202 * will cause an immediate interrupt. Because this value must be a
1203 * bit mask, there are only a few valid values that can be used. To
1204 * turn this feature off, the driver can write the value xFFFF to the
1205 * lower word of this instruction (in the same way that the other
1206 * parameters are used). Likewise, a value of 0xF800 (2047) would
1207 * cause an interrupt to be generated for every frame, because all
1208 * standard Ethernet frames are <= 2047 bytes in length.
1209 *************************************************************************/
1210
1211 /* if you wish to disable the ucode functionality, while maintaining the
1212 * workarounds it provides, set the following defines to:
1213 * BUNDLESMALL 0
1214 * BUNDLEMAX 1
1215 * INTDELAY 1
1216 */
1217 #define BUNDLESMALL 1
1218 #define BUNDLEMAX (u16)6
1219 #define INTDELAY (u16)1536 /* 0x600 */
1220
1221 /* Initialize firmware */
1222 static const struct firmware *e100_request_firmware(struct nic *nic)
1223 {
1224 const char *fw_name;
1225 const struct firmware *fw;
1226 u8 timer, bundle, min_size;
1227 int err;
1228
1229 /* do not load u-code for ICH devices */
1230 if (nic->flags & ich)
1231 return NULL;
1232
1233 /* Search for ucode match against h/w revision */
1234 if (nic->mac == mac_82559_D101M)
1235 fw_name = FIRMWARE_D101M;
1236 else if (nic->mac == mac_82559_D101S)
1237 fw_name = FIRMWARE_D101S;
1238 else if (nic->mac == mac_82551_F || nic->mac == mac_82551_10)
1239 fw_name = FIRMWARE_D102E;
1240 else /* No ucode on other devices */
1241 return NULL;
1242
1243 err = request_firmware(&fw, fw_name, &nic->pdev->dev);
1244 if (err) {
1245 DPRINTK(PROBE, ERR, "Failed to load firmware \"%s\": %d\n",
1246 fw_name, err);
1247 return ERR_PTR(err);
1248 }
1249 /* Firmware should be precisely UCODE_SIZE (words) plus three bytes
1250 indicating the offsets for BUNDLESMALL, BUNDLEMAX, INTDELAY */
1251 if (fw->size != UCODE_SIZE * 4 + 3) {
1252 DPRINTK(PROBE, ERR, "Firmware \"%s\" has wrong size %zu\n",
1253 fw_name, fw->size);
1254 release_firmware(fw);
1255 return ERR_PTR(-EINVAL);
1256 }
1257
1258 /* Read timer, bundle and min_size from end of firmware blob */
1259 timer = fw->data[UCODE_SIZE * 4];
1260 bundle = fw->data[UCODE_SIZE * 4 + 1];
1261 min_size = fw->data[UCODE_SIZE * 4 + 2];
1262
1263 if (timer >= UCODE_SIZE || bundle >= UCODE_SIZE ||
1264 min_size >= UCODE_SIZE) {
1265 DPRINTK(PROBE, ERR,
1266 "\"%s\" has bogus offset values (0x%x,0x%x,0x%x)\n",
1267 fw_name, timer, bundle, min_size);
1268 release_firmware(fw);
1269 return ERR_PTR(-EINVAL);
1270 }
1271 /* OK, firmware is validated and ready to use... */
1272 return fw;
1273 }
1274
1275 static void e100_setup_ucode(struct nic *nic, struct cb *cb,
1276 struct sk_buff *skb)
1277 {
1278 const struct firmware *fw = (void *)skb;
1279 u8 timer, bundle, min_size;
1280
1281 /* It's not a real skb; we just abused the fact that e100_exec_cb
1282 will pass it through to here... */
1283 cb->skb = NULL;
1284
1285 /* firmware is stored as little endian already */
1286 memcpy(cb->u.ucode, fw->data, UCODE_SIZE * 4);
1287
1288 /* Read timer, bundle and min_size from end of firmware blob */
1289 timer = fw->data[UCODE_SIZE * 4];
1290 bundle = fw->data[UCODE_SIZE * 4 + 1];
1291 min_size = fw->data[UCODE_SIZE * 4 + 2];
1292
1293 /* Insert user-tunable settings in cb->u.ucode */
1294 cb->u.ucode[timer] &= cpu_to_le32(0xFFFF0000);
1295 cb->u.ucode[timer] |= cpu_to_le32(INTDELAY);
1296 cb->u.ucode[bundle] &= cpu_to_le32(0xFFFF0000);
1297 cb->u.ucode[bundle] |= cpu_to_le32(BUNDLEMAX);
1298 cb->u.ucode[min_size] &= cpu_to_le32(0xFFFF0000);
1299 cb->u.ucode[min_size] |= cpu_to_le32((BUNDLESMALL) ? 0xFFFF : 0xFF80);
1300
1301 cb->command = cpu_to_le16(cb_ucode | cb_el);
1302 }
1303
1304 static inline int e100_load_ucode_wait(struct nic *nic)
1305 {
1306 const struct firmware *fw;
1307 int err = 0, counter = 50;
1308 struct cb *cb = nic->cb_to_clean;
1309
1310 fw = e100_request_firmware(nic);
1311 /* If it's NULL, then no ucode is required */
1312 if (!fw || IS_ERR(fw))
1313 return PTR_ERR(fw);
1314
1315 if ((err = e100_exec_cb(nic, (void *)fw, e100_setup_ucode)))
1316 DPRINTK(PROBE,ERR, "ucode cmd failed with error %d\n", err);
1317
1318 /* must restart cuc */
1319 nic->cuc_cmd = cuc_start;
1320
1321 /* wait for completion */
1322 e100_write_flush(nic);
1323 udelay(10);
1324
1325 /* wait for possibly (ouch) 500ms */
1326 while (!(cb->status & cpu_to_le16(cb_complete))) {
1327 msleep(10);
1328 if (!--counter) break;
1329 }
1330
1331 /* ack any interrupts, something could have been set */
1332 iowrite8(~0, &nic->csr->scb.stat_ack);
1333
1334 /* if the command failed, or is not OK, notify and return */
1335 if (!counter || !(cb->status & cpu_to_le16(cb_ok))) {
1336 DPRINTK(PROBE,ERR, "ucode load failed\n");
1337 err = -EPERM;
1338 }
1339
1340 return err;
1341 }
1342
1343 static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
1344 struct sk_buff *skb)
1345 {
1346 cb->command = cpu_to_le16(cb_iaaddr);
1347 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1348 }
1349
1350 static void e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1351 {
1352 cb->command = cpu_to_le16(cb_dump);
1353 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
1354 offsetof(struct mem, dump_buf));
1355 }
1356
1357 static int e100_phy_check_without_mii(struct nic *nic)
1358 {
1359 u8 phy_type;
1360 int without_mii;
1361
1362 phy_type = (nic->eeprom[eeprom_phy_iface] >> 8) & 0x0f;
1363
1364 switch (phy_type) {
1365 case NoSuchPhy: /* Non-MII PHY; UNTESTED! */
1366 case I82503: /* Non-MII PHY; UNTESTED! */
1367 case S80C24: /* Non-MII PHY; tested and working */
1368 /* paragraph from the FreeBSD driver, "FXP_PHY_80C24":
1369 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
1370 * doesn't have a programming interface of any sort. The
1371 * media is sensed automatically based on how the link partner
1372 * is configured. This is, in essence, manual configuration.
1373 */
1374 DPRINTK(PROBE, INFO,
1375 "found MII-less i82503 or 80c24 or other PHY\n");
1376
1377 nic->mdio_ctrl = mdio_ctrl_phy_mii_emulated;
1378 nic->mii.phy_id = 0; /* is this ok for an MII-less PHY? */
1379
1380 /* these might be needed for certain MII-less cards...
1381 * nic->flags |= ich;
1382 * nic->flags |= ich_10h_workaround; */
1383
1384 without_mii = 1;
1385 break;
1386 default:
1387 without_mii = 0;
1388 break;
1389 }
1390 return without_mii;
1391 }
1392
1393 #define NCONFIG_AUTO_SWITCH 0x0080
1394 #define MII_NSC_CONG MII_RESV1
1395 #define NSC_CONG_ENABLE 0x0100
1396 #define NSC_CONG_TXREADY 0x0400
1397 #define ADVERTISE_FC_SUPPORTED 0x0400
1398 static int e100_phy_init(struct nic *nic)
1399 {
1400 struct net_device *netdev = nic->netdev;
1401 u32 addr;
1402 u16 bmcr, stat, id_lo, id_hi, cong;
1403
1404 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
1405 for (addr = 0; addr < 32; addr++) {
1406 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1407 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1408 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1409 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1410 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1411 break;
1412 }
1413 if (addr == 32) {
1414 /* uhoh, no PHY detected: check whether we seem to be some
1415 * weird, rare variant which is *known* to not have any MII.
1416 * But do this AFTER MII checking only, since this does
1417 * lookup of EEPROM values which may easily be unreliable. */
1418 if (e100_phy_check_without_mii(nic))
1419 return 0; /* simply return and hope for the best */
1420 else {
1421 /* for unknown cases log a fatal error */
1422 DPRINTK(HW, ERR,
1423 "Failed to locate any known PHY, aborting.\n");
1424 return -EAGAIN;
1425 }
1426 } else
1427 DPRINTK(HW, DEBUG, "phy_addr = %d\n", nic->mii.phy_id);
1428
1429 /* Isolate all the PHY ids */
1430 for (addr = 0; addr < 32; addr++)
1431 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1432 /* Select the discovered PHY */
1433 bmcr &= ~BMCR_ISOLATE;
1434 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, bmcr);
1435
1436 /* Get phy ID */
1437 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1438 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1439 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
1440 DPRINTK(HW, DEBUG, "phy ID = 0x%08X\n", nic->phy);
1441
1442 /* Handle National tx phys */
1443 #define NCS_PHY_MODEL_MASK 0xFFF0FFFF
1444 if ((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1445 /* Disable congestion control */
1446 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1447 cong |= NSC_CONG_TXREADY;
1448 cong &= ~NSC_CONG_ENABLE;
1449 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1450 }
1451
1452 if (nic->phy == phy_82552_v) {
1453 u16 advert = mdio_read(netdev, nic->mii.phy_id, MII_ADVERTISE);
1454
1455 /* assign special tweaked mdio_ctrl() function */
1456 nic->mdio_ctrl = mdio_ctrl_phy_82552_v;
1457
1458 /* Workaround Si not advertising flow-control during autoneg */
1459 advert |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1460 mdio_write(netdev, nic->mii.phy_id, MII_ADVERTISE, advert);
1461
1462 /* Reset for the above changes to take effect */
1463 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1464 bmcr |= BMCR_RESET;
1465 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, bmcr);
1466 } else if ((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
1467 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) &&
1468 !(nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled))) {
1469 /* enable/disable MDI/MDI-X auto-switching. */
1470 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
1471 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH);
1472 }
1473
1474 return 0;
1475 }
1476
1477 static int e100_hw_init(struct nic *nic)
1478 {
1479 int err;
1480
1481 e100_hw_reset(nic);
1482
1483 DPRINTK(HW, ERR, "e100_hw_init\n");
1484 if (!in_interrupt() && (err = e100_self_test(nic)))
1485 return err;
1486
1487 if ((err = e100_phy_init(nic)))
1488 return err;
1489 if ((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1490 return err;
1491 if ((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1492 return err;
1493 if ((err = e100_load_ucode_wait(nic)))
1494 return err;
1495 if ((err = e100_exec_cb(nic, NULL, e100_configure)))
1496 return err;
1497 if ((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1498 return err;
1499 if ((err = e100_exec_cmd(nic, cuc_dump_addr,
1500 nic->dma_addr + offsetof(struct mem, stats))))
1501 return err;
1502 if ((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1503 return err;
1504
1505 e100_disable_irq(nic);
1506
1507 return 0;
1508 }
1509
1510 static void e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1511 {
1512 struct net_device *netdev = nic->netdev;
1513 struct dev_mc_list *list = netdev->mc_list;
1514 u16 i, count = min(netdev->mc_count, E100_MAX_MULTICAST_ADDRS);
1515
1516 cb->command = cpu_to_le16(cb_multi);
1517 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
1518 for (i = 0; list && i < count; i++, list = list->next)
1519 memcpy(&cb->u.multi.addr[i*ETH_ALEN], &list->dmi_addr,
1520 ETH_ALEN);
1521 }
1522
1523 static void e100_set_multicast_list(struct net_device *netdev)
1524 {
1525 struct nic *nic = netdev_priv(netdev);
1526
1527 DPRINTK(HW, DEBUG, "mc_count=%d, flags=0x%04X\n",
1528 netdev->mc_count, netdev->flags);
1529
1530 if (netdev->flags & IFF_PROMISC)
1531 nic->flags |= promiscuous;
1532 else
1533 nic->flags &= ~promiscuous;
1534
1535 if (netdev->flags & IFF_ALLMULTI ||
1536 netdev->mc_count > E100_MAX_MULTICAST_ADDRS)
1537 nic->flags |= multicast_all;
1538 else
1539 nic->flags &= ~multicast_all;
1540
1541 e100_exec_cb(nic, NULL, e100_configure);
1542 e100_exec_cb(nic, NULL, e100_multi);
1543 }
1544
1545 static void e100_update_stats(struct nic *nic)
1546 {
1547 struct net_device *dev = nic->netdev;
1548 struct net_device_stats *ns = &dev->stats;
1549 struct stats *s = &nic->mem->stats;
1550 __le32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1551 (nic->mac < mac_82559_D101M) ? (__le32 *)&s->xmt_tco_frames :
1552 &s->complete;
1553
1554 /* Device's stats reporting may take several microseconds to
1555 * complete, so we're always waiting for results of the
1556 * previous command. */
1557
1558 if (*complete == cpu_to_le32(cuc_dump_reset_complete)) {
1559 *complete = 0;
1560 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1561 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1562 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1563 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1564 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1565 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1566 ns->collisions += nic->tx_collisions;
1567 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1568 le32_to_cpu(s->tx_lost_crs);
1569 ns->rx_length_errors += le32_to_cpu(s->rx_short_frame_errors) +
1570 nic->rx_over_length_errors;
1571 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1572 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1573 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1574 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
1575 ns->rx_missed_errors += le32_to_cpu(s->rx_resource_errors);
1576 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1577 le32_to_cpu(s->rx_alignment_errors) +
1578 le32_to_cpu(s->rx_short_frame_errors) +
1579 le32_to_cpu(s->rx_cdt_errors);
1580 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1581 nic->tx_single_collisions +=
1582 le32_to_cpu(s->tx_single_collisions);
1583 nic->tx_multiple_collisions +=
1584 le32_to_cpu(s->tx_multiple_collisions);
1585 if (nic->mac >= mac_82558_D101_A4) {
1586 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1587 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1588 nic->rx_fc_unsupported +=
1589 le32_to_cpu(s->fc_rcv_unsupported);
1590 if (nic->mac >= mac_82559_D101M) {
1591 nic->tx_tco_frames +=
1592 le16_to_cpu(s->xmt_tco_frames);
1593 nic->rx_tco_frames +=
1594 le16_to_cpu(s->rcv_tco_frames);
1595 }
1596 }
1597 }
1598
1599
1600 if (e100_exec_cmd(nic, cuc_dump_reset, 0))
1601 DPRINTK(TX_ERR, DEBUG, "exec cuc_dump_reset failed\n");
1602 }
1603
1604 static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1605 {
1606 /* Adjust inter-frame-spacing (IFS) between two transmits if
1607 * we're getting collisions on a half-duplex connection. */
1608
1609 if (duplex == DUPLEX_HALF) {
1610 u32 prev = nic->adaptive_ifs;
1611 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1612
1613 if ((nic->tx_frames / 32 < nic->tx_collisions) &&
1614 (nic->tx_frames > min_frames)) {
1615 if (nic->adaptive_ifs < 60)
1616 nic->adaptive_ifs += 5;
1617 } else if (nic->tx_frames < min_frames) {
1618 if (nic->adaptive_ifs >= 5)
1619 nic->adaptive_ifs -= 5;
1620 }
1621 if (nic->adaptive_ifs != prev)
1622 e100_exec_cb(nic, NULL, e100_configure);
1623 }
1624 }
1625
1626 static void e100_watchdog(unsigned long data)
1627 {
1628 struct nic *nic = (struct nic *)data;
1629 struct ethtool_cmd cmd;
1630
1631 DPRINTK(TIMER, DEBUG, "right now = %ld\n", jiffies);
1632
1633 /* mii library handles link maintenance tasks */
1634
1635 mii_ethtool_gset(&nic->mii, &cmd);
1636
1637 if (mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
1638 printk(KERN_INFO "e100: %s NIC Link is Up %s Mbps %s Duplex\n",
1639 nic->netdev->name,
1640 cmd.speed == SPEED_100 ? "100" : "10",
1641 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1642 } else if (!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
1643 printk(KERN_INFO "e100: %s NIC Link is Down\n",
1644 nic->netdev->name);
1645 }
1646
1647 mii_check_link(&nic->mii);
1648
1649 /* Software generated interrupt to recover from (rare) Rx
1650 * allocation failure.
1651 * Unfortunately have to use a spinlock to not re-enable interrupts
1652 * accidentally, due to hardware that shares a register between the
1653 * interrupt mask bit and the SW Interrupt generation bit */
1654 spin_lock_irq(&nic->cmd_lock);
1655 iowrite8(ioread8(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
1656 e100_write_flush(nic);
1657 spin_unlock_irq(&nic->cmd_lock);
1658
1659 e100_update_stats(nic);
1660 e100_adjust_adaptive_ifs(nic, cmd.speed, cmd.duplex);
1661
1662 if (nic->mac <= mac_82557_D100_C)
1663 /* Issue a multicast command to workaround a 557 lock up */
1664 e100_set_multicast_list(nic->netdev);
1665
1666 if (nic->flags & ich && cmd.speed==SPEED_10 && cmd.duplex==DUPLEX_HALF)
1667 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1668 nic->flags |= ich_10h_workaround;
1669 else
1670 nic->flags &= ~ich_10h_workaround;
1671
1672 mod_timer(&nic->watchdog,
1673 round_jiffies(jiffies + E100_WATCHDOG_PERIOD));
1674 }
1675
1676 static void e100_xmit_prepare(struct nic *nic, struct cb *cb,
1677 struct sk_buff *skb)
1678 {
1679 cb->command = nic->tx_command;
1680 /* interrupt every 16 packets regardless of delay */
1681 if ((nic->cbs_avail & ~15) == nic->cbs_avail)
1682 cb->command |= cpu_to_le16(cb_i);
1683 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1684 cb->u.tcb.tcb_byte_count = 0;
1685 cb->u.tcb.threshold = nic->tx_threshold;
1686 cb->u.tcb.tbd_count = 1;
1687 cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
1688 skb->data, skb->len, PCI_DMA_TODEVICE));
1689 /* check for mapping failure? */
1690 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1691 }
1692
1693 static netdev_tx_t e100_xmit_frame(struct sk_buff *skb,
1694 struct net_device *netdev)
1695 {
1696 struct nic *nic = netdev_priv(netdev);
1697 int err;
1698
1699 if (nic->flags & ich_10h_workaround) {
1700 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1701 Issue a NOP command followed by a 1us delay before
1702 issuing the Tx command. */
1703 if (e100_exec_cmd(nic, cuc_nop, 0))
1704 DPRINTK(TX_ERR, DEBUG, "exec cuc_nop failed\n");
1705 udelay(1);
1706 }
1707
1708 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1709
1710 switch (err) {
1711 case -ENOSPC:
1712 /* We queued the skb, but now we're out of space. */
1713 DPRINTK(TX_ERR, DEBUG, "No space for CB\n");
1714 netif_stop_queue(netdev);
1715 break;
1716 case -ENOMEM:
1717 /* This is a hard error - log it. */
1718 DPRINTK(TX_ERR, DEBUG, "Out of Tx resources, returning skb\n");
1719 netif_stop_queue(netdev);
1720 return NETDEV_TX_BUSY;
1721 }
1722
1723 netdev->trans_start = jiffies;
1724 return NETDEV_TX_OK;
1725 }
1726
1727 static int e100_tx_clean(struct nic *nic)
1728 {
1729 struct net_device *dev = nic->netdev;
1730 struct cb *cb;
1731 int tx_cleaned = 0;
1732
1733 spin_lock(&nic->cb_lock);
1734
1735 /* Clean CBs marked complete */
1736 for (cb = nic->cb_to_clean;
1737 cb->status & cpu_to_le16(cb_complete);
1738 cb = nic->cb_to_clean = cb->next) {
1739 DPRINTK(TX_DONE, DEBUG, "cb[%d]->status = 0x%04X\n",
1740 (int)(((void*)cb - (void*)nic->cbs)/sizeof(struct cb)),
1741 cb->status);
1742
1743 if (likely(cb->skb != NULL)) {
1744 dev->stats.tx_packets++;
1745 dev->stats.tx_bytes += cb->skb->len;
1746
1747 pci_unmap_single(nic->pdev,
1748 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1749 le16_to_cpu(cb->u.tcb.tbd.size),
1750 PCI_DMA_TODEVICE);
1751 dev_kfree_skb_any(cb->skb);
1752 cb->skb = NULL;
1753 tx_cleaned = 1;
1754 }
1755 cb->status = 0;
1756 nic->cbs_avail++;
1757 }
1758
1759 spin_unlock(&nic->cb_lock);
1760
1761 /* Recover from running out of Tx resources in xmit_frame */
1762 if (unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1763 netif_wake_queue(nic->netdev);
1764
1765 return tx_cleaned;
1766 }
1767
1768 static void e100_clean_cbs(struct nic *nic)
1769 {
1770 if (nic->cbs) {
1771 while (nic->cbs_avail != nic->params.cbs.count) {
1772 struct cb *cb = nic->cb_to_clean;
1773 if (cb->skb) {
1774 pci_unmap_single(nic->pdev,
1775 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1776 le16_to_cpu(cb->u.tcb.tbd.size),
1777 PCI_DMA_TODEVICE);
1778 dev_kfree_skb(cb->skb);
1779 }
1780 nic->cb_to_clean = nic->cb_to_clean->next;
1781 nic->cbs_avail++;
1782 }
1783 pci_free_consistent(nic->pdev,
1784 sizeof(struct cb) * nic->params.cbs.count,
1785 nic->cbs, nic->cbs_dma_addr);
1786 nic->cbs = NULL;
1787 nic->cbs_avail = 0;
1788 }
1789 nic->cuc_cmd = cuc_start;
1790 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1791 nic->cbs;
1792 }
1793
1794 static int e100_alloc_cbs(struct nic *nic)
1795 {
1796 struct cb *cb;
1797 unsigned int i, count = nic->params.cbs.count;
1798
1799 nic->cuc_cmd = cuc_start;
1800 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1801 nic->cbs_avail = 0;
1802
1803 nic->cbs = pci_alloc_consistent(nic->pdev,
1804 sizeof(struct cb) * count, &nic->cbs_dma_addr);
1805 if (!nic->cbs)
1806 return -ENOMEM;
1807
1808 for (cb = nic->cbs, i = 0; i < count; cb++, i++) {
1809 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1810 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1811
1812 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1813 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1814 ((i+1) % count) * sizeof(struct cb));
1815 cb->skb = NULL;
1816 }
1817
1818 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1819 nic->cbs_avail = count;
1820
1821 return 0;
1822 }
1823
1824 static inline void e100_start_receiver(struct nic *nic, struct rx *rx)
1825 {
1826 if (!nic->rxs) return;
1827 if (RU_SUSPENDED != nic->ru_running) return;
1828
1829 /* handle init time starts */
1830 if (!rx) rx = nic->rxs;
1831
1832 /* (Re)start RU if suspended or idle and RFA is non-NULL */
1833 if (rx->skb) {
1834 e100_exec_cmd(nic, ruc_start, rx->dma_addr);
1835 nic->ru_running = RU_RUNNING;
1836 }
1837 }
1838
1839 #define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN)
1840 static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1841 {
1842 if (!(rx->skb = netdev_alloc_skb(nic->netdev, RFD_BUF_LEN + NET_IP_ALIGN)))
1843 return -ENOMEM;
1844
1845 /* Align, init, and map the RFD. */
1846 skb_reserve(rx->skb, NET_IP_ALIGN);
1847 skb_copy_to_linear_data(rx->skb, &nic->blank_rfd, sizeof(struct rfd));
1848 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1849 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1850
1851 if (pci_dma_mapping_error(nic->pdev, rx->dma_addr)) {
1852 dev_kfree_skb_any(rx->skb);
1853 rx->skb = NULL;
1854 rx->dma_addr = 0;
1855 return -ENOMEM;
1856 }
1857
1858 /* Link the RFD to end of RFA by linking previous RFD to
1859 * this one. We are safe to touch the previous RFD because
1860 * it is protected by the before last buffer's el bit being set */
1861 if (rx->prev->skb) {
1862 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
1863 put_unaligned_le32(rx->dma_addr, &prev_rfd->link);
1864 pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr,
1865 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1866 }
1867
1868 return 0;
1869 }
1870
1871 static int e100_rx_indicate(struct nic *nic, struct rx *rx,
1872 unsigned int *work_done, unsigned int work_to_do)
1873 {
1874 struct net_device *dev = nic->netdev;
1875 struct sk_buff *skb = rx->skb;
1876 struct rfd *rfd = (struct rfd *)skb->data;
1877 u16 rfd_status, actual_size;
1878
1879 if (unlikely(work_done && *work_done >= work_to_do))
1880 return -EAGAIN;
1881
1882 /* Need to sync before taking a peek at cb_complete bit */
1883 pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
1884 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1885 rfd_status = le16_to_cpu(rfd->status);
1886
1887 DPRINTK(RX_STATUS, DEBUG, "status=0x%04X\n", rfd_status);
1888
1889 /* If data isn't ready, nothing to indicate */
1890 if (unlikely(!(rfd_status & cb_complete))) {
1891 /* If the next buffer has the el bit, but we think the receiver
1892 * is still running, check to see if it really stopped while
1893 * we had interrupts off.
1894 * This allows for a fast restart without re-enabling
1895 * interrupts */
1896 if ((le16_to_cpu(rfd->command) & cb_el) &&
1897 (RU_RUNNING == nic->ru_running))
1898
1899 if (ioread8(&nic->csr->scb.status) & rus_no_res)
1900 nic->ru_running = RU_SUSPENDED;
1901 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
1902 sizeof(struct rfd),
1903 PCI_DMA_FROMDEVICE);
1904 return -ENODATA;
1905 }
1906
1907 /* Get actual data size */
1908 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
1909 if (unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1910 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1911
1912 /* Get data */
1913 pci_unmap_single(nic->pdev, rx->dma_addr,
1914 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1915
1916 /* If this buffer has the el bit, but we think the receiver
1917 * is still running, check to see if it really stopped while
1918 * we had interrupts off.
1919 * This allows for a fast restart without re-enabling interrupts.
1920 * This can happen when the RU sees the size change but also sees
1921 * the el bit set. */
1922 if ((le16_to_cpu(rfd->command) & cb_el) &&
1923 (RU_RUNNING == nic->ru_running)) {
1924
1925 if (ioread8(&nic->csr->scb.status) & rus_no_res)
1926 nic->ru_running = RU_SUSPENDED;
1927 }
1928
1929 /* Pull off the RFD and put the actual data (minus eth hdr) */
1930 skb_reserve(skb, sizeof(struct rfd));
1931 skb_put(skb, actual_size);
1932 skb->protocol = eth_type_trans(skb, nic->netdev);
1933
1934 if (unlikely(!(rfd_status & cb_ok))) {
1935 /* Don't indicate if hardware indicates errors */
1936 dev_kfree_skb_any(skb);
1937 } else if (actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN) {
1938 /* Don't indicate oversized frames */
1939 nic->rx_over_length_errors++;
1940 dev_kfree_skb_any(skb);
1941 } else {
1942 dev->stats.rx_packets++;
1943 dev->stats.rx_bytes += actual_size;
1944 netif_receive_skb(skb);
1945 if (work_done)
1946 (*work_done)++;
1947 }
1948
1949 rx->skb = NULL;
1950
1951 return 0;
1952 }
1953
1954 static void e100_rx_clean(struct nic *nic, unsigned int *work_done,
1955 unsigned int work_to_do)
1956 {
1957 struct rx *rx;
1958 int restart_required = 0, err = 0;
1959 struct rx *old_before_last_rx, *new_before_last_rx;
1960 struct rfd *old_before_last_rfd, *new_before_last_rfd;
1961
1962 /* Indicate newly arrived packets */
1963 for (rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
1964 err = e100_rx_indicate(nic, rx, work_done, work_to_do);
1965 /* Hit quota or no more to clean */
1966 if (-EAGAIN == err || -ENODATA == err)
1967 break;
1968 }
1969
1970
1971 /* On EAGAIN, hit quota so have more work to do, restart once
1972 * cleanup is complete.
1973 * Else, are we already rnr? then pay attention!!! this ensures that
1974 * the state machine progression never allows a start with a
1975 * partially cleaned list, avoiding a race between hardware
1976 * and rx_to_clean when in NAPI mode */
1977 if (-EAGAIN != err && RU_SUSPENDED == nic->ru_running)
1978 restart_required = 1;
1979
1980 old_before_last_rx = nic->rx_to_use->prev->prev;
1981 old_before_last_rfd = (struct rfd *)old_before_last_rx->skb->data;
1982
1983 /* Alloc new skbs to refill list */
1984 for (rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
1985 if (unlikely(e100_rx_alloc_skb(nic, rx)))
1986 break; /* Better luck next time (see watchdog) */
1987 }
1988
1989 new_before_last_rx = nic->rx_to_use->prev->prev;
1990 if (new_before_last_rx != old_before_last_rx) {
1991 /* Set the el-bit on the buffer that is before the last buffer.
1992 * This lets us update the next pointer on the last buffer
1993 * without worrying about hardware touching it.
1994 * We set the size to 0 to prevent hardware from touching this
1995 * buffer.
1996 * When the hardware hits the before last buffer with el-bit
1997 * and size of 0, it will RNR interrupt, the RUS will go into
1998 * the No Resources state. It will not complete nor write to
1999 * this buffer. */
2000 new_before_last_rfd =
2001 (struct rfd *)new_before_last_rx->skb->data;
2002 new_before_last_rfd->size = 0;
2003 new_before_last_rfd->command |= cpu_to_le16(cb_el);
2004 pci_dma_sync_single_for_device(nic->pdev,
2005 new_before_last_rx->dma_addr, sizeof(struct rfd),
2006 PCI_DMA_BIDIRECTIONAL);
2007
2008 /* Now that we have a new stopping point, we can clear the old
2009 * stopping point. We must sync twice to get the proper
2010 * ordering on the hardware side of things. */
2011 old_before_last_rfd->command &= ~cpu_to_le16(cb_el);
2012 pci_dma_sync_single_for_device(nic->pdev,
2013 old_before_last_rx->dma_addr, sizeof(struct rfd),
2014 PCI_DMA_BIDIRECTIONAL);
2015 old_before_last_rfd->size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
2016 pci_dma_sync_single_for_device(nic->pdev,
2017 old_before_last_rx->dma_addr, sizeof(struct rfd),
2018 PCI_DMA_BIDIRECTIONAL);
2019 }
2020
2021 if (restart_required) {
2022 // ack the rnr?
2023 iowrite8(stat_ack_rnr, &nic->csr->scb.stat_ack);
2024 e100_start_receiver(nic, nic->rx_to_clean);
2025 if (work_done)
2026 (*work_done)++;
2027 }
2028 }
2029
2030 static void e100_rx_clean_list(struct nic *nic)
2031 {
2032 struct rx *rx;
2033 unsigned int i, count = nic->params.rfds.count;
2034
2035 nic->ru_running = RU_UNINITIALIZED;
2036
2037 if (nic->rxs) {
2038 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2039 if (rx->skb) {
2040 pci_unmap_single(nic->pdev, rx->dma_addr,
2041 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
2042 dev_kfree_skb(rx->skb);
2043 }
2044 }
2045 kfree(nic->rxs);
2046 nic->rxs = NULL;
2047 }
2048
2049 nic->rx_to_use = nic->rx_to_clean = NULL;
2050 }
2051
2052 static int e100_rx_alloc_list(struct nic *nic)
2053 {
2054 struct rx *rx;
2055 unsigned int i, count = nic->params.rfds.count;
2056 struct rfd *before_last;
2057
2058 nic->rx_to_use = nic->rx_to_clean = NULL;
2059 nic->ru_running = RU_UNINITIALIZED;
2060
2061 if (!(nic->rxs = kcalloc(count, sizeof(struct rx), GFP_ATOMIC)))
2062 return -ENOMEM;
2063
2064 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2065 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
2066 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
2067 if (e100_rx_alloc_skb(nic, rx)) {
2068 e100_rx_clean_list(nic);
2069 return -ENOMEM;
2070 }
2071 }
2072 /* Set the el-bit on the buffer that is before the last buffer.
2073 * This lets us update the next pointer on the last buffer without
2074 * worrying about hardware touching it.
2075 * We set the size to 0 to prevent hardware from touching this buffer.
2076 * When the hardware hits the before last buffer with el-bit and size
2077 * of 0, it will RNR interrupt, the RU will go into the No Resources
2078 * state. It will not complete nor write to this buffer. */
2079 rx = nic->rxs->prev->prev;
2080 before_last = (struct rfd *)rx->skb->data;
2081 before_last->command |= cpu_to_le16(cb_el);
2082 before_last->size = 0;
2083 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
2084 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
2085
2086 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
2087 nic->ru_running = RU_SUSPENDED;
2088
2089 return 0;
2090 }
2091
2092 static irqreturn_t e100_intr(int irq, void *dev_id)
2093 {
2094 struct net_device *netdev = dev_id;
2095 struct nic *nic = netdev_priv(netdev);
2096 u8 stat_ack = ioread8(&nic->csr->scb.stat_ack);
2097
2098 DPRINTK(INTR, DEBUG, "stat_ack = 0x%02X\n", stat_ack);
2099
2100 if (stat_ack == stat_ack_not_ours || /* Not our interrupt */
2101 stat_ack == stat_ack_not_present) /* Hardware is ejected */
2102 return IRQ_NONE;
2103
2104 /* Ack interrupt(s) */
2105 iowrite8(stat_ack, &nic->csr->scb.stat_ack);
2106
2107 /* We hit Receive No Resource (RNR); restart RU after cleaning */
2108 if (stat_ack & stat_ack_rnr)
2109 nic->ru_running = RU_SUSPENDED;
2110
2111 if (likely(napi_schedule_prep(&nic->napi))) {
2112 e100_disable_irq(nic);
2113 __napi_schedule(&nic->napi);
2114 }
2115
2116 return IRQ_HANDLED;
2117 }
2118
2119 static int e100_poll(struct napi_struct *napi, int budget)
2120 {
2121 struct nic *nic = container_of(napi, struct nic, napi);
2122 unsigned int work_done = 0;
2123
2124 e100_rx_clean(nic, &work_done, budget);
2125 e100_tx_clean(nic);
2126
2127 /* If budget not fully consumed, exit the polling mode */
2128 if (work_done < budget) {
2129 napi_complete(napi);
2130 e100_enable_irq(nic);
2131 }
2132
2133 return work_done;
2134 }
2135
2136 #ifdef CONFIG_NET_POLL_CONTROLLER
2137 static void e100_netpoll(struct net_device *netdev)
2138 {
2139 struct nic *nic = netdev_priv(netdev);
2140
2141 e100_disable_irq(nic);
2142 e100_intr(nic->pdev->irq, netdev);
2143 e100_tx_clean(nic);
2144 e100_enable_irq(nic);
2145 }
2146 #endif
2147
2148 static int e100_set_mac_address(struct net_device *netdev, void *p)
2149 {
2150 struct nic *nic = netdev_priv(netdev);
2151 struct sockaddr *addr = p;
2152
2153 if (!is_valid_ether_addr(addr->sa_data))
2154 return -EADDRNOTAVAIL;
2155
2156 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2157 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
2158
2159 return 0;
2160 }
2161
2162 static int e100_change_mtu(struct net_device *netdev, int new_mtu)
2163 {
2164 if (new_mtu < ETH_ZLEN || new_mtu > ETH_DATA_LEN)
2165 return -EINVAL;
2166 netdev->mtu = new_mtu;
2167 return 0;
2168 }
2169
2170 static int e100_asf(struct nic *nic)
2171 {
2172 /* ASF can be enabled from eeprom */
2173 return((nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
2174 (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
2175 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
2176 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE));
2177 }
2178
2179 static int e100_up(struct nic *nic)
2180 {
2181 int err;
2182
2183 if ((err = e100_rx_alloc_list(nic)))
2184 return err;
2185 if ((err = e100_alloc_cbs(nic)))
2186 goto err_rx_clean_list;
2187 if ((err = e100_hw_init(nic)))
2188 goto err_clean_cbs;
2189 e100_set_multicast_list(nic->netdev);
2190 e100_start_receiver(nic, NULL);
2191 mod_timer(&nic->watchdog, jiffies);
2192 if ((err = request_irq(nic->pdev->irq, e100_intr, IRQF_SHARED,
2193 nic->netdev->name, nic->netdev)))
2194 goto err_no_irq;
2195 netif_wake_queue(nic->netdev);
2196 napi_enable(&nic->napi);
2197 /* enable ints _after_ enabling poll, preventing a race between
2198 * disable ints+schedule */
2199 e100_enable_irq(nic);
2200 return 0;
2201
2202 err_no_irq:
2203 del_timer_sync(&nic->watchdog);
2204 err_clean_cbs:
2205 e100_clean_cbs(nic);
2206 err_rx_clean_list:
2207 e100_rx_clean_list(nic);
2208 return err;
2209 }
2210
2211 static void e100_down(struct nic *nic)
2212 {
2213 /* wait here for poll to complete */
2214 napi_disable(&nic->napi);
2215 netif_stop_queue(nic->netdev);
2216 e100_hw_reset(nic);
2217 free_irq(nic->pdev->irq, nic->netdev);
2218 del_timer_sync(&nic->watchdog);
2219 netif_carrier_off(nic->netdev);
2220 e100_clean_cbs(nic);
2221 e100_rx_clean_list(nic);
2222 }
2223
2224 static void e100_tx_timeout(struct net_device *netdev)
2225 {
2226 struct nic *nic = netdev_priv(netdev);
2227
2228 /* Reset outside of interrupt context, to avoid request_irq
2229 * in interrupt context */
2230 schedule_work(&nic->tx_timeout_task);
2231 }
2232
2233 static void e100_tx_timeout_task(struct work_struct *work)
2234 {
2235 struct nic *nic = container_of(work, struct nic, tx_timeout_task);
2236 struct net_device *netdev = nic->netdev;
2237
2238 DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n",
2239 ioread8(&nic->csr->scb.status));
2240 e100_down(netdev_priv(netdev));
2241 e100_up(netdev_priv(netdev));
2242 }
2243
2244 static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
2245 {
2246 int err;
2247 struct sk_buff *skb;
2248
2249 /* Use driver resources to perform internal MAC or PHY
2250 * loopback test. A single packet is prepared and transmitted
2251 * in loopback mode, and the test passes if the received
2252 * packet compares byte-for-byte to the transmitted packet. */
2253
2254 if ((err = e100_rx_alloc_list(nic)))
2255 return err;
2256 if ((err = e100_alloc_cbs(nic)))
2257 goto err_clean_rx;
2258
2259 /* ICH PHY loopback is broken so do MAC loopback instead */
2260 if (nic->flags & ich && loopback_mode == lb_phy)
2261 loopback_mode = lb_mac;
2262
2263 nic->loopback = loopback_mode;
2264 if ((err = e100_hw_init(nic)))
2265 goto err_loopback_none;
2266
2267 if (loopback_mode == lb_phy)
2268 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
2269 BMCR_LOOPBACK);
2270
2271 e100_start_receiver(nic, NULL);
2272
2273 if (!(skb = netdev_alloc_skb(nic->netdev, ETH_DATA_LEN))) {
2274 err = -ENOMEM;
2275 goto err_loopback_none;
2276 }
2277 skb_put(skb, ETH_DATA_LEN);
2278 memset(skb->data, 0xFF, ETH_DATA_LEN);
2279 e100_xmit_frame(skb, nic->netdev);
2280
2281 msleep(10);
2282
2283 pci_dma_sync_single_for_cpu(nic->pdev, nic->rx_to_clean->dma_addr,
2284 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
2285
2286 if (memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
2287 skb->data, ETH_DATA_LEN))
2288 err = -EAGAIN;
2289
2290 err_loopback_none:
2291 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
2292 nic->loopback = lb_none;
2293 e100_clean_cbs(nic);
2294 e100_hw_reset(nic);
2295 err_clean_rx:
2296 e100_rx_clean_list(nic);
2297 return err;
2298 }
2299
2300 #define MII_LED_CONTROL 0x1B
2301 #define E100_82552_LED_OVERRIDE 0x19
2302 #define E100_82552_LED_ON 0x000F /* LEDTX and LED_RX both on */
2303 #define E100_82552_LED_OFF 0x000A /* LEDTX and LED_RX both off */
2304 static void e100_blink_led(unsigned long data)
2305 {
2306 struct nic *nic = (struct nic *)data;
2307 enum led_state {
2308 led_on = 0x01,
2309 led_off = 0x04,
2310 led_on_559 = 0x05,
2311 led_on_557 = 0x07,
2312 };
2313 u16 led_reg = MII_LED_CONTROL;
2314
2315 if (nic->phy == phy_82552_v) {
2316 led_reg = E100_82552_LED_OVERRIDE;
2317
2318 nic->leds = (nic->leds == E100_82552_LED_ON) ?
2319 E100_82552_LED_OFF : E100_82552_LED_ON;
2320 } else {
2321 nic->leds = (nic->leds & led_on) ? led_off :
2322 (nic->mac < mac_82559_D101M) ? led_on_557 :
2323 led_on_559;
2324 }
2325 mdio_write(nic->netdev, nic->mii.phy_id, led_reg, nic->leds);
2326 mod_timer(&nic->blink_timer, jiffies + HZ / 4);
2327 }
2328
2329 static int e100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2330 {
2331 struct nic *nic = netdev_priv(netdev);
2332 return mii_ethtool_gset(&nic->mii, cmd);
2333 }
2334
2335 static int e100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2336 {
2337 struct nic *nic = netdev_priv(netdev);
2338 int err;
2339
2340 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
2341 err = mii_ethtool_sset(&nic->mii, cmd);
2342 e100_exec_cb(nic, NULL, e100_configure);
2343
2344 return err;
2345 }
2346
2347 static void e100_get_drvinfo(struct net_device *netdev,
2348 struct ethtool_drvinfo *info)
2349 {
2350 struct nic *nic = netdev_priv(netdev);
2351 strcpy(info->driver, DRV_NAME);
2352 strcpy(info->version, DRV_VERSION);
2353 strcpy(info->fw_version, "N/A");
2354 strcpy(info->bus_info, pci_name(nic->pdev));
2355 }
2356
2357 #define E100_PHY_REGS 0x1C
2358 static int e100_get_regs_len(struct net_device *netdev)
2359 {
2360 struct nic *nic = netdev_priv(netdev);
2361 return 1 + E100_PHY_REGS + sizeof(nic->mem->dump_buf);
2362 }
2363
2364 static void e100_get_regs(struct net_device *netdev,
2365 struct ethtool_regs *regs, void *p)
2366 {
2367 struct nic *nic = netdev_priv(netdev);
2368 u32 *buff = p;
2369 int i;
2370
2371 regs->version = (1 << 24) | nic->pdev->revision;
2372 buff[0] = ioread8(&nic->csr->scb.cmd_hi) << 24 |
2373 ioread8(&nic->csr->scb.cmd_lo) << 16 |
2374 ioread16(&nic->csr->scb.status);
2375 for (i = E100_PHY_REGS; i >= 0; i--)
2376 buff[1 + E100_PHY_REGS - i] =
2377 mdio_read(netdev, nic->mii.phy_id, i);
2378 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
2379 e100_exec_cb(nic, NULL, e100_dump);
2380 msleep(10);
2381 memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
2382 sizeof(nic->mem->dump_buf));
2383 }
2384
2385 static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2386 {
2387 struct nic *nic = netdev_priv(netdev);
2388 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
2389 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
2390 }
2391
2392 static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2393 {
2394 struct nic *nic = netdev_priv(netdev);
2395
2396 if ((wol->wolopts && wol->wolopts != WAKE_MAGIC) ||
2397 !device_can_wakeup(&nic->pdev->dev))
2398 return -EOPNOTSUPP;
2399
2400 if (wol->wolopts)
2401 nic->flags |= wol_magic;
2402 else
2403 nic->flags &= ~wol_magic;
2404
2405 device_set_wakeup_enable(&nic->pdev->dev, wol->wolopts);
2406
2407 e100_exec_cb(nic, NULL, e100_configure);
2408
2409 return 0;
2410 }
2411
2412 static u32 e100_get_msglevel(struct net_device *netdev)
2413 {
2414 struct nic *nic = netdev_priv(netdev);
2415 return nic->msg_enable;
2416 }
2417
2418 static void e100_set_msglevel(struct net_device *netdev, u32 value)
2419 {
2420 struct nic *nic = netdev_priv(netdev);
2421 nic->msg_enable = value;
2422 }
2423
2424 static int e100_nway_reset(struct net_device *netdev)
2425 {
2426 struct nic *nic = netdev_priv(netdev);
2427 return mii_nway_restart(&nic->mii);
2428 }
2429
2430 static u32 e100_get_link(struct net_device *netdev)
2431 {
2432 struct nic *nic = netdev_priv(netdev);
2433 return mii_link_ok(&nic->mii);
2434 }
2435
2436 static int e100_get_eeprom_len(struct net_device *netdev)
2437 {
2438 struct nic *nic = netdev_priv(netdev);
2439 return nic->eeprom_wc << 1;
2440 }
2441
2442 #define E100_EEPROM_MAGIC 0x1234
2443 static int e100_get_eeprom(struct net_device *netdev,
2444 struct ethtool_eeprom *eeprom, u8 *bytes)
2445 {
2446 struct nic *nic = netdev_priv(netdev);
2447
2448 eeprom->magic = E100_EEPROM_MAGIC;
2449 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
2450
2451 return 0;
2452 }
2453
2454 static int e100_set_eeprom(struct net_device *netdev,
2455 struct ethtool_eeprom *eeprom, u8 *bytes)
2456 {
2457 struct nic *nic = netdev_priv(netdev);
2458
2459 if (eeprom->magic != E100_EEPROM_MAGIC)
2460 return -EINVAL;
2461
2462 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
2463
2464 return e100_eeprom_save(nic, eeprom->offset >> 1,
2465 (eeprom->len >> 1) + 1);
2466 }
2467
2468 static void e100_get_ringparam(struct net_device *netdev,
2469 struct ethtool_ringparam *ring)
2470 {
2471 struct nic *nic = netdev_priv(netdev);
2472 struct param_range *rfds = &nic->params.rfds;
2473 struct param_range *cbs = &nic->params.cbs;
2474
2475 ring->rx_max_pending = rfds->max;
2476 ring->tx_max_pending = cbs->max;
2477 ring->rx_mini_max_pending = 0;
2478 ring->rx_jumbo_max_pending = 0;
2479 ring->rx_pending = rfds->count;
2480 ring->tx_pending = cbs->count;
2481 ring->rx_mini_pending = 0;
2482 ring->rx_jumbo_pending = 0;
2483 }
2484
2485 static int e100_set_ringparam(struct net_device *netdev,
2486 struct ethtool_ringparam *ring)
2487 {
2488 struct nic *nic = netdev_priv(netdev);
2489 struct param_range *rfds = &nic->params.rfds;
2490 struct param_range *cbs = &nic->params.cbs;
2491
2492 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2493 return -EINVAL;
2494
2495 if (netif_running(netdev))
2496 e100_down(nic);
2497 rfds->count = max(ring->rx_pending, rfds->min);
2498 rfds->count = min(rfds->count, rfds->max);
2499 cbs->count = max(ring->tx_pending, cbs->min);
2500 cbs->count = min(cbs->count, cbs->max);
2501 DPRINTK(DRV, INFO, "Ring Param settings: rx: %d, tx %d\n",
2502 rfds->count, cbs->count);
2503 if (netif_running(netdev))
2504 e100_up(nic);
2505
2506 return 0;
2507 }
2508
2509 static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
2510 "Link test (on/offline)",
2511 "Eeprom test (on/offline)",
2512 "Self test (offline)",
2513 "Mac loopback (offline)",
2514 "Phy loopback (offline)",
2515 };
2516 #define E100_TEST_LEN ARRAY_SIZE(e100_gstrings_test)
2517
2518 static void e100_diag_test(struct net_device *netdev,
2519 struct ethtool_test *test, u64 *data)
2520 {
2521 struct ethtool_cmd cmd;
2522 struct nic *nic = netdev_priv(netdev);
2523 int i, err;
2524
2525 memset(data, 0, E100_TEST_LEN * sizeof(u64));
2526 data[0] = !mii_link_ok(&nic->mii);
2527 data[1] = e100_eeprom_load(nic);
2528 if (test->flags & ETH_TEST_FL_OFFLINE) {
2529
2530 /* save speed, duplex & autoneg settings */
2531 err = mii_ethtool_gset(&nic->mii, &cmd);
2532
2533 if (netif_running(netdev))
2534 e100_down(nic);
2535 data[2] = e100_self_test(nic);
2536 data[3] = e100_loopback_test(nic, lb_mac);
2537 data[4] = e100_loopback_test(nic, lb_phy);
2538
2539 /* restore speed, duplex & autoneg settings */
2540 err = mii_ethtool_sset(&nic->mii, &cmd);
2541
2542 if (netif_running(netdev))
2543 e100_up(nic);
2544 }
2545 for (i = 0; i < E100_TEST_LEN; i++)
2546 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
2547
2548 msleep_interruptible(4 * 1000);
2549 }
2550
2551 static int e100_phys_id(struct net_device *netdev, u32 data)
2552 {
2553 struct nic *nic = netdev_priv(netdev);
2554 u16 led_reg = (nic->phy == phy_82552_v) ? E100_82552_LED_OVERRIDE :
2555 MII_LED_CONTROL;
2556
2557 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
2558 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
2559 mod_timer(&nic->blink_timer, jiffies);
2560 msleep_interruptible(data * 1000);
2561 del_timer_sync(&nic->blink_timer);
2562 mdio_write(netdev, nic->mii.phy_id, led_reg, 0);
2563
2564 return 0;
2565 }
2566
2567 static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2568 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2569 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2570 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2571 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2572 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2573 "tx_heartbeat_errors", "tx_window_errors",
2574 /* device-specific stats */
2575 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2576 "tx_flow_control_pause", "rx_flow_control_pause",
2577 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2578 };
2579 #define E100_NET_STATS_LEN 21
2580 #define E100_STATS_LEN ARRAY_SIZE(e100_gstrings_stats)
2581
2582 static int e100_get_sset_count(struct net_device *netdev, int sset)
2583 {
2584 switch (sset) {
2585 case ETH_SS_TEST:
2586 return E100_TEST_LEN;
2587 case ETH_SS_STATS:
2588 return E100_STATS_LEN;
2589 default:
2590 return -EOPNOTSUPP;
2591 }
2592 }
2593
2594 static void e100_get_ethtool_stats(struct net_device *netdev,
2595 struct ethtool_stats *stats, u64 *data)
2596 {
2597 struct nic *nic = netdev_priv(netdev);
2598 int i;
2599
2600 for (i = 0; i < E100_NET_STATS_LEN; i++)
2601 data[i] = ((unsigned long *)&netdev->stats)[i];
2602
2603 data[i++] = nic->tx_deferred;
2604 data[i++] = nic->tx_single_collisions;
2605 data[i++] = nic->tx_multiple_collisions;
2606 data[i++] = nic->tx_fc_pause;
2607 data[i++] = nic->rx_fc_pause;
2608 data[i++] = nic->rx_fc_unsupported;
2609 data[i++] = nic->tx_tco_frames;
2610 data[i++] = nic->rx_tco_frames;
2611 }
2612
2613 static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2614 {
2615 switch (stringset) {
2616 case ETH_SS_TEST:
2617 memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
2618 break;
2619 case ETH_SS_STATS:
2620 memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
2621 break;
2622 }
2623 }
2624
2625 static const struct ethtool_ops e100_ethtool_ops = {
2626 .get_settings = e100_get_settings,
2627 .set_settings = e100_set_settings,
2628 .get_drvinfo = e100_get_drvinfo,
2629 .get_regs_len = e100_get_regs_len,
2630 .get_regs = e100_get_regs,
2631 .get_wol = e100_get_wol,
2632 .set_wol = e100_set_wol,
2633 .get_msglevel = e100_get_msglevel,
2634 .set_msglevel = e100_set_msglevel,
2635 .nway_reset = e100_nway_reset,
2636 .get_link = e100_get_link,
2637 .get_eeprom_len = e100_get_eeprom_len,
2638 .get_eeprom = e100_get_eeprom,
2639 .set_eeprom = e100_set_eeprom,
2640 .get_ringparam = e100_get_ringparam,
2641 .set_ringparam = e100_set_ringparam,
2642 .self_test = e100_diag_test,
2643 .get_strings = e100_get_strings,
2644 .phys_id = e100_phys_id,
2645 .get_ethtool_stats = e100_get_ethtool_stats,
2646 .get_sset_count = e100_get_sset_count,
2647 };
2648
2649 static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2650 {
2651 struct nic *nic = netdev_priv(netdev);
2652
2653 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2654 }
2655
2656 static int e100_alloc(struct nic *nic)
2657 {
2658 nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
2659 &nic->dma_addr);
2660 return nic->mem ? 0 : -ENOMEM;
2661 }
2662
2663 static void e100_free(struct nic *nic)
2664 {
2665 if (nic->mem) {
2666 pci_free_consistent(nic->pdev, sizeof(struct mem),
2667 nic->mem, nic->dma_addr);
2668 nic->mem = NULL;
2669 }
2670 }
2671
2672 static int e100_open(struct net_device *netdev)
2673 {
2674 struct nic *nic = netdev_priv(netdev);
2675 int err = 0;
2676
2677 netif_carrier_off(netdev);
2678 if ((err = e100_up(nic)))
2679 DPRINTK(IFUP, ERR, "Cannot open interface, aborting.\n");
2680 return err;
2681 }
2682
2683 static int e100_close(struct net_device *netdev)
2684 {
2685 e100_down(netdev_priv(netdev));
2686 return 0;
2687 }
2688
2689 static const struct net_device_ops e100_netdev_ops = {
2690 .ndo_open = e100_open,
2691 .ndo_stop = e100_close,
2692 .ndo_start_xmit = e100_xmit_frame,
2693 .ndo_validate_addr = eth_validate_addr,
2694 .ndo_set_multicast_list = e100_set_multicast_list,
2695 .ndo_set_mac_address = e100_set_mac_address,
2696 .ndo_change_mtu = e100_change_mtu,
2697 .ndo_do_ioctl = e100_do_ioctl,
2698 .ndo_tx_timeout = e100_tx_timeout,
2699 #ifdef CONFIG_NET_POLL_CONTROLLER
2700 .ndo_poll_controller = e100_netpoll,
2701 #endif
2702 };
2703
2704 static int __devinit e100_probe(struct pci_dev *pdev,
2705 const struct pci_device_id *ent)
2706 {
2707 struct net_device *netdev;
2708 struct nic *nic;
2709 int err;
2710
2711 if (!(netdev = alloc_etherdev(sizeof(struct nic)))) {
2712 if (((1 << debug) - 1) & NETIF_MSG_PROBE)
2713 printk(KERN_ERR PFX "Etherdev alloc failed, abort.\n");
2714 return -ENOMEM;
2715 }
2716
2717 netdev->netdev_ops = &e100_netdev_ops;
2718 SET_ETHTOOL_OPS(netdev, &e100_ethtool_ops);
2719 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
2720 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2721
2722 nic = netdev_priv(netdev);
2723 netif_napi_add(netdev, &nic->napi, e100_poll, E100_NAPI_WEIGHT);
2724 nic->netdev = netdev;
2725 nic->pdev = pdev;
2726 nic->msg_enable = (1 << debug) - 1;
2727 nic->mdio_ctrl = mdio_ctrl_hw;
2728 pci_set_drvdata(pdev, netdev);
2729
2730 if ((err = pci_enable_device(pdev))) {
2731 DPRINTK(PROBE, ERR, "Cannot enable PCI device, aborting.\n");
2732 goto err_out_free_dev;
2733 }
2734
2735 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2736 DPRINTK(PROBE, ERR, "Cannot find proper PCI device "
2737 "base address, aborting.\n");
2738 err = -ENODEV;
2739 goto err_out_disable_pdev;
2740 }
2741
2742 if ((err = pci_request_regions(pdev, DRV_NAME))) {
2743 DPRINTK(PROBE, ERR, "Cannot obtain PCI resources, aborting.\n");
2744 goto err_out_disable_pdev;
2745 }
2746
2747 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
2748 DPRINTK(PROBE, ERR, "No usable DMA configuration, aborting.\n");
2749 goto err_out_free_res;
2750 }
2751
2752 SET_NETDEV_DEV(netdev, &pdev->dev);
2753
2754 if (use_io)
2755 DPRINTK(PROBE, INFO, "using i/o access mode\n");
2756
2757 nic->csr = pci_iomap(pdev, (use_io ? 1 : 0), sizeof(struct csr));
2758 if (!nic->csr) {
2759 DPRINTK(PROBE, ERR, "Cannot map device registers, aborting.\n");
2760 err = -ENOMEM;
2761 goto err_out_free_res;
2762 }
2763
2764 if (ent->driver_data)
2765 nic->flags |= ich;
2766 else
2767 nic->flags &= ~ich;
2768
2769 e100_get_defaults(nic);
2770
2771 /* locks must be initialized before calling hw_reset */
2772 spin_lock_init(&nic->cb_lock);
2773 spin_lock_init(&nic->cmd_lock);
2774 spin_lock_init(&nic->mdio_lock);
2775
2776 /* Reset the device before pci_set_master() in case device is in some
2777 * funky state and has an interrupt pending - hint: we don't have the
2778 * interrupt handler registered yet. */
2779 e100_hw_reset(nic);
2780
2781 pci_set_master(pdev);
2782
2783 init_timer(&nic->watchdog);
2784 nic->watchdog.function = e100_watchdog;
2785 nic->watchdog.data = (unsigned long)nic;
2786 init_timer(&nic->blink_timer);
2787 nic->blink_timer.function = e100_blink_led;
2788 nic->blink_timer.data = (unsigned long)nic;
2789
2790 INIT_WORK(&nic->tx_timeout_task, e100_tx_timeout_task);
2791
2792 if ((err = e100_alloc(nic))) {
2793 DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n");
2794 goto err_out_iounmap;
2795 }
2796
2797 if ((err = e100_eeprom_load(nic)))
2798 goto err_out_free;
2799
2800 e100_phy_init(nic);
2801
2802 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
2803 memcpy(netdev->perm_addr, nic->eeprom, ETH_ALEN);
2804 if (!is_valid_ether_addr(netdev->perm_addr)) {
2805 if (!eeprom_bad_csum_allow) {
2806 DPRINTK(PROBE, ERR, "Invalid MAC address from "
2807 "EEPROM, aborting.\n");
2808 err = -EAGAIN;
2809 goto err_out_free;
2810 } else {
2811 DPRINTK(PROBE, ERR, "Invalid MAC address from EEPROM, "
2812 "you MUST configure one.\n");
2813 }
2814 }
2815
2816 /* Wol magic packet can be enabled from eeprom */
2817 if ((nic->mac >= mac_82558_D101_A4) &&
2818 (nic->eeprom[eeprom_id] & eeprom_id_wol)) {
2819 nic->flags |= wol_magic;
2820 device_set_wakeup_enable(&pdev->dev, true);
2821 }
2822
2823 /* ack any pending wake events, disable PME */
2824 pci_pme_active(pdev, false);
2825
2826 strcpy(netdev->name, "eth%d");
2827 if ((err = register_netdev(netdev))) {
2828 DPRINTK(PROBE, ERR, "Cannot register net device, aborting.\n");
2829 goto err_out_free;
2830 }
2831
2832 DPRINTK(PROBE, INFO, "addr 0x%llx, irq %d, MAC addr %pM\n",
2833 (unsigned long long)pci_resource_start(pdev, use_io ? 1 : 0),
2834 pdev->irq, netdev->dev_addr);
2835
2836 return 0;
2837
2838 err_out_free:
2839 e100_free(nic);
2840 err_out_iounmap:
2841 pci_iounmap(pdev, nic->csr);
2842 err_out_free_res:
2843 pci_release_regions(pdev);
2844 err_out_disable_pdev:
2845 pci_disable_device(pdev);
2846 err_out_free_dev:
2847 pci_set_drvdata(pdev, NULL);
2848 free_netdev(netdev);
2849 return err;
2850 }
2851
2852 static void __devexit e100_remove(struct pci_dev *pdev)
2853 {
2854 struct net_device *netdev = pci_get_drvdata(pdev);
2855
2856 if (netdev) {
2857 struct nic *nic = netdev_priv(netdev);
2858 unregister_netdev(netdev);
2859 e100_free(nic);
2860 pci_iounmap(pdev, nic->csr);
2861 free_netdev(netdev);
2862 pci_release_regions(pdev);
2863 pci_disable_device(pdev);
2864 pci_set_drvdata(pdev, NULL);
2865 }
2866 }
2867
2868 #define E100_82552_SMARTSPEED 0x14 /* SmartSpeed Ctrl register */
2869 #define E100_82552_REV_ANEG 0x0200 /* Reverse auto-negotiation */
2870 #define E100_82552_ANEG_NOW 0x0400 /* Auto-negotiate now */
2871 static void __e100_shutdown(struct pci_dev *pdev, bool *enable_wake)
2872 {
2873 struct net_device *netdev = pci_get_drvdata(pdev);
2874 struct nic *nic = netdev_priv(netdev);
2875
2876 if (netif_running(netdev))
2877 e100_down(nic);
2878 netif_device_detach(netdev);
2879
2880 pci_save_state(pdev);
2881
2882 if ((nic->flags & wol_magic) | e100_asf(nic)) {
2883 /* enable reverse auto-negotiation */
2884 if (nic->phy == phy_82552_v) {
2885 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
2886 E100_82552_SMARTSPEED);
2887
2888 mdio_write(netdev, nic->mii.phy_id,
2889 E100_82552_SMARTSPEED, smartspeed |
2890 E100_82552_REV_ANEG | E100_82552_ANEG_NOW);
2891 }
2892 *enable_wake = true;
2893 } else {
2894 *enable_wake = false;
2895 }
2896
2897 pci_disable_device(pdev);
2898 }
2899
2900 static int __e100_power_off(struct pci_dev *pdev, bool wake)
2901 {
2902 if (wake)
2903 return pci_prepare_to_sleep(pdev);
2904
2905 pci_wake_from_d3(pdev, false);
2906 pci_set_power_state(pdev, PCI_D3hot);
2907
2908 return 0;
2909 }
2910
2911 #ifdef CONFIG_PM
2912 static int e100_suspend(struct pci_dev *pdev, pm_message_t state)
2913 {
2914 bool wake;
2915 __e100_shutdown(pdev, &wake);
2916 return __e100_power_off(pdev, wake);
2917 }
2918
2919 static int e100_resume(struct pci_dev *pdev)
2920 {
2921 struct net_device *netdev = pci_get_drvdata(pdev);
2922 struct nic *nic = netdev_priv(netdev);
2923
2924 pci_set_power_state(pdev, PCI_D0);
2925 pci_restore_state(pdev);
2926 /* ack any pending wake events, disable PME */
2927 pci_enable_wake(pdev, 0, 0);
2928
2929 /* disable reverse auto-negotiation */
2930 if (nic->phy == phy_82552_v) {
2931 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
2932 E100_82552_SMARTSPEED);
2933
2934 mdio_write(netdev, nic->mii.phy_id,
2935 E100_82552_SMARTSPEED,
2936 smartspeed & ~(E100_82552_REV_ANEG));
2937 }
2938
2939 netif_device_attach(netdev);
2940 if (netif_running(netdev))
2941 e100_up(nic);
2942
2943 return 0;
2944 }
2945 #endif /* CONFIG_PM */
2946
2947 static void e100_shutdown(struct pci_dev *pdev)
2948 {
2949 bool wake;
2950 __e100_shutdown(pdev, &wake);
2951 if (system_state == SYSTEM_POWER_OFF)
2952 __e100_power_off(pdev, wake);
2953 }
2954
2955 /* ------------------ PCI Error Recovery infrastructure -------------- */
2956 /**
2957 * e100_io_error_detected - called when PCI error is detected.
2958 * @pdev: Pointer to PCI device
2959 * @state: The current pci connection state
2960 */
2961 static pci_ers_result_t e100_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
2962 {
2963 struct net_device *netdev = pci_get_drvdata(pdev);
2964 struct nic *nic = netdev_priv(netdev);
2965
2966 netif_device_detach(netdev);
2967
2968 if (state == pci_channel_io_perm_failure)
2969 return PCI_ERS_RESULT_DISCONNECT;
2970
2971 if (netif_running(netdev))
2972 e100_down(nic);
2973 pci_disable_device(pdev);
2974
2975 /* Request a slot reset. */
2976 return PCI_ERS_RESULT_NEED_RESET;
2977 }
2978
2979 /**
2980 * e100_io_slot_reset - called after the pci bus has been reset.
2981 * @pdev: Pointer to PCI device
2982 *
2983 * Restart the card from scratch.
2984 */
2985 static pci_ers_result_t e100_io_slot_reset(struct pci_dev *pdev)
2986 {
2987 struct net_device *netdev = pci_get_drvdata(pdev);
2988 struct nic *nic = netdev_priv(netdev);
2989
2990 if (pci_enable_device(pdev)) {
2991 printk(KERN_ERR "e100: Cannot re-enable PCI device after reset.\n");
2992 return PCI_ERS_RESULT_DISCONNECT;
2993 }
2994 pci_set_master(pdev);
2995
2996 /* Only one device per card can do a reset */
2997 if (0 != PCI_FUNC(pdev->devfn))
2998 return PCI_ERS_RESULT_RECOVERED;
2999 e100_hw_reset(nic);
3000 e100_phy_init(nic);
3001
3002 return PCI_ERS_RESULT_RECOVERED;
3003 }
3004
3005 /**
3006 * e100_io_resume - resume normal operations
3007 * @pdev: Pointer to PCI device
3008 *
3009 * Resume normal operations after an error recovery
3010 * sequence has been completed.
3011 */
3012 static void e100_io_resume(struct pci_dev *pdev)
3013 {
3014 struct net_device *netdev = pci_get_drvdata(pdev);
3015 struct nic *nic = netdev_priv(netdev);
3016
3017 /* ack any pending wake events, disable PME */
3018 pci_enable_wake(pdev, 0, 0);
3019
3020 netif_device_attach(netdev);
3021 if (netif_running(netdev)) {
3022 e100_open(netdev);
3023 mod_timer(&nic->watchdog, jiffies);
3024 }
3025 }
3026
3027 static struct pci_error_handlers e100_err_handler = {
3028 .error_detected = e100_io_error_detected,
3029 .slot_reset = e100_io_slot_reset,
3030 .resume = e100_io_resume,
3031 };
3032
3033 static struct pci_driver e100_driver = {
3034 .name = DRV_NAME,
3035 .id_table = e100_id_table,
3036 .probe = e100_probe,
3037 .remove = __devexit_p(e100_remove),
3038 #ifdef CONFIG_PM
3039 /* Power Management hooks */
3040 .suspend = e100_suspend,
3041 .resume = e100_resume,
3042 #endif
3043 .shutdown = e100_shutdown,
3044 .err_handler = &e100_err_handler,
3045 };
3046
3047 static int __init e100_init_module(void)
3048 {
3049 if (((1 << debug) - 1) & NETIF_MSG_DRV) {
3050 printk(KERN_INFO PFX "%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
3051 printk(KERN_INFO PFX "%s\n", DRV_COPYRIGHT);
3052 }
3053 return pci_register_driver(&e100_driver);
3054 }
3055
3056 static void __exit e100_cleanup_module(void)
3057 {
3058 pci_unregister_driver(&e100_driver);
3059 }
3060
3061 module_init(e100_init_module);
3062 module_exit(e100_cleanup_module);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree