drivers/net/igb/igb.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28
  29 /* Linux PRO/1000 Ethernet Driver main header file */
  30
  31 #ifndef _IGB_H_
  32 #define _IGB_H_
  33
  34 #include "e1000_mac.h"
  35 #include "e1000_82575.h"
  36
  37 struct igb_adapter;
  38
  39 /* Interrupt defines */
  40 #define IGB_MIN_DYN_ITR 3000
  41 #define IGB_MAX_DYN_ITR 96000
  42
  43 /* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
  44 #define IGB_START_ITR 648
  45
  46 #define IGB_DYN_ITR_PACKET_THRESHOLD 2
  47 #define IGB_DYN_ITR_LENGTH_LOW 200
  48 #define IGB_DYN_ITR_LENGTH_HIGH 1000
  49
  50 /* TX/RX descriptor defines */
  51 #define IGB_DEFAULT_TXD                  256
  52 #define IGB_MIN_TXD                       80
  53 #define IGB_MAX_TXD                     4096
  54
  55 #define IGB_DEFAULT_RXD                  256
  56 #define IGB_MIN_RXD                       80
  57 #define IGB_MAX_RXD                     4096
  58
  59 #define IGB_DEFAULT_ITR                    3 /* dynamic */
  60 #define IGB_MAX_ITR_USECS              10000
  61 #define IGB_MIN_ITR_USECS                 10
  62
  63 /* Transmit and receive queues */
  64 #define IGB_MAX_RX_QUEUES                  4
  65 #define IGB_MAX_TX_QUEUES                  4
  66
  67 /* RX descriptor control thresholds.
  68  * PTHRESH - MAC will consider prefetch if it has fewer than this number of
  69  *           descriptors available in its onboard memory.
  70  *           Setting this to 0 disables RX descriptor prefetch.
  71  * HTHRESH - MAC will only prefetch if there are at least this many descriptors
  72  *           available in host memory.
  73  *           If PTHRESH is 0, this should also be 0.
  74  * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
  75  *           descriptors until either it has this many to write back, or the
  76  *           ITR timer expires.
  77  */
  78 #define IGB_RX_PTHRESH                    16
  79 #define IGB_RX_HTHRESH                     8
  80 #define IGB_RX_WTHRESH                     1
  81
  82 /* this is the size past which hardware will drop packets when setting LPE=0 */
  83 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
  84
  85 /* Supported Rx Buffer Sizes */
  86 #define IGB_RXBUFFER_128   128    /* Used for packet split */
  87 #define IGB_RXBUFFER_256   256    /* Used for packet split */
  88 #define IGB_RXBUFFER_512   512
  89 #define IGB_RXBUFFER_1024  1024
  90 #define IGB_RXBUFFER_2048  2048
  91 #define IGB_RXBUFFER_4096  4096
  92 #define IGB_RXBUFFER_8192  8192
  93 #define IGB_RXBUFFER_16384 16384
  94
  95 /* Packet Buffer allocations */
  96
  97
  98 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
  99 #define IGB_TX_QUEUE_WAKE       16
 100 /* How many Rx Buffers do we bundle into one write to the hardware ? */
 101 #define IGB_RX_BUFFER_WRITE     16      /* Must be power of 2 */
 102
 103 #define AUTO_ALL_MODES            0
 104 #define IGB_EEPROM_APME         0x0400
 105
 106 #ifndef IGB_MASTER_SLAVE
 107 /* Switch to override PHY master/slave setting */
 108 #define IGB_MASTER_SLAVE        e1000_ms_hw_default
 109 #endif
 110
 111 #define IGB_MNG_VLAN_NONE -1
 112
 113 /* wrapper around a pointer to a socket buffer,
 114  * so a DMA handle can be stored along with the buffer */
 115 struct igb_buffer {
 116         struct sk_buff *skb;
 117         dma_addr_t dma;
 118         union {
 119                 /* TX */
 120                 struct {
 121                         unsigned long time_stamp;
 122                         u16 length;
 123                         u16 next_to_watch;
 124                 };
 125                 /* RX */
 126                 struct {
 127                         struct page *page;
 128                         u64 page_dma;
 129                         unsigned int page_offset;
 130                 };
 131         };
 132 };
 133
 134 struct igb_queue_stats {
 135         u64 packets;
 136         u64 bytes;
 137 };
 138
 139 struct igb_ring {
 140         struct igb_adapter *adapter; /* backlink */
 141         void *desc;                  /* descriptor ring memory */
 142         dma_addr_t dma;              /* phys address of the ring */
 143         unsigned int size;           /* length of desc. ring in bytes */
 144         unsigned int count;          /* number of desc. in the ring */
 145         u16 next_to_use;
 146         u16 next_to_clean;
 147         u16 head;
 148         u16 tail;
 149         struct igb_buffer *buffer_info; /* array of buffer info structs */
 150
 151         u32 eims_value;
 152         u32 itr_val;
 153         u16 itr_register;
 154         u16 cpu;
 155
 156         u16 queue_index;
 157         u16 reg_idx;
 158         unsigned int total_bytes;
 159         unsigned int total_packets;
 160
 161         union {
 162                 /* TX */
 163                 struct {
 164                         struct igb_queue_stats tx_stats;
 165                         bool detect_tx_hung;
 166                 };
 167                 /* RX */
 168                 struct {
 169                         struct igb_queue_stats rx_stats;
 170                         struct napi_struct napi;
 171                         int set_itr;
 172                         struct igb_ring *buddy;
 173                 };
 174         };
 175
 176         char name[IFNAMSIZ + 5];
 177 };
 178
 179 #define IGB_DESC_UNUSED(R) \
 180         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 181         (R)->next_to_clean - (R)->next_to_use - 1)
 182
 183 #define E1000_RX_DESC_ADV(R, i)     \
 184         (&(((union e1000_adv_rx_desc *)((R).desc))[i]))
 185 #define E1000_TX_DESC_ADV(R, i)     \
 186         (&(((union e1000_adv_tx_desc *)((R).desc))[i]))
 187 #define E1000_TX_CTXTDESC_ADV(R, i)         \
 188         (&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
 189 #define E1000_GET_DESC(R, i, type)      (&(((struct type *)((R).desc))[i]))
 190 #define E1000_TX_DESC(R, i)             E1000_GET_DESC(R, i, e1000_tx_desc)
 191 #define E1000_RX_DESC(R, i)             E1000_GET_DESC(R, i, e1000_rx_desc)
 192
 193 /* board specific private data structure */
 194
 195 struct igb_adapter {
 196         struct timer_list watchdog_timer;
 197         struct timer_list phy_info_timer;
 198         struct vlan_group *vlgrp;
 199         u16 mng_vlan_id;
 200         u32 bd_number;
 201         u32 rx_buffer_len;
 202         u32 wol;
 203         u32 en_mng_pt;
 204         u16 link_speed;
 205         u16 link_duplex;
 206         unsigned int total_tx_bytes;
 207         unsigned int total_tx_packets;
 208         unsigned int total_rx_bytes;
 209         unsigned int total_rx_packets;
 210         /* Interrupt Throttle Rate */
 211         u32 itr;
 212         u32 itr_setting;
 213         u16 tx_itr;
 214         u16 rx_itr;
 215
 216         struct work_struct reset_task;
 217         struct work_struct watchdog_task;
 218         bool fc_autoneg;
 219         u8  tx_timeout_factor;
 220         struct timer_list blink_timer;
 221         unsigned long led_status;
 222
 223         /* TX */
 224         struct igb_ring *tx_ring;      /* One per active queue */
 225         unsigned int restart_queue;
 226         unsigned long tx_queue_len;
 227         u32 txd_cmd;
 228         u32 gotc;
 229         u64 gotc_old;
 230         u64 tpt_old;
 231         u64 colc_old;
 232         u32 tx_timeout_count;
 233
 234         /* RX */
 235         struct igb_ring *rx_ring;      /* One per active queue */
 236         int num_tx_queues;
 237         int num_rx_queues;
 238
 239         u64 hw_csum_err;
 240         u64 hw_csum_good;
 241         u32 alloc_rx_buff_failed;
 242         bool rx_csum;
 243         u32 gorc;
 244         u64 gorc_old;
 245         u16 rx_ps_hdr_size;
 246         u32 max_frame_size;
 247         u32 min_frame_size;
 248
 249         /* OS defined structs */
 250         struct net_device *netdev;
 251         struct napi_struct napi;
 252         struct pci_dev *pdev;
 253         struct net_device_stats net_stats;
 254
 255         /* structs defined in e1000_hw.h */
 256         struct e1000_hw hw;
 257         struct e1000_hw_stats stats;
 258         struct e1000_phy_info phy_info;
 259         struct e1000_phy_stats phy_stats;
 260
 261         u32 test_icr;
 262         struct igb_ring test_tx_ring;
 263         struct igb_ring test_rx_ring;
 264
 265         int msg_enable;
 266         struct msix_entry *msix_entries;
 267         u32 eims_enable_mask;
 268         u32 eims_other;
 269
 270         /* to not mess up cache alignment, always add to the bottom */
 271         unsigned long state;
 272         unsigned int flags;
 273         u32 eeprom_wol;
 274
 275         struct igb_ring *multi_tx_table[IGB_MAX_TX_QUEUES];
 276         unsigned int tx_ring_count;
 277         unsigned int rx_ring_count;
 278 };
 279
 280 #define IGB_FLAG_HAS_MSI           (1 << 0)
 281 #define IGB_FLAG_MSI_ENABLE        (1 << 1)
 282 #define IGB_FLAG_DCA_ENABLED       (1 << 2)
 283 #define IGB_FLAG_QUAD_PORT_A       (1 << 3)
 284 #define IGB_FLAG_NEED_CTX_IDX      (1 << 4)
 285
 286 enum e1000_state_t {
 287         __IGB_TESTING,
 288         __IGB_RESETTING,
 289         __IGB_DOWN
 290 };
 291
 292 enum igb_boards {
 293         board_82575,
 294 };
 295
 296 extern char igb_driver_name[];
 297 extern char igb_driver_version[];
 298
 299 extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
 300 extern int igb_up(struct igb_adapter *);
 301 extern void igb_down(struct igb_adapter *);
 302 extern void igb_reinit_locked(struct igb_adapter *);
 303 extern void igb_reset(struct igb_adapter *);
 304 extern int igb_set_spd_dplx(struct igb_adapter *, u16);
 305 extern int igb_setup_tx_resources(struct igb_adapter *, struct igb_ring *);
 306 extern int igb_setup_rx_resources(struct igb_adapter *, struct igb_ring *);
 307 extern void igb_free_tx_resources(struct igb_ring *);
 308 extern void igb_free_rx_resources(struct igb_ring *);
 309 extern void igb_update_stats(struct igb_adapter *);
 310 extern void igb_set_ethtool_ops(struct net_device *);
 311
 312 static inline s32 igb_reset_phy(struct e1000_hw *hw)
 313 {
 314         if (hw->phy.ops.reset)
 315                 return hw->phy.ops.reset(hw);
 316
 317         return 0;
 318 }
 319
 320 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
 321 {
 322         if (hw->phy.ops.read_reg)
 323                 return hw->phy.ops.read_reg(hw, offset, data);
 324
 325         return 0;
 326 }
 327
 328 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
 329 {
 330         if (hw->phy.ops.write_reg)
 331                 return hw->phy.ops.write_reg(hw, offset, data);
 332
 333         return 0;
 334 }
 335
 336 static inline s32 igb_get_phy_info(struct e1000_hw *hw)
 337 {
 338         if (hw->phy.ops.get_phy_info)
 339                 return hw->phy.ops.get_phy_info(hw);
 340
 341         return 0;
 342 }
 343
 344 #endif /* _IGB_H_ */