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usb: musb: Fix a bug by making suspend interrupt available in device mode
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / usb / musb / musb_core.c
blob4531eae0e0101bc4925fa4a188af4142f51f6ad2
1 /*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 /*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82 /*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101
102 #ifdef CONFIG_ARM
103 #include <mach/hardware.h>
104 #include <mach/memory.h>
105 #include <asm/mach-types.h>
106 #endif
107
108 #include "musb_core.h"
109
110
111 #ifdef CONFIG_ARCH_DAVINCI
112 #include "davinci.h"
113 #endif
114
115 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
116
117
118 unsigned musb_debug;
119 module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR);
120 MODULE_PARM_DESC(debug, "Debug message level. Default = 0");
121
122 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
123 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
124
125 #define MUSB_VERSION "6.0"
126
127 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
128
129 #define MUSB_DRIVER_NAME "musb_hdrc"
130 const char musb_driver_name[] = MUSB_DRIVER_NAME;
131
132 MODULE_DESCRIPTION(DRIVER_INFO);
133 MODULE_AUTHOR(DRIVER_AUTHOR);
134 MODULE_LICENSE("GPL");
135 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
136
137
138 /*-------------------------------------------------------------------------*/
139
140 static inline struct musb *dev_to_musb(struct device *dev)
141 {
142 #ifdef CONFIG_USB_MUSB_HDRC_HCD
143 /* usbcore insists dev->driver_data is a "struct hcd *" */
144 return hcd_to_musb(dev_get_drvdata(dev));
145 #else
146 return dev_get_drvdata(dev);
147 #endif
148 }
149
150 /*-------------------------------------------------------------------------*/
151
152 #if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN)
153
154 /*
155 * Load an endpoint's FIFO
156 */
157 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
158 {
159 void __iomem *fifo = hw_ep->fifo;
160
161 prefetch((u8 *)src);
162
163 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
164 'T', hw_ep->epnum, fifo, len, src);
165
166 /* we can't assume unaligned reads work */
167 if (likely((0x01 & (unsigned long) src) == 0)) {
168 u16 index = 0;
169
170 /* best case is 32bit-aligned source address */
171 if ((0x02 & (unsigned long) src) == 0) {
172 if (len >= 4) {
173 writesl(fifo, src + index, len >> 2);
174 index += len & ~0x03;
175 }
176 if (len & 0x02) {
177 musb_writew(fifo, 0, *(u16 *)&src[index]);
178 index += 2;
179 }
180 } else {
181 if (len >= 2) {
182 writesw(fifo, src + index, len >> 1);
183 index += len & ~0x01;
184 }
185 }
186 if (len & 0x01)
187 musb_writeb(fifo, 0, src[index]);
188 } else {
189 /* byte aligned */
190 writesb(fifo, src, len);
191 }
192 }
193
194 /*
195 * Unload an endpoint's FIFO
196 */
197 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
198 {
199 void __iomem *fifo = hw_ep->fifo;
200
201 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
202 'R', hw_ep->epnum, fifo, len, dst);
203
204 /* we can't assume unaligned writes work */
205 if (likely((0x01 & (unsigned long) dst) == 0)) {
206 u16 index = 0;
207
208 /* best case is 32bit-aligned destination address */
209 if ((0x02 & (unsigned long) dst) == 0) {
210 if (len >= 4) {
211 readsl(fifo, dst, len >> 2);
212 index = len & ~0x03;
213 }
214 if (len & 0x02) {
215 *(u16 *)&dst[index] = musb_readw(fifo, 0);
216 index += 2;
217 }
218 } else {
219 if (len >= 2) {
220 readsw(fifo, dst, len >> 1);
221 index = len & ~0x01;
222 }
223 }
224 if (len & 0x01)
225 dst[index] = musb_readb(fifo, 0);
226 } else {
227 /* byte aligned */
228 readsb(fifo, dst, len);
229 }
230 }
231
232 #endif /* normal PIO */
233
234
235 /*-------------------------------------------------------------------------*/
236
237 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
238 static const u8 musb_test_packet[53] = {
239 /* implicit SYNC then DATA0 to start */
240
241 /* JKJKJKJK x9 */
242 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
243 /* JJKKJJKK x8 */
244 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
245 /* JJJJKKKK x8 */
246 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
247 /* JJJJJJJKKKKKKK x8 */
248 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
249 /* JJJJJJJK x8 */
250 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
251 /* JKKKKKKK x10, JK */
252 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
253
254 /* implicit CRC16 then EOP to end */
255 };
256
257 void musb_load_testpacket(struct musb *musb)
258 {
259 void __iomem *regs = musb->endpoints[0].regs;
260
261 musb_ep_select(musb->mregs, 0);
262 musb_write_fifo(musb->control_ep,
263 sizeof(musb_test_packet), musb_test_packet);
264 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
265 }
266
267 /*-------------------------------------------------------------------------*/
268
269 const char *otg_state_string(struct musb *musb)
270 {
271 switch (musb->xceiv->state) {
272 case OTG_STATE_A_IDLE: return "a_idle";
273 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
274 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
275 case OTG_STATE_A_HOST: return "a_host";
276 case OTG_STATE_A_SUSPEND: return "a_suspend";
277 case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
278 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
279 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
280 case OTG_STATE_B_IDLE: return "b_idle";
281 case OTG_STATE_B_SRP_INIT: return "b_srp_init";
282 case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
283 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
284 case OTG_STATE_B_HOST: return "b_host";
285 default: return "UNDEFINED";
286 }
287 }
288
289 #ifdef CONFIG_USB_MUSB_OTG
290
291 /*
292 * Handles OTG hnp timeouts, such as b_ase0_brst
293 */
294 void musb_otg_timer_func(unsigned long data)
295 {
296 struct musb *musb = (struct musb *)data;
297 unsigned long flags;
298
299 spin_lock_irqsave(&musb->lock, flags);
300 switch (musb->xceiv->state) {
301 case OTG_STATE_B_WAIT_ACON:
302 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
303 musb_g_disconnect(musb);
304 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
305 musb->is_active = 0;
306 break;
307 case OTG_STATE_A_SUSPEND:
308 case OTG_STATE_A_WAIT_BCON:
309 DBG(1, "HNP: %s timeout\n", otg_state_string(musb));
310 musb_set_vbus(musb, 0);
311 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
312 break;
313 default:
314 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
315 }
316 musb->ignore_disconnect = 0;
317 spin_unlock_irqrestore(&musb->lock, flags);
318 }
319
320 /*
321 * Stops the HNP transition. Caller must take care of locking.
322 */
323 void musb_hnp_stop(struct musb *musb)
324 {
325 struct usb_hcd *hcd = musb_to_hcd(musb);
326 void __iomem *mbase = musb->mregs;
327 u8 reg;
328
329 DBG(1, "HNP: stop from %s\n", otg_state_string(musb));
330
331 switch (musb->xceiv->state) {
332 case OTG_STATE_A_PERIPHERAL:
333 musb_g_disconnect(musb);
334 DBG(1, "HNP: back to %s\n", otg_state_string(musb));
335 break;
336 case OTG_STATE_B_HOST:
337 DBG(1, "HNP: Disabling HR\n");
338 hcd->self.is_b_host = 0;
339 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
340 MUSB_DEV_MODE(musb);
341 reg = musb_readb(mbase, MUSB_POWER);
342 reg |= MUSB_POWER_SUSPENDM;
343 musb_writeb(mbase, MUSB_POWER, reg);
344 /* REVISIT: Start SESSION_REQUEST here? */
345 break;
346 default:
347 DBG(1, "HNP: Stopping in unknown state %s\n",
348 otg_state_string(musb));
349 }
350
351 /*
352 * When returning to A state after HNP, avoid hub_port_rebounce(),
353 * which cause occasional OPT A "Did not receive reset after connect"
354 * errors.
355 */
356 musb->port1_status &=
357 ~(1 << USB_PORT_FEAT_C_CONNECTION);
358 }
359
360 #endif
361
362 /*
363 * Interrupt Service Routine to record USB "global" interrupts.
364 * Since these do not happen often and signify things of
365 * paramount importance, it seems OK to check them individually;
366 * the order of the tests is specified in the manual
367 *
368 * @param musb instance pointer
369 * @param int_usb register contents
370 * @param devctl
371 * @param power
372 */
373
374 #define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \
375 | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \
376 | MUSB_INTR_RESET)
377
378 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
379 u8 devctl, u8 power)
380 {
381 irqreturn_t handled = IRQ_NONE;
382
383 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
384 int_usb);
385
386 /* in host mode, the peripheral may issue remote wakeup.
387 * in peripheral mode, the host may resume the link.
388 * spurious RESUME irqs happen too, paired with SUSPEND.
389 */
390 if (int_usb & MUSB_INTR_RESUME) {
391 handled = IRQ_HANDLED;
392 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
393
394 if (devctl & MUSB_DEVCTL_HM) {
395 #ifdef CONFIG_USB_MUSB_HDRC_HCD
396 void __iomem *mbase = musb->mregs;
397
398 switch (musb->xceiv->state) {
399 case OTG_STATE_A_SUSPEND:
400 /* remote wakeup? later, GetPortStatus
401 * will stop RESUME signaling
402 */
403
404 if (power & MUSB_POWER_SUSPENDM) {
405 /* spurious */
406 musb->int_usb &= ~MUSB_INTR_SUSPEND;
407 DBG(2, "Spurious SUSPENDM\n");
408 break;
409 }
410
411 power &= ~MUSB_POWER_SUSPENDM;
412 musb_writeb(mbase, MUSB_POWER,
413 power | MUSB_POWER_RESUME);
414
415 musb->port1_status |=
416 (USB_PORT_STAT_C_SUSPEND << 16)
417 | MUSB_PORT_STAT_RESUME;
418 musb->rh_timer = jiffies
419 + msecs_to_jiffies(20);
420
421 musb->xceiv->state = OTG_STATE_A_HOST;
422 musb->is_active = 1;
423 usb_hcd_resume_root_hub(musb_to_hcd(musb));
424 break;
425 case OTG_STATE_B_WAIT_ACON:
426 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
427 musb->is_active = 1;
428 MUSB_DEV_MODE(musb);
429 break;
430 default:
431 WARNING("bogus %s RESUME (%s)\n",
432 "host",
433 otg_state_string(musb));
434 }
435 #endif
436 } else {
437 switch (musb->xceiv->state) {
438 #ifdef CONFIG_USB_MUSB_HDRC_HCD
439 case OTG_STATE_A_SUSPEND:
440 /* possibly DISCONNECT is upcoming */
441 musb->xceiv->state = OTG_STATE_A_HOST;
442 usb_hcd_resume_root_hub(musb_to_hcd(musb));
443 break;
444 #endif
445 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
446 case OTG_STATE_B_WAIT_ACON:
447 case OTG_STATE_B_PERIPHERAL:
448 /* disconnect while suspended? we may
449 * not get a disconnect irq...
450 */
451 if ((devctl & MUSB_DEVCTL_VBUS)
452 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
453 ) {
454 musb->int_usb |= MUSB_INTR_DISCONNECT;
455 musb->int_usb &= ~MUSB_INTR_SUSPEND;
456 break;
457 }
458 musb_g_resume(musb);
459 break;
460 case OTG_STATE_B_IDLE:
461 musb->int_usb &= ~MUSB_INTR_SUSPEND;
462 break;
463 #endif
464 default:
465 WARNING("bogus %s RESUME (%s)\n",
466 "peripheral",
467 otg_state_string(musb));
468 }
469 }
470 }
471
472 #ifdef CONFIG_USB_MUSB_HDRC_HCD
473 /* see manual for the order of the tests */
474 if (int_usb & MUSB_INTR_SESSREQ) {
475 void __iomem *mbase = musb->mregs;
476
477 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
478
479 /* IRQ arrives from ID pin sense or (later, if VBUS power
480 * is removed) SRP. responses are time critical:
481 * - turn on VBUS (with silicon-specific mechanism)
482 * - go through A_WAIT_VRISE
483 * - ... to A_WAIT_BCON.
484 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
485 */
486 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
487 musb->ep0_stage = MUSB_EP0_START;
488 musb->xceiv->state = OTG_STATE_A_IDLE;
489 MUSB_HST_MODE(musb);
490 musb_set_vbus(musb, 1);
491
492 handled = IRQ_HANDLED;
493 }
494
495 if (int_usb & MUSB_INTR_VBUSERROR) {
496 int ignore = 0;
497
498 /* During connection as an A-Device, we may see a short
499 * current spikes causing voltage drop, because of cable
500 * and peripheral capacitance combined with vbus draw.
501 * (So: less common with truly self-powered devices, where
502 * vbus doesn't act like a power supply.)
503 *
504 * Such spikes are short; usually less than ~500 usec, max
505 * of ~2 msec. That is, they're not sustained overcurrent
506 * errors, though they're reported using VBUSERROR irqs.
507 *
508 * Workarounds: (a) hardware: use self powered devices.
509 * (b) software: ignore non-repeated VBUS errors.
510 *
511 * REVISIT: do delays from lots of DEBUG_KERNEL checks
512 * make trouble here, keeping VBUS < 4.4V ?
513 */
514 switch (musb->xceiv->state) {
515 case OTG_STATE_A_HOST:
516 /* recovery is dicey once we've gotten past the
517 * initial stages of enumeration, but if VBUS
518 * stayed ok at the other end of the link, and
519 * another reset is due (at least for high speed,
520 * to redo the chirp etc), it might work OK...
521 */
522 case OTG_STATE_A_WAIT_BCON:
523 case OTG_STATE_A_WAIT_VRISE:
524 if (musb->vbuserr_retry) {
525 void __iomem *mbase = musb->mregs;
526
527 musb->vbuserr_retry--;
528 ignore = 1;
529 devctl |= MUSB_DEVCTL_SESSION;
530 musb_writeb(mbase, MUSB_DEVCTL, devctl);
531 } else {
532 musb->port1_status |=
533 (1 << USB_PORT_FEAT_OVER_CURRENT)
534 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
535 }
536 break;
537 default:
538 break;
539 }
540
541 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
542 otg_state_string(musb),
543 devctl,
544 ({ char *s;
545 switch (devctl & MUSB_DEVCTL_VBUS) {
546 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
547 s = "<SessEnd"; break;
548 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
549 s = "<AValid"; break;
550 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
551 s = "<VBusValid"; break;
552 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
553 default:
554 s = "VALID"; break;
555 }; s; }),
556 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
557 musb->port1_status);
558
559 /* go through A_WAIT_VFALL then start a new session */
560 if (!ignore)
561 musb_set_vbus(musb, 0);
562 handled = IRQ_HANDLED;
563 }
564
565 #endif
566 if (int_usb & MUSB_INTR_SUSPEND) {
567 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
568 otg_state_string(musb), devctl, power);
569 handled = IRQ_HANDLED;
570
571 switch (musb->xceiv->state) {
572 #ifdef CONFIG_USB_MUSB_OTG
573 case OTG_STATE_A_PERIPHERAL:
574 /* We also come here if the cable is removed, since
575 * this silicon doesn't report ID-no-longer-grounded.
576 *
577 * We depend on T(a_wait_bcon) to shut us down, and
578 * hope users don't do anything dicey during this
579 * undesired detour through A_WAIT_BCON.
580 */
581 musb_hnp_stop(musb);
582 usb_hcd_resume_root_hub(musb_to_hcd(musb));
583 musb_root_disconnect(musb);
584 musb_platform_try_idle(musb, jiffies
585 + msecs_to_jiffies(musb->a_wait_bcon
586 ? : OTG_TIME_A_WAIT_BCON));
587
588 break;
589 #endif
590 case OTG_STATE_B_IDLE:
591 if (!musb->is_active)
592 break;
593 case OTG_STATE_B_PERIPHERAL:
594 musb_g_suspend(musb);
595 musb->is_active = is_otg_enabled(musb)
596 && musb->xceiv->gadget->b_hnp_enable;
597 if (musb->is_active) {
598 #ifdef CONFIG_USB_MUSB_OTG
599 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
600 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
601 mod_timer(&musb->otg_timer, jiffies
602 + msecs_to_jiffies(
603 OTG_TIME_B_ASE0_BRST));
604 #endif
605 }
606 break;
607 case OTG_STATE_A_WAIT_BCON:
608 if (musb->a_wait_bcon != 0)
609 musb_platform_try_idle(musb, jiffies
610 + msecs_to_jiffies(musb->a_wait_bcon));
611 break;
612 case OTG_STATE_A_HOST:
613 musb->xceiv->state = OTG_STATE_A_SUSPEND;
614 musb->is_active = is_otg_enabled(musb)
615 && musb->xceiv->host->b_hnp_enable;
616 break;
617 case OTG_STATE_B_HOST:
618 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
619 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
620 break;
621 default:
622 /* "should not happen" */
623 musb->is_active = 0;
624 break;
625 }
626 }
627
628 #ifdef CONFIG_USB_MUSB_HDRC_HCD
629 if (int_usb & MUSB_INTR_CONNECT) {
630 struct usb_hcd *hcd = musb_to_hcd(musb);
631 void __iomem *mbase = musb->mregs;
632
633 handled = IRQ_HANDLED;
634 musb->is_active = 1;
635 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
636
637 musb->ep0_stage = MUSB_EP0_START;
638
639 #ifdef CONFIG_USB_MUSB_OTG
640 /* flush endpoints when transitioning from Device Mode */
641 if (is_peripheral_active(musb)) {
642 /* REVISIT HNP; just force disconnect */
643 }
644 musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
645 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
646 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
647 #endif
648 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
649 |USB_PORT_STAT_HIGH_SPEED
650 |USB_PORT_STAT_ENABLE
651 );
652 musb->port1_status |= USB_PORT_STAT_CONNECTION
653 |(USB_PORT_STAT_C_CONNECTION << 16);
654
655 /* high vs full speed is just a guess until after reset */
656 if (devctl & MUSB_DEVCTL_LSDEV)
657 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
658
659 /* indicate new connection to OTG machine */
660 switch (musb->xceiv->state) {
661 case OTG_STATE_B_PERIPHERAL:
662 if (int_usb & MUSB_INTR_SUSPEND) {
663 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
664 int_usb &= ~MUSB_INTR_SUSPEND;
665 goto b_host;
666 } else
667 DBG(1, "CONNECT as b_peripheral???\n");
668 break;
669 case OTG_STATE_B_WAIT_ACON:
670 DBG(1, "HNP: CONNECT, now b_host\n");
671 b_host:
672 musb->xceiv->state = OTG_STATE_B_HOST;
673 hcd->self.is_b_host = 1;
674 musb->ignore_disconnect = 0;
675 del_timer(&musb->otg_timer);
676 break;
677 default:
678 if ((devctl & MUSB_DEVCTL_VBUS)
679 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
680 musb->xceiv->state = OTG_STATE_A_HOST;
681 hcd->self.is_b_host = 0;
682 }
683 break;
684 }
685
686 /* poke the root hub */
687 MUSB_HST_MODE(musb);
688 if (hcd->status_urb)
689 usb_hcd_poll_rh_status(hcd);
690 else
691 usb_hcd_resume_root_hub(hcd);
692
693 DBG(1, "CONNECT (%s) devctl %02x\n",
694 otg_state_string(musb), devctl);
695 }
696 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
697
698 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
699 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
700 otg_state_string(musb),
701 MUSB_MODE(musb), devctl);
702 handled = IRQ_HANDLED;
703
704 switch (musb->xceiv->state) {
705 #ifdef CONFIG_USB_MUSB_HDRC_HCD
706 case OTG_STATE_A_HOST:
707 case OTG_STATE_A_SUSPEND:
708 usb_hcd_resume_root_hub(musb_to_hcd(musb));
709 musb_root_disconnect(musb);
710 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
711 musb_platform_try_idle(musb, jiffies
712 + msecs_to_jiffies(musb->a_wait_bcon));
713 break;
714 #endif /* HOST */
715 #ifdef CONFIG_USB_MUSB_OTG
716 case OTG_STATE_B_HOST:
717 /* REVISIT this behaves for "real disconnect"
718 * cases; make sure the other transitions from
719 * from B_HOST act right too. The B_HOST code
720 * in hnp_stop() is currently not used...
721 */
722 musb_root_disconnect(musb);
723 musb_to_hcd(musb)->self.is_b_host = 0;
724 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
725 MUSB_DEV_MODE(musb);
726 musb_g_disconnect(musb);
727 break;
728 case OTG_STATE_A_PERIPHERAL:
729 musb_hnp_stop(musb);
730 musb_root_disconnect(musb);
731 /* FALLTHROUGH */
732 case OTG_STATE_B_WAIT_ACON:
733 /* FALLTHROUGH */
734 #endif /* OTG */
735 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
736 case OTG_STATE_B_PERIPHERAL:
737 case OTG_STATE_B_IDLE:
738 musb_g_disconnect(musb);
739 break;
740 #endif /* GADGET */
741 default:
742 WARNING("unhandled DISCONNECT transition (%s)\n",
743 otg_state_string(musb));
744 break;
745 }
746 }
747
748 /* mentor saves a bit: bus reset and babble share the same irq.
749 * only host sees babble; only peripheral sees bus reset.
750 */
751 if (int_usb & MUSB_INTR_RESET) {
752 handled = IRQ_HANDLED;
753 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
754 /*
755 * Looks like non-HS BABBLE can be ignored, but
756 * HS BABBLE is an error condition. For HS the solution
757 * is to avoid babble in the first place and fix what
758 * caused BABBLE. When HS BABBLE happens we can only
759 * stop the session.
760 */
761 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
762 DBG(1, "BABBLE devctl: %02x\n", devctl);
763 else {
764 ERR("Stopping host session -- babble\n");
765 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
766 }
767 } else if (is_peripheral_capable()) {
768 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
769 switch (musb->xceiv->state) {
770 #ifdef CONFIG_USB_OTG
771 case OTG_STATE_A_SUSPEND:
772 /* We need to ignore disconnect on suspend
773 * otherwise tusb 2.0 won't reconnect after a
774 * power cycle, which breaks otg compliance.
775 */
776 musb->ignore_disconnect = 1;
777 musb_g_reset(musb);
778 /* FALLTHROUGH */
779 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
780 /* never use invalid T(a_wait_bcon) */
781 DBG(1, "HNP: in %s, %d msec timeout\n",
782 otg_state_string(musb),
783 TA_WAIT_BCON(musb));
784 mod_timer(&musb->otg_timer, jiffies
785 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
786 break;
787 case OTG_STATE_A_PERIPHERAL:
788 musb->ignore_disconnect = 0;
789 del_timer(&musb->otg_timer);
790 musb_g_reset(musb);
791 break;
792 case OTG_STATE_B_WAIT_ACON:
793 DBG(1, "HNP: RESET (%s), to b_peripheral\n",
794 otg_state_string(musb));
795 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
796 musb_g_reset(musb);
797 break;
798 #endif
799 case OTG_STATE_B_IDLE:
800 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
801 /* FALLTHROUGH */
802 case OTG_STATE_B_PERIPHERAL:
803 musb_g_reset(musb);
804 break;
805 default:
806 DBG(1, "Unhandled BUS RESET as %s\n",
807 otg_state_string(musb));
808 }
809 }
810 }
811
812 #if 0
813 /* REVISIT ... this would be for multiplexing periodic endpoints, or
814 * supporting transfer phasing to prevent exceeding ISO bandwidth
815 * limits of a given frame or microframe.
816 *
817 * It's not needed for peripheral side, which dedicates endpoints;
818 * though it _might_ use SOF irqs for other purposes.
819 *
820 * And it's not currently needed for host side, which also dedicates
821 * endpoints, relies on TX/RX interval registers, and isn't claimed
822 * to support ISO transfers yet.
823 */
824 if (int_usb & MUSB_INTR_SOF) {
825 void __iomem *mbase = musb->mregs;
826 struct musb_hw_ep *ep;
827 u8 epnum;
828 u16 frame;
829
830 DBG(6, "START_OF_FRAME\n");
831 handled = IRQ_HANDLED;
832
833 /* start any periodic Tx transfers waiting for current frame */
834 frame = musb_readw(mbase, MUSB_FRAME);
835 ep = musb->endpoints;
836 for (epnum = 1; (epnum < musb->nr_endpoints)
837 && (musb->epmask >= (1 << epnum));
838 epnum++, ep++) {
839 /*
840 * FIXME handle framecounter wraps (12 bits)
841 * eliminate duplicated StartUrb logic
842 */
843 if (ep->dwWaitFrame >= frame) {
844 ep->dwWaitFrame = 0;
845 pr_debug("SOF --> periodic TX%s on %d\n",
846 ep->tx_channel ? " DMA" : "",
847 epnum);
848 if (!ep->tx_channel)
849 musb_h_tx_start(musb, epnum);
850 else
851 cppi_hostdma_start(musb, epnum);
852 }
853 } /* end of for loop */
854 }
855 #endif
856
857 schedule_work(&musb->irq_work);
858
859 return handled;
860 }
861
862 /*-------------------------------------------------------------------------*/
863
864 /*
865 * Program the HDRC to start (enable interrupts, dma, etc.).
866 */
867 void musb_start(struct musb *musb)
868 {
869 void __iomem *regs = musb->mregs;
870 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
871
872 DBG(2, "<== devctl %02x\n", devctl);
873
874 /* Set INT enable registers, enable interrupts */
875 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
876 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
877 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
878
879 musb_writeb(regs, MUSB_TESTMODE, 0);
880
881 /* put into basic highspeed mode and start session */
882 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
883 | MUSB_POWER_SOFTCONN
884 | MUSB_POWER_HSENAB
885 /* ENSUSPEND wedges tusb */
886 /* | MUSB_POWER_ENSUSPEND */
887 );
888
889 musb->is_active = 0;
890 devctl = musb_readb(regs, MUSB_DEVCTL);
891 devctl &= ~MUSB_DEVCTL_SESSION;
892
893 if (is_otg_enabled(musb)) {
894 /* session started after:
895 * (a) ID-grounded irq, host mode;
896 * (b) vbus present/connect IRQ, peripheral mode;
897 * (c) peripheral initiates, using SRP
898 */
899 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
900 musb->is_active = 1;
901 else
902 devctl |= MUSB_DEVCTL_SESSION;
903
904 } else if (is_host_enabled(musb)) {
905 /* assume ID pin is hard-wired to ground */
906 devctl |= MUSB_DEVCTL_SESSION;
907
908 } else /* peripheral is enabled */ {
909 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
910 musb->is_active = 1;
911 }
912 musb_platform_enable(musb);
913 musb_writeb(regs, MUSB_DEVCTL, devctl);
914 }
915
916
917 static void musb_generic_disable(struct musb *musb)
918 {
919 void __iomem *mbase = musb->mregs;
920 u16 temp;
921
922 /* disable interrupts */
923 musb_writeb(mbase, MUSB_INTRUSBE, 0);
924 musb_writew(mbase, MUSB_INTRTXE, 0);
925 musb_writew(mbase, MUSB_INTRRXE, 0);
926
927 /* off */
928 musb_writeb(mbase, MUSB_DEVCTL, 0);
929
930 /* flush pending interrupts */
931 temp = musb_readb(mbase, MUSB_INTRUSB);
932 temp = musb_readw(mbase, MUSB_INTRTX);
933 temp = musb_readw(mbase, MUSB_INTRRX);
934
935 }
936
937 /*
938 * Make the HDRC stop (disable interrupts, etc.);
939 * reversible by musb_start
940 * called on gadget driver unregister
941 * with controller locked, irqs blocked
942 * acts as a NOP unless some role activated the hardware
943 */
944 void musb_stop(struct musb *musb)
945 {
946 /* stop IRQs, timers, ... */
947 musb_platform_disable(musb);
948 musb_generic_disable(musb);
949 DBG(3, "HDRC disabled\n");
950
951 /* FIXME
952 * - mark host and/or peripheral drivers unusable/inactive
953 * - disable DMA (and enable it in HdrcStart)
954 * - make sure we can musb_start() after musb_stop(); with
955 * OTG mode, gadget driver module rmmod/modprobe cycles that
956 * - ...
957 */
958 musb_platform_try_idle(musb, 0);
959 }
960
961 static void musb_shutdown(struct platform_device *pdev)
962 {
963 struct musb *musb = dev_to_musb(&pdev->dev);
964 unsigned long flags;
965
966 spin_lock_irqsave(&musb->lock, flags);
967 musb_platform_disable(musb);
968 musb_generic_disable(musb);
969 if (musb->clock)
970 clk_put(musb->clock);
971 spin_unlock_irqrestore(&musb->lock, flags);
972
973 /* FIXME power down */
974 }
975
976
977 /*-------------------------------------------------------------------------*/
978
979 /*
980 * The silicon either has hard-wired endpoint configurations, or else
981 * "dynamic fifo" sizing. The driver has support for both, though at this
982 * writing only the dynamic sizing is very well tested. Since we switched
983 * away from compile-time hardware parameters, we can no longer rely on
984 * dead code elimination to leave only the relevant one in the object file.
985 *
986 * We don't currently use dynamic fifo setup capability to do anything
987 * more than selecting one of a bunch of predefined configurations.
988 */
989 #if defined(CONFIG_USB_TUSB6010) || \
990 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
991 static ushort __initdata fifo_mode = 4;
992 #else
993 static ushort __initdata fifo_mode = 2;
994 #endif
995
996 /* "modprobe ... fifo_mode=1" etc */
997 module_param(fifo_mode, ushort, 0);
998 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
999
1000
1001 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
1002 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
1003
1004 struct fifo_cfg {
1005 u8 hw_ep_num;
1006 enum fifo_style style;
1007 enum buf_mode mode;
1008 u16 maxpacket;
1009 };
1010
1011 /*
1012 * tables defining fifo_mode values. define more if you like.
1013 * for host side, make sure both halves of ep1 are set up.
1014 */
1015
1016 /* mode 0 - fits in 2KB */
1017 static struct fifo_cfg __initdata mode_0_cfg[] = {
1018 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1019 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1020 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1021 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1022 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1023 };
1024
1025 /* mode 1 - fits in 4KB */
1026 static struct fifo_cfg __initdata mode_1_cfg[] = {
1027 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1028 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1029 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1030 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1031 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1032 };
1033
1034 /* mode 2 - fits in 4KB */
1035 static struct fifo_cfg __initdata mode_2_cfg[] = {
1036 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1037 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1038 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1039 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1040 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1041 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1042 };
1043
1044 /* mode 3 - fits in 4KB */
1045 static struct fifo_cfg __initdata mode_3_cfg[] = {
1046 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1047 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1048 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1049 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1050 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1051 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1052 };
1053
1054 /* mode 4 - fits in 16KB */
1055 static struct fifo_cfg __initdata mode_4_cfg[] = {
1056 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1057 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1058 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1059 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1060 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1061 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1062 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1063 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1064 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1065 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1066 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1067 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1068 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1069 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1070 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1071 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1072 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1073 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1074 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1075 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1076 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1077 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1078 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1079 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1080 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1081 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1082 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1083 };
1084
1085 /* mode 5 - fits in 8KB */
1086 static struct fifo_cfg __initdata mode_5_cfg[] = {
1087 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1088 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1089 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1090 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1091 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1092 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1093 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1094 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1095 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1096 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1097 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1098 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1099 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1100 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1101 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1102 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1103 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1104 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1105 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1106 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1107 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1108 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1109 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1110 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1111 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1112 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1113 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1114 };
1115
1116 /*
1117 * configure a fifo; for non-shared endpoints, this may be called
1118 * once for a tx fifo and once for an rx fifo.
1119 *
1120 * returns negative errno or offset for next fifo.
1121 */
1122 static int __init
1123 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1124 const struct fifo_cfg *cfg, u16 offset)
1125 {
1126 void __iomem *mbase = musb->mregs;
1127 int size = 0;
1128 u16 maxpacket = cfg->maxpacket;
1129 u16 c_off = offset >> 3;
1130 u8 c_size;
1131
1132 /* expect hw_ep has already been zero-initialized */
1133
1134 size = ffs(max(maxpacket, (u16) 8)) - 1;
1135 maxpacket = 1 << size;
1136
1137 c_size = size - 3;
1138 if (cfg->mode == BUF_DOUBLE) {
1139 if ((offset + (maxpacket << 1)) >
1140 (1 << (musb->config->ram_bits + 2)))
1141 return -EMSGSIZE;
1142 c_size |= MUSB_FIFOSZ_DPB;
1143 } else {
1144 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1145 return -EMSGSIZE;
1146 }
1147
1148 /* configure the FIFO */
1149 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1150
1151 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1152 /* EP0 reserved endpoint for control, bidirectional;
1153 * EP1 reserved for bulk, two unidirection halves.
1154 */
1155 if (hw_ep->epnum == 1)
1156 musb->bulk_ep = hw_ep;
1157 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1158 #endif
1159 switch (cfg->style) {
1160 case FIFO_TX:
1161 musb_write_txfifosz(mbase, c_size);
1162 musb_write_txfifoadd(mbase, c_off);
1163 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1164 hw_ep->max_packet_sz_tx = maxpacket;
1165 break;
1166 case FIFO_RX:
1167 musb_write_rxfifosz(mbase, c_size);
1168 musb_write_rxfifoadd(mbase, c_off);
1169 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1170 hw_ep->max_packet_sz_rx = maxpacket;
1171 break;
1172 case FIFO_RXTX:
1173 musb_write_txfifosz(mbase, c_size);
1174 musb_write_txfifoadd(mbase, c_off);
1175 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1176 hw_ep->max_packet_sz_rx = maxpacket;
1177
1178 musb_write_rxfifosz(mbase, c_size);
1179 musb_write_rxfifoadd(mbase, c_off);
1180 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1181 hw_ep->max_packet_sz_tx = maxpacket;
1182
1183 hw_ep->is_shared_fifo = true;
1184 break;
1185 }
1186
1187 /* NOTE rx and tx endpoint irqs aren't managed separately,
1188 * which happens to be ok
1189 */
1190 musb->epmask |= (1 << hw_ep->epnum);
1191
1192 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1193 }
1194
1195 static struct fifo_cfg __initdata ep0_cfg = {
1196 .style = FIFO_RXTX, .maxpacket = 64,
1197 };
1198
1199 static int __init ep_config_from_table(struct musb *musb)
1200 {
1201 const struct fifo_cfg *cfg;
1202 unsigned i, n;
1203 int offset;
1204 struct musb_hw_ep *hw_ep = musb->endpoints;
1205
1206 switch (fifo_mode) {
1207 default:
1208 fifo_mode = 0;
1209 /* FALLTHROUGH */
1210 case 0:
1211 cfg = mode_0_cfg;
1212 n = ARRAY_SIZE(mode_0_cfg);
1213 break;
1214 case 1:
1215 cfg = mode_1_cfg;
1216 n = ARRAY_SIZE(mode_1_cfg);
1217 break;
1218 case 2:
1219 cfg = mode_2_cfg;
1220 n = ARRAY_SIZE(mode_2_cfg);
1221 break;
1222 case 3:
1223 cfg = mode_3_cfg;
1224 n = ARRAY_SIZE(mode_3_cfg);
1225 break;
1226 case 4:
1227 cfg = mode_4_cfg;
1228 n = ARRAY_SIZE(mode_4_cfg);
1229 break;
1230 case 5:
1231 cfg = mode_5_cfg;
1232 n = ARRAY_SIZE(mode_5_cfg);
1233 break;
1234 }
1235
1236 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1237 musb_driver_name, fifo_mode);
1238
1239
1240 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1241 /* assert(offset > 0) */
1242
1243 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1244 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1245 */
1246
1247 for (i = 0; i < n; i++) {
1248 u8 epn = cfg->hw_ep_num;
1249
1250 if (epn >= musb->config->num_eps) {
1251 pr_debug("%s: invalid ep %d\n",
1252 musb_driver_name, epn);
1253 return -EINVAL;
1254 }
1255 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1256 if (offset < 0) {
1257 pr_debug("%s: mem overrun, ep %d\n",
1258 musb_driver_name, epn);
1259 return -EINVAL;
1260 }
1261 epn++;
1262 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1263 }
1264
1265 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1266 musb_driver_name,
1267 n + 1, musb->config->num_eps * 2 - 1,
1268 offset, (1 << (musb->config->ram_bits + 2)));
1269
1270 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1271 if (!musb->bulk_ep) {
1272 pr_debug("%s: missing bulk\n", musb_driver_name);
1273 return -EINVAL;
1274 }
1275 #endif
1276
1277 return 0;
1278 }
1279
1280
1281 /*
1282 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1283 * @param musb the controller
1284 */
1285 static int __init ep_config_from_hw(struct musb *musb)
1286 {
1287 u8 epnum = 0;
1288 struct musb_hw_ep *hw_ep;
1289 void *mbase = musb->mregs;
1290 int ret = 0;
1291
1292 DBG(2, "<== static silicon ep config\n");
1293
1294 /* FIXME pick up ep0 maxpacket size */
1295
1296 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1297 musb_ep_select(mbase, epnum);
1298 hw_ep = musb->endpoints + epnum;
1299
1300 ret = musb_read_fifosize(musb, hw_ep, epnum);
1301 if (ret < 0)
1302 break;
1303
1304 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1305
1306 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1307 /* pick an RX/TX endpoint for bulk */
1308 if (hw_ep->max_packet_sz_tx < 512
1309 || hw_ep->max_packet_sz_rx < 512)
1310 continue;
1311
1312 /* REVISIT: this algorithm is lazy, we should at least
1313 * try to pick a double buffered endpoint.
1314 */
1315 if (musb->bulk_ep)
1316 continue;
1317 musb->bulk_ep = hw_ep;
1318 #endif
1319 }
1320
1321 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1322 if (!musb->bulk_ep) {
1323 pr_debug("%s: missing bulk\n", musb_driver_name);
1324 return -EINVAL;
1325 }
1326 #endif
1327
1328 return 0;
1329 }
1330
1331 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1332
1333 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1334 * configure endpoints, or take their config from silicon
1335 */
1336 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1337 {
1338 u8 reg;
1339 char *type;
1340 char aInfo[90], aRevision[32], aDate[12];
1341 void __iomem *mbase = musb->mregs;
1342 int status = 0;
1343 int i;
1344
1345 /* log core options (read using indexed model) */
1346 reg = musb_read_configdata(mbase);
1347
1348 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1349 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1350 strcat(aInfo, ", dyn FIFOs");
1351 musb->dyn_fifo = true;
1352 }
1353 if (reg & MUSB_CONFIGDATA_MPRXE) {
1354 strcat(aInfo, ", bulk combine");
1355 musb->bulk_combine = true;
1356 }
1357 if (reg & MUSB_CONFIGDATA_MPTXE) {
1358 strcat(aInfo, ", bulk split");
1359 musb->bulk_split = true;
1360 }
1361 if (reg & MUSB_CONFIGDATA_HBRXE) {
1362 strcat(aInfo, ", HB-ISO Rx");
1363 musb->hb_iso_rx = true;
1364 }
1365 if (reg & MUSB_CONFIGDATA_HBTXE) {
1366 strcat(aInfo, ", HB-ISO Tx");
1367 musb->hb_iso_tx = true;
1368 }
1369 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1370 strcat(aInfo, ", SoftConn");
1371
1372 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1373 musb_driver_name, reg, aInfo);
1374
1375 aDate[0] = 0;
1376 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1377 musb->is_multipoint = 1;
1378 type = "M";
1379 } else {
1380 musb->is_multipoint = 0;
1381 type = "";
1382 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1383 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1384 printk(KERN_ERR
1385 "%s: kernel must blacklist external hubs\n",
1386 musb_driver_name);
1387 #endif
1388 #endif
1389 }
1390
1391 /* log release info */
1392 musb->hwvers = musb_read_hwvers(mbase);
1393 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1394 MUSB_HWVERS_MINOR(musb->hwvers),
1395 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1396 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1397 musb_driver_name, type, aRevision, aDate);
1398
1399 /* configure ep0 */
1400 musb_configure_ep0(musb);
1401
1402 /* discover endpoint configuration */
1403 musb->nr_endpoints = 1;
1404 musb->epmask = 1;
1405
1406 if (musb->dyn_fifo)
1407 status = ep_config_from_table(musb);
1408 else
1409 status = ep_config_from_hw(musb);
1410
1411 if (status < 0)
1412 return status;
1413
1414 /* finish init, and print endpoint config */
1415 for (i = 0; i < musb->nr_endpoints; i++) {
1416 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1417
1418 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1419 #ifdef CONFIG_USB_TUSB6010
1420 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1421 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1422 hw_ep->fifo_sync_va =
1423 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1424
1425 if (i == 0)
1426 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1427 else
1428 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1429 #endif
1430
1431 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1432 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1433 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1434 hw_ep->rx_reinit = 1;
1435 hw_ep->tx_reinit = 1;
1436 #endif
1437
1438 if (hw_ep->max_packet_sz_tx) {
1439 DBG(1,
1440 "%s: hw_ep %d%s, %smax %d\n",
1441 musb_driver_name, i,
1442 hw_ep->is_shared_fifo ? "shared" : "tx",
1443 hw_ep->tx_double_buffered
1444 ? "doublebuffer, " : "",
1445 hw_ep->max_packet_sz_tx);
1446 }
1447 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1448 DBG(1,
1449 "%s: hw_ep %d%s, %smax %d\n",
1450 musb_driver_name, i,
1451 "rx",
1452 hw_ep->rx_double_buffered
1453 ? "doublebuffer, " : "",
1454 hw_ep->max_packet_sz_rx);
1455 }
1456 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1457 DBG(1, "hw_ep %d not configured\n", i);
1458 }
1459
1460 return 0;
1461 }
1462
1463 /*-------------------------------------------------------------------------*/
1464
1465 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
1466
1467 static irqreturn_t generic_interrupt(int irq, void *__hci)
1468 {
1469 unsigned long flags;
1470 irqreturn_t retval = IRQ_NONE;
1471 struct musb *musb = __hci;
1472
1473 spin_lock_irqsave(&musb->lock, flags);
1474
1475 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1476 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1477 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1478
1479 if (musb->int_usb || musb->int_tx || musb->int_rx)
1480 retval = musb_interrupt(musb);
1481
1482 spin_unlock_irqrestore(&musb->lock, flags);
1483
1484 return retval;
1485 }
1486
1487 #else
1488 #define generic_interrupt NULL
1489 #endif
1490
1491 /*
1492 * handle all the irqs defined by the HDRC core. for now we expect: other
1493 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1494 * will be assigned, and the irq will already have been acked.
1495 *
1496 * called in irq context with spinlock held, irqs blocked
1497 */
1498 irqreturn_t musb_interrupt(struct musb *musb)
1499 {
1500 irqreturn_t retval = IRQ_NONE;
1501 u8 devctl, power;
1502 int ep_num;
1503 u32 reg;
1504
1505 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1506 power = musb_readb(musb->mregs, MUSB_POWER);
1507
1508 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1509 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1510 musb->int_usb, musb->int_tx, musb->int_rx);
1511
1512 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1513 if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
1514 if (!musb->gadget_driver) {
1515 DBG(5, "No gadget driver loaded\n");
1516 return IRQ_HANDLED;
1517 }
1518 #endif
1519
1520 /* the core can interrupt us for multiple reasons; docs have
1521 * a generic interrupt flowchart to follow
1522 */
1523 if (musb->int_usb & STAGE0_MASK)
1524 retval |= musb_stage0_irq(musb, musb->int_usb,
1525 devctl, power);
1526
1527 /* "stage 1" is handling endpoint irqs */
1528
1529 /* handle endpoint 0 first */
1530 if (musb->int_tx & 1) {
1531 if (devctl & MUSB_DEVCTL_HM)
1532 retval |= musb_h_ep0_irq(musb);
1533 else
1534 retval |= musb_g_ep0_irq(musb);
1535 }
1536
1537 /* RX on endpoints 1-15 */
1538 reg = musb->int_rx >> 1;
1539 ep_num = 1;
1540 while (reg) {
1541 if (reg & 1) {
1542 /* musb_ep_select(musb->mregs, ep_num); */
1543 /* REVISIT just retval = ep->rx_irq(...) */
1544 retval = IRQ_HANDLED;
1545 if (devctl & MUSB_DEVCTL_HM) {
1546 if (is_host_capable())
1547 musb_host_rx(musb, ep_num);
1548 } else {
1549 if (is_peripheral_capable())
1550 musb_g_rx(musb, ep_num);
1551 }
1552 }
1553
1554 reg >>= 1;
1555 ep_num++;
1556 }
1557
1558 /* TX on endpoints 1-15 */
1559 reg = musb->int_tx >> 1;
1560 ep_num = 1;
1561 while (reg) {
1562 if (reg & 1) {
1563 /* musb_ep_select(musb->mregs, ep_num); */
1564 /* REVISIT just retval |= ep->tx_irq(...) */
1565 retval = IRQ_HANDLED;
1566 if (devctl & MUSB_DEVCTL_HM) {
1567 if (is_host_capable())
1568 musb_host_tx(musb, ep_num);
1569 } else {
1570 if (is_peripheral_capable())
1571 musb_g_tx(musb, ep_num);
1572 }
1573 }
1574 reg >>= 1;
1575 ep_num++;
1576 }
1577
1578 return retval;
1579 }
1580
1581
1582 #ifndef CONFIG_MUSB_PIO_ONLY
1583 static int __initdata use_dma = 1;
1584
1585 /* "modprobe ... use_dma=0" etc */
1586 module_param(use_dma, bool, 0);
1587 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1588
1589 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1590 {
1591 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1592
1593 /* called with controller lock already held */
1594
1595 if (!epnum) {
1596 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1597 if (!is_cppi_enabled()) {
1598 /* endpoint 0 */
1599 if (devctl & MUSB_DEVCTL_HM)
1600 musb_h_ep0_irq(musb);
1601 else
1602 musb_g_ep0_irq(musb);
1603 }
1604 #endif
1605 } else {
1606 /* endpoints 1..15 */
1607 if (transmit) {
1608 if (devctl & MUSB_DEVCTL_HM) {
1609 if (is_host_capable())
1610 musb_host_tx(musb, epnum);
1611 } else {
1612 if (is_peripheral_capable())
1613 musb_g_tx(musb, epnum);
1614 }
1615 } else {
1616 /* receive */
1617 if (devctl & MUSB_DEVCTL_HM) {
1618 if (is_host_capable())
1619 musb_host_rx(musb, epnum);
1620 } else {
1621 if (is_peripheral_capable())
1622 musb_g_rx(musb, epnum);
1623 }
1624 }
1625 }
1626 }
1627
1628 #else
1629 #define use_dma 0
1630 #endif
1631
1632 /*-------------------------------------------------------------------------*/
1633
1634 #ifdef CONFIG_SYSFS
1635
1636 static ssize_t
1637 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1638 {
1639 struct musb *musb = dev_to_musb(dev);
1640 unsigned long flags;
1641 int ret = -EINVAL;
1642
1643 spin_lock_irqsave(&musb->lock, flags);
1644 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1645 spin_unlock_irqrestore(&musb->lock, flags);
1646
1647 return ret;
1648 }
1649
1650 static ssize_t
1651 musb_mode_store(struct device *dev, struct device_attribute *attr,
1652 const char *buf, size_t n)
1653 {
1654 struct musb *musb = dev_to_musb(dev);
1655 unsigned long flags;
1656 int status;
1657
1658 spin_lock_irqsave(&musb->lock, flags);
1659 if (sysfs_streq(buf, "host"))
1660 status = musb_platform_set_mode(musb, MUSB_HOST);
1661 else if (sysfs_streq(buf, "peripheral"))
1662 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1663 else if (sysfs_streq(buf, "otg"))
1664 status = musb_platform_set_mode(musb, MUSB_OTG);
1665 else
1666 status = -EINVAL;
1667 spin_unlock_irqrestore(&musb->lock, flags);
1668
1669 return (status == 0) ? n : status;
1670 }
1671 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1672
1673 static ssize_t
1674 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1675 const char *buf, size_t n)
1676 {
1677 struct musb *musb = dev_to_musb(dev);
1678 unsigned long flags;
1679 unsigned long val;
1680
1681 if (sscanf(buf, "%lu", &val) < 1) {
1682 dev_err(dev, "Invalid VBUS timeout ms value\n");
1683 return -EINVAL;
1684 }
1685
1686 spin_lock_irqsave(&musb->lock, flags);
1687 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1688 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1689 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1690 musb->is_active = 0;
1691 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1692 spin_unlock_irqrestore(&musb->lock, flags);
1693
1694 return n;
1695 }
1696
1697 static ssize_t
1698 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1699 {
1700 struct musb *musb = dev_to_musb(dev);
1701 unsigned long flags;
1702 unsigned long val;
1703 int vbus;
1704
1705 spin_lock_irqsave(&musb->lock, flags);
1706 val = musb->a_wait_bcon;
1707 /* FIXME get_vbus_status() is normally #defined as false...
1708 * and is effectively TUSB-specific.
1709 */
1710 vbus = musb_platform_get_vbus_status(musb);
1711 spin_unlock_irqrestore(&musb->lock, flags);
1712
1713 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1714 vbus ? "on" : "off", val);
1715 }
1716 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1717
1718 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1719
1720 /* Gadget drivers can't know that a host is connected so they might want
1721 * to start SRP, but users can. This allows userspace to trigger SRP.
1722 */
1723 static ssize_t
1724 musb_srp_store(struct device *dev, struct device_attribute *attr,
1725 const char *buf, size_t n)
1726 {
1727 struct musb *musb = dev_to_musb(dev);
1728 unsigned short srp;
1729
1730 if (sscanf(buf, "%hu", &srp) != 1
1731 || (srp != 1)) {
1732 dev_err(dev, "SRP: Value must be 1\n");
1733 return -EINVAL;
1734 }
1735
1736 if (srp == 1)
1737 musb_g_wakeup(musb);
1738
1739 return n;
1740 }
1741 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1742
1743 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1744
1745 static struct attribute *musb_attributes[] = {
1746 &dev_attr_mode.attr,
1747 &dev_attr_vbus.attr,
1748 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1749 &dev_attr_srp.attr,
1750 #endif
1751 NULL
1752 };
1753
1754 static const struct attribute_group musb_attr_group = {
1755 .attrs = musb_attributes,
1756 };
1757
1758 #endif /* sysfs */
1759
1760 /* Only used to provide driver mode change events */
1761 static void musb_irq_work(struct work_struct *data)
1762 {
1763 struct musb *musb = container_of(data, struct musb, irq_work);
1764 static int old_state;
1765
1766 if (musb->xceiv->state != old_state) {
1767 old_state = musb->xceiv->state;
1768 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1769 }
1770 }
1771
1772 /* --------------------------------------------------------------------------
1773 * Init support
1774 */
1775
1776 static struct musb *__init
1777 allocate_instance(struct device *dev,
1778 struct musb_hdrc_config *config, void __iomem *mbase)
1779 {
1780 struct musb *musb;
1781 struct musb_hw_ep *ep;
1782 int epnum;
1783 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1784 struct usb_hcd *hcd;
1785
1786 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1787 if (!hcd)
1788 return NULL;
1789 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1790
1791 musb = hcd_to_musb(hcd);
1792 INIT_LIST_HEAD(&musb->control);
1793 INIT_LIST_HEAD(&musb->in_bulk);
1794 INIT_LIST_HEAD(&musb->out_bulk);
1795
1796 hcd->uses_new_polling = 1;
1797
1798 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1799 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1800 #else
1801 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1802 if (!musb)
1803 return NULL;
1804 dev_set_drvdata(dev, musb);
1805
1806 #endif
1807
1808 musb->mregs = mbase;
1809 musb->ctrl_base = mbase;
1810 musb->nIrq = -ENODEV;
1811 musb->config = config;
1812 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1813 for (epnum = 0, ep = musb->endpoints;
1814 epnum < musb->config->num_eps;
1815 epnum++, ep++) {
1816 ep->musb = musb;
1817 ep->epnum = epnum;
1818 }
1819
1820 musb->controller = dev;
1821 return musb;
1822 }
1823
1824 static void musb_free(struct musb *musb)
1825 {
1826 /* this has multiple entry modes. it handles fault cleanup after
1827 * probe(), where things may be partially set up, as well as rmmod
1828 * cleanup after everything's been de-activated.
1829 */
1830
1831 #ifdef CONFIG_SYSFS
1832 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1833 #endif
1834
1835 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1836 musb_gadget_cleanup(musb);
1837 #endif
1838
1839 if (musb->nIrq >= 0) {
1840 if (musb->irq_wake)
1841 disable_irq_wake(musb->nIrq);
1842 free_irq(musb->nIrq, musb);
1843 }
1844 if (is_dma_capable() && musb->dma_controller) {
1845 struct dma_controller *c = musb->dma_controller;
1846
1847 (void) c->stop(c);
1848 dma_controller_destroy(c);
1849 }
1850
1851 #ifdef CONFIG_USB_MUSB_OTG
1852 put_device(musb->xceiv->dev);
1853 #endif
1854
1855 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1856 usb_put_hcd(musb_to_hcd(musb));
1857 #else
1858 kfree(musb);
1859 #endif
1860 }
1861
1862 /*
1863 * Perform generic per-controller initialization.
1864 *
1865 * @pDevice: the controller (already clocked, etc)
1866 * @nIrq: irq
1867 * @mregs: virtual address of controller registers,
1868 * not yet corrected for platform-specific offsets
1869 */
1870 static int __init
1871 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1872 {
1873 int status;
1874 struct musb *musb;
1875 struct musb_hdrc_platform_data *plat = dev->platform_data;
1876
1877 /* The driver might handle more features than the board; OK.
1878 * Fail when the board needs a feature that's not enabled.
1879 */
1880 if (!plat) {
1881 dev_dbg(dev, "no platform_data?\n");
1882 status = -ENODEV;
1883 goto fail0;
1884 }
1885
1886 switch (plat->mode) {
1887 case MUSB_HOST:
1888 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1889 break;
1890 #else
1891 goto bad_config;
1892 #endif
1893 case MUSB_PERIPHERAL:
1894 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1895 break;
1896 #else
1897 goto bad_config;
1898 #endif
1899 case MUSB_OTG:
1900 #ifdef CONFIG_USB_MUSB_OTG
1901 break;
1902 #else
1903 bad_config:
1904 #endif
1905 default:
1906 dev_err(dev, "incompatible Kconfig role setting\n");
1907 status = -EINVAL;
1908 goto fail0;
1909 }
1910
1911 /* allocate */
1912 musb = allocate_instance(dev, plat->config, ctrl);
1913 if (!musb) {
1914 status = -ENOMEM;
1915 goto fail0;
1916 }
1917
1918 spin_lock_init(&musb->lock);
1919 musb->board_mode = plat->mode;
1920 musb->board_set_power = plat->set_power;
1921 musb->set_clock = plat->set_clock;
1922 musb->min_power = plat->min_power;
1923
1924 /* Clock usage is chip-specific ... functional clock (DaVinci,
1925 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
1926 * code does is make sure a clock handle is available; platform
1927 * code manages it during start/stop and suspend/resume.
1928 */
1929 if (plat->clock) {
1930 musb->clock = clk_get(dev, plat->clock);
1931 if (IS_ERR(musb->clock)) {
1932 status = PTR_ERR(musb->clock);
1933 musb->clock = NULL;
1934 goto fail1;
1935 }
1936 }
1937
1938 /* The musb_platform_init() call:
1939 * - adjusts musb->mregs and musb->isr if needed,
1940 * - may initialize an integrated tranceiver
1941 * - initializes musb->xceiv, usually by otg_get_transceiver()
1942 * - activates clocks.
1943 * - stops powering VBUS
1944 * - assigns musb->board_set_vbus if host mode is enabled
1945 *
1946 * There are various transciever configurations. Blackfin,
1947 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1948 * external/discrete ones in various flavors (twl4030 family,
1949 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1950 */
1951 musb->isr = generic_interrupt;
1952 status = musb_platform_init(musb);
1953 if (status < 0)
1954 goto fail2;
1955
1956 if (!musb->isr) {
1957 status = -ENODEV;
1958 goto fail3;
1959 }
1960
1961 #ifndef CONFIG_MUSB_PIO_ONLY
1962 if (use_dma && dev->dma_mask) {
1963 struct dma_controller *c;
1964
1965 c = dma_controller_create(musb, musb->mregs);
1966 musb->dma_controller = c;
1967 if (c)
1968 (void) c->start(c);
1969 }
1970 #endif
1971 /* ideally this would be abstracted in platform setup */
1972 if (!is_dma_capable() || !musb->dma_controller)
1973 dev->dma_mask = NULL;
1974
1975 /* be sure interrupts are disabled before connecting ISR */
1976 musb_platform_disable(musb);
1977 musb_generic_disable(musb);
1978
1979 /* setup musb parts of the core (especially endpoints) */
1980 status = musb_core_init(plat->config->multipoint
1981 ? MUSB_CONTROLLER_MHDRC
1982 : MUSB_CONTROLLER_HDRC, musb);
1983 if (status < 0)
1984 goto fail3;
1985
1986 #ifdef CONFIG_USB_MUSB_OTG
1987 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
1988 #endif
1989
1990 /* Init IRQ workqueue before request_irq */
1991 INIT_WORK(&musb->irq_work, musb_irq_work);
1992
1993 /* attach to the IRQ */
1994 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
1995 dev_err(dev, "request_irq %d failed!\n", nIrq);
1996 status = -ENODEV;
1997 goto fail3;
1998 }
1999 musb->nIrq = nIrq;
2000 /* FIXME this handles wakeup irqs wrong */
2001 if (enable_irq_wake(nIrq) == 0) {
2002 musb->irq_wake = 1;
2003 device_init_wakeup(dev, 1);
2004 } else {
2005 musb->irq_wake = 0;
2006 }
2007
2008 /* host side needs more setup */
2009 if (is_host_enabled(musb)) {
2010 struct usb_hcd *hcd = musb_to_hcd(musb);
2011
2012 otg_set_host(musb->xceiv, &hcd->self);
2013
2014 if (is_otg_enabled(musb))
2015 hcd->self.otg_port = 1;
2016 musb->xceiv->host = &hcd->self;
2017 hcd->power_budget = 2 * (plat->power ? : 250);
2018
2019 /* program PHY to use external vBus if required */
2020 if (plat->extvbus) {
2021 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2022 busctl |= MUSB_ULPI_USE_EXTVBUS;
2023 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2024 }
2025 }
2026
2027 /* For the host-only role, we can activate right away.
2028 * (We expect the ID pin to be forcibly grounded!!)
2029 * Otherwise, wait till the gadget driver hooks up.
2030 */
2031 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2032 MUSB_HST_MODE(musb);
2033 musb->xceiv->default_a = 1;
2034 musb->xceiv->state = OTG_STATE_A_IDLE;
2035
2036 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2037
2038 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2039 "HOST", status,
2040 musb_readb(musb->mregs, MUSB_DEVCTL),
2041 (musb_readb(musb->mregs, MUSB_DEVCTL)
2042 & MUSB_DEVCTL_BDEVICE
2043 ? 'B' : 'A'));
2044
2045 } else /* peripheral is enabled */ {
2046 MUSB_DEV_MODE(musb);
2047 musb->xceiv->default_a = 0;
2048 musb->xceiv->state = OTG_STATE_B_IDLE;
2049
2050 status = musb_gadget_setup(musb);
2051
2052 DBG(1, "%s mode, status %d, dev%02x\n",
2053 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2054 status,
2055 musb_readb(musb->mregs, MUSB_DEVCTL));
2056
2057 }
2058 if (status < 0)
2059 goto fail3;
2060
2061 #ifdef CONFIG_SYSFS
2062 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2063 if (status)
2064 goto fail4;
2065 #endif
2066
2067 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
2068 ({char *s;
2069 switch (musb->board_mode) {
2070 case MUSB_HOST: s = "Host"; break;
2071 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2072 default: s = "OTG"; break;
2073 }; s; }),
2074 ctrl,
2075 (is_dma_capable() && musb->dma_controller)
2076 ? "DMA" : "PIO",
2077 musb->nIrq);
2078
2079 return 0;
2080
2081 fail4:
2082 if (!is_otg_enabled(musb) && is_host_enabled(musb))
2083 usb_remove_hcd(musb_to_hcd(musb));
2084 else
2085 musb_gadget_cleanup(musb);
2086
2087 fail3:
2088 if (musb->irq_wake)
2089 device_init_wakeup(dev, 0);
2090 musb_platform_exit(musb);
2091
2092 fail2:
2093 if (musb->clock)
2094 clk_put(musb->clock);
2095
2096 fail1:
2097 dev_err(musb->controller,
2098 "musb_init_controller failed with status %d\n", status);
2099
2100 musb_free(musb);
2101
2102 fail0:
2103
2104 return status;
2105
2106 }
2107
2108 /*-------------------------------------------------------------------------*/
2109
2110 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2111 * bridge to a platform device; this driver then suffices.
2112 */
2113
2114 #ifndef CONFIG_MUSB_PIO_ONLY
2115 static u64 *orig_dma_mask;
2116 #endif
2117
2118 static int __init musb_probe(struct platform_device *pdev)
2119 {
2120 struct device *dev = &pdev->dev;
2121 int irq = platform_get_irq(pdev, 0);
2122 int status;
2123 struct resource *iomem;
2124 void __iomem *base;
2125
2126 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2127 if (!iomem || irq == 0)
2128 return -ENODEV;
2129
2130 base = ioremap(iomem->start, resource_size(iomem));
2131 if (!base) {
2132 dev_err(dev, "ioremap failed\n");
2133 return -ENOMEM;
2134 }
2135
2136 #ifndef CONFIG_MUSB_PIO_ONLY
2137 /* clobbered by use_dma=n */
2138 orig_dma_mask = dev->dma_mask;
2139 #endif
2140 status = musb_init_controller(dev, irq, base);
2141 if (status < 0)
2142 iounmap(base);
2143
2144 return status;
2145 }
2146
2147 static int __exit musb_remove(struct platform_device *pdev)
2148 {
2149 struct musb *musb = dev_to_musb(&pdev->dev);
2150 void __iomem *ctrl_base = musb->ctrl_base;
2151
2152 /* this gets called on rmmod.
2153 * - Host mode: host may still be active
2154 * - Peripheral mode: peripheral is deactivated (or never-activated)
2155 * - OTG mode: both roles are deactivated (or never-activated)
2156 */
2157 musb_shutdown(pdev);
2158 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2159 if (musb->board_mode == MUSB_HOST)
2160 usb_remove_hcd(musb_to_hcd(musb));
2161 #endif
2162 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2163 musb_platform_exit(musb);
2164 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2165
2166 musb_free(musb);
2167 iounmap(ctrl_base);
2168 device_init_wakeup(&pdev->dev, 0);
2169 #ifndef CONFIG_MUSB_PIO_ONLY
2170 pdev->dev.dma_mask = orig_dma_mask;
2171 #endif
2172 return 0;
2173 }
2174
2175 #ifdef CONFIG_PM
2176
2177 static struct musb_context_registers musb_context;
2178
2179 void musb_save_context(struct musb *musb)
2180 {
2181 int i;
2182 void __iomem *musb_base = musb->mregs;
2183
2184 if (is_host_enabled(musb)) {
2185 musb_context.frame = musb_readw(musb_base, MUSB_FRAME);
2186 musb_context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2187 musb_context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2188 }
2189 musb_context.power = musb_readb(musb_base, MUSB_POWER);
2190 musb_context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2191 musb_context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2192 musb_context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2193 musb_context.index = musb_readb(musb_base, MUSB_INDEX);
2194 musb_context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2195
2196 for (i = 0; i < MUSB_C_NUM_EPS; ++i) {
2197 musb_writeb(musb_base, MUSB_INDEX, i);
2198 musb_context.index_regs[i].txmaxp =
2199 musb_readw(musb_base, 0x10 + MUSB_TXMAXP);
2200 musb_context.index_regs[i].txcsr =
2201 musb_readw(musb_base, 0x10 + MUSB_TXCSR);
2202 musb_context.index_regs[i].rxmaxp =
2203 musb_readw(musb_base, 0x10 + MUSB_RXMAXP);
2204 musb_context.index_regs[i].rxcsr =
2205 musb_readw(musb_base, 0x10 + MUSB_RXCSR);
2206
2207 if (musb->dyn_fifo) {
2208 musb_context.index_regs[i].txfifoadd =
2209 musb_read_txfifoadd(musb_base);
2210 musb_context.index_regs[i].rxfifoadd =
2211 musb_read_rxfifoadd(musb_base);
2212 musb_context.index_regs[i].txfifosz =
2213 musb_read_txfifosz(musb_base);
2214 musb_context.index_regs[i].rxfifosz =
2215 musb_read_rxfifosz(musb_base);
2216 }
2217 if (is_host_enabled(musb)) {
2218 musb_context.index_regs[i].txtype =
2219 musb_readb(musb_base, 0x10 + MUSB_TXTYPE);
2220 musb_context.index_regs[i].txinterval =
2221 musb_readb(musb_base, 0x10 + MUSB_TXINTERVAL);
2222 musb_context.index_regs[i].rxtype =
2223 musb_readb(musb_base, 0x10 + MUSB_RXTYPE);
2224 musb_context.index_regs[i].rxinterval =
2225 musb_readb(musb_base, 0x10 + MUSB_RXINTERVAL);
2226
2227 musb_context.index_regs[i].txfunaddr =
2228 musb_read_txfunaddr(musb_base, i);
2229 musb_context.index_regs[i].txhubaddr =
2230 musb_read_txhubaddr(musb_base, i);
2231 musb_context.index_regs[i].txhubport =
2232 musb_read_txhubport(musb_base, i);
2233
2234 musb_context.index_regs[i].rxfunaddr =
2235 musb_read_rxfunaddr(musb_base, i);
2236 musb_context.index_regs[i].rxhubaddr =
2237 musb_read_rxhubaddr(musb_base, i);
2238 musb_context.index_regs[i].rxhubport =
2239 musb_read_rxhubport(musb_base, i);
2240 }
2241 }
2242
2243 musb_writeb(musb_base, MUSB_INDEX, musb_context.index);
2244
2245 musb_platform_save_context(musb, &musb_context);
2246 }
2247
2248 void musb_restore_context(struct musb *musb)
2249 {
2250 int i;
2251 void __iomem *musb_base = musb->mregs;
2252 void __iomem *ep_target_regs;
2253
2254 musb_platform_restore_context(musb, &musb_context);
2255
2256 if (is_host_enabled(musb)) {
2257 musb_writew(musb_base, MUSB_FRAME, musb_context.frame);
2258 musb_writeb(musb_base, MUSB_TESTMODE, musb_context.testmode);
2259 musb_write_ulpi_buscontrol(musb->mregs, musb_context.busctl);
2260 }
2261 musb_writeb(musb_base, MUSB_POWER, musb_context.power);
2262 musb_writew(musb_base, MUSB_INTRTXE, musb_context.intrtxe);
2263 musb_writew(musb_base, MUSB_INTRRXE, musb_context.intrrxe);
2264 musb_writeb(musb_base, MUSB_INTRUSBE, musb_context.intrusbe);
2265 musb_writeb(musb_base, MUSB_DEVCTL, musb_context.devctl);
2266
2267 for (i = 0; i < MUSB_C_NUM_EPS; ++i) {
2268 musb_writeb(musb_base, MUSB_INDEX, i);
2269 musb_writew(musb_base, 0x10 + MUSB_TXMAXP,
2270 musb_context.index_regs[i].txmaxp);
2271 musb_writew(musb_base, 0x10 + MUSB_TXCSR,
2272 musb_context.index_regs[i].txcsr);
2273 musb_writew(musb_base, 0x10 + MUSB_RXMAXP,
2274 musb_context.index_regs[i].rxmaxp);
2275 musb_writew(musb_base, 0x10 + MUSB_RXCSR,
2276 musb_context.index_regs[i].rxcsr);
2277
2278 if (musb->dyn_fifo) {
2279 musb_write_txfifosz(musb_base,
2280 musb_context.index_regs[i].txfifosz);
2281 musb_write_rxfifosz(musb_base,
2282 musb_context.index_regs[i].rxfifosz);
2283 musb_write_txfifoadd(musb_base,
2284 musb_context.index_regs[i].txfifoadd);
2285 musb_write_rxfifoadd(musb_base,
2286 musb_context.index_regs[i].rxfifoadd);
2287 }
2288
2289 if (is_host_enabled(musb)) {
2290 musb_writeb(musb_base, 0x10 + MUSB_TXTYPE,
2291 musb_context.index_regs[i].txtype);
2292 musb_writeb(musb_base, 0x10 + MUSB_TXINTERVAL,
2293 musb_context.index_regs[i].txinterval);
2294 musb_writeb(musb_base, 0x10 + MUSB_RXTYPE,
2295 musb_context.index_regs[i].rxtype);
2296 musb_writeb(musb_base, 0x10 + MUSB_RXINTERVAL,
2297
2298 musb_context.index_regs[i].rxinterval);
2299 musb_write_txfunaddr(musb_base, i,
2300 musb_context.index_regs[i].txfunaddr);
2301 musb_write_txhubaddr(musb_base, i,
2302 musb_context.index_regs[i].txhubaddr);
2303 musb_write_txhubport(musb_base, i,
2304 musb_context.index_regs[i].txhubport);
2305
2306 ep_target_regs =
2307 musb_read_target_reg_base(i, musb_base);
2308
2309 musb_write_rxfunaddr(ep_target_regs,
2310 musb_context.index_regs[i].rxfunaddr);
2311 musb_write_rxhubaddr(ep_target_regs,
2312 musb_context.index_regs[i].rxhubaddr);
2313 musb_write_rxhubport(ep_target_regs,
2314 musb_context.index_regs[i].rxhubport);
2315 }
2316 }
2317
2318 musb_writeb(musb_base, MUSB_INDEX, musb_context.index);
2319 }
2320
2321 static int musb_suspend(struct device *dev)
2322 {
2323 struct platform_device *pdev = to_platform_device(dev);
2324 unsigned long flags;
2325 struct musb *musb = dev_to_musb(&pdev->dev);
2326
2327 if (!musb->clock)
2328 return 0;
2329
2330 spin_lock_irqsave(&musb->lock, flags);
2331
2332 if (is_peripheral_active(musb)) {
2333 /* FIXME force disconnect unless we know USB will wake
2334 * the system up quickly enough to respond ...
2335 */
2336 } else if (is_host_active(musb)) {
2337 /* we know all the children are suspended; sometimes
2338 * they will even be wakeup-enabled.
2339 */
2340 }
2341
2342 musb_save_context(musb);
2343
2344 if (musb->set_clock)
2345 musb->set_clock(musb->clock, 0);
2346 else
2347 clk_disable(musb->clock);
2348 spin_unlock_irqrestore(&musb->lock, flags);
2349 return 0;
2350 }
2351
2352 static int musb_resume_noirq(struct device *dev)
2353 {
2354 struct platform_device *pdev = to_platform_device(dev);
2355 struct musb *musb = dev_to_musb(&pdev->dev);
2356
2357 if (!musb->clock)
2358 return 0;
2359
2360 if (musb->set_clock)
2361 musb->set_clock(musb->clock, 1);
2362 else
2363 clk_enable(musb->clock);
2364
2365 musb_restore_context(musb);
2366
2367 /* for static cmos like DaVinci, register values were preserved
2368 * unless for some reason the whole soc powered down or the USB
2369 * module got reset through the PSC (vs just being disabled).
2370 */
2371 return 0;
2372 }
2373
2374 static const struct dev_pm_ops musb_dev_pm_ops = {
2375 .suspend = musb_suspend,
2376 .resume_noirq = musb_resume_noirq,
2377 };
2378
2379 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2380 #else
2381 #define MUSB_DEV_PM_OPS NULL
2382 #endif
2383
2384 static struct platform_driver musb_driver = {
2385 .driver = {
2386 .name = (char *)musb_driver_name,
2387 .bus = &platform_bus_type,
2388 .owner = THIS_MODULE,
2389 .pm = MUSB_DEV_PM_OPS,
2390 },
2391 .remove = __exit_p(musb_remove),
2392 .shutdown = musb_shutdown,
2393 };
2394
2395 /*-------------------------------------------------------------------------*/
2396
2397 static int __init musb_init(void)
2398 {
2399 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2400 if (usb_disabled())
2401 return 0;
2402 #endif
2403
2404 pr_info("%s: version " MUSB_VERSION ", "
2405 #ifdef CONFIG_MUSB_PIO_ONLY
2406 "pio"
2407 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2408 "cppi-dma"
2409 #elif defined(CONFIG_USB_INVENTRA_DMA)
2410 "musb-dma"
2411 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2412 "tusb-omap-dma"
2413 #else
2414 "?dma?"
2415 #endif
2416 ", "
2417 #ifdef CONFIG_USB_MUSB_OTG
2418 "otg (peripheral+host)"
2419 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2420 "peripheral"
2421 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2422 "host"
2423 #endif
2424 ", debug=%d\n",
2425 musb_driver_name, musb_debug);
2426 return platform_driver_probe(&musb_driver, musb_probe);
2427 }
2428
2429 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2430 * and before usb gadget and host-side drivers start to register
2431 */
2432 fs_initcall(musb_init);
2433
2434 static void __exit musb_cleanup(void)
2435 {
2436 platform_driver_unregister(&musb_driver);
2437 }
2438 module_exit(musb_cleanup);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree