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crypto: omap - Updates omap sham device related platform code
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / arm / mach-omap2 / clock3xxx_data.c
blob5a974dcbcecc156853345643be576cba5959491b
1 /*
2 * OMAP3 clock data
3 *
4 * Copyright (C) 2007-2010 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
10 *
11 */
12
13 /*
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/clk.h>
21 #include <linux/list.h>
22
23 #include <plat/control.h>
24 #include <plat/clkdev_omap.h>
25
26 #include "clock.h"
27 #include "clock3xxx.h"
28 #include "clock34xx.h"
29 #include "clock36xx.h"
30 #include "clock3517.h"
31
32 #include "cm.h"
33 #include "cm-regbits-34xx.h"
34 #include "prm.h"
35 #include "prm-regbits-34xx.h"
36
37 /*
38 * clocks
39 */
40
41 #define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
42
43 /* Maximum DPLL multiplier, divider values for OMAP3 */
44 #define OMAP3_MAX_DPLL_MULT 2047
45 #define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
46 #define OMAP3_MAX_DPLL_DIV 128
47
48 /*
49 * DPLL1 supplies clock to the MPU.
50 * DPLL2 supplies clock to the IVA2.
51 * DPLL3 supplies CORE domain clocks.
52 * DPLL4 supplies peripheral clocks.
53 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
54 */
55
56 /* Forward declarations for DPLL bypass clocks */
57 static struct clk dpll1_fck;
58 static struct clk dpll2_fck;
59
60 /* PRM CLOCKS */
61
62 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
63 static struct clk omap_32k_fck = {
64 .name = "omap_32k_fck",
65 .ops = &clkops_null,
66 .rate = 32768,
67 };
68
69 static struct clk secure_32k_fck = {
70 .name = "secure_32k_fck",
71 .ops = &clkops_null,
72 .rate = 32768,
73 };
74
75 /* Virtual source clocks for osc_sys_ck */
76 static struct clk virt_12m_ck = {
77 .name = "virt_12m_ck",
78 .ops = &clkops_null,
79 .rate = 12000000,
80 };
81
82 static struct clk virt_13m_ck = {
83 .name = "virt_13m_ck",
84 .ops = &clkops_null,
85 .rate = 13000000,
86 };
87
88 static struct clk virt_16_8m_ck = {
89 .name = "virt_16_8m_ck",
90 .ops = &clkops_null,
91 .rate = 16800000,
92 };
93
94 static struct clk virt_19_2m_ck = {
95 .name = "virt_19_2m_ck",
96 .ops = &clkops_null,
97 .rate = 19200000,
98 };
99
100 static struct clk virt_26m_ck = {
101 .name = "virt_26m_ck",
102 .ops = &clkops_null,
103 .rate = 26000000,
104 };
105
106 static struct clk virt_38_4m_ck = {
107 .name = "virt_38_4m_ck",
108 .ops = &clkops_null,
109 .rate = 38400000,
110 };
111
112 static const struct clksel_rate osc_sys_12m_rates[] = {
113 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
114 { .div = 0 }
115 };
116
117 static const struct clksel_rate osc_sys_13m_rates[] = {
118 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
119 { .div = 0 }
120 };
121
122 static const struct clksel_rate osc_sys_16_8m_rates[] = {
123 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
124 { .div = 0 }
125 };
126
127 static const struct clksel_rate osc_sys_19_2m_rates[] = {
128 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
129 { .div = 0 }
130 };
131
132 static const struct clksel_rate osc_sys_26m_rates[] = {
133 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
134 { .div = 0 }
135 };
136
137 static const struct clksel_rate osc_sys_38_4m_rates[] = {
138 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
139 { .div = 0 }
140 };
141
142 static const struct clksel osc_sys_clksel[] = {
143 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
144 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
145 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
146 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
147 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
148 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
149 { .parent = NULL },
150 };
151
152 /* Oscillator clock */
153 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
154 static struct clk osc_sys_ck = {
155 .name = "osc_sys_ck",
156 .ops = &clkops_null,
157 .init = &omap2_init_clksel_parent,
158 .clksel_reg = OMAP3430_PRM_CLKSEL,
159 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
160 .clksel = osc_sys_clksel,
161 /* REVISIT: deal with autoextclkmode? */
162 .recalc = &omap2_clksel_recalc,
163 };
164
165 static const struct clksel_rate div2_rates[] = {
166 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
167 { .div = 2, .val = 2, .flags = RATE_IN_343X },
168 { .div = 0 }
169 };
170
171 static const struct clksel sys_clksel[] = {
172 { .parent = &osc_sys_ck, .rates = div2_rates },
173 { .parent = NULL }
174 };
175
176 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
177 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
178 static struct clk sys_ck = {
179 .name = "sys_ck",
180 .ops = &clkops_null,
181 .parent = &osc_sys_ck,
182 .init = &omap2_init_clksel_parent,
183 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
184 .clksel_mask = OMAP_SYSCLKDIV_MASK,
185 .clksel = sys_clksel,
186 .recalc = &omap2_clksel_recalc,
187 };
188
189 static struct clk sys_altclk = {
190 .name = "sys_altclk",
191 .ops = &clkops_null,
192 };
193
194 /* Optional external clock input for some McBSPs */
195 static struct clk mcbsp_clks = {
196 .name = "mcbsp_clks",
197 .ops = &clkops_null,
198 };
199
200 /* PRM EXTERNAL CLOCK OUTPUT */
201
202 static struct clk sys_clkout1 = {
203 .name = "sys_clkout1",
204 .ops = &clkops_omap2_dflt,
205 .parent = &osc_sys_ck,
206 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
207 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
208 .recalc = &followparent_recalc,
209 };
210
211 /* DPLLS */
212
213 /* CM CLOCKS */
214
215 static const struct clksel_rate div16_dpll_rates[] = {
216 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
217 { .div = 2, .val = 2, .flags = RATE_IN_343X },
218 { .div = 3, .val = 3, .flags = RATE_IN_343X },
219 { .div = 4, .val = 4, .flags = RATE_IN_343X },
220 { .div = 5, .val = 5, .flags = RATE_IN_343X },
221 { .div = 6, .val = 6, .flags = RATE_IN_343X },
222 { .div = 7, .val = 7, .flags = RATE_IN_343X },
223 { .div = 8, .val = 8, .flags = RATE_IN_343X },
224 { .div = 9, .val = 9, .flags = RATE_IN_343X },
225 { .div = 10, .val = 10, .flags = RATE_IN_343X },
226 { .div = 11, .val = 11, .flags = RATE_IN_343X },
227 { .div = 12, .val = 12, .flags = RATE_IN_343X },
228 { .div = 13, .val = 13, .flags = RATE_IN_343X },
229 { .div = 14, .val = 14, .flags = RATE_IN_343X },
230 { .div = 15, .val = 15, .flags = RATE_IN_343X },
231 { .div = 16, .val = 16, .flags = RATE_IN_343X },
232 { .div = 0 }
233 };
234
235 static const struct clksel_rate div32_dpll4_rates_3630[] = {
236 { .div = 1, .val = 1, .flags = RATE_IN_36XX | DEFAULT_RATE },
237 { .div = 2, .val = 2, .flags = RATE_IN_36XX },
238 { .div = 3, .val = 3, .flags = RATE_IN_36XX },
239 { .div = 4, .val = 4, .flags = RATE_IN_36XX },
240 { .div = 5, .val = 5, .flags = RATE_IN_36XX },
241 { .div = 6, .val = 6, .flags = RATE_IN_36XX },
242 { .div = 7, .val = 7, .flags = RATE_IN_36XX },
243 { .div = 8, .val = 8, .flags = RATE_IN_36XX },
244 { .div = 9, .val = 9, .flags = RATE_IN_36XX },
245 { .div = 10, .val = 10, .flags = RATE_IN_36XX },
246 { .div = 11, .val = 11, .flags = RATE_IN_36XX },
247 { .div = 12, .val = 12, .flags = RATE_IN_36XX },
248 { .div = 13, .val = 13, .flags = RATE_IN_36XX },
249 { .div = 14, .val = 14, .flags = RATE_IN_36XX },
250 { .div = 15, .val = 15, .flags = RATE_IN_36XX },
251 { .div = 16, .val = 16, .flags = RATE_IN_36XX },
252 { .div = 17, .val = 17, .flags = RATE_IN_36XX },
253 { .div = 18, .val = 18, .flags = RATE_IN_36XX },
254 { .div = 19, .val = 19, .flags = RATE_IN_36XX },
255 { .div = 20, .val = 20, .flags = RATE_IN_36XX },
256 { .div = 21, .val = 21, .flags = RATE_IN_36XX },
257 { .div = 22, .val = 22, .flags = RATE_IN_36XX },
258 { .div = 23, .val = 23, .flags = RATE_IN_36XX },
259 { .div = 24, .val = 24, .flags = RATE_IN_36XX },
260 { .div = 25, .val = 25, .flags = RATE_IN_36XX },
261 { .div = 26, .val = 26, .flags = RATE_IN_36XX },
262 { .div = 27, .val = 27, .flags = RATE_IN_36XX },
263 { .div = 28, .val = 28, .flags = RATE_IN_36XX },
264 { .div = 29, .val = 29, .flags = RATE_IN_36XX },
265 { .div = 30, .val = 30, .flags = RATE_IN_36XX },
266 { .div = 31, .val = 31, .flags = RATE_IN_36XX },
267 { .div = 32, .val = 32, .flags = RATE_IN_36XX },
268 { .div = 0 }
269 };
270
271 /* DPLL1 */
272 /* MPU clock source */
273 /* Type: DPLL */
274 static struct dpll_data dpll1_dd = {
275 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
276 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
277 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
278 .clk_bypass = &dpll1_fck,
279 .clk_ref = &sys_ck,
280 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
281 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
282 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
283 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
284 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
285 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
286 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
287 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
288 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
289 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
290 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
291 .max_multiplier = OMAP3_MAX_DPLL_MULT,
292 .min_divider = 1,
293 .max_divider = OMAP3_MAX_DPLL_DIV,
294 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
295 };
296
297 static struct clk dpll1_ck = {
298 .name = "dpll1_ck",
299 .ops = &clkops_null,
300 .parent = &sys_ck,
301 .dpll_data = &dpll1_dd,
302 .round_rate = &omap2_dpll_round_rate,
303 .set_rate = &omap3_noncore_dpll_set_rate,
304 .clkdm_name = "dpll1_clkdm",
305 .recalc = &omap3_dpll_recalc,
306 };
307
308 /*
309 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
310 * DPLL isn't bypassed.
311 */
312 static struct clk dpll1_x2_ck = {
313 .name = "dpll1_x2_ck",
314 .ops = &clkops_null,
315 .parent = &dpll1_ck,
316 .clkdm_name = "dpll1_clkdm",
317 .recalc = &omap3_clkoutx2_recalc,
318 };
319
320 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
321 static const struct clksel div16_dpll1_x2m2_clksel[] = {
322 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
323 { .parent = NULL }
324 };
325
326 /*
327 * Does not exist in the TRM - needed to separate the M2 divider from
328 * bypass selection in mpu_ck
329 */
330 static struct clk dpll1_x2m2_ck = {
331 .name = "dpll1_x2m2_ck",
332 .ops = &clkops_null,
333 .parent = &dpll1_x2_ck,
334 .init = &omap2_init_clksel_parent,
335 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
336 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
337 .clksel = div16_dpll1_x2m2_clksel,
338 .clkdm_name = "dpll1_clkdm",
339 .recalc = &omap2_clksel_recalc,
340 };
341
342 /* DPLL2 */
343 /* IVA2 clock source */
344 /* Type: DPLL */
345
346 static struct dpll_data dpll2_dd = {
347 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
348 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
349 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
350 .clk_bypass = &dpll2_fck,
351 .clk_ref = &sys_ck,
352 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
353 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
354 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
355 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
356 (1 << DPLL_LOW_POWER_BYPASS),
357 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
358 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
359 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
360 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
361 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
362 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
363 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
364 .max_multiplier = OMAP3_MAX_DPLL_MULT,
365 .min_divider = 1,
366 .max_divider = OMAP3_MAX_DPLL_DIV,
367 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
368 };
369
370 static struct clk dpll2_ck = {
371 .name = "dpll2_ck",
372 .ops = &clkops_omap3_noncore_dpll_ops,
373 .parent = &sys_ck,
374 .dpll_data = &dpll2_dd,
375 .round_rate = &omap2_dpll_round_rate,
376 .set_rate = &omap3_noncore_dpll_set_rate,
377 .clkdm_name = "dpll2_clkdm",
378 .recalc = &omap3_dpll_recalc,
379 };
380
381 static const struct clksel div16_dpll2_m2x2_clksel[] = {
382 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
383 { .parent = NULL }
384 };
385
386 /*
387 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
388 * or CLKOUTX2. CLKOUT seems most plausible.
389 */
390 static struct clk dpll2_m2_ck = {
391 .name = "dpll2_m2_ck",
392 .ops = &clkops_null,
393 .parent = &dpll2_ck,
394 .init = &omap2_init_clksel_parent,
395 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
396 OMAP3430_CM_CLKSEL2_PLL),
397 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
398 .clksel = div16_dpll2_m2x2_clksel,
399 .clkdm_name = "dpll2_clkdm",
400 .recalc = &omap2_clksel_recalc,
401 };
402
403 /*
404 * DPLL3
405 * Source clock for all interfaces and for some device fclks
406 * REVISIT: Also supports fast relock bypass - not included below
407 */
408 static struct dpll_data dpll3_dd = {
409 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
410 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
411 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
412 .clk_bypass = &sys_ck,
413 .clk_ref = &sys_ck,
414 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
415 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
416 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
417 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
418 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
419 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
420 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
421 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
422 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
423 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
424 .max_multiplier = OMAP3_MAX_DPLL_MULT,
425 .min_divider = 1,
426 .max_divider = OMAP3_MAX_DPLL_DIV,
427 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
428 };
429
430 static struct clk dpll3_ck = {
431 .name = "dpll3_ck",
432 .ops = &clkops_null,
433 .parent = &sys_ck,
434 .dpll_data = &dpll3_dd,
435 .round_rate = &omap2_dpll_round_rate,
436 .clkdm_name = "dpll3_clkdm",
437 .recalc = &omap3_dpll_recalc,
438 };
439
440 /*
441 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
442 * DPLL isn't bypassed
443 */
444 static struct clk dpll3_x2_ck = {
445 .name = "dpll3_x2_ck",
446 .ops = &clkops_null,
447 .parent = &dpll3_ck,
448 .clkdm_name = "dpll3_clkdm",
449 .recalc = &omap3_clkoutx2_recalc,
450 };
451
452 static const struct clksel_rate div31_dpll3_rates[] = {
453 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
454 { .div = 2, .val = 2, .flags = RATE_IN_343X },
455 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
456 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
457 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
458 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
459 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
460 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
461 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
462 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
463 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
464 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
465 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
466 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
467 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
468 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
469 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
470 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
471 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
472 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
473 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
474 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
475 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
476 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
477 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
478 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
479 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
480 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
481 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
482 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
483 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
484 { .div = 0 },
485 };
486
487 static const struct clksel div31_dpll3m2_clksel[] = {
488 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
489 { .parent = NULL }
490 };
491
492 /* DPLL3 output M2 - primary control point for CORE speed */
493 static struct clk dpll3_m2_ck = {
494 .name = "dpll3_m2_ck",
495 .ops = &clkops_null,
496 .parent = &dpll3_ck,
497 .init = &omap2_init_clksel_parent,
498 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
499 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
500 .clksel = div31_dpll3m2_clksel,
501 .clkdm_name = "dpll3_clkdm",
502 .round_rate = &omap2_clksel_round_rate,
503 .set_rate = &omap3_core_dpll_m2_set_rate,
504 .recalc = &omap2_clksel_recalc,
505 };
506
507 static struct clk core_ck = {
508 .name = "core_ck",
509 .ops = &clkops_null,
510 .parent = &dpll3_m2_ck,
511 .recalc = &followparent_recalc,
512 };
513
514 static struct clk dpll3_m2x2_ck = {
515 .name = "dpll3_m2x2_ck",
516 .ops = &clkops_null,
517 .parent = &dpll3_m2_ck,
518 .clkdm_name = "dpll3_clkdm",
519 .recalc = &omap3_clkoutx2_recalc,
520 };
521
522 /* The PWRDN bit is apparently only available on 3430ES2 and above */
523 static const struct clksel div16_dpll3_clksel[] = {
524 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
525 { .parent = NULL }
526 };
527
528 /* This virtual clock is the source for dpll3_m3x2_ck */
529 static struct clk dpll3_m3_ck = {
530 .name = "dpll3_m3_ck",
531 .ops = &clkops_null,
532 .parent = &dpll3_ck,
533 .init = &omap2_init_clksel_parent,
534 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
535 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
536 .clksel = div16_dpll3_clksel,
537 .clkdm_name = "dpll3_clkdm",
538 .recalc = &omap2_clksel_recalc,
539 };
540
541 /* The PWRDN bit is apparently only available on 3430ES2 and above */
542 static struct clk dpll3_m3x2_ck = {
543 .name = "dpll3_m3x2_ck",
544 .ops = &clkops_omap2_dflt_wait,
545 .parent = &dpll3_m3_ck,
546 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
547 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
548 .flags = INVERT_ENABLE,
549 .clkdm_name = "dpll3_clkdm",
550 .recalc = &omap3_clkoutx2_recalc,
551 };
552
553 static struct clk emu_core_alwon_ck = {
554 .name = "emu_core_alwon_ck",
555 .ops = &clkops_null,
556 .parent = &dpll3_m3x2_ck,
557 .clkdm_name = "dpll3_clkdm",
558 .recalc = &followparent_recalc,
559 };
560
561 /* DPLL4 */
562 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
563 /* Type: DPLL */
564 static struct dpll_data dpll4_dd;
565 static struct dpll_data dpll4_dd_34xx __initdata = {
566 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
567 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
568 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
569 .clk_bypass = &sys_ck,
570 .clk_ref = &sys_ck,
571 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
572 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
573 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
574 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
575 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
576 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
577 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
578 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
579 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
580 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
581 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
582 .max_multiplier = OMAP3_MAX_DPLL_MULT,
583 .min_divider = 1,
584 .max_divider = OMAP3_MAX_DPLL_DIV,
585 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
586 };
587
588 static struct dpll_data dpll4_dd_3630 __initdata = {
589 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
590 .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK,
591 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
592 .clk_bypass = &sys_ck,
593 .clk_ref = &sys_ck,
594 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
595 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
596 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
597 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
598 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
599 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
600 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
601 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
602 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
603 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
604 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
605 .min_divider = 1,
606 .max_divider = OMAP3_MAX_DPLL_DIV,
607 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE,
608 .flags = DPLL_J_TYPE
609 };
610
611 static struct clk dpll4_ck = {
612 .name = "dpll4_ck",
613 .ops = &clkops_omap3_noncore_dpll_ops,
614 .parent = &sys_ck,
615 .dpll_data = &dpll4_dd,
616 .round_rate = &omap2_dpll_round_rate,
617 .set_rate = &omap3_dpll4_set_rate,
618 .clkdm_name = "dpll4_clkdm",
619 .recalc = &omap3_dpll_recalc,
620 };
621
622 /*
623 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
624 * DPLL isn't bypassed --
625 * XXX does this serve any downstream clocks?
626 */
627 static struct clk dpll4_x2_ck = {
628 .name = "dpll4_x2_ck",
629 .ops = &clkops_null,
630 .parent = &dpll4_ck,
631 .clkdm_name = "dpll4_clkdm",
632 .recalc = &omap3_clkoutx2_recalc,
633 };
634
635 static const struct clksel div16_dpll4_clksel[] = {
636 { .parent = &dpll4_ck, .rates = div16_dpll_rates },
637 { .parent = NULL }
638 };
639
640 static const struct clksel div32_dpll4_clksel[] = {
641 { .parent = &dpll4_ck, .rates = div32_dpll4_rates_3630 },
642 { .parent = NULL }
643 };
644
645 /* This virtual clock is the source for dpll4_m2x2_ck */
646 static struct clk dpll4_m2_ck;
647
648 static struct clk dpll4_m2_ck_34xx __initdata = {
649 .name = "dpll4_m2_ck",
650 .ops = &clkops_null,
651 .parent = &dpll4_ck,
652 .init = &omap2_init_clksel_parent,
653 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
654 .clksel_mask = OMAP3430_DIV_96M_MASK,
655 .clksel = div16_dpll4_clksel,
656 .clkdm_name = "dpll4_clkdm",
657 .recalc = &omap2_clksel_recalc,
658 };
659
660 static struct clk dpll4_m2_ck_3630 __initdata = {
661 .name = "dpll4_m2_ck",
662 .ops = &clkops_null,
663 .parent = &dpll4_ck,
664 .init = &omap2_init_clksel_parent,
665 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
666 .clksel_mask = OMAP3630_DIV_96M_MASK,
667 .clksel = div32_dpll4_clksel,
668 .clkdm_name = "dpll4_clkdm",
669 .recalc = &omap2_clksel_recalc,
670 };
671
672 /* The PWRDN bit is apparently only available on 3430ES2 and above */
673 static struct clk dpll4_m2x2_ck = {
674 .name = "dpll4_m2x2_ck",
675 .ops = &clkops_omap2_dflt_wait,
676 .parent = &dpll4_m2_ck,
677 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
678 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
679 .flags = INVERT_ENABLE,
680 .clkdm_name = "dpll4_clkdm",
681 .recalc = &omap3_clkoutx2_recalc,
682 };
683
684 /*
685 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
686 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
687 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
688 * CM_96K_(F)CLK.
689 */
690
691 /* Adding 192MHz Clock node needed by SGX */
692 static struct clk omap_192m_alwon_fck = {
693 .name = "omap_192m_alwon_fck",
694 .ops = &clkops_null,
695 .parent = &dpll4_m2x2_ck,
696 .recalc = &followparent_recalc,
697 };
698
699 static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
700 { .div = 1, .val = 1, .flags = RATE_IN_36XX },
701 { .div = 2, .val = 2, .flags = RATE_IN_36XX | DEFAULT_RATE },
702 { .div = 0 }
703 };
704
705 static const struct clksel omap_96m_alwon_fck_clksel[] = {
706 { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
707 { .parent = NULL }
708 };
709
710 static const struct clksel_rate omap_96m_dpll_rates[] = {
711 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
712 { .div = 0 }
713 };
714
715 static const struct clksel_rate omap_96m_sys_rates[] = {
716 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
717 { .div = 0 }
718 };
719
720 static struct clk omap_96m_alwon_fck = {
721 .name = "omap_96m_alwon_fck",
722 .ops = &clkops_null,
723 .parent = &dpll4_m2x2_ck,
724 .recalc = &followparent_recalc,
725 };
726
727 static struct clk omap_96m_alwon_fck_3630 = {
728 .name = "omap_96m_alwon_fck",
729 .parent = &omap_192m_alwon_fck,
730 .init = &omap2_init_clksel_parent,
731 .ops = &clkops_null,
732 .recalc = &omap2_clksel_recalc,
733 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
734 .clksel_mask = OMAP3630_CLKSEL_96M_MASK,
735 .clksel = omap_96m_alwon_fck_clksel
736 };
737
738 static struct clk cm_96m_fck = {
739 .name = "cm_96m_fck",
740 .ops = &clkops_null,
741 .parent = &omap_96m_alwon_fck,
742 .recalc = &followparent_recalc,
743 };
744
745 static const struct clksel omap_96m_fck_clksel[] = {
746 { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
747 { .parent = &sys_ck, .rates = omap_96m_sys_rates },
748 { .parent = NULL }
749 };
750
751 static struct clk omap_96m_fck = {
752 .name = "omap_96m_fck",
753 .ops = &clkops_null,
754 .parent = &sys_ck,
755 .init = &omap2_init_clksel_parent,
756 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
757 .clksel_mask = OMAP3430_SOURCE_96M_MASK,
758 .clksel = omap_96m_fck_clksel,
759 .recalc = &omap2_clksel_recalc,
760 };
761
762 /* This virtual clock is the source for dpll4_m3x2_ck */
763 static struct clk dpll4_m3_ck;
764
765 static struct clk dpll4_m3_ck_34xx __initdata = {
766 .name = "dpll4_m3_ck",
767 .ops = &clkops_null,
768 .parent = &dpll4_ck,
769 .init = &omap2_init_clksel_parent,
770 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
771 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
772 .clksel = div16_dpll4_clksel,
773 .clkdm_name = "dpll4_clkdm",
774 .recalc = &omap2_clksel_recalc,
775 };
776
777 static struct clk dpll4_m3_ck_3630 __initdata = {
778 .name = "dpll4_m3_ck",
779 .ops = &clkops_null,
780 .parent = &dpll4_ck,
781 .init = &omap2_init_clksel_parent,
782 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
783 .clksel_mask = OMAP3630_CLKSEL_TV_MASK,
784 .clksel = div32_dpll4_clksel,
785 .clkdm_name = "dpll4_clkdm",
786 .recalc = &omap2_clksel_recalc,
787 };
788
789 /* The PWRDN bit is apparently only available on 3430ES2 and above */
790 static struct clk dpll4_m3x2_ck = {
791 .name = "dpll4_m3x2_ck",
792 .ops = &clkops_omap2_dflt_wait,
793 .parent = &dpll4_m3_ck,
794 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
795 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
796 .flags = INVERT_ENABLE,
797 .clkdm_name = "dpll4_clkdm",
798 .recalc = &omap3_clkoutx2_recalc,
799 };
800
801 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
802 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
803 { .div = 0 }
804 };
805
806 static const struct clksel_rate omap_54m_alt_rates[] = {
807 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
808 { .div = 0 }
809 };
810
811 static const struct clksel omap_54m_clksel[] = {
812 { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
813 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
814 { .parent = NULL }
815 };
816
817 static struct clk omap_54m_fck = {
818 .name = "omap_54m_fck",
819 .ops = &clkops_null,
820 .init = &omap2_init_clksel_parent,
821 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
822 .clksel_mask = OMAP3430_SOURCE_54M_MASK,
823 .clksel = omap_54m_clksel,
824 .recalc = &omap2_clksel_recalc,
825 };
826
827 static const struct clksel_rate omap_48m_cm96m_rates[] = {
828 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
829 { .div = 0 }
830 };
831
832 static const struct clksel_rate omap_48m_alt_rates[] = {
833 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
834 { .div = 0 }
835 };
836
837 static const struct clksel omap_48m_clksel[] = {
838 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
839 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
840 { .parent = NULL }
841 };
842
843 static struct clk omap_48m_fck = {
844 .name = "omap_48m_fck",
845 .ops = &clkops_null,
846 .init = &omap2_init_clksel_parent,
847 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
848 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
849 .clksel = omap_48m_clksel,
850 .recalc = &omap2_clksel_recalc,
851 };
852
853 static struct clk omap_12m_fck = {
854 .name = "omap_12m_fck",
855 .ops = &clkops_null,
856 .parent = &omap_48m_fck,
857 .fixed_div = 4,
858 .recalc = &omap_fixed_divisor_recalc,
859 };
860
861 /* This virstual clock is the source for dpll4_m4x2_ck */
862 static struct clk dpll4_m4_ck;
863
864 static struct clk dpll4_m4_ck_34xx __initdata = {
865 .name = "dpll4_m4_ck",
866 .ops = &clkops_null,
867 .parent = &dpll4_ck,
868 .init = &omap2_init_clksel_parent,
869 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
870 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
871 .clksel = div16_dpll4_clksel,
872 .clkdm_name = "dpll4_clkdm",
873 .recalc = &omap2_clksel_recalc,
874 .set_rate = &omap2_clksel_set_rate,
875 .round_rate = &omap2_clksel_round_rate,
876 };
877
878 static struct clk dpll4_m4_ck_3630 __initdata = {
879 .name = "dpll4_m4_ck",
880 .ops = &clkops_null,
881 .parent = &dpll4_ck,
882 .init = &omap2_init_clksel_parent,
883 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
884 .clksel_mask = OMAP3630_CLKSEL_DSS1_MASK,
885 .clksel = div32_dpll4_clksel,
886 .clkdm_name = "dpll4_clkdm",
887 .recalc = &omap2_clksel_recalc,
888 .set_rate = &omap2_clksel_set_rate,
889 .round_rate = &omap2_clksel_round_rate,
890 };
891
892 /* The PWRDN bit is apparently only available on 3430ES2 and above */
893 static struct clk dpll4_m4x2_ck = {
894 .name = "dpll4_m4x2_ck",
895 .ops = &clkops_omap2_dflt_wait,
896 .parent = &dpll4_m4_ck,
897 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
898 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
899 .flags = INVERT_ENABLE,
900 .clkdm_name = "dpll4_clkdm",
901 .recalc = &omap3_clkoutx2_recalc,
902 };
903
904 /* This virtual clock is the source for dpll4_m5x2_ck */
905 static struct clk dpll4_m5_ck;
906
907 static struct clk dpll4_m5_ck_34xx __initdata = {
908 .name = "dpll4_m5_ck",
909 .ops = &clkops_null,
910 .parent = &dpll4_ck,
911 .init = &omap2_init_clksel_parent,
912 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
913 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
914 .clksel = div16_dpll4_clksel,
915 .clkdm_name = "dpll4_clkdm",
916 .set_rate = &omap2_clksel_set_rate,
917 .round_rate = &omap2_clksel_round_rate,
918 .recalc = &omap2_clksel_recalc,
919 };
920
921 static struct clk dpll4_m5_ck_3630 __initdata = {
922 .name = "dpll4_m5_ck",
923 .ops = &clkops_null,
924 .parent = &dpll4_ck,
925 .init = &omap2_init_clksel_parent,
926 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
927 .clksel_mask = OMAP3630_CLKSEL_CAM_MASK,
928 .clksel = div32_dpll4_clksel,
929 .clkdm_name = "dpll4_clkdm",
930 .set_rate = &omap2_clksel_set_rate,
931 .round_rate = &omap2_clksel_round_rate,
932 .recalc = &omap2_clksel_recalc,
933 };
934
935 /* The PWRDN bit is apparently only available on 3430ES2 and above */
936 static struct clk dpll4_m5x2_ck = {
937 .name = "dpll4_m5x2_ck",
938 .ops = &clkops_omap2_dflt_wait,
939 .parent = &dpll4_m5_ck,
940 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
941 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
942 .flags = INVERT_ENABLE,
943 .clkdm_name = "dpll4_clkdm",
944 .recalc = &omap3_clkoutx2_recalc,
945 };
946
947 /* This virtual clock is the source for dpll4_m6x2_ck */
948 static struct clk dpll4_m6_ck;
949
950 static struct clk dpll4_m6_ck_34xx __initdata = {
951 .name = "dpll4_m6_ck",
952 .ops = &clkops_null,
953 .parent = &dpll4_ck,
954 .init = &omap2_init_clksel_parent,
955 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
956 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
957 .clksel = div16_dpll4_clksel,
958 .clkdm_name = "dpll4_clkdm",
959 .recalc = &omap2_clksel_recalc,
960 };
961
962 static struct clk dpll4_m6_ck_3630 __initdata = {
963 .name = "dpll4_m6_ck",
964 .ops = &clkops_null,
965 .parent = &dpll4_ck,
966 .init = &omap2_init_clksel_parent,
967 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
968 .clksel_mask = OMAP3630_DIV_DPLL4_MASK,
969 .clksel = div32_dpll4_clksel,
970 .clkdm_name = "dpll4_clkdm",
971 .recalc = &omap2_clksel_recalc,
972 };
973
974 /* The PWRDN bit is apparently only available on 3430ES2 and above */
975 static struct clk dpll4_m6x2_ck = {
976 .name = "dpll4_m6x2_ck",
977 .ops = &clkops_omap2_dflt_wait,
978 .parent = &dpll4_m6_ck,
979 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
980 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
981 .flags = INVERT_ENABLE,
982 .clkdm_name = "dpll4_clkdm",
983 .recalc = &omap3_clkoutx2_recalc,
984 };
985
986 static struct clk emu_per_alwon_ck = {
987 .name = "emu_per_alwon_ck",
988 .ops = &clkops_null,
989 .parent = &dpll4_m6x2_ck,
990 .clkdm_name = "dpll4_clkdm",
991 .recalc = &followparent_recalc,
992 };
993
994 /* DPLL5 */
995 /* Supplies 120MHz clock, USIM source clock */
996 /* Type: DPLL */
997 /* 3430ES2 only */
998 static struct dpll_data dpll5_dd = {
999 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
1000 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
1001 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
1002 .clk_bypass = &sys_ck,
1003 .clk_ref = &sys_ck,
1004 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
1005 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
1006 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
1007 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
1008 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
1009 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
1010 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
1011 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
1012 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
1013 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
1014 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
1015 .max_multiplier = OMAP3_MAX_DPLL_MULT,
1016 .min_divider = 1,
1017 .max_divider = OMAP3_MAX_DPLL_DIV,
1018 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
1019 };
1020
1021 static struct clk dpll5_ck = {
1022 .name = "dpll5_ck",
1023 .ops = &clkops_omap3_noncore_dpll_ops,
1024 .parent = &sys_ck,
1025 .dpll_data = &dpll5_dd,
1026 .round_rate = &omap2_dpll_round_rate,
1027 .set_rate = &omap3_noncore_dpll_set_rate,
1028 .clkdm_name = "dpll5_clkdm",
1029 .recalc = &omap3_dpll_recalc,
1030 };
1031
1032 static const struct clksel div16_dpll5_clksel[] = {
1033 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
1034 { .parent = NULL }
1035 };
1036
1037 static struct clk dpll5_m2_ck = {
1038 .name = "dpll5_m2_ck",
1039 .ops = &clkops_null,
1040 .parent = &dpll5_ck,
1041 .init = &omap2_init_clksel_parent,
1042 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
1043 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
1044 .clksel = div16_dpll5_clksel,
1045 .clkdm_name = "dpll5_clkdm",
1046 .recalc = &omap2_clksel_recalc,
1047 };
1048
1049 /* CM EXTERNAL CLOCK OUTPUTS */
1050
1051 static const struct clksel_rate clkout2_src_core_rates[] = {
1052 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1053 { .div = 0 }
1054 };
1055
1056 static const struct clksel_rate clkout2_src_sys_rates[] = {
1057 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1058 { .div = 0 }
1059 };
1060
1061 static const struct clksel_rate clkout2_src_96m_rates[] = {
1062 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
1063 { .div = 0 }
1064 };
1065
1066 static const struct clksel_rate clkout2_src_54m_rates[] = {
1067 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1068 { .div = 0 }
1069 };
1070
1071 static const struct clksel clkout2_src_clksel[] = {
1072 { .parent = &core_ck, .rates = clkout2_src_core_rates },
1073 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
1074 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
1075 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
1076 { .parent = NULL }
1077 };
1078
1079 static struct clk clkout2_src_ck = {
1080 .name = "clkout2_src_ck",
1081 .ops = &clkops_omap2_dflt,
1082 .init = &omap2_init_clksel_parent,
1083 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
1084 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
1085 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
1086 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
1087 .clksel = clkout2_src_clksel,
1088 .clkdm_name = "core_clkdm",
1089 .recalc = &omap2_clksel_recalc,
1090 };
1091
1092 static const struct clksel_rate sys_clkout2_rates[] = {
1093 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1094 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1095 { .div = 4, .val = 2, .flags = RATE_IN_343X },
1096 { .div = 8, .val = 3, .flags = RATE_IN_343X },
1097 { .div = 16, .val = 4, .flags = RATE_IN_343X },
1098 { .div = 0 },
1099 };
1100
1101 static const struct clksel sys_clkout2_clksel[] = {
1102 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1103 { .parent = NULL },
1104 };
1105
1106 static struct clk sys_clkout2 = {
1107 .name = "sys_clkout2",
1108 .ops = &clkops_null,
1109 .init = &omap2_init_clksel_parent,
1110 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
1111 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
1112 .clksel = sys_clkout2_clksel,
1113 .recalc = &omap2_clksel_recalc,
1114 };
1115
1116 /* CM OUTPUT CLOCKS */
1117
1118 static struct clk corex2_fck = {
1119 .name = "corex2_fck",
1120 .ops = &clkops_null,
1121 .parent = &dpll3_m2x2_ck,
1122 .recalc = &followparent_recalc,
1123 };
1124
1125 /* DPLL power domain clock controls */
1126
1127 static const struct clksel_rate div4_rates[] = {
1128 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1129 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1130 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1131 { .div = 0 }
1132 };
1133
1134 static const struct clksel div4_core_clksel[] = {
1135 { .parent = &core_ck, .rates = div4_rates },
1136 { .parent = NULL }
1137 };
1138
1139 /*
1140 * REVISIT: Are these in DPLL power domain or CM power domain? docs
1141 * may be inconsistent here?
1142 */
1143 static struct clk dpll1_fck = {
1144 .name = "dpll1_fck",
1145 .ops = &clkops_null,
1146 .parent = &core_ck,
1147 .init = &omap2_init_clksel_parent,
1148 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1149 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
1150 .clksel = div4_core_clksel,
1151 .recalc = &omap2_clksel_recalc,
1152 };
1153
1154 static struct clk mpu_ck = {
1155 .name = "mpu_ck",
1156 .ops = &clkops_null,
1157 .parent = &dpll1_x2m2_ck,
1158 .clkdm_name = "mpu_clkdm",
1159 .recalc = &followparent_recalc,
1160 };
1161
1162 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1163 static const struct clksel_rate arm_fck_rates[] = {
1164 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1165 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1166 { .div = 0 },
1167 };
1168
1169 static const struct clksel arm_fck_clksel[] = {
1170 { .parent = &mpu_ck, .rates = arm_fck_rates },
1171 { .parent = NULL }
1172 };
1173
1174 static struct clk arm_fck = {
1175 .name = "arm_fck",
1176 .ops = &clkops_null,
1177 .parent = &mpu_ck,
1178 .init = &omap2_init_clksel_parent,
1179 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1180 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1181 .clksel = arm_fck_clksel,
1182 .clkdm_name = "mpu_clkdm",
1183 .recalc = &omap2_clksel_recalc,
1184 };
1185
1186 /* XXX What about neon_clkdm ? */
1187
1188 /*
1189 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1190 * although it is referenced - so this is a guess
1191 */
1192 static struct clk emu_mpu_alwon_ck = {
1193 .name = "emu_mpu_alwon_ck",
1194 .ops = &clkops_null,
1195 .parent = &mpu_ck,
1196 .recalc = &followparent_recalc,
1197 };
1198
1199 static struct clk dpll2_fck = {
1200 .name = "dpll2_fck",
1201 .ops = &clkops_null,
1202 .parent = &core_ck,
1203 .init = &omap2_init_clksel_parent,
1204 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1205 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1206 .clksel = div4_core_clksel,
1207 .recalc = &omap2_clksel_recalc,
1208 };
1209
1210 static struct clk iva2_ck = {
1211 .name = "iva2_ck",
1212 .ops = &clkops_omap2_dflt_wait,
1213 .parent = &dpll2_m2_ck,
1214 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1215 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1216 .clkdm_name = "iva2_clkdm",
1217 .recalc = &followparent_recalc,
1218 };
1219
1220 /* Common interface clocks */
1221
1222 static const struct clksel div2_core_clksel[] = {
1223 { .parent = &core_ck, .rates = div2_rates },
1224 { .parent = NULL }
1225 };
1226
1227 static struct clk l3_ick = {
1228 .name = "l3_ick",
1229 .ops = &clkops_null,
1230 .parent = &core_ck,
1231 .init = &omap2_init_clksel_parent,
1232 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1233 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1234 .clksel = div2_core_clksel,
1235 .clkdm_name = "core_l3_clkdm",
1236 .recalc = &omap2_clksel_recalc,
1237 };
1238
1239 static const struct clksel div2_l3_clksel[] = {
1240 { .parent = &l3_ick, .rates = div2_rates },
1241 { .parent = NULL }
1242 };
1243
1244 static struct clk l4_ick = {
1245 .name = "l4_ick",
1246 .ops = &clkops_null,
1247 .parent = &l3_ick,
1248 .init = &omap2_init_clksel_parent,
1249 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1250 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1251 .clksel = div2_l3_clksel,
1252 .clkdm_name = "core_l4_clkdm",
1253 .recalc = &omap2_clksel_recalc,
1254
1255 };
1256
1257 static const struct clksel div2_l4_clksel[] = {
1258 { .parent = &l4_ick, .rates = div2_rates },
1259 { .parent = NULL }
1260 };
1261
1262 static struct clk rm_ick = {
1263 .name = "rm_ick",
1264 .ops = &clkops_null,
1265 .parent = &l4_ick,
1266 .init = &omap2_init_clksel_parent,
1267 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1268 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1269 .clksel = div2_l4_clksel,
1270 .recalc = &omap2_clksel_recalc,
1271 };
1272
1273 /* GFX power domain */
1274
1275 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1276
1277 static const struct clksel gfx_l3_clksel[] = {
1278 { .parent = &l3_ick, .rates = gfx_l3_rates },
1279 { .parent = NULL }
1280 };
1281
1282 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1283 static struct clk gfx_l3_ck = {
1284 .name = "gfx_l3_ck",
1285 .ops = &clkops_omap2_dflt_wait,
1286 .parent = &l3_ick,
1287 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1288 .enable_bit = OMAP_EN_GFX_SHIFT,
1289 .recalc = &followparent_recalc,
1290 };
1291
1292 static struct clk gfx_l3_fck = {
1293 .name = "gfx_l3_fck",
1294 .ops = &clkops_null,
1295 .parent = &gfx_l3_ck,
1296 .init = &omap2_init_clksel_parent,
1297 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1298 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1299 .clksel = gfx_l3_clksel,
1300 .clkdm_name = "gfx_3430es1_clkdm",
1301 .recalc = &omap2_clksel_recalc,
1302 };
1303
1304 static struct clk gfx_l3_ick = {
1305 .name = "gfx_l3_ick",
1306 .ops = &clkops_null,
1307 .parent = &gfx_l3_ck,
1308 .clkdm_name = "gfx_3430es1_clkdm",
1309 .recalc = &followparent_recalc,
1310 };
1311
1312 static struct clk gfx_cg1_ck = {
1313 .name = "gfx_cg1_ck",
1314 .ops = &clkops_omap2_dflt_wait,
1315 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1316 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1317 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1318 .clkdm_name = "gfx_3430es1_clkdm",
1319 .recalc = &followparent_recalc,
1320 };
1321
1322 static struct clk gfx_cg2_ck = {
1323 .name = "gfx_cg2_ck",
1324 .ops = &clkops_omap2_dflt_wait,
1325 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1326 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1327 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1328 .clkdm_name = "gfx_3430es1_clkdm",
1329 .recalc = &followparent_recalc,
1330 };
1331
1332 /* SGX power domain - 3430ES2 only */
1333
1334 static const struct clksel_rate sgx_core_rates[] = {
1335 { .div = 2, .val = 5, .flags = RATE_IN_36XX },
1336 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1337 { .div = 4, .val = 1, .flags = RATE_IN_343X },
1338 { .div = 6, .val = 2, .flags = RATE_IN_343X },
1339 { .div = 0 },
1340 };
1341
1342 static const struct clksel_rate sgx_192m_rates[] = {
1343 { .div = 1, .val = 4, .flags = RATE_IN_36XX | DEFAULT_RATE },
1344 { .div = 0 },
1345 };
1346
1347 static const struct clksel_rate sgx_corex2_rates[] = {
1348 { .div = 3, .val = 6, .flags = RATE_IN_36XX | DEFAULT_RATE },
1349 { .div = 5, .val = 7, .flags = RATE_IN_36XX },
1350 { .div = 0 },
1351 };
1352
1353 static const struct clksel_rate sgx_96m_rates[] = {
1354 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1355 { .div = 0 },
1356 };
1357
1358 static const struct clksel sgx_clksel[] = {
1359 { .parent = &core_ck, .rates = sgx_core_rates },
1360 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1361 { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
1362 { .parent = &corex2_fck, .rates = sgx_corex2_rates },
1363 { .parent = NULL }
1364 };
1365
1366 static struct clk sgx_fck = {
1367 .name = "sgx_fck",
1368 .ops = &clkops_omap2_dflt_wait,
1369 .init = &omap2_init_clksel_parent,
1370 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1371 .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1372 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1373 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1374 .clksel = sgx_clksel,
1375 .clkdm_name = "sgx_clkdm",
1376 .recalc = &omap2_clksel_recalc,
1377 .set_rate = &omap2_clksel_set_rate,
1378 .round_rate = &omap2_clksel_round_rate
1379 };
1380
1381 static struct clk sgx_ick = {
1382 .name = "sgx_ick",
1383 .ops = &clkops_omap2_dflt_wait,
1384 .parent = &l3_ick,
1385 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1386 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1387 .clkdm_name = "sgx_clkdm",
1388 .recalc = &followparent_recalc,
1389 };
1390
1391 /* CORE power domain */
1392
1393 static struct clk d2d_26m_fck = {
1394 .name = "d2d_26m_fck",
1395 .ops = &clkops_omap2_dflt_wait,
1396 .parent = &sys_ck,
1397 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1398 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1399 .clkdm_name = "d2d_clkdm",
1400 .recalc = &followparent_recalc,
1401 };
1402
1403 static struct clk modem_fck = {
1404 .name = "modem_fck",
1405 .ops = &clkops_omap2_dflt_wait,
1406 .parent = &sys_ck,
1407 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1408 .enable_bit = OMAP3430_EN_MODEM_SHIFT,
1409 .clkdm_name = "d2d_clkdm",
1410 .recalc = &followparent_recalc,
1411 };
1412
1413 static struct clk sad2d_ick = {
1414 .name = "sad2d_ick",
1415 .ops = &clkops_omap2_dflt_wait,
1416 .parent = &l3_ick,
1417 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1418 .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
1419 .clkdm_name = "d2d_clkdm",
1420 .recalc = &followparent_recalc,
1421 };
1422
1423 static struct clk mad2d_ick = {
1424 .name = "mad2d_ick",
1425 .ops = &clkops_omap2_dflt_wait,
1426 .parent = &l3_ick,
1427 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1428 .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
1429 .clkdm_name = "d2d_clkdm",
1430 .recalc = &followparent_recalc,
1431 };
1432
1433 static const struct clksel omap343x_gpt_clksel[] = {
1434 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1435 { .parent = &sys_ck, .rates = gpt_sys_rates },
1436 { .parent = NULL}
1437 };
1438
1439 static struct clk gpt10_fck = {
1440 .name = "gpt10_fck",
1441 .ops = &clkops_omap2_dflt_wait,
1442 .parent = &sys_ck,
1443 .init = &omap2_init_clksel_parent,
1444 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1445 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1446 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1447 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1448 .clksel = omap343x_gpt_clksel,
1449 .clkdm_name = "core_l4_clkdm",
1450 .recalc = &omap2_clksel_recalc,
1451 };
1452
1453 static struct clk gpt11_fck = {
1454 .name = "gpt11_fck",
1455 .ops = &clkops_omap2_dflt_wait,
1456 .parent = &sys_ck,
1457 .init = &omap2_init_clksel_parent,
1458 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1459 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1460 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1461 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1462 .clksel = omap343x_gpt_clksel,
1463 .clkdm_name = "core_l4_clkdm",
1464 .recalc = &omap2_clksel_recalc,
1465 };
1466
1467 static struct clk cpefuse_fck = {
1468 .name = "cpefuse_fck",
1469 .ops = &clkops_omap2_dflt,
1470 .parent = &sys_ck,
1471 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1472 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1473 .recalc = &followparent_recalc,
1474 };
1475
1476 static struct clk ts_fck = {
1477 .name = "ts_fck",
1478 .ops = &clkops_omap2_dflt,
1479 .parent = &omap_32k_fck,
1480 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1481 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1482 .recalc = &followparent_recalc,
1483 };
1484
1485 static struct clk usbtll_fck = {
1486 .name = "usbtll_fck",
1487 .ops = &clkops_omap2_dflt,
1488 .parent = &dpll5_m2_ck,
1489 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1490 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1491 .recalc = &followparent_recalc,
1492 };
1493
1494 /* CORE 96M FCLK-derived clocks */
1495
1496 static struct clk core_96m_fck = {
1497 .name = "core_96m_fck",
1498 .ops = &clkops_null,
1499 .parent = &omap_96m_fck,
1500 .clkdm_name = "core_l4_clkdm",
1501 .recalc = &followparent_recalc,
1502 };
1503
1504 static struct clk mmchs3_fck = {
1505 .name = "mmchs3_fck",
1506 .ops = &clkops_omap2_dflt_wait,
1507 .parent = &core_96m_fck,
1508 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1509 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1510 .clkdm_name = "core_l4_clkdm",
1511 .recalc = &followparent_recalc,
1512 };
1513
1514 static struct clk mmchs2_fck = {
1515 .name = "mmchs2_fck",
1516 .ops = &clkops_omap2_dflt_wait,
1517 .parent = &core_96m_fck,
1518 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1519 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1520 .clkdm_name = "core_l4_clkdm",
1521 .recalc = &followparent_recalc,
1522 };
1523
1524 static struct clk mspro_fck = {
1525 .name = "mspro_fck",
1526 .ops = &clkops_omap2_dflt_wait,
1527 .parent = &core_96m_fck,
1528 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1529 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1530 .clkdm_name = "core_l4_clkdm",
1531 .recalc = &followparent_recalc,
1532 };
1533
1534 static struct clk mmchs1_fck = {
1535 .name = "mmchs1_fck",
1536 .ops = &clkops_omap2_dflt_wait,
1537 .parent = &core_96m_fck,
1538 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1539 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1540 .clkdm_name = "core_l4_clkdm",
1541 .recalc = &followparent_recalc,
1542 };
1543
1544 static struct clk i2c3_fck = {
1545 .name = "i2c3_fck",
1546 .ops = &clkops_omap2_dflt_wait,
1547 .parent = &core_96m_fck,
1548 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1549 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1550 .clkdm_name = "core_l4_clkdm",
1551 .recalc = &followparent_recalc,
1552 };
1553
1554 static struct clk i2c2_fck = {
1555 .name = "i2c2_fck",
1556 .ops = &clkops_omap2_dflt_wait,
1557 .parent = &core_96m_fck,
1558 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1559 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1560 .clkdm_name = "core_l4_clkdm",
1561 .recalc = &followparent_recalc,
1562 };
1563
1564 static struct clk i2c1_fck = {
1565 .name = "i2c1_fck",
1566 .ops = &clkops_omap2_dflt_wait,
1567 .parent = &core_96m_fck,
1568 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1569 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1570 .clkdm_name = "core_l4_clkdm",
1571 .recalc = &followparent_recalc,
1572 };
1573
1574 /*
1575 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1576 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1577 */
1578 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1579 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1580 { .div = 0 }
1581 };
1582
1583 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1584 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1585 { .div = 0 }
1586 };
1587
1588 static const struct clksel mcbsp_15_clksel[] = {
1589 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1590 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1591 { .parent = NULL }
1592 };
1593
1594 static struct clk mcbsp5_fck = {
1595 .name = "mcbsp5_fck",
1596 .ops = &clkops_omap2_dflt_wait,
1597 .init = &omap2_init_clksel_parent,
1598 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1599 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1600 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1601 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1602 .clksel = mcbsp_15_clksel,
1603 .clkdm_name = "core_l4_clkdm",
1604 .recalc = &omap2_clksel_recalc,
1605 };
1606
1607 static struct clk mcbsp1_fck = {
1608 .name = "mcbsp1_fck",
1609 .ops = &clkops_omap2_dflt_wait,
1610 .init = &omap2_init_clksel_parent,
1611 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1612 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1613 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1614 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1615 .clksel = mcbsp_15_clksel,
1616 .clkdm_name = "core_l4_clkdm",
1617 .recalc = &omap2_clksel_recalc,
1618 };
1619
1620 /* CORE_48M_FCK-derived clocks */
1621
1622 static struct clk core_48m_fck = {
1623 .name = "core_48m_fck",
1624 .ops = &clkops_null,
1625 .parent = &omap_48m_fck,
1626 .clkdm_name = "core_l4_clkdm",
1627 .recalc = &followparent_recalc,
1628 };
1629
1630 static struct clk mcspi4_fck = {
1631 .name = "mcspi4_fck",
1632 .ops = &clkops_omap2_dflt_wait,
1633 .parent = &core_48m_fck,
1634 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1635 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1636 .recalc = &followparent_recalc,
1637 };
1638
1639 static struct clk mcspi3_fck = {
1640 .name = "mcspi3_fck",
1641 .ops = &clkops_omap2_dflt_wait,
1642 .parent = &core_48m_fck,
1643 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1644 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1645 .recalc = &followparent_recalc,
1646 };
1647
1648 static struct clk mcspi2_fck = {
1649 .name = "mcspi2_fck",
1650 .ops = &clkops_omap2_dflt_wait,
1651 .parent = &core_48m_fck,
1652 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1653 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1654 .recalc = &followparent_recalc,
1655 };
1656
1657 static struct clk mcspi1_fck = {
1658 .name = "mcspi1_fck",
1659 .ops = &clkops_omap2_dflt_wait,
1660 .parent = &core_48m_fck,
1661 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1662 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1663 .recalc = &followparent_recalc,
1664 };
1665
1666 static struct clk uart2_fck = {
1667 .name = "uart2_fck",
1668 .ops = &clkops_omap2_dflt_wait,
1669 .parent = &core_48m_fck,
1670 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1671 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1672 .clkdm_name = "core_l4_clkdm",
1673 .recalc = &followparent_recalc,
1674 };
1675
1676 static struct clk uart1_fck = {
1677 .name = "uart1_fck",
1678 .ops = &clkops_omap2_dflt_wait,
1679 .parent = &core_48m_fck,
1680 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1681 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1682 .clkdm_name = "core_l4_clkdm",
1683 .recalc = &followparent_recalc,
1684 };
1685
1686 static struct clk fshostusb_fck = {
1687 .name = "fshostusb_fck",
1688 .ops = &clkops_omap2_dflt_wait,
1689 .parent = &core_48m_fck,
1690 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1691 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1692 .recalc = &followparent_recalc,
1693 };
1694
1695 /* CORE_12M_FCK based clocks */
1696
1697 static struct clk core_12m_fck = {
1698 .name = "core_12m_fck",
1699 .ops = &clkops_null,
1700 .parent = &omap_12m_fck,
1701 .clkdm_name = "core_l4_clkdm",
1702 .recalc = &followparent_recalc,
1703 };
1704
1705 static struct clk hdq_fck = {
1706 .name = "hdq_fck",
1707 .ops = &clkops_omap2_dflt_wait,
1708 .parent = &core_12m_fck,
1709 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1710 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1711 .recalc = &followparent_recalc,
1712 };
1713
1714 /* DPLL3-derived clock */
1715
1716 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1717 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1718 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1719 { .div = 3, .val = 3, .flags = RATE_IN_343X },
1720 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1721 { .div = 6, .val = 6, .flags = RATE_IN_343X },
1722 { .div = 8, .val = 8, .flags = RATE_IN_343X },
1723 { .div = 0 }
1724 };
1725
1726 static const struct clksel ssi_ssr_clksel[] = {
1727 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1728 { .parent = NULL }
1729 };
1730
1731 static struct clk ssi_ssr_fck_3430es1 = {
1732 .name = "ssi_ssr_fck",
1733 .ops = &clkops_omap2_dflt,
1734 .init = &omap2_init_clksel_parent,
1735 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1736 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1737 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1738 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1739 .clksel = ssi_ssr_clksel,
1740 .clkdm_name = "core_l4_clkdm",
1741 .recalc = &omap2_clksel_recalc,
1742 };
1743
1744 static struct clk ssi_ssr_fck_3430es2 = {
1745 .name = "ssi_ssr_fck",
1746 .ops = &clkops_omap3430es2_ssi_wait,
1747 .init = &omap2_init_clksel_parent,
1748 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1749 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1750 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1751 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1752 .clksel = ssi_ssr_clksel,
1753 .clkdm_name = "core_l4_clkdm",
1754 .recalc = &omap2_clksel_recalc,
1755 };
1756
1757 static struct clk ssi_sst_fck_3430es1 = {
1758 .name = "ssi_sst_fck",
1759 .ops = &clkops_null,
1760 .parent = &ssi_ssr_fck_3430es1,
1761 .fixed_div = 2,
1762 .recalc = &omap_fixed_divisor_recalc,
1763 };
1764
1765 static struct clk ssi_sst_fck_3430es2 = {
1766 .name = "ssi_sst_fck",
1767 .ops = &clkops_null,
1768 .parent = &ssi_ssr_fck_3430es2,
1769 .fixed_div = 2,
1770 .recalc = &omap_fixed_divisor_recalc,
1771 };
1772
1773
1774
1775 /* CORE_L3_ICK based clocks */
1776
1777 /*
1778 * XXX must add clk_enable/clk_disable for these if standard code won't
1779 * handle it
1780 */
1781 static struct clk core_l3_ick = {
1782 .name = "core_l3_ick",
1783 .ops = &clkops_null,
1784 .parent = &l3_ick,
1785 .clkdm_name = "core_l3_clkdm",
1786 .recalc = &followparent_recalc,
1787 };
1788
1789 static struct clk hsotgusb_ick_3430es1 = {
1790 .name = "hsotgusb_ick",
1791 .ops = &clkops_omap2_dflt,
1792 .parent = &core_l3_ick,
1793 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1794 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1795 .clkdm_name = "core_l3_clkdm",
1796 .recalc = &followparent_recalc,
1797 };
1798
1799 static struct clk hsotgusb_ick_3430es2 = {
1800 .name = "hsotgusb_ick",
1801 .ops = &clkops_omap3430es2_hsotgusb_wait,
1802 .parent = &core_l3_ick,
1803 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1804 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1805 .clkdm_name = "core_l3_clkdm",
1806 .recalc = &followparent_recalc,
1807 };
1808
1809 static struct clk sdrc_ick = {
1810 .name = "sdrc_ick",
1811 .ops = &clkops_omap2_dflt_wait,
1812 .parent = &core_l3_ick,
1813 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1814 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1815 .flags = ENABLE_ON_INIT,
1816 .clkdm_name = "core_l3_clkdm",
1817 .recalc = &followparent_recalc,
1818 };
1819
1820 static struct clk gpmc_fck = {
1821 .name = "gpmc_fck",
1822 .ops = &clkops_null,
1823 .parent = &core_l3_ick,
1824 .flags = ENABLE_ON_INIT, /* huh? */
1825 .clkdm_name = "core_l3_clkdm",
1826 .recalc = &followparent_recalc,
1827 };
1828
1829 /* SECURITY_L3_ICK based clocks */
1830
1831 static struct clk security_l3_ick = {
1832 .name = "security_l3_ick",
1833 .ops = &clkops_null,
1834 .parent = &l3_ick,
1835 .recalc = &followparent_recalc,
1836 };
1837
1838 static struct clk pka_ick = {
1839 .name = "pka_ick",
1840 .ops = &clkops_omap2_dflt_wait,
1841 .parent = &security_l3_ick,
1842 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1843 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1844 .recalc = &followparent_recalc,
1845 };
1846
1847 /* CORE_L4_ICK based clocks */
1848
1849 static struct clk core_l4_ick = {
1850 .name = "core_l4_ick",
1851 .ops = &clkops_null,
1852 .parent = &l4_ick,
1853 .clkdm_name = "core_l4_clkdm",
1854 .recalc = &followparent_recalc,
1855 };
1856
1857 static struct clk usbtll_ick = {
1858 .name = "usbtll_ick",
1859 .ops = &clkops_omap2_dflt_wait,
1860 .parent = &core_l4_ick,
1861 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1862 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1863 .clkdm_name = "core_l4_clkdm",
1864 .recalc = &followparent_recalc,
1865 };
1866
1867 static struct clk mmchs3_ick = {
1868 .name = "mmchs3_ick",
1869 .ops = &clkops_omap2_dflt_wait,
1870 .parent = &core_l4_ick,
1871 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1872 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1873 .clkdm_name = "core_l4_clkdm",
1874 .recalc = &followparent_recalc,
1875 };
1876
1877 /* Intersystem Communication Registers - chassis mode only */
1878 static struct clk icr_ick = {
1879 .name = "icr_ick",
1880 .ops = &clkops_omap2_dflt_wait,
1881 .parent = &core_l4_ick,
1882 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1883 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1884 .clkdm_name = "core_l4_clkdm",
1885 .recalc = &followparent_recalc,
1886 };
1887
1888 static struct clk aes2_ick = {
1889 .name = "aes2_ick",
1890 .ops = &clkops_omap2_dflt_wait,
1891 .parent = &core_l4_ick,
1892 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1893 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1894 .clkdm_name = "core_l4_clkdm",
1895 .recalc = &followparent_recalc,
1896 };
1897
1898 static struct clk sha12_ick = {
1899 .name = "sha12_ick",
1900 .ops = &clkops_omap2_dflt_wait,
1901 .parent = &core_l4_ick,
1902 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1903 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1904 .clkdm_name = "core_l4_clkdm",
1905 .recalc = &followparent_recalc,
1906 };
1907
1908 static struct clk des2_ick = {
1909 .name = "des2_ick",
1910 .ops = &clkops_omap2_dflt_wait,
1911 .parent = &core_l4_ick,
1912 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1913 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1914 .clkdm_name = "core_l4_clkdm",
1915 .recalc = &followparent_recalc,
1916 };
1917
1918 static struct clk mmchs2_ick = {
1919 .name = "mmchs2_ick",
1920 .ops = &clkops_omap2_dflt_wait,
1921 .parent = &core_l4_ick,
1922 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1923 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1924 .clkdm_name = "core_l4_clkdm",
1925 .recalc = &followparent_recalc,
1926 };
1927
1928 static struct clk mmchs1_ick = {
1929 .name = "mmchs1_ick",
1930 .ops = &clkops_omap2_dflt_wait,
1931 .parent = &core_l4_ick,
1932 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1933 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1934 .clkdm_name = "core_l4_clkdm",
1935 .recalc = &followparent_recalc,
1936 };
1937
1938 static struct clk mspro_ick = {
1939 .name = "mspro_ick",
1940 .ops = &clkops_omap2_dflt_wait,
1941 .parent = &core_l4_ick,
1942 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1943 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1944 .clkdm_name = "core_l4_clkdm",
1945 .recalc = &followparent_recalc,
1946 };
1947
1948 static struct clk hdq_ick = {
1949 .name = "hdq_ick",
1950 .ops = &clkops_omap2_dflt_wait,
1951 .parent = &core_l4_ick,
1952 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1953 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1954 .clkdm_name = "core_l4_clkdm",
1955 .recalc = &followparent_recalc,
1956 };
1957
1958 static struct clk mcspi4_ick = {
1959 .name = "mcspi4_ick",
1960 .ops = &clkops_omap2_dflt_wait,
1961 .parent = &core_l4_ick,
1962 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1963 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1964 .clkdm_name = "core_l4_clkdm",
1965 .recalc = &followparent_recalc,
1966 };
1967
1968 static struct clk mcspi3_ick = {
1969 .name = "mcspi3_ick",
1970 .ops = &clkops_omap2_dflt_wait,
1971 .parent = &core_l4_ick,
1972 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1973 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1974 .clkdm_name = "core_l4_clkdm",
1975 .recalc = &followparent_recalc,
1976 };
1977
1978 static struct clk mcspi2_ick = {
1979 .name = "mcspi2_ick",
1980 .ops = &clkops_omap2_dflt_wait,
1981 .parent = &core_l4_ick,
1982 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1983 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1984 .clkdm_name = "core_l4_clkdm",
1985 .recalc = &followparent_recalc,
1986 };
1987
1988 static struct clk mcspi1_ick = {
1989 .name = "mcspi1_ick",
1990 .ops = &clkops_omap2_dflt_wait,
1991 .parent = &core_l4_ick,
1992 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1993 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1994 .clkdm_name = "core_l4_clkdm",
1995 .recalc = &followparent_recalc,
1996 };
1997
1998 static struct clk i2c3_ick = {
1999 .name = "i2c3_ick",
2000 .ops = &clkops_omap2_dflt_wait,
2001 .parent = &core_l4_ick,
2002 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2003 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
2004 .clkdm_name = "core_l4_clkdm",
2005 .recalc = &followparent_recalc,
2006 };
2007
2008 static struct clk i2c2_ick = {
2009 .name = "i2c2_ick",
2010 .ops = &clkops_omap2_dflt_wait,
2011 .parent = &core_l4_ick,
2012 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2013 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
2014 .clkdm_name = "core_l4_clkdm",
2015 .recalc = &followparent_recalc,
2016 };
2017
2018 static struct clk i2c1_ick = {
2019 .name = "i2c1_ick",
2020 .ops = &clkops_omap2_dflt_wait,
2021 .parent = &core_l4_ick,
2022 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2023 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
2024 .clkdm_name = "core_l4_clkdm",
2025 .recalc = &followparent_recalc,
2026 };
2027
2028 static struct clk uart2_ick = {
2029 .name = "uart2_ick",
2030 .ops = &clkops_omap2_dflt_wait,
2031 .parent = &core_l4_ick,
2032 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2033 .enable_bit = OMAP3430_EN_UART2_SHIFT,
2034 .clkdm_name = "core_l4_clkdm",
2035 .recalc = &followparent_recalc,
2036 };
2037
2038 static struct clk uart1_ick = {
2039 .name = "uart1_ick",
2040 .ops = &clkops_omap2_dflt_wait,
2041 .parent = &core_l4_ick,
2042 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2043 .enable_bit = OMAP3430_EN_UART1_SHIFT,
2044 .clkdm_name = "core_l4_clkdm",
2045 .recalc = &followparent_recalc,
2046 };
2047
2048 static struct clk gpt11_ick = {
2049 .name = "gpt11_ick",
2050 .ops = &clkops_omap2_dflt_wait,
2051 .parent = &core_l4_ick,
2052 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2053 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
2054 .clkdm_name = "core_l4_clkdm",
2055 .recalc = &followparent_recalc,
2056 };
2057
2058 static struct clk gpt10_ick = {
2059 .name = "gpt10_ick",
2060 .ops = &clkops_omap2_dflt_wait,
2061 .parent = &core_l4_ick,
2062 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2063 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
2064 .clkdm_name = "core_l4_clkdm",
2065 .recalc = &followparent_recalc,
2066 };
2067
2068 static struct clk mcbsp5_ick = {
2069 .name = "mcbsp5_ick",
2070 .ops = &clkops_omap2_dflt_wait,
2071 .parent = &core_l4_ick,
2072 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2073 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
2074 .clkdm_name = "core_l4_clkdm",
2075 .recalc = &followparent_recalc,
2076 };
2077
2078 static struct clk mcbsp1_ick = {
2079 .name = "mcbsp1_ick",
2080 .ops = &clkops_omap2_dflt_wait,
2081 .parent = &core_l4_ick,
2082 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2083 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
2084 .clkdm_name = "core_l4_clkdm",
2085 .recalc = &followparent_recalc,
2086 };
2087
2088 static struct clk fac_ick = {
2089 .name = "fac_ick",
2090 .ops = &clkops_omap2_dflt_wait,
2091 .parent = &core_l4_ick,
2092 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2093 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
2094 .clkdm_name = "core_l4_clkdm",
2095 .recalc = &followparent_recalc,
2096 };
2097
2098 static struct clk mailboxes_ick = {
2099 .name = "mailboxes_ick",
2100 .ops = &clkops_omap2_dflt_wait,
2101 .parent = &core_l4_ick,
2102 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2103 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2104 .clkdm_name = "core_l4_clkdm",
2105 .recalc = &followparent_recalc,
2106 };
2107
2108 static struct clk omapctrl_ick = {
2109 .name = "omapctrl_ick",
2110 .ops = &clkops_omap2_dflt_wait,
2111 .parent = &core_l4_ick,
2112 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2113 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2114 .flags = ENABLE_ON_INIT,
2115 .recalc = &followparent_recalc,
2116 };
2117
2118 /* SSI_L4_ICK based clocks */
2119
2120 static struct clk ssi_l4_ick = {
2121 .name = "ssi_l4_ick",
2122 .ops = &clkops_null,
2123 .parent = &l4_ick,
2124 .clkdm_name = "core_l4_clkdm",
2125 .recalc = &followparent_recalc,
2126 };
2127
2128 static struct clk ssi_ick_3430es1 = {
2129 .name = "ssi_ick",
2130 .ops = &clkops_omap2_dflt,
2131 .parent = &ssi_l4_ick,
2132 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2133 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2134 .clkdm_name = "core_l4_clkdm",
2135 .recalc = &followparent_recalc,
2136 };
2137
2138 static struct clk ssi_ick_3430es2 = {
2139 .name = "ssi_ick",
2140 .ops = &clkops_omap3430es2_ssi_wait,
2141 .parent = &ssi_l4_ick,
2142 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2143 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2144 .clkdm_name = "core_l4_clkdm",
2145 .recalc = &followparent_recalc,
2146 };
2147
2148 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2149 * but l4_ick makes more sense to me */
2150
2151 static const struct clksel usb_l4_clksel[] = {
2152 { .parent = &l4_ick, .rates = div2_rates },
2153 { .parent = NULL },
2154 };
2155
2156 static struct clk usb_l4_ick = {
2157 .name = "usb_l4_ick",
2158 .ops = &clkops_omap2_dflt_wait,
2159 .parent = &l4_ick,
2160 .init = &omap2_init_clksel_parent,
2161 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2162 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2163 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2164 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2165 .clksel = usb_l4_clksel,
2166 .recalc = &omap2_clksel_recalc,
2167 };
2168
2169 /* SECURITY_L4_ICK2 based clocks */
2170
2171 static struct clk security_l4_ick2 = {
2172 .name = "security_l4_ick2",
2173 .ops = &clkops_null,
2174 .parent = &l4_ick,
2175 .recalc = &followparent_recalc,
2176 };
2177
2178 static struct clk aes1_ick = {
2179 .name = "aes1_ick",
2180 .ops = &clkops_omap2_dflt_wait,
2181 .parent = &security_l4_ick2,
2182 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2183 .enable_bit = OMAP3430_EN_AES1_SHIFT,
2184 .recalc = &followparent_recalc,
2185 };
2186
2187 static struct clk rng_ick = {
2188 .name = "rng_ick",
2189 .ops = &clkops_omap2_dflt_wait,
2190 .parent = &security_l4_ick2,
2191 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2192 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2193 .recalc = &followparent_recalc,
2194 };
2195
2196 static struct clk sha11_ick = {
2197 .name = "sha11_ick",
2198 .ops = &clkops_omap2_dflt_wait,
2199 .parent = &security_l4_ick2,
2200 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2201 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2202 .recalc = &followparent_recalc,
2203 };
2204
2205 static struct clk des1_ick = {
2206 .name = "des1_ick",
2207 .ops = &clkops_omap2_dflt_wait,
2208 .parent = &security_l4_ick2,
2209 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2210 .enable_bit = OMAP3430_EN_DES1_SHIFT,
2211 .recalc = &followparent_recalc,
2212 };
2213
2214 /* DSS */
2215 static struct clk dss1_alwon_fck_3430es1 = {
2216 .name = "dss1_alwon_fck",
2217 .ops = &clkops_omap2_dflt,
2218 .parent = &dpll4_m4x2_ck,
2219 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2220 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2221 .clkdm_name = "dss_clkdm",
2222 .recalc = &followparent_recalc,
2223 };
2224
2225 static struct clk dss1_alwon_fck_3430es2 = {
2226 .name = "dss1_alwon_fck",
2227 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2228 .parent = &dpll4_m4x2_ck,
2229 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2230 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2231 .clkdm_name = "dss_clkdm",
2232 .recalc = &followparent_recalc,
2233 };
2234
2235 static struct clk dss_tv_fck = {
2236 .name = "dss_tv_fck",
2237 .ops = &clkops_omap2_dflt,
2238 .parent = &omap_54m_fck,
2239 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2240 .enable_bit = OMAP3430_EN_TV_SHIFT,
2241 .clkdm_name = "dss_clkdm",
2242 .recalc = &followparent_recalc,
2243 };
2244
2245 static struct clk dss_96m_fck = {
2246 .name = "dss_96m_fck",
2247 .ops = &clkops_omap2_dflt,
2248 .parent = &omap_96m_fck,
2249 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2250 .enable_bit = OMAP3430_EN_TV_SHIFT,
2251 .clkdm_name = "dss_clkdm",
2252 .recalc = &followparent_recalc,
2253 };
2254
2255 static struct clk dss2_alwon_fck = {
2256 .name = "dss2_alwon_fck",
2257 .ops = &clkops_omap2_dflt,
2258 .parent = &sys_ck,
2259 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2260 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2261 .clkdm_name = "dss_clkdm",
2262 .recalc = &followparent_recalc,
2263 };
2264
2265 static struct clk dss_ick_3430es1 = {
2266 /* Handles both L3 and L4 clocks */
2267 .name = "dss_ick",
2268 .ops = &clkops_omap2_dflt,
2269 .parent = &l4_ick,
2270 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2271 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2272 .clkdm_name = "dss_clkdm",
2273 .recalc = &followparent_recalc,
2274 };
2275
2276 static struct clk dss_ick_3430es2 = {
2277 /* Handles both L3 and L4 clocks */
2278 .name = "dss_ick",
2279 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2280 .parent = &l4_ick,
2281 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2282 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2283 .clkdm_name = "dss_clkdm",
2284 .recalc = &followparent_recalc,
2285 };
2286
2287 /* CAM */
2288
2289 static struct clk cam_mclk = {
2290 .name = "cam_mclk",
2291 .ops = &clkops_omap2_dflt,
2292 .parent = &dpll4_m5x2_ck,
2293 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2294 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2295 .clkdm_name = "cam_clkdm",
2296 .recalc = &followparent_recalc,
2297 };
2298
2299 static struct clk cam_ick = {
2300 /* Handles both L3 and L4 clocks */
2301 .name = "cam_ick",
2302 .ops = &clkops_omap2_dflt,
2303 .parent = &l4_ick,
2304 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2305 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2306 .clkdm_name = "cam_clkdm",
2307 .recalc = &followparent_recalc,
2308 };
2309
2310 static struct clk csi2_96m_fck = {
2311 .name = "csi2_96m_fck",
2312 .ops = &clkops_omap2_dflt,
2313 .parent = &core_96m_fck,
2314 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2315 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
2316 .clkdm_name = "cam_clkdm",
2317 .recalc = &followparent_recalc,
2318 };
2319
2320 /* USBHOST - 3430ES2 only */
2321
2322 static struct clk usbhost_120m_fck = {
2323 .name = "usbhost_120m_fck",
2324 .ops = &clkops_omap2_dflt,
2325 .parent = &dpll5_m2_ck,
2326 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2327 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2328 .clkdm_name = "usbhost_clkdm",
2329 .recalc = &followparent_recalc,
2330 };
2331
2332 static struct clk usbhost_48m_fck = {
2333 .name = "usbhost_48m_fck",
2334 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2335 .parent = &omap_48m_fck,
2336 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2337 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2338 .clkdm_name = "usbhost_clkdm",
2339 .recalc = &followparent_recalc,
2340 };
2341
2342 static struct clk usbhost_ick = {
2343 /* Handles both L3 and L4 clocks */
2344 .name = "usbhost_ick",
2345 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2346 .parent = &l4_ick,
2347 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2348 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2349 .clkdm_name = "usbhost_clkdm",
2350 .recalc = &followparent_recalc,
2351 };
2352
2353 /* WKUP */
2354
2355 static const struct clksel_rate usim_96m_rates[] = {
2356 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2357 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2358 { .div = 8, .val = 5, .flags = RATE_IN_343X },
2359 { .div = 10, .val = 6, .flags = RATE_IN_343X },
2360 { .div = 0 },
2361 };
2362
2363 static const struct clksel_rate usim_120m_rates[] = {
2364 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
2365 { .div = 8, .val = 8, .flags = RATE_IN_343X },
2366 { .div = 16, .val = 9, .flags = RATE_IN_343X },
2367 { .div = 20, .val = 10, .flags = RATE_IN_343X },
2368 { .div = 0 },
2369 };
2370
2371 static const struct clksel usim_clksel[] = {
2372 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2373 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
2374 { .parent = &sys_ck, .rates = div2_rates },
2375 { .parent = NULL },
2376 };
2377
2378 /* 3430ES2 only */
2379 static struct clk usim_fck = {
2380 .name = "usim_fck",
2381 .ops = &clkops_omap2_dflt_wait,
2382 .init = &omap2_init_clksel_parent,
2383 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2384 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2385 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2386 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2387 .clksel = usim_clksel,
2388 .recalc = &omap2_clksel_recalc,
2389 };
2390
2391 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2392 static struct clk gpt1_fck = {
2393 .name = "gpt1_fck",
2394 .ops = &clkops_omap2_dflt_wait,
2395 .init = &omap2_init_clksel_parent,
2396 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2397 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2398 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2399 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2400 .clksel = omap343x_gpt_clksel,
2401 .clkdm_name = "wkup_clkdm",
2402 .recalc = &omap2_clksel_recalc,
2403 };
2404
2405 static struct clk wkup_32k_fck = {
2406 .name = "wkup_32k_fck",
2407 .ops = &clkops_null,
2408 .parent = &omap_32k_fck,
2409 .clkdm_name = "wkup_clkdm",
2410 .recalc = &followparent_recalc,
2411 };
2412
2413 static struct clk gpio1_dbck = {
2414 .name = "gpio1_dbck",
2415 .ops = &clkops_omap2_dflt,
2416 .parent = &wkup_32k_fck,
2417 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2418 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2419 .clkdm_name = "wkup_clkdm",
2420 .recalc = &followparent_recalc,
2421 };
2422
2423 static struct clk wdt2_fck = {
2424 .name = "wdt2_fck",
2425 .ops = &clkops_omap2_dflt_wait,
2426 .parent = &wkup_32k_fck,
2427 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2428 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2429 .clkdm_name = "wkup_clkdm",
2430 .recalc = &followparent_recalc,
2431 };
2432
2433 static struct clk wkup_l4_ick = {
2434 .name = "wkup_l4_ick",
2435 .ops = &clkops_null,
2436 .parent = &sys_ck,
2437 .clkdm_name = "wkup_clkdm",
2438 .recalc = &followparent_recalc,
2439 };
2440
2441 /* 3430ES2 only */
2442 /* Never specifically named in the TRM, so we have to infer a likely name */
2443 static struct clk usim_ick = {
2444 .name = "usim_ick",
2445 .ops = &clkops_omap2_dflt_wait,
2446 .parent = &wkup_l4_ick,
2447 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2448 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2449 .clkdm_name = "wkup_clkdm",
2450 .recalc = &followparent_recalc,
2451 };
2452
2453 static struct clk wdt2_ick = {
2454 .name = "wdt2_ick",
2455 .ops = &clkops_omap2_dflt_wait,
2456 .parent = &wkup_l4_ick,
2457 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2458 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2459 .clkdm_name = "wkup_clkdm",
2460 .recalc = &followparent_recalc,
2461 };
2462
2463 static struct clk wdt1_ick = {
2464 .name = "wdt1_ick",
2465 .ops = &clkops_omap2_dflt_wait,
2466 .parent = &wkup_l4_ick,
2467 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2468 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2469 .clkdm_name = "wkup_clkdm",
2470 .recalc = &followparent_recalc,
2471 };
2472
2473 static struct clk gpio1_ick = {
2474 .name = "gpio1_ick",
2475 .ops = &clkops_omap2_dflt_wait,
2476 .parent = &wkup_l4_ick,
2477 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2478 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2479 .clkdm_name = "wkup_clkdm",
2480 .recalc = &followparent_recalc,
2481 };
2482
2483 static struct clk omap_32ksync_ick = {
2484 .name = "omap_32ksync_ick",
2485 .ops = &clkops_omap2_dflt_wait,
2486 .parent = &wkup_l4_ick,
2487 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2488 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2489 .clkdm_name = "wkup_clkdm",
2490 .recalc = &followparent_recalc,
2491 };
2492
2493 /* XXX This clock no longer exists in 3430 TRM rev F */
2494 static struct clk gpt12_ick = {
2495 .name = "gpt12_ick",
2496 .ops = &clkops_omap2_dflt_wait,
2497 .parent = &wkup_l4_ick,
2498 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2499 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2500 .clkdm_name = "wkup_clkdm",
2501 .recalc = &followparent_recalc,
2502 };
2503
2504 static struct clk gpt1_ick = {
2505 .name = "gpt1_ick",
2506 .ops = &clkops_omap2_dflt_wait,
2507 .parent = &wkup_l4_ick,
2508 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2509 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2510 .clkdm_name = "wkup_clkdm",
2511 .recalc = &followparent_recalc,
2512 };
2513
2514
2515
2516 /* PER clock domain */
2517
2518 static struct clk per_96m_fck = {
2519 .name = "per_96m_fck",
2520 .ops = &clkops_null,
2521 .parent = &omap_96m_alwon_fck,
2522 .clkdm_name = "per_clkdm",
2523 .recalc = &followparent_recalc,
2524 };
2525
2526 static struct clk per_48m_fck = {
2527 .name = "per_48m_fck",
2528 .ops = &clkops_null,
2529 .parent = &omap_48m_fck,
2530 .clkdm_name = "per_clkdm",
2531 .recalc = &followparent_recalc,
2532 };
2533
2534 static struct clk uart3_fck = {
2535 .name = "uart3_fck",
2536 .ops = &clkops_omap2_dflt_wait,
2537 .parent = &per_48m_fck,
2538 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2539 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2540 .clkdm_name = "per_clkdm",
2541 .recalc = &followparent_recalc,
2542 };
2543
2544 static struct clk gpt2_fck = {
2545 .name = "gpt2_fck",
2546 .ops = &clkops_omap2_dflt_wait,
2547 .init = &omap2_init_clksel_parent,
2548 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2549 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2550 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2551 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2552 .clksel = omap343x_gpt_clksel,
2553 .clkdm_name = "per_clkdm",
2554 .recalc = &omap2_clksel_recalc,
2555 };
2556
2557 static struct clk gpt3_fck = {
2558 .name = "gpt3_fck",
2559 .ops = &clkops_omap2_dflt_wait,
2560 .init = &omap2_init_clksel_parent,
2561 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2562 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2563 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2564 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2565 .clksel = omap343x_gpt_clksel,
2566 .clkdm_name = "per_clkdm",
2567 .recalc = &omap2_clksel_recalc,
2568 };
2569
2570 static struct clk gpt4_fck = {
2571 .name = "gpt4_fck",
2572 .ops = &clkops_omap2_dflt_wait,
2573 .init = &omap2_init_clksel_parent,
2574 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2575 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2576 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2577 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2578 .clksel = omap343x_gpt_clksel,
2579 .clkdm_name = "per_clkdm",
2580 .recalc = &omap2_clksel_recalc,
2581 };
2582
2583 static struct clk gpt5_fck = {
2584 .name = "gpt5_fck",
2585 .ops = &clkops_omap2_dflt_wait,
2586 .init = &omap2_init_clksel_parent,
2587 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2588 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2589 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2590 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2591 .clksel = omap343x_gpt_clksel,
2592 .clkdm_name = "per_clkdm",
2593 .recalc = &omap2_clksel_recalc,
2594 };
2595
2596 static struct clk gpt6_fck = {
2597 .name = "gpt6_fck",
2598 .ops = &clkops_omap2_dflt_wait,
2599 .init = &omap2_init_clksel_parent,
2600 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2601 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2602 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2603 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2604 .clksel = omap343x_gpt_clksel,
2605 .clkdm_name = "per_clkdm",
2606 .recalc = &omap2_clksel_recalc,
2607 };
2608
2609 static struct clk gpt7_fck = {
2610 .name = "gpt7_fck",
2611 .ops = &clkops_omap2_dflt_wait,
2612 .init = &omap2_init_clksel_parent,
2613 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2614 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2615 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2616 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2617 .clksel = omap343x_gpt_clksel,
2618 .clkdm_name = "per_clkdm",
2619 .recalc = &omap2_clksel_recalc,
2620 };
2621
2622 static struct clk gpt8_fck = {
2623 .name = "gpt8_fck",
2624 .ops = &clkops_omap2_dflt_wait,
2625 .init = &omap2_init_clksel_parent,
2626 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2627 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2628 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2629 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2630 .clksel = omap343x_gpt_clksel,
2631 .clkdm_name = "per_clkdm",
2632 .recalc = &omap2_clksel_recalc,
2633 };
2634
2635 static struct clk gpt9_fck = {
2636 .name = "gpt9_fck",
2637 .ops = &clkops_omap2_dflt_wait,
2638 .init = &omap2_init_clksel_parent,
2639 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2640 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2641 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2642 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2643 .clksel = omap343x_gpt_clksel,
2644 .clkdm_name = "per_clkdm",
2645 .recalc = &omap2_clksel_recalc,
2646 };
2647
2648 static struct clk per_32k_alwon_fck = {
2649 .name = "per_32k_alwon_fck",
2650 .ops = &clkops_null,
2651 .parent = &omap_32k_fck,
2652 .clkdm_name = "per_clkdm",
2653 .recalc = &followparent_recalc,
2654 };
2655
2656 static struct clk gpio6_dbck = {
2657 .name = "gpio6_dbck",
2658 .ops = &clkops_omap2_dflt,
2659 .parent = &per_32k_alwon_fck,
2660 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2661 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2662 .clkdm_name = "per_clkdm",
2663 .recalc = &followparent_recalc,
2664 };
2665
2666 static struct clk gpio5_dbck = {
2667 .name = "gpio5_dbck",
2668 .ops = &clkops_omap2_dflt,
2669 .parent = &per_32k_alwon_fck,
2670 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2671 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2672 .clkdm_name = "per_clkdm",
2673 .recalc = &followparent_recalc,
2674 };
2675
2676 static struct clk gpio4_dbck = {
2677 .name = "gpio4_dbck",
2678 .ops = &clkops_omap2_dflt,
2679 .parent = &per_32k_alwon_fck,
2680 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2681 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2682 .clkdm_name = "per_clkdm",
2683 .recalc = &followparent_recalc,
2684 };
2685
2686 static struct clk gpio3_dbck = {
2687 .name = "gpio3_dbck",
2688 .ops = &clkops_omap2_dflt,
2689 .parent = &per_32k_alwon_fck,
2690 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2691 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2692 .clkdm_name = "per_clkdm",
2693 .recalc = &followparent_recalc,
2694 };
2695
2696 static struct clk gpio2_dbck = {
2697 .name = "gpio2_dbck",
2698 .ops = &clkops_omap2_dflt,
2699 .parent = &per_32k_alwon_fck,
2700 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2701 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2702 .clkdm_name = "per_clkdm",
2703 .recalc = &followparent_recalc,
2704 };
2705
2706 static struct clk wdt3_fck = {
2707 .name = "wdt3_fck",
2708 .ops = &clkops_omap2_dflt_wait,
2709 .parent = &per_32k_alwon_fck,
2710 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2711 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2712 .clkdm_name = "per_clkdm",
2713 .recalc = &followparent_recalc,
2714 };
2715
2716 static struct clk per_l4_ick = {
2717 .name = "per_l4_ick",
2718 .ops = &clkops_null,
2719 .parent = &l4_ick,
2720 .clkdm_name = "per_clkdm",
2721 .recalc = &followparent_recalc,
2722 };
2723
2724 static struct clk gpio6_ick = {
2725 .name = "gpio6_ick",
2726 .ops = &clkops_omap2_dflt_wait,
2727 .parent = &per_l4_ick,
2728 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2729 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2730 .clkdm_name = "per_clkdm",
2731 .recalc = &followparent_recalc,
2732 };
2733
2734 static struct clk gpio5_ick = {
2735 .name = "gpio5_ick",
2736 .ops = &clkops_omap2_dflt_wait,
2737 .parent = &per_l4_ick,
2738 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2739 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2740 .clkdm_name = "per_clkdm",
2741 .recalc = &followparent_recalc,
2742 };
2743
2744 static struct clk gpio4_ick = {
2745 .name = "gpio4_ick",
2746 .ops = &clkops_omap2_dflt_wait,
2747 .parent = &per_l4_ick,
2748 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2749 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2750 .clkdm_name = "per_clkdm",
2751 .recalc = &followparent_recalc,
2752 };
2753
2754 static struct clk gpio3_ick = {
2755 .name = "gpio3_ick",
2756 .ops = &clkops_omap2_dflt_wait,
2757 .parent = &per_l4_ick,
2758 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2759 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2760 .clkdm_name = "per_clkdm",
2761 .recalc = &followparent_recalc,
2762 };
2763
2764 static struct clk gpio2_ick = {
2765 .name = "gpio2_ick",
2766 .ops = &clkops_omap2_dflt_wait,
2767 .parent = &per_l4_ick,
2768 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2769 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2770 .clkdm_name = "per_clkdm",
2771 .recalc = &followparent_recalc,
2772 };
2773
2774 static struct clk wdt3_ick = {
2775 .name = "wdt3_ick",
2776 .ops = &clkops_omap2_dflt_wait,
2777 .parent = &per_l4_ick,
2778 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2779 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2780 .clkdm_name = "per_clkdm",
2781 .recalc = &followparent_recalc,
2782 };
2783
2784 static struct clk uart3_ick = {
2785 .name = "uart3_ick",
2786 .ops = &clkops_omap2_dflt_wait,
2787 .parent = &per_l4_ick,
2788 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2789 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2790 .clkdm_name = "per_clkdm",
2791 .recalc = &followparent_recalc,
2792 };
2793
2794 static struct clk gpt9_ick = {
2795 .name = "gpt9_ick",
2796 .ops = &clkops_omap2_dflt_wait,
2797 .parent = &per_l4_ick,
2798 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2799 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2800 .clkdm_name = "per_clkdm",
2801 .recalc = &followparent_recalc,
2802 };
2803
2804 static struct clk gpt8_ick = {
2805 .name = "gpt8_ick",
2806 .ops = &clkops_omap2_dflt_wait,
2807 .parent = &per_l4_ick,
2808 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2809 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2810 .clkdm_name = "per_clkdm",
2811 .recalc = &followparent_recalc,
2812 };
2813
2814 static struct clk gpt7_ick = {
2815 .name = "gpt7_ick",
2816 .ops = &clkops_omap2_dflt_wait,
2817 .parent = &per_l4_ick,
2818 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2819 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2820 .clkdm_name = "per_clkdm",
2821 .recalc = &followparent_recalc,
2822 };
2823
2824 static struct clk gpt6_ick = {
2825 .name = "gpt6_ick",
2826 .ops = &clkops_omap2_dflt_wait,
2827 .parent = &per_l4_ick,
2828 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2829 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2830 .clkdm_name = "per_clkdm",
2831 .recalc = &followparent_recalc,
2832 };
2833
2834 static struct clk gpt5_ick = {
2835 .name = "gpt5_ick",
2836 .ops = &clkops_omap2_dflt_wait,
2837 .parent = &per_l4_ick,
2838 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2839 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2840 .clkdm_name = "per_clkdm",
2841 .recalc = &followparent_recalc,
2842 };
2843
2844 static struct clk gpt4_ick = {
2845 .name = "gpt4_ick",
2846 .ops = &clkops_omap2_dflt_wait,
2847 .parent = &per_l4_ick,
2848 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2849 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2850 .clkdm_name = "per_clkdm",
2851 .recalc = &followparent_recalc,
2852 };
2853
2854 static struct clk gpt3_ick = {
2855 .name = "gpt3_ick",
2856 .ops = &clkops_omap2_dflt_wait,
2857 .parent = &per_l4_ick,
2858 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2859 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2860 .clkdm_name = "per_clkdm",
2861 .recalc = &followparent_recalc,
2862 };
2863
2864 static struct clk gpt2_ick = {
2865 .name = "gpt2_ick",
2866 .ops = &clkops_omap2_dflt_wait,
2867 .parent = &per_l4_ick,
2868 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2869 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2870 .clkdm_name = "per_clkdm",
2871 .recalc = &followparent_recalc,
2872 };
2873
2874 static struct clk mcbsp2_ick = {
2875 .name = "mcbsp2_ick",
2876 .ops = &clkops_omap2_dflt_wait,
2877 .parent = &per_l4_ick,
2878 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2879 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2880 .clkdm_name = "per_clkdm",
2881 .recalc = &followparent_recalc,
2882 };
2883
2884 static struct clk mcbsp3_ick = {
2885 .name = "mcbsp3_ick",
2886 .ops = &clkops_omap2_dflt_wait,
2887 .parent = &per_l4_ick,
2888 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2889 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2890 .clkdm_name = "per_clkdm",
2891 .recalc = &followparent_recalc,
2892 };
2893
2894 static struct clk mcbsp4_ick = {
2895 .name = "mcbsp4_ick",
2896 .ops = &clkops_omap2_dflt_wait,
2897 .parent = &per_l4_ick,
2898 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2899 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2900 .clkdm_name = "per_clkdm",
2901 .recalc = &followparent_recalc,
2902 };
2903
2904 static const struct clksel mcbsp_234_clksel[] = {
2905 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2906 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2907 { .parent = NULL }
2908 };
2909
2910 static struct clk mcbsp2_fck = {
2911 .name = "mcbsp2_fck",
2912 .ops = &clkops_omap2_dflt_wait,
2913 .init = &omap2_init_clksel_parent,
2914 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2915 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2916 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2917 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2918 .clksel = mcbsp_234_clksel,
2919 .clkdm_name = "per_clkdm",
2920 .recalc = &omap2_clksel_recalc,
2921 };
2922
2923 static struct clk mcbsp3_fck = {
2924 .name = "mcbsp3_fck",
2925 .ops = &clkops_omap2_dflt_wait,
2926 .init = &omap2_init_clksel_parent,
2927 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2928 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2929 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2930 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2931 .clksel = mcbsp_234_clksel,
2932 .clkdm_name = "per_clkdm",
2933 .recalc = &omap2_clksel_recalc,
2934 };
2935
2936 static struct clk mcbsp4_fck = {
2937 .name = "mcbsp4_fck",
2938 .ops = &clkops_omap2_dflt_wait,
2939 .init = &omap2_init_clksel_parent,
2940 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2941 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2942 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2943 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2944 .clksel = mcbsp_234_clksel,
2945 .clkdm_name = "per_clkdm",
2946 .recalc = &omap2_clksel_recalc,
2947 };
2948
2949 /* EMU clocks */
2950
2951 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2952
2953 static const struct clksel_rate emu_src_sys_rates[] = {
2954 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2955 { .div = 0 },
2956 };
2957
2958 static const struct clksel_rate emu_src_core_rates[] = {
2959 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2960 { .div = 0 },
2961 };
2962
2963 static const struct clksel_rate emu_src_per_rates[] = {
2964 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2965 { .div = 0 },
2966 };
2967
2968 static const struct clksel_rate emu_src_mpu_rates[] = {
2969 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2970 { .div = 0 },
2971 };
2972
2973 static const struct clksel emu_src_clksel[] = {
2974 { .parent = &sys_ck, .rates = emu_src_sys_rates },
2975 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2976 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
2977 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
2978 { .parent = NULL },
2979 };
2980
2981 /*
2982 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2983 * to switch the source of some of the EMU clocks.
2984 * XXX Are there CLKEN bits for these EMU clks?
2985 */
2986 static struct clk emu_src_ck = {
2987 .name = "emu_src_ck",
2988 .ops = &clkops_null,
2989 .init = &omap2_init_clksel_parent,
2990 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2991 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2992 .clksel = emu_src_clksel,
2993 .clkdm_name = "emu_clkdm",
2994 .recalc = &omap2_clksel_recalc,
2995 };
2996
2997 static const struct clksel_rate pclk_emu_rates[] = {
2998 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2999 { .div = 3, .val = 3, .flags = RATE_IN_343X },
3000 { .div = 4, .val = 4, .flags = RATE_IN_343X },
3001 { .div = 6, .val = 6, .flags = RATE_IN_343X },
3002 { .div = 0 },
3003 };
3004
3005 static const struct clksel pclk_emu_clksel[] = {
3006 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
3007 { .parent = NULL },
3008 };
3009
3010 static struct clk pclk_fck = {
3011 .name = "pclk_fck",
3012 .ops = &clkops_null,
3013 .init = &omap2_init_clksel_parent,
3014 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3015 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
3016 .clksel = pclk_emu_clksel,
3017 .clkdm_name = "emu_clkdm",
3018 .recalc = &omap2_clksel_recalc,
3019 };
3020
3021 static const struct clksel_rate pclkx2_emu_rates[] = {
3022 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3023 { .div = 2, .val = 2, .flags = RATE_IN_343X },
3024 { .div = 3, .val = 3, .flags = RATE_IN_343X },
3025 { .div = 0 },
3026 };
3027
3028 static const struct clksel pclkx2_emu_clksel[] = {
3029 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
3030 { .parent = NULL },
3031 };
3032
3033 static struct clk pclkx2_fck = {
3034 .name = "pclkx2_fck",
3035 .ops = &clkops_null,
3036 .init = &omap2_init_clksel_parent,
3037 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3038 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
3039 .clksel = pclkx2_emu_clksel,
3040 .clkdm_name = "emu_clkdm",
3041 .recalc = &omap2_clksel_recalc,
3042 };
3043
3044 static const struct clksel atclk_emu_clksel[] = {
3045 { .parent = &emu_src_ck, .rates = div2_rates },
3046 { .parent = NULL },
3047 };
3048
3049 static struct clk atclk_fck = {
3050 .name = "atclk_fck",
3051 .ops = &clkops_null,
3052 .init = &omap2_init_clksel_parent,
3053 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3054 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
3055 .clksel = atclk_emu_clksel,
3056 .clkdm_name = "emu_clkdm",
3057 .recalc = &omap2_clksel_recalc,
3058 };
3059
3060 static struct clk traceclk_src_fck = {
3061 .name = "traceclk_src_fck",
3062 .ops = &clkops_null,
3063 .init = &omap2_init_clksel_parent,
3064 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3065 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
3066 .clksel = emu_src_clksel,
3067 .clkdm_name = "emu_clkdm",
3068 .recalc = &omap2_clksel_recalc,
3069 };
3070
3071 static const struct clksel_rate traceclk_rates[] = {
3072 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3073 { .div = 2, .val = 2, .flags = RATE_IN_343X },
3074 { .div = 4, .val = 4, .flags = RATE_IN_343X },
3075 { .div = 0 },
3076 };
3077
3078 static const struct clksel traceclk_clksel[] = {
3079 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3080 { .parent = NULL },
3081 };
3082
3083 static struct clk traceclk_fck = {
3084 .name = "traceclk_fck",
3085 .ops = &clkops_null,
3086 .init = &omap2_init_clksel_parent,
3087 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3088 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
3089 .clksel = traceclk_clksel,
3090 .clkdm_name = "emu_clkdm",
3091 .recalc = &omap2_clksel_recalc,
3092 };
3093
3094 /* SR clocks */
3095
3096 /* SmartReflex fclk (VDD1) */
3097 static struct clk sr1_fck = {
3098 .name = "sr1_fck",
3099 .ops = &clkops_omap2_dflt_wait,
3100 .parent = &sys_ck,
3101 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3102 .enable_bit = OMAP3430_EN_SR1_SHIFT,
3103 .recalc = &followparent_recalc,
3104 };
3105
3106 /* SmartReflex fclk (VDD2) */
3107 static struct clk sr2_fck = {
3108 .name = "sr2_fck",
3109 .ops = &clkops_omap2_dflt_wait,
3110 .parent = &sys_ck,
3111 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3112 .enable_bit = OMAP3430_EN_SR2_SHIFT,
3113 .recalc = &followparent_recalc,
3114 };
3115
3116 static struct clk sr_l4_ick = {
3117 .name = "sr_l4_ick",
3118 .ops = &clkops_null, /* RMK: missing? */
3119 .parent = &l4_ick,
3120 .clkdm_name = "core_l4_clkdm",
3121 .recalc = &followparent_recalc,
3122 };
3123
3124 /* SECURE_32K_FCK clocks */
3125
3126 static struct clk gpt12_fck = {
3127 .name = "gpt12_fck",
3128 .ops = &clkops_null,
3129 .parent = &secure_32k_fck,
3130 .recalc = &followparent_recalc,
3131 };
3132
3133 static struct clk wdt1_fck = {
3134 .name = "wdt1_fck",
3135 .ops = &clkops_null,
3136 .parent = &secure_32k_fck,
3137 .recalc = &followparent_recalc,
3138 };
3139
3140 /* Clocks for AM35XX */
3141 static struct clk ipss_ick = {
3142 .name = "ipss_ick",
3143 .ops = &clkops_am35xx_ipss_wait,
3144 .parent = &core_l3_ick,
3145 .clkdm_name = "core_l3_clkdm",
3146 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3147 .enable_bit = AM35XX_EN_IPSS_SHIFT,
3148 .recalc = &followparent_recalc,
3149 };
3150
3151 static struct clk emac_ick = {
3152 .name = "emac_ick",
3153 .ops = &clkops_am35xx_ipss_module_wait,
3154 .parent = &ipss_ick,
3155 .clkdm_name = "core_l3_clkdm",
3156 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3157 .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
3158 .recalc = &followparent_recalc,
3159 };
3160
3161 static struct clk rmii_ck = {
3162 .name = "rmii_ck",
3163 .ops = &clkops_null,
3164 .rate = 50000000,
3165 };
3166
3167 static struct clk emac_fck = {
3168 .name = "emac_fck",
3169 .ops = &clkops_omap2_dflt,
3170 .parent = &rmii_ck,
3171 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3172 .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT,
3173 .recalc = &followparent_recalc,
3174 };
3175
3176 static struct clk hsotgusb_ick_am35xx = {
3177 .name = "hsotgusb_ick",
3178 .ops = &clkops_am35xx_ipss_module_wait,
3179 .parent = &ipss_ick,
3180 .clkdm_name = "core_l3_clkdm",
3181 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3182 .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
3183 .recalc = &followparent_recalc,
3184 };
3185
3186 static struct clk hsotgusb_fck_am35xx = {
3187 .name = "hsotgusb_fck",
3188 .ops = &clkops_omap2_dflt,
3189 .parent = &sys_ck,
3190 .clkdm_name = "core_l3_clkdm",
3191 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3192 .enable_bit = AM35XX_USBOTG_FCLK_SHIFT,
3193 .recalc = &followparent_recalc,
3194 };
3195
3196 static struct clk hecc_ck = {
3197 .name = "hecc_ck",
3198 .ops = &clkops_am35xx_ipss_module_wait,
3199 .parent = &sys_ck,
3200 .clkdm_name = "core_l3_clkdm",
3201 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3202 .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT,
3203 .recalc = &followparent_recalc,
3204 };
3205
3206 static struct clk vpfe_ick = {
3207 .name = "vpfe_ick",
3208 .ops = &clkops_am35xx_ipss_module_wait,
3209 .parent = &ipss_ick,
3210 .clkdm_name = "core_l3_clkdm",
3211 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3212 .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3213 .recalc = &followparent_recalc,
3214 };
3215
3216 static struct clk pclk_ck = {
3217 .name = "pclk_ck",
3218 .ops = &clkops_null,
3219 .rate = 27000000,
3220 };
3221
3222 static struct clk vpfe_fck = {
3223 .name = "vpfe_fck",
3224 .ops = &clkops_omap2_dflt,
3225 .parent = &pclk_ck,
3226 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3227 .enable_bit = AM35XX_VPFE_FCLK_SHIFT,
3228 .recalc = &followparent_recalc,
3229 };
3230
3231 /*
3232 * The UART1/2 functional clock acts as the functional
3233 * clock for UART4. No separate fclk control available.
3234 */
3235 static struct clk uart4_ick_am35xx = {
3236 .name = "uart4_ick",
3237 .ops = &clkops_omap2_dflt_wait,
3238 .parent = &core_l4_ick,
3239 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3240 .enable_bit = AM35XX_EN_UART4_SHIFT,
3241 .clkdm_name = "core_l4_clkdm",
3242 .recalc = &followparent_recalc,
3243 };
3244
3245
3246 /*
3247 * clkdev
3248 */
3249
3250 /* XXX At some point we should rename this file to clock3xxx_data.c */
3251 static struct omap_clk omap3xxx_clks[] = {
3252 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX),
3253 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX),
3254 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX),
3255 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2 | CK_AM35XX),
3256 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
3257 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX),
3258 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
3259 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX),
3260 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX),
3261 CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX),
3262 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX),
3263 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX),
3264 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX),
3265 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX),
3266 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
3267 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X),
3268 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X),
3269 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX),
3270 CLK(NULL, "core_ck", &core_ck, CK_3XXX),
3271 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX),
3272 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX),
3273 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
3274 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX),
3275 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
3276 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
3277 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX),
3278 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX),
3279 CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
3280 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
3281 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX),
3282 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX),
3283 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX),
3284 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX),
3285 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX),
3286 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX),
3287 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
3288 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX),
3289 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
3290 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX),
3291 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
3292 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX),
3293 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
3294 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX),
3295 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
3296 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3297 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2 | CK_AM35XX),
3298 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2 | CK_AM35XX),
3299 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
3300 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX),
3301 CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX),
3302 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX),
3303 CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX),
3304 CLK(NULL, "arm_fck", &arm_fck, CK_3XXX),
3305 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
3306 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X),
3307 CLK(NULL, "iva2_ck", &iva2_ck, CK_343X),
3308 CLK(NULL, "l3_ick", &l3_ick, CK_3XXX),
3309 CLK(NULL, "l4_ick", &l4_ick, CK_3XXX),
3310 CLK(NULL, "rm_ick", &rm_ick, CK_3XXX),
3311 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
3312 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
3313 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
3314 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
3315 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
3316 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2 | CK_3517),
3317 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2 | CK_3517),
3318 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
3319 CLK(NULL, "modem_fck", &modem_fck, CK_343X),
3320 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X),
3321 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X),
3322 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX),
3323 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX),
3324 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2 | CK_AM35XX),
3325 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2 | CK_AM35XX),
3326 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_AM35XX),
3327 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
3328 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2 | CK_AM35XX),
3329 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX),
3330 CLK(NULL, "mspro_fck", &mspro_fck, CK_343X),
3331 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX),
3332 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_3XXX),
3333 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_3XXX),
3334 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_3XXX),
3335 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_3XXX),
3336 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_3XXX),
3337 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX),
3338 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_3XXX),
3339 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_3XXX),
3340 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_3XXX),
3341 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_3XXX),
3342 CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX),
3343 CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX),
3344 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
3345 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
3346 CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
3347 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
3348 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2),
3349 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
3350 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2),
3351 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX),
3352 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
3353 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2),
3354 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX),
3355 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX),
3356 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
3357 CLK(NULL, "pka_ick", &pka_ick, CK_343X),
3358 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
3359 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2 | CK_AM35XX),
3360 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2 | CK_AM35XX),
3361 CLK(NULL, "icr_ick", &icr_ick, CK_343X),
3362 CLK(NULL, "aes2_ick", &aes2_ick, CK_343X),
3363 CLK("omap-sham", "ick", &sha12_ick, CK_343X),
3364 CLK(NULL, "des2_ick", &des2_ick, CK_343X),
3365 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX),
3366 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX),
3367 CLK(NULL, "mspro_ick", &mspro_ick, CK_343X),
3368 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
3369 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
3370 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX),
3371 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX),
3372 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX),
3373 CLK("i2c_omap.3", "ick", &i2c3_ick, CK_3XXX),
3374 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_3XXX),
3375 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_3XXX),
3376 CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX),
3377 CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX),
3378 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX),
3379 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX),
3380 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX),
3381 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX),
3382 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
3383 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
3384 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX),
3385 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
3386 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
3387 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2),
3388 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
3389 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
3390 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
3391 CLK("omap_rng", "ick", &rng_ick, CK_343X),
3392 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
3393 CLK(NULL, "des1_ick", &des1_ick, CK_343X),
3394 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
3395 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2 | CK_AM35XX),
3396 CLK("omapdss", "tv_fck", &dss_tv_fck, CK_3XXX),
3397 CLK("omapdss", "video_fck", &dss_96m_fck, CK_3XXX),
3398 CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_3XXX),
3399 CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1),
3400 CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2 | CK_AM35XX),
3401 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
3402 CLK(NULL, "cam_ick", &cam_ick, CK_343X),
3403 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
3404 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2 | CK_AM35XX),
3405 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2 | CK_AM35XX),
3406 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2 | CK_AM35XX),
3407 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2),
3408 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
3409 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
3410 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
3411 CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX),
3412 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X),
3413 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2),
3414 CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
3415 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX),
3416 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX),
3417 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3418 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX),
3419 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX),
3420 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX),
3421 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
3422 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
3423 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
3424 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
3425 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
3426 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX),
3427 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX),
3428 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX),
3429 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX),
3430 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX),
3431 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
3432 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX),
3433 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX),
3434 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_3XXX),
3435 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_3XXX),
3436 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_3XXX),
3437 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_3XXX),
3438 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_3XXX),
3439 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_3XXX),
3440 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_3XXX),
3441 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_3XXX),
3442 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_3XXX),
3443 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX),
3444 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX),
3445 CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX),
3446 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX),
3447 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX),
3448 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX),
3449 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_3XXX),
3450 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_3XXX),
3451 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_3XXX),
3452 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_3XXX),
3453 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_3XXX),
3454 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
3455 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
3456 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
3457 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_3XXX),
3458 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_3XXX),
3459 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_3XXX),
3460 CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX),
3461 CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX),
3462 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX),
3463 CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX),
3464 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
3465 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX),
3466 CLK(NULL, "sr1_fck", &sr1_fck, CK_343X),
3467 CLK(NULL, "sr2_fck", &sr2_fck, CK_343X),
3468 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X),
3469 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX),
3470 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX),
3471 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX),
3472 CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
3473 CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
3474 CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
3475 CLK("davinci_emac", "ick", &emac_ick, CK_AM35XX),
3476 CLK("davinci_emac", "fck", &emac_fck, CK_AM35XX),
3477 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
3478 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
3479 CLK("musb_hdrc", "ick", &hsotgusb_ick_am35xx, CK_AM35XX),
3480 CLK("musb_hdrc", "fck", &hsotgusb_fck_am35xx, CK_AM35XX),
3481 CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
3482 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
3483 };
3484
3485
3486 int __init omap3xxx_clk_init(void)
3487 {
3488 struct omap_clk *c;
3489 u32 cpu_clkflg = CK_3XXX;
3490
3491 if (cpu_is_omap3517()) {
3492 cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
3493 cpu_clkflg |= CK_3517;
3494 } else if (cpu_is_omap3505()) {
3495 cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
3496 cpu_clkflg |= CK_3505;
3497 } else if (cpu_is_omap34xx()) {
3498 cpu_mask = RATE_IN_343X;
3499 cpu_clkflg |= CK_343X;
3500
3501 /*
3502 * Update this if there are further clock changes between ES2
3503 * and production parts
3504 */
3505 if (omap_rev() == OMAP3430_REV_ES1_0) {
3506 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
3507 cpu_clkflg |= CK_3430ES1;
3508 } else {
3509 cpu_mask |= RATE_IN_3430ES2;
3510 cpu_clkflg |= CK_3430ES2;
3511 }
3512 }
3513 if (omap3_has_192mhz_clk())
3514 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3515
3516 if (cpu_is_omap3630()) {
3517 cpu_mask |= RATE_IN_36XX;
3518 cpu_clkflg |= CK_36XX;
3519
3520 /*
3521 * XXX This type of dynamic rewriting of the clock tree is
3522 * deprecated and should be revised soon.
3523 */
3524 dpll4_m2_ck = dpll4_m2_ck_3630;
3525 dpll4_m3_ck = dpll4_m3_ck_3630;
3526 dpll4_m4_ck = dpll4_m4_ck_3630;
3527 dpll4_m5_ck = dpll4_m5_ck_3630;
3528 dpll4_m6_ck = dpll4_m6_ck_3630;
3529
3530 /*
3531 * For 3630: override clkops_omap2_dflt_wait for the
3532 * clocks affected from PWRDN reset Limitation
3533 */
3534 dpll3_m3x2_ck.ops =
3535 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3536 dpll4_m2x2_ck.ops =
3537 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3538 dpll4_m3x2_ck.ops =
3539 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3540 dpll4_m4x2_ck.ops =
3541 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3542 dpll4_m5x2_ck.ops =
3543 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3544 dpll4_m6x2_ck.ops =
3545 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3546 } else {
3547 /*
3548 * XXX This type of dynamic rewriting of the clock tree is
3549 * deprecated and should be revised soon.
3550 */
3551 dpll4_m2_ck = dpll4_m2_ck_34xx;
3552 dpll4_m3_ck = dpll4_m3_ck_34xx;
3553 dpll4_m4_ck = dpll4_m4_ck_34xx;
3554 dpll4_m5_ck = dpll4_m5_ck_34xx;
3555 dpll4_m6_ck = dpll4_m6_ck_34xx;
3556 }
3557
3558 if (cpu_is_omap3630())
3559 dpll4_dd = dpll4_dd_3630;
3560 else
3561 dpll4_dd = dpll4_dd_34xx;
3562
3563 clk_init(&omap2_clk_functions);
3564
3565 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3566 c++)
3567 clk_preinit(c->lk.clk);
3568
3569 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3570 c++)
3571 if (c->cpu & cpu_clkflg) {
3572 clkdev_add(&c->lk);
3573 clk_register(c->lk.clk);
3574 omap2_init_clk_clkdm(c->lk.clk);
3575 }
3576
3577 recalculate_root_clocks();
3578
3579 printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
3580 "%ld.%01ld/%ld/%ld MHz\n",
3581 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3582 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
3583
3584 /*
3585 * Only enable those clocks we will need, let the drivers
3586 * enable other clocks as necessary
3587 */
3588 clk_enable_init_clocks();
3589
3590 /*
3591 * Lock DPLL5 and put it in autoidle.
3592 */
3593 if (omap_rev() >= OMAP3430_REV_ES2_0)
3594 omap3_clk_lock_dpll5();
3595
3596 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3597 sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3598 arm_fck_p = clk_get(NULL, "arm_fck");
3599
3600 return 0;
3601 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree