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TTY: serial, fix includes in some drivers
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / tty / serial / pch_uart.c
blobecc8506f3b420dd8753cec4d7b666488bf0b286e
1 /*
2 *Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
3 *
4 *This program is free software; you can redistribute it and/or modify
5 *it under the terms of the GNU General Public License as published by
6 *the Free Software Foundation; version 2 of the License.
7 *
8 *This program is distributed in the hope that it will be useful,
9 *but WITHOUT ANY WARRANTY; without even the implied warranty of
10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 *GNU General Public License for more details.
12 *
13 *You should have received a copy of the GNU General Public License
14 *along with this program; if not, write to the Free Software
15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17 #include <linux/kernel.h>
18 #include <linux/serial_reg.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/serial_core.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/interrupt.h>
26 #include <linux/io.h>
27 #include <linux/dmi.h>
28
29 #include <linux/dmaengine.h>
30 #include <linux/pch_dma.h>
31
32 enum {
33 PCH_UART_HANDLED_RX_INT_SHIFT,
34 PCH_UART_HANDLED_TX_INT_SHIFT,
35 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
36 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
37 PCH_UART_HANDLED_MS_INT_SHIFT,
38 };
39
40 enum {
41 PCH_UART_8LINE,
42 PCH_UART_2LINE,
43 };
44
45 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
46
47 /* Set the max number of UART port
48 * Intel EG20T PCH: 4 port
49 * OKI SEMICONDUCTOR ML7213 IOH: 3 port
50 * OKI SEMICONDUCTOR ML7223 IOH: 2 port
51 */
52 #define PCH_UART_NR 4
53
54 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
55 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
56 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
57 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
58 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
59 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
60 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
61
62 #define PCH_UART_RBR 0x00
63 #define PCH_UART_THR 0x00
64
65 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
66 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
67 #define PCH_UART_IER_ERBFI 0x00000001
68 #define PCH_UART_IER_ETBEI 0x00000002
69 #define PCH_UART_IER_ELSI 0x00000004
70 #define PCH_UART_IER_EDSSI 0x00000008
71
72 #define PCH_UART_IIR_IP 0x00000001
73 #define PCH_UART_IIR_IID 0x00000006
74 #define PCH_UART_IIR_MSI 0x00000000
75 #define PCH_UART_IIR_TRI 0x00000002
76 #define PCH_UART_IIR_RRI 0x00000004
77 #define PCH_UART_IIR_REI 0x00000006
78 #define PCH_UART_IIR_TOI 0x00000008
79 #define PCH_UART_IIR_FIFO256 0x00000020
80 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
81 #define PCH_UART_IIR_FE 0x000000C0
82
83 #define PCH_UART_FCR_FIFOE 0x00000001
84 #define PCH_UART_FCR_RFR 0x00000002
85 #define PCH_UART_FCR_TFR 0x00000004
86 #define PCH_UART_FCR_DMS 0x00000008
87 #define PCH_UART_FCR_FIFO256 0x00000020
88 #define PCH_UART_FCR_RFTL 0x000000C0
89
90 #define PCH_UART_FCR_RFTL1 0x00000000
91 #define PCH_UART_FCR_RFTL64 0x00000040
92 #define PCH_UART_FCR_RFTL128 0x00000080
93 #define PCH_UART_FCR_RFTL224 0x000000C0
94 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
95 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
96 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
97 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
98 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
99 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
100 #define PCH_UART_FCR_RFTL_SHIFT 6
101
102 #define PCH_UART_LCR_WLS 0x00000003
103 #define PCH_UART_LCR_STB 0x00000004
104 #define PCH_UART_LCR_PEN 0x00000008
105 #define PCH_UART_LCR_EPS 0x00000010
106 #define PCH_UART_LCR_SP 0x00000020
107 #define PCH_UART_LCR_SB 0x00000040
108 #define PCH_UART_LCR_DLAB 0x00000080
109 #define PCH_UART_LCR_NP 0x00000000
110 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN
111 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
112 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
113 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
114 PCH_UART_LCR_SP)
115
116 #define PCH_UART_LCR_5BIT 0x00000000
117 #define PCH_UART_LCR_6BIT 0x00000001
118 #define PCH_UART_LCR_7BIT 0x00000002
119 #define PCH_UART_LCR_8BIT 0x00000003
120
121 #define PCH_UART_MCR_DTR 0x00000001
122 #define PCH_UART_MCR_RTS 0x00000002
123 #define PCH_UART_MCR_OUT 0x0000000C
124 #define PCH_UART_MCR_LOOP 0x00000010
125 #define PCH_UART_MCR_AFE 0x00000020
126
127 #define PCH_UART_LSR_DR 0x00000001
128 #define PCH_UART_LSR_ERR (1<<7)
129
130 #define PCH_UART_MSR_DCTS 0x00000001
131 #define PCH_UART_MSR_DDSR 0x00000002
132 #define PCH_UART_MSR_TERI 0x00000004
133 #define PCH_UART_MSR_DDCD 0x00000008
134 #define PCH_UART_MSR_CTS 0x00000010
135 #define PCH_UART_MSR_DSR 0x00000020
136 #define PCH_UART_MSR_RI 0x00000040
137 #define PCH_UART_MSR_DCD 0x00000080
138 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
139 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
140
141 #define PCH_UART_DLL 0x00
142 #define PCH_UART_DLM 0x01
143
144 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
145 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
146 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
147 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
148 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
149
150 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
151 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
152 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
153 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
154 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
155 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
156 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
157 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
158 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
159 #define PCH_UART_HAL_STB1 0
160 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
161
162 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
163 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
164 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
165 PCH_UART_HAL_CLR_RX_FIFO)
166
167 #define PCH_UART_HAL_DMA_MODE0 0
168 #define PCH_UART_HAL_FIFO_DIS 0
169 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
170 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
171 PCH_UART_FCR_FIFO256)
172 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
173 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
174 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
175 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
176 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
177 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
178 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
179 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
180 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
181 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
182 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
183 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
184 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
185 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
186
187 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
188 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
189 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
190 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
191 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
192
193 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
194 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
195 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
196 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
197 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
198
199 #define PCI_VENDOR_ID_ROHM 0x10DB
200
201 struct pch_uart_buffer {
202 unsigned char *buf;
203 int size;
204 };
205
206 struct eg20t_port {
207 struct uart_port port;
208 int port_type;
209 void __iomem *membase;
210 resource_size_t mapbase;
211 unsigned int iobase;
212 struct pci_dev *pdev;
213 int fifo_size;
214 int base_baud;
215 int start_tx;
216 int start_rx;
217 int tx_empty;
218 int int_dis_flag;
219 int trigger;
220 int trigger_level;
221 struct pch_uart_buffer rxbuf;
222 unsigned int dmsr;
223 unsigned int fcr;
224 unsigned int mcr;
225 unsigned int use_dma;
226 unsigned int use_dma_flag;
227 struct dma_async_tx_descriptor *desc_tx;
228 struct dma_async_tx_descriptor *desc_rx;
229 struct pch_dma_slave param_tx;
230 struct pch_dma_slave param_rx;
231 struct dma_chan *chan_tx;
232 struct dma_chan *chan_rx;
233 struct scatterlist *sg_tx_p;
234 int nent;
235 struct scatterlist sg_rx;
236 int tx_dma_use;
237 void *rx_buf_virt;
238 dma_addr_t rx_buf_dma;
239 };
240
241 /**
242 * struct pch_uart_driver_data - private data structure for UART-DMA
243 * @port_type: The number of DMA channel
244 * @line_no: UART port line number (0, 1, 2...)
245 */
246 struct pch_uart_driver_data {
247 int port_type;
248 int line_no;
249 };
250
251 enum pch_uart_num_t {
252 pch_et20t_uart0 = 0,
253 pch_et20t_uart1,
254 pch_et20t_uart2,
255 pch_et20t_uart3,
256 pch_ml7213_uart0,
257 pch_ml7213_uart1,
258 pch_ml7213_uart2,
259 pch_ml7223_uart0,
260 pch_ml7223_uart1,
261 };
262
263 static struct pch_uart_driver_data drv_dat[] = {
264 [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
265 [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
266 [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
267 [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
268 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
269 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
270 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
271 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
272 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
273 };
274
275 static unsigned int default_baud = 9600;
276 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
277 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
278 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
279 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
280
281 static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize,
282 int base_baud)
283 {
284 struct eg20t_port *priv = pci_get_drvdata(pdev);
285
286 priv->trigger_level = 1;
287 priv->fcr = 0;
288 }
289
290 static unsigned int get_msr(struct eg20t_port *priv, void __iomem *base)
291 {
292 unsigned int msr = ioread8(base + UART_MSR);
293 priv->dmsr |= msr & PCH_UART_MSR_DELTA;
294
295 return msr;
296 }
297
298 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
299 unsigned int flag)
300 {
301 u8 ier = ioread8(priv->membase + UART_IER);
302 ier |= flag & PCH_UART_IER_MASK;
303 iowrite8(ier, priv->membase + UART_IER);
304 }
305
306 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
307 unsigned int flag)
308 {
309 u8 ier = ioread8(priv->membase + UART_IER);
310 ier &= ~(flag & PCH_UART_IER_MASK);
311 iowrite8(ier, priv->membase + UART_IER);
312 }
313
314 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
315 unsigned int parity, unsigned int bits,
316 unsigned int stb)
317 {
318 unsigned int dll, dlm, lcr;
319 int div;
320
321 div = DIV_ROUND_CLOSEST(priv->base_baud / 16, baud);
322 if (div < 0 || USHRT_MAX <= div) {
323 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
324 return -EINVAL;
325 }
326
327 dll = (unsigned int)div & 0x00FFU;
328 dlm = ((unsigned int)div >> 8) & 0x00FFU;
329
330 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
331 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
332 return -EINVAL;
333 }
334
335 if (bits & ~PCH_UART_LCR_WLS) {
336 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
337 return -EINVAL;
338 }
339
340 if (stb & ~PCH_UART_LCR_STB) {
341 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
342 return -EINVAL;
343 }
344
345 lcr = parity;
346 lcr |= bits;
347 lcr |= stb;
348
349 dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
350 __func__, baud, div, lcr, jiffies);
351 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
352 iowrite8(dll, priv->membase + PCH_UART_DLL);
353 iowrite8(dlm, priv->membase + PCH_UART_DLM);
354 iowrite8(lcr, priv->membase + UART_LCR);
355
356 return 0;
357 }
358
359 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
360 unsigned int flag)
361 {
362 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
363 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
364 __func__, flag);
365 return -EINVAL;
366 }
367
368 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
369 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
370 priv->membase + UART_FCR);
371 iowrite8(priv->fcr, priv->membase + UART_FCR);
372
373 return 0;
374 }
375
376 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
377 unsigned int dmamode,
378 unsigned int fifo_size, unsigned int trigger)
379 {
380 u8 fcr;
381
382 if (dmamode & ~PCH_UART_FCR_DMS) {
383 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
384 __func__, dmamode);
385 return -EINVAL;
386 }
387
388 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
389 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
390 __func__, fifo_size);
391 return -EINVAL;
392 }
393
394 if (trigger & ~PCH_UART_FCR_RFTL) {
395 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
396 __func__, trigger);
397 return -EINVAL;
398 }
399
400 switch (priv->fifo_size) {
401 case 256:
402 priv->trigger_level =
403 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
404 break;
405 case 64:
406 priv->trigger_level =
407 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
408 break;
409 case 16:
410 priv->trigger_level =
411 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
412 break;
413 default:
414 priv->trigger_level =
415 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
416 break;
417 }
418 fcr =
419 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
420 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
421 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
422 priv->membase + UART_FCR);
423 iowrite8(fcr, priv->membase + UART_FCR);
424 priv->fcr = fcr;
425
426 return 0;
427 }
428
429 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
430 {
431 priv->dmsr = 0;
432 return get_msr(priv, priv->membase);
433 }
434
435 static void pch_uart_hal_write(struct eg20t_port *priv,
436 const unsigned char *buf, int tx_size)
437 {
438 int i;
439 unsigned int thr;
440
441 for (i = 0; i < tx_size;) {
442 thr = buf[i++];
443 iowrite8(thr, priv->membase + PCH_UART_THR);
444 }
445 }
446
447 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
448 int rx_size)
449 {
450 int i;
451 u8 rbr, lsr;
452
453 lsr = ioread8(priv->membase + UART_LSR);
454 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
455 i < rx_size && lsr & UART_LSR_DR;
456 lsr = ioread8(priv->membase + UART_LSR)) {
457 rbr = ioread8(priv->membase + PCH_UART_RBR);
458 buf[i++] = rbr;
459 }
460 return i;
461 }
462
463 static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv)
464 {
465 unsigned int iir;
466 int ret;
467
468 iir = ioread8(priv->membase + UART_IIR);
469 ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP));
470 return ret;
471 }
472
473 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
474 {
475 return ioread8(priv->membase + UART_LSR);
476 }
477
478 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
479 {
480 unsigned int lcr;
481
482 lcr = ioread8(priv->membase + UART_LCR);
483 if (on)
484 lcr |= PCH_UART_LCR_SB;
485 else
486 lcr &= ~PCH_UART_LCR_SB;
487
488 iowrite8(lcr, priv->membase + UART_LCR);
489 }
490
491 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
492 int size)
493 {
494 struct uart_port *port;
495 struct tty_struct *tty;
496
497 port = &priv->port;
498 tty = tty_port_tty_get(&port->state->port);
499 if (!tty) {
500 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
501 return -EBUSY;
502 }
503
504 tty_insert_flip_string(tty, buf, size);
505 tty_flip_buffer_push(tty);
506 tty_kref_put(tty);
507
508 return 0;
509 }
510
511 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
512 {
513 int ret;
514 struct uart_port *port = &priv->port;
515
516 if (port->x_char) {
517 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
518 __func__, port->x_char, jiffies);
519 buf[0] = port->x_char;
520 port->x_char = 0;
521 ret = 1;
522 } else {
523 ret = 0;
524 }
525
526 return ret;
527 }
528
529 static int dma_push_rx(struct eg20t_port *priv, int size)
530 {
531 struct tty_struct *tty;
532 int room;
533 struct uart_port *port = &priv->port;
534
535 port = &priv->port;
536 tty = tty_port_tty_get(&port->state->port);
537 if (!tty) {
538 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
539 return 0;
540 }
541
542 room = tty_buffer_request_room(tty, size);
543
544 if (room < size)
545 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
546 size - room);
547 if (!room)
548 return room;
549
550 tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size);
551
552 port->icount.rx += room;
553 tty_kref_put(tty);
554
555 return room;
556 }
557
558 static void pch_free_dma(struct uart_port *port)
559 {
560 struct eg20t_port *priv;
561 priv = container_of(port, struct eg20t_port, port);
562
563 if (priv->chan_tx) {
564 dma_release_channel(priv->chan_tx);
565 priv->chan_tx = NULL;
566 }
567 if (priv->chan_rx) {
568 dma_release_channel(priv->chan_rx);
569 priv->chan_rx = NULL;
570 }
571 if (sg_dma_address(&priv->sg_rx))
572 dma_free_coherent(port->dev, port->fifosize,
573 sg_virt(&priv->sg_rx),
574 sg_dma_address(&priv->sg_rx));
575
576 return;
577 }
578
579 static bool filter(struct dma_chan *chan, void *slave)
580 {
581 struct pch_dma_slave *param = slave;
582
583 if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
584 chan->device->dev)) {
585 chan->private = param;
586 return true;
587 } else {
588 return false;
589 }
590 }
591
592 static void pch_request_dma(struct uart_port *port)
593 {
594 dma_cap_mask_t mask;
595 struct dma_chan *chan;
596 struct pci_dev *dma_dev;
597 struct pch_dma_slave *param;
598 struct eg20t_port *priv =
599 container_of(port, struct eg20t_port, port);
600 dma_cap_zero(mask);
601 dma_cap_set(DMA_SLAVE, mask);
602
603 dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(0xa, 0)); /* Get DMA's dev
604 information */
605 /* Set Tx DMA */
606 param = &priv->param_tx;
607 param->dma_dev = &dma_dev->dev;
608 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
609
610 param->tx_reg = port->mapbase + UART_TX;
611 chan = dma_request_channel(mask, filter, param);
612 if (!chan) {
613 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
614 __func__);
615 return;
616 }
617 priv->chan_tx = chan;
618
619 /* Set Rx DMA */
620 param = &priv->param_rx;
621 param->dma_dev = &dma_dev->dev;
622 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
623
624 param->rx_reg = port->mapbase + UART_RX;
625 chan = dma_request_channel(mask, filter, param);
626 if (!chan) {
627 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
628 __func__);
629 dma_release_channel(priv->chan_tx);
630 return;
631 }
632
633 /* Get Consistent memory for DMA */
634 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
635 &priv->rx_buf_dma, GFP_KERNEL);
636 priv->chan_rx = chan;
637 }
638
639 static void pch_dma_rx_complete(void *arg)
640 {
641 struct eg20t_port *priv = arg;
642 struct uart_port *port = &priv->port;
643 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
644 int count;
645
646 if (!tty) {
647 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
648 return;
649 }
650
651 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
652 count = dma_push_rx(priv, priv->trigger_level);
653 if (count)
654 tty_flip_buffer_push(tty);
655 tty_kref_put(tty);
656 async_tx_ack(priv->desc_rx);
657 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
658 }
659
660 static void pch_dma_tx_complete(void *arg)
661 {
662 struct eg20t_port *priv = arg;
663 struct uart_port *port = &priv->port;
664 struct circ_buf *xmit = &port->state->xmit;
665 struct scatterlist *sg = priv->sg_tx_p;
666 int i;
667
668 for (i = 0; i < priv->nent; i++, sg++) {
669 xmit->tail += sg_dma_len(sg);
670 port->icount.tx += sg_dma_len(sg);
671 }
672 xmit->tail &= UART_XMIT_SIZE - 1;
673 async_tx_ack(priv->desc_tx);
674 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
675 priv->tx_dma_use = 0;
676 priv->nent = 0;
677 kfree(priv->sg_tx_p);
678 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
679 }
680
681 static int pop_tx(struct eg20t_port *priv, int size)
682 {
683 int count = 0;
684 struct uart_port *port = &priv->port;
685 struct circ_buf *xmit = &port->state->xmit;
686
687 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
688 goto pop_tx_end;
689
690 do {
691 int cnt_to_end =
692 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
693 int sz = min(size - count, cnt_to_end);
694 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
695 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
696 count += sz;
697 } while (!uart_circ_empty(xmit) && count < size);
698
699 pop_tx_end:
700 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
701 count, size - count, jiffies);
702
703 return count;
704 }
705
706 static int handle_rx_to(struct eg20t_port *priv)
707 {
708 struct pch_uart_buffer *buf;
709 int rx_size;
710 int ret;
711 if (!priv->start_rx) {
712 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
713 return 0;
714 }
715 buf = &priv->rxbuf;
716 do {
717 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
718 ret = push_rx(priv, buf->buf, rx_size);
719 if (ret)
720 return 0;
721 } while (rx_size == buf->size);
722
723 return PCH_UART_HANDLED_RX_INT;
724 }
725
726 static int handle_rx(struct eg20t_port *priv)
727 {
728 return handle_rx_to(priv);
729 }
730
731 static int dma_handle_rx(struct eg20t_port *priv)
732 {
733 struct uart_port *port = &priv->port;
734 struct dma_async_tx_descriptor *desc;
735 struct scatterlist *sg;
736
737 priv = container_of(port, struct eg20t_port, port);
738 sg = &priv->sg_rx;
739
740 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
741
742 sg_dma_len(sg) = priv->trigger_level;
743
744 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
745 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
746 ~PAGE_MASK);
747
748 sg_dma_address(sg) = priv->rx_buf_dma;
749
750 desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx,
751 sg, 1, DMA_FROM_DEVICE,
752 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
753
754 if (!desc)
755 return 0;
756
757 priv->desc_rx = desc;
758 desc->callback = pch_dma_rx_complete;
759 desc->callback_param = priv;
760 desc->tx_submit(desc);
761 dma_async_issue_pending(priv->chan_rx);
762
763 return PCH_UART_HANDLED_RX_INT;
764 }
765
766 static unsigned int handle_tx(struct eg20t_port *priv)
767 {
768 struct uart_port *port = &priv->port;
769 struct circ_buf *xmit = &port->state->xmit;
770 int fifo_size;
771 int tx_size;
772 int size;
773 int tx_empty;
774
775 if (!priv->start_tx) {
776 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
777 __func__, jiffies);
778 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
779 priv->tx_empty = 1;
780 return 0;
781 }
782
783 fifo_size = max(priv->fifo_size, 1);
784 tx_empty = 1;
785 if (pop_tx_x(priv, xmit->buf)) {
786 pch_uart_hal_write(priv, xmit->buf, 1);
787 port->icount.tx++;
788 tx_empty = 0;
789 fifo_size--;
790 }
791 size = min(xmit->head - xmit->tail, fifo_size);
792 if (size < 0)
793 size = fifo_size;
794
795 tx_size = pop_tx(priv, size);
796 if (tx_size > 0) {
797 port->icount.tx += tx_size;
798 tx_empty = 0;
799 }
800
801 priv->tx_empty = tx_empty;
802
803 if (tx_empty) {
804 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
805 uart_write_wakeup(port);
806 }
807
808 return PCH_UART_HANDLED_TX_INT;
809 }
810
811 static unsigned int dma_handle_tx(struct eg20t_port *priv)
812 {
813 struct uart_port *port = &priv->port;
814 struct circ_buf *xmit = &port->state->xmit;
815 struct scatterlist *sg;
816 int nent;
817 int fifo_size;
818 int tx_empty;
819 struct dma_async_tx_descriptor *desc;
820 int num;
821 int i;
822 int bytes;
823 int size;
824 int rem;
825
826 if (!priv->start_tx) {
827 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
828 __func__, jiffies);
829 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
830 priv->tx_empty = 1;
831 return 0;
832 }
833
834 if (priv->tx_dma_use) {
835 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
836 __func__, jiffies);
837 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
838 priv->tx_empty = 1;
839 return 0;
840 }
841
842 fifo_size = max(priv->fifo_size, 1);
843 tx_empty = 1;
844 if (pop_tx_x(priv, xmit->buf)) {
845 pch_uart_hal_write(priv, xmit->buf, 1);
846 port->icount.tx++;
847 tx_empty = 0;
848 fifo_size--;
849 }
850
851 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
852 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
853 xmit->tail, UART_XMIT_SIZE));
854 if (!bytes) {
855 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
856 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
857 uart_write_wakeup(port);
858 return 0;
859 }
860
861 if (bytes > fifo_size) {
862 num = bytes / fifo_size + 1;
863 size = fifo_size;
864 rem = bytes % fifo_size;
865 } else {
866 num = 1;
867 size = bytes;
868 rem = bytes;
869 }
870
871 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
872 __func__, num, size, rem);
873
874 priv->tx_dma_use = 1;
875
876 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
877
878 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
879 sg = priv->sg_tx_p;
880
881 for (i = 0; i < num; i++, sg++) {
882 if (i == (num - 1))
883 sg_set_page(sg, virt_to_page(xmit->buf),
884 rem, fifo_size * i);
885 else
886 sg_set_page(sg, virt_to_page(xmit->buf),
887 size, fifo_size * i);
888 }
889
890 sg = priv->sg_tx_p;
891 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
892 if (!nent) {
893 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
894 return 0;
895 }
896 priv->nent = nent;
897
898 for (i = 0; i < nent; i++, sg++) {
899 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
900 fifo_size * i;
901 sg_dma_address(sg) = (sg_dma_address(sg) &
902 ~(UART_XMIT_SIZE - 1)) + sg->offset;
903 if (i == (nent - 1))
904 sg_dma_len(sg) = rem;
905 else
906 sg_dma_len(sg) = size;
907 }
908
909 desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx,
910 priv->sg_tx_p, nent, DMA_TO_DEVICE,
911 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
912 if (!desc) {
913 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
914 __func__);
915 return 0;
916 }
917 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
918 priv->desc_tx = desc;
919 desc->callback = pch_dma_tx_complete;
920 desc->callback_param = priv;
921
922 desc->tx_submit(desc);
923
924 dma_async_issue_pending(priv->chan_tx);
925
926 return PCH_UART_HANDLED_TX_INT;
927 }
928
929 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
930 {
931 u8 fcr = ioread8(priv->membase + UART_FCR);
932
933 /* Reset FIFO */
934 fcr |= UART_FCR_CLEAR_RCVR;
935 iowrite8(fcr, priv->membase + UART_FCR);
936
937 if (lsr & PCH_UART_LSR_ERR)
938 dev_err(&priv->pdev->dev, "Error data in FIFO\n");
939
940 if (lsr & UART_LSR_FE)
941 dev_err(&priv->pdev->dev, "Framing Error\n");
942
943 if (lsr & UART_LSR_PE)
944 dev_err(&priv->pdev->dev, "Parity Error\n");
945
946 if (lsr & UART_LSR_OE)
947 dev_err(&priv->pdev->dev, "Overrun Error\n");
948 }
949
950 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
951 {
952 struct eg20t_port *priv = dev_id;
953 unsigned int handled;
954 u8 lsr;
955 int ret = 0;
956 unsigned int iid;
957 unsigned long flags;
958
959 spin_lock_irqsave(&priv->port.lock, flags);
960 handled = 0;
961 while ((iid = pch_uart_hal_get_iid(priv)) > 1) {
962 switch (iid) {
963 case PCH_UART_IID_RLS: /* Receiver Line Status */
964 lsr = pch_uart_hal_get_line_status(priv);
965 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
966 UART_LSR_PE | UART_LSR_OE)) {
967 pch_uart_err_ir(priv, lsr);
968 ret = PCH_UART_HANDLED_RX_ERR_INT;
969 }
970 break;
971 case PCH_UART_IID_RDR: /* Received Data Ready */
972 if (priv->use_dma) {
973 pch_uart_hal_disable_interrupt(priv,
974 PCH_UART_HAL_RX_INT);
975 ret = dma_handle_rx(priv);
976 if (!ret)
977 pch_uart_hal_enable_interrupt(priv,
978 PCH_UART_HAL_RX_INT);
979 } else {
980 ret = handle_rx(priv);
981 }
982 break;
983 case PCH_UART_IID_RDR_TO: /* Received Data Ready
984 (FIFO Timeout) */
985 ret = handle_rx_to(priv);
986 break;
987 case PCH_UART_IID_THRE: /* Transmitter Holding Register
988 Empty */
989 if (priv->use_dma)
990 ret = dma_handle_tx(priv);
991 else
992 ret = handle_tx(priv);
993 break;
994 case PCH_UART_IID_MS: /* Modem Status */
995 ret = PCH_UART_HANDLED_MS_INT;
996 break;
997 default: /* Never junp to this label */
998 dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__,
999 iid, jiffies);
1000 ret = -1;
1001 break;
1002 }
1003 handled |= (unsigned int)ret;
1004 }
1005 if (handled == 0 && iid <= 1) {
1006 if (priv->int_dis_flag)
1007 priv->int_dis_flag = 0;
1008 }
1009
1010 spin_unlock_irqrestore(&priv->port.lock, flags);
1011 return IRQ_RETVAL(handled);
1012 }
1013
1014 /* This function tests whether the transmitter fifo and shifter for the port
1015 described by 'port' is empty. */
1016 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1017 {
1018 struct eg20t_port *priv;
1019 int ret;
1020 priv = container_of(port, struct eg20t_port, port);
1021 if (priv->tx_empty)
1022 ret = TIOCSER_TEMT;
1023 else
1024 ret = 0;
1025
1026 return ret;
1027 }
1028
1029 /* Returns the current state of modem control inputs. */
1030 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1031 {
1032 struct eg20t_port *priv;
1033 u8 modem;
1034 unsigned int ret = 0;
1035
1036 priv = container_of(port, struct eg20t_port, port);
1037 modem = pch_uart_hal_get_modem(priv);
1038
1039 if (modem & UART_MSR_DCD)
1040 ret |= TIOCM_CAR;
1041
1042 if (modem & UART_MSR_RI)
1043 ret |= TIOCM_RNG;
1044
1045 if (modem & UART_MSR_DSR)
1046 ret |= TIOCM_DSR;
1047
1048 if (modem & UART_MSR_CTS)
1049 ret |= TIOCM_CTS;
1050
1051 return ret;
1052 }
1053
1054 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1055 {
1056 u32 mcr = 0;
1057 struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1058
1059 if (mctrl & TIOCM_DTR)
1060 mcr |= UART_MCR_DTR;
1061 if (mctrl & TIOCM_RTS)
1062 mcr |= UART_MCR_RTS;
1063 if (mctrl & TIOCM_LOOP)
1064 mcr |= UART_MCR_LOOP;
1065
1066 if (priv->mcr & UART_MCR_AFE)
1067 mcr |= UART_MCR_AFE;
1068
1069 if (mctrl)
1070 iowrite8(mcr, priv->membase + UART_MCR);
1071 }
1072
1073 static void pch_uart_stop_tx(struct uart_port *port)
1074 {
1075 struct eg20t_port *priv;
1076 priv = container_of(port, struct eg20t_port, port);
1077 priv->start_tx = 0;
1078 priv->tx_dma_use = 0;
1079 }
1080
1081 static void pch_uart_start_tx(struct uart_port *port)
1082 {
1083 struct eg20t_port *priv;
1084
1085 priv = container_of(port, struct eg20t_port, port);
1086
1087 if (priv->use_dma) {
1088 if (priv->tx_dma_use) {
1089 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1090 __func__);
1091 return;
1092 }
1093 }
1094
1095 priv->start_tx = 1;
1096 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1097 }
1098
1099 static void pch_uart_stop_rx(struct uart_port *port)
1100 {
1101 struct eg20t_port *priv;
1102 priv = container_of(port, struct eg20t_port, port);
1103 priv->start_rx = 0;
1104 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
1105 priv->int_dis_flag = 1;
1106 }
1107
1108 /* Enable the modem status interrupts. */
1109 static void pch_uart_enable_ms(struct uart_port *port)
1110 {
1111 struct eg20t_port *priv;
1112 priv = container_of(port, struct eg20t_port, port);
1113 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1114 }
1115
1116 /* Control the transmission of a break signal. */
1117 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1118 {
1119 struct eg20t_port *priv;
1120 unsigned long flags;
1121
1122 priv = container_of(port, struct eg20t_port, port);
1123 spin_lock_irqsave(&port->lock, flags);
1124 pch_uart_hal_set_break(priv, ctl);
1125 spin_unlock_irqrestore(&port->lock, flags);
1126 }
1127
1128 /* Grab any interrupt resources and initialise any low level driver state. */
1129 static int pch_uart_startup(struct uart_port *port)
1130 {
1131 struct eg20t_port *priv;
1132 int ret;
1133 int fifo_size;
1134 int trigger_level;
1135
1136 priv = container_of(port, struct eg20t_port, port);
1137 priv->tx_empty = 1;
1138
1139 if (port->uartclk)
1140 priv->base_baud = port->uartclk;
1141 else
1142 port->uartclk = priv->base_baud;
1143
1144 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1145 ret = pch_uart_hal_set_line(priv, default_baud,
1146 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1147 PCH_UART_HAL_STB1);
1148 if (ret)
1149 return ret;
1150
1151 switch (priv->fifo_size) {
1152 case 256:
1153 fifo_size = PCH_UART_HAL_FIFO256;
1154 break;
1155 case 64:
1156 fifo_size = PCH_UART_HAL_FIFO64;
1157 break;
1158 case 16:
1159 fifo_size = PCH_UART_HAL_FIFO16;
1160 case 1:
1161 default:
1162 fifo_size = PCH_UART_HAL_FIFO_DIS;
1163 break;
1164 }
1165
1166 switch (priv->trigger) {
1167 case PCH_UART_HAL_TRIGGER1:
1168 trigger_level = 1;
1169 break;
1170 case PCH_UART_HAL_TRIGGER_L:
1171 trigger_level = priv->fifo_size / 4;
1172 break;
1173 case PCH_UART_HAL_TRIGGER_M:
1174 trigger_level = priv->fifo_size / 2;
1175 break;
1176 case PCH_UART_HAL_TRIGGER_H:
1177 default:
1178 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1179 break;
1180 }
1181
1182 priv->trigger_level = trigger_level;
1183 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1184 fifo_size, priv->trigger);
1185 if (ret < 0)
1186 return ret;
1187
1188 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1189 KBUILD_MODNAME, priv);
1190 if (ret < 0)
1191 return ret;
1192
1193 if (priv->use_dma)
1194 pch_request_dma(port);
1195
1196 priv->start_rx = 1;
1197 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
1198 uart_update_timeout(port, CS8, default_baud);
1199
1200 return 0;
1201 }
1202
1203 static void pch_uart_shutdown(struct uart_port *port)
1204 {
1205 struct eg20t_port *priv;
1206 int ret;
1207
1208 priv = container_of(port, struct eg20t_port, port);
1209 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1210 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1211 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1212 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1213 if (ret)
1214 dev_err(priv->port.dev,
1215 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1216
1217 if (priv->use_dma_flag)
1218 pch_free_dma(port);
1219
1220 free_irq(priv->port.irq, priv);
1221 }
1222
1223 /* Change the port parameters, including word length, parity, stop
1224 *bits. Update read_status_mask and ignore_status_mask to indicate
1225 *the types of events we are interested in receiving. */
1226 static void pch_uart_set_termios(struct uart_port *port,
1227 struct ktermios *termios, struct ktermios *old)
1228 {
1229 int baud;
1230 int rtn;
1231 unsigned int parity, bits, stb;
1232 struct eg20t_port *priv;
1233 unsigned long flags;
1234
1235 priv = container_of(port, struct eg20t_port, port);
1236 switch (termios->c_cflag & CSIZE) {
1237 case CS5:
1238 bits = PCH_UART_HAL_5BIT;
1239 break;
1240 case CS6:
1241 bits = PCH_UART_HAL_6BIT;
1242 break;
1243 case CS7:
1244 bits = PCH_UART_HAL_7BIT;
1245 break;
1246 default: /* CS8 */
1247 bits = PCH_UART_HAL_8BIT;
1248 break;
1249 }
1250 if (termios->c_cflag & CSTOPB)
1251 stb = PCH_UART_HAL_STB2;
1252 else
1253 stb = PCH_UART_HAL_STB1;
1254
1255 if (termios->c_cflag & PARENB) {
1256 if (!(termios->c_cflag & PARODD))
1257 parity = PCH_UART_HAL_PARITY_ODD;
1258 else
1259 parity = PCH_UART_HAL_PARITY_EVEN;
1260
1261 } else {
1262 parity = PCH_UART_HAL_PARITY_NONE;
1263 }
1264
1265 /* Only UART0 has auto hardware flow function */
1266 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1267 priv->mcr |= UART_MCR_AFE;
1268 else
1269 priv->mcr &= ~UART_MCR_AFE;
1270
1271 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1272
1273 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1274
1275 spin_lock_irqsave(&port->lock, flags);
1276
1277 uart_update_timeout(port, termios->c_cflag, baud);
1278 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1279 if (rtn)
1280 goto out;
1281
1282 /* Don't rewrite B0 */
1283 if (tty_termios_baud_rate(termios))
1284 tty_termios_encode_baud_rate(termios, baud, baud);
1285
1286 out:
1287 spin_unlock_irqrestore(&port->lock, flags);
1288 }
1289
1290 static const char *pch_uart_type(struct uart_port *port)
1291 {
1292 return KBUILD_MODNAME;
1293 }
1294
1295 static void pch_uart_release_port(struct uart_port *port)
1296 {
1297 struct eg20t_port *priv;
1298
1299 priv = container_of(port, struct eg20t_port, port);
1300 pci_iounmap(priv->pdev, priv->membase);
1301 pci_release_regions(priv->pdev);
1302 }
1303
1304 static int pch_uart_request_port(struct uart_port *port)
1305 {
1306 struct eg20t_port *priv;
1307 int ret;
1308 void __iomem *membase;
1309
1310 priv = container_of(port, struct eg20t_port, port);
1311 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1312 if (ret < 0)
1313 return -EBUSY;
1314
1315 membase = pci_iomap(priv->pdev, 1, 0);
1316 if (!membase) {
1317 pci_release_regions(priv->pdev);
1318 return -EBUSY;
1319 }
1320 priv->membase = port->membase = membase;
1321
1322 return 0;
1323 }
1324
1325 static void pch_uart_config_port(struct uart_port *port, int type)
1326 {
1327 struct eg20t_port *priv;
1328
1329 priv = container_of(port, struct eg20t_port, port);
1330 if (type & UART_CONFIG_TYPE) {
1331 port->type = priv->port_type;
1332 pch_uart_request_port(port);
1333 }
1334 }
1335
1336 static int pch_uart_verify_port(struct uart_port *port,
1337 struct serial_struct *serinfo)
1338 {
1339 struct eg20t_port *priv;
1340
1341 priv = container_of(port, struct eg20t_port, port);
1342 if (serinfo->flags & UPF_LOW_LATENCY) {
1343 dev_info(priv->port.dev,
1344 "PCH UART : Use PIO Mode (without DMA)\n");
1345 priv->use_dma = 0;
1346 serinfo->flags &= ~UPF_LOW_LATENCY;
1347 } else {
1348 #ifndef CONFIG_PCH_DMA
1349 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1350 __func__);
1351 return -EOPNOTSUPP;
1352 #endif
1353 priv->use_dma = 1;
1354 priv->use_dma_flag = 1;
1355 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
1356 }
1357
1358 return 0;
1359 }
1360
1361 static struct uart_ops pch_uart_ops = {
1362 .tx_empty = pch_uart_tx_empty,
1363 .set_mctrl = pch_uart_set_mctrl,
1364 .get_mctrl = pch_uart_get_mctrl,
1365 .stop_tx = pch_uart_stop_tx,
1366 .start_tx = pch_uart_start_tx,
1367 .stop_rx = pch_uart_stop_rx,
1368 .enable_ms = pch_uart_enable_ms,
1369 .break_ctl = pch_uart_break_ctl,
1370 .startup = pch_uart_startup,
1371 .shutdown = pch_uart_shutdown,
1372 .set_termios = pch_uart_set_termios,
1373 /* .pm = pch_uart_pm, Not supported yet */
1374 /* .set_wake = pch_uart_set_wake, Not supported yet */
1375 .type = pch_uart_type,
1376 .release_port = pch_uart_release_port,
1377 .request_port = pch_uart_request_port,
1378 .config_port = pch_uart_config_port,
1379 .verify_port = pch_uart_verify_port
1380 };
1381
1382 static struct uart_driver pch_uart_driver = {
1383 .owner = THIS_MODULE,
1384 .driver_name = KBUILD_MODNAME,
1385 .dev_name = PCH_UART_DRIVER_DEVICE,
1386 .major = 0,
1387 .minor = 0,
1388 .nr = PCH_UART_NR,
1389 };
1390
1391 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1392 const struct pci_device_id *id)
1393 {
1394 struct eg20t_port *priv;
1395 int ret;
1396 unsigned int iobase;
1397 unsigned int mapbase;
1398 unsigned char *rxbuf;
1399 int fifosize, base_baud;
1400 int port_type;
1401 struct pch_uart_driver_data *board;
1402 const char *board_name;
1403
1404 board = &drv_dat[id->driver_data];
1405 port_type = board->port_type;
1406
1407 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1408 if (priv == NULL)
1409 goto init_port_alloc_err;
1410
1411 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1412 if (!rxbuf)
1413 goto init_port_free_txbuf;
1414
1415 base_baud = 1843200; /* 1.8432MHz */
1416
1417 /* quirk for CM-iTC board */
1418 board_name = dmi_get_system_info(DMI_BOARD_NAME);
1419 if (board_name && strstr(board_name, "CM-iTC"))
1420 base_baud = 192000000; /* 192.0MHz */
1421
1422 switch (port_type) {
1423 case PORT_UNKNOWN:
1424 fifosize = 256; /* EG20T/ML7213: UART0 */
1425 break;
1426 case PORT_8250:
1427 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
1428 break;
1429 default:
1430 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1431 goto init_port_hal_free;
1432 }
1433
1434 pci_enable_msi(pdev);
1435
1436 iobase = pci_resource_start(pdev, 0);
1437 mapbase = pci_resource_start(pdev, 1);
1438 priv->mapbase = mapbase;
1439 priv->iobase = iobase;
1440 priv->pdev = pdev;
1441 priv->tx_empty = 1;
1442 priv->rxbuf.buf = rxbuf;
1443 priv->rxbuf.size = PAGE_SIZE;
1444
1445 priv->fifo_size = fifosize;
1446 priv->base_baud = base_baud;
1447 priv->port_type = PORT_MAX_8250 + port_type + 1;
1448 priv->port.dev = &pdev->dev;
1449 priv->port.iobase = iobase;
1450 priv->port.membase = NULL;
1451 priv->port.mapbase = mapbase;
1452 priv->port.irq = pdev->irq;
1453 priv->port.iotype = UPIO_PORT;
1454 priv->port.ops = &pch_uart_ops;
1455 priv->port.flags = UPF_BOOT_AUTOCONF;
1456 priv->port.fifosize = fifosize;
1457 priv->port.line = board->line_no;
1458 priv->trigger = PCH_UART_HAL_TRIGGER_M;
1459
1460 spin_lock_init(&priv->port.lock);
1461
1462 pci_set_drvdata(pdev, priv);
1463 pch_uart_hal_request(pdev, fifosize, base_baud);
1464
1465 ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1466 if (ret < 0)
1467 goto init_port_hal_free;
1468
1469 return priv;
1470
1471 init_port_hal_free:
1472 free_page((unsigned long)rxbuf);
1473 init_port_free_txbuf:
1474 kfree(priv);
1475 init_port_alloc_err:
1476
1477 return NULL;
1478 }
1479
1480 static void pch_uart_exit_port(struct eg20t_port *priv)
1481 {
1482 uart_remove_one_port(&pch_uart_driver, &priv->port);
1483 pci_set_drvdata(priv->pdev, NULL);
1484 free_page((unsigned long)priv->rxbuf.buf);
1485 }
1486
1487 static void pch_uart_pci_remove(struct pci_dev *pdev)
1488 {
1489 struct eg20t_port *priv;
1490
1491 priv = (struct eg20t_port *)pci_get_drvdata(pdev);
1492
1493 pci_disable_msi(pdev);
1494 pch_uart_exit_port(priv);
1495 pci_disable_device(pdev);
1496 kfree(priv);
1497 return;
1498 }
1499 #ifdef CONFIG_PM
1500 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1501 {
1502 struct eg20t_port *priv = pci_get_drvdata(pdev);
1503
1504 uart_suspend_port(&pch_uart_driver, &priv->port);
1505
1506 pci_save_state(pdev);
1507 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1508 return 0;
1509 }
1510
1511 static int pch_uart_pci_resume(struct pci_dev *pdev)
1512 {
1513 struct eg20t_port *priv = pci_get_drvdata(pdev);
1514 int ret;
1515
1516 pci_set_power_state(pdev, PCI_D0);
1517 pci_restore_state(pdev);
1518
1519 ret = pci_enable_device(pdev);
1520 if (ret) {
1521 dev_err(&pdev->dev,
1522 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1523 return ret;
1524 }
1525
1526 uart_resume_port(&pch_uart_driver, &priv->port);
1527
1528 return 0;
1529 }
1530 #else
1531 #define pch_uart_pci_suspend NULL
1532 #define pch_uart_pci_resume NULL
1533 #endif
1534
1535 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1536 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1537 .driver_data = pch_et20t_uart0},
1538 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1539 .driver_data = pch_et20t_uart1},
1540 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1541 .driver_data = pch_et20t_uart2},
1542 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1543 .driver_data = pch_et20t_uart3},
1544 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1545 .driver_data = pch_ml7213_uart0},
1546 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1547 .driver_data = pch_ml7213_uart1},
1548 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1549 .driver_data = pch_ml7213_uart2},
1550 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1551 .driver_data = pch_ml7223_uart0},
1552 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1553 .driver_data = pch_ml7223_uart1},
1554 {0,},
1555 };
1556
1557 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev,
1558 const struct pci_device_id *id)
1559 {
1560 int ret;
1561 struct eg20t_port *priv;
1562
1563 ret = pci_enable_device(pdev);
1564 if (ret < 0)
1565 goto probe_error;
1566
1567 priv = pch_uart_init_port(pdev, id);
1568 if (!priv) {
1569 ret = -EBUSY;
1570 goto probe_disable_device;
1571 }
1572 pci_set_drvdata(pdev, priv);
1573
1574 return ret;
1575
1576 probe_disable_device:
1577 pci_disable_msi(pdev);
1578 pci_disable_device(pdev);
1579 probe_error:
1580 return ret;
1581 }
1582
1583 static struct pci_driver pch_uart_pci_driver = {
1584 .name = "pch_uart",
1585 .id_table = pch_uart_pci_id,
1586 .probe = pch_uart_pci_probe,
1587 .remove = __devexit_p(pch_uart_pci_remove),
1588 .suspend = pch_uart_pci_suspend,
1589 .resume = pch_uart_pci_resume,
1590 };
1591
1592 static int __init pch_uart_module_init(void)
1593 {
1594 int ret;
1595
1596 /* register as UART driver */
1597 ret = uart_register_driver(&pch_uart_driver);
1598 if (ret < 0)
1599 return ret;
1600
1601 /* register as PCI driver */
1602 ret = pci_register_driver(&pch_uart_pci_driver);
1603 if (ret < 0)
1604 uart_unregister_driver(&pch_uart_driver);
1605
1606 return ret;
1607 }
1608 module_init(pch_uart_module_init);
1609
1610 static void __exit pch_uart_module_exit(void)
1611 {
1612 pci_unregister_driver(&pch_uart_pci_driver);
1613 uart_unregister_driver(&pch_uart_driver);
1614 }
1615 module_exit(pch_uart_module_exit);
1616
1617 MODULE_LICENSE("GPL v2");
1618 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1619 module_param(default_baud, uint, S_IRUGO);
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