arch/arm/mach-bcmring/core.c

   1 /*
   2  *  derived from linux/arch/arm/mach-versatile/core.c
   3  *  linux/arch/arm/mach-bcmring/core.c
   4  *
   5  *  Copyright (C) 1999 - 2003 ARM Limited
   6  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22 /* Portions copyright Broadcom 2008 */
  23
  24 #include <linux/init.h>
  25 #include <linux/device.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/sysdev.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/amba/bus.h>
  31 #include <linux/clocksource.h>
  32 #include <linux/clockchips.h>
  33 #include <linux/clkdev.h>
  34
  35 #include <mach/csp/mm_addr.h>
  36 #include <mach/hardware.h>
  37 #include <linux/io.h>
  38 #include <asm/irq.h>
  39 #include <asm/hardware/arm_timer.h>
  40 #include <asm/mach-types.h>
  41
  42 #include <asm/mach/arch.h>
  43 #include <asm/mach/flash.h>
  44 #include <asm/mach/irq.h>
  45 #include <asm/mach/time.h>
  46 #include <asm/mach/map.h>
  47
  48 #include <cfg_global.h>
  49
  50 #include "clock.h"
  51
  52 #include <csp/secHw.h>
  53 #include <mach/csp/secHw_def.h>
  54 #include <mach/csp/chipcHw_inline.h>
  55 #include <mach/csp/tmrHw_reg.h>
  56
  57 #define AMBA_DEVICE(name, initname, base, plat, size)       \
  58 static struct amba_device name##_device = {     \
  59    .dev = {                                     \
  60       .coherent_dma_mask = ~0,                  \
  61       .init_name = initname,                    \
  62       .platform_data = plat                     \
  63    },                                           \
  64    .res = {                                     \
  65       .start = MM_ADDR_IO_##base,               \
  66                 .end = MM_ADDR_IO_##base + (size) - 1,    \
  67       .flags = IORESOURCE_MEM                   \
  68    },                                           \
  69    .dma_mask = ~0,                              \
  70    .irq = {                                     \
  71       IRQ_##base                                \
  72    }                                            \
  73 }
  74
  75
  76 AMBA_DEVICE(uartA, "uarta", UARTA, NULL, SZ_4K);
  77 AMBA_DEVICE(uartB, "uartb", UARTB, NULL, SZ_4K);
  78
  79 static struct clk pll1_clk = {
  80         .name = "PLL1",
  81         .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1,
  82         .rate_hz = 2000000000,
  83         .use_cnt = 7,
  84 };
  85
  86 static struct clk uart_clk = {
  87         .name = "UART",
  88         .type = CLK_TYPE_PROGRAMMABLE,
  89         .csp_id = chipcHw_CLOCK_UART,
  90         .rate_hz = HW_CFG_UART_CLK_HZ,
  91         .parent = &pll1_clk,
  92 };
  93
  94 static struct clk dummy_apb_pclk = {
  95         .name = "BUSCLK",
  96         .type = CLK_TYPE_PRIMARY,
  97         .mode = CLK_MODE_XTAL,
  98 };
  99
 100 static struct clk_lookup lookups[] = {
 101         {                       /* Bus clock */
 102                 .con_id = "apb_pclk",
 103                 .clk = &dummy_apb_pclk,
 104         }, {                    /* UART0 */
 105                 .dev_id = "uarta",
 106                 .clk = &uart_clk,
 107         }, {                    /* UART1 */
 108                 .dev_id = "uartb",
 109                 .clk = &uart_clk,
 110         }
 111 };
 112
 113 static struct amba_device *amba_devs[] __initdata = {
 114         &uartA_device,
 115         &uartB_device,
 116 };
 117
 118 void __init bcmring_amba_init(void)
 119 {
 120         int i;
 121         u32 bus_clock;
 122
 123 /* Linux is run initially in non-secure mode. Secure peripherals */
 124 /* generate FIQ, and must be handled in secure mode. Until we have */
 125 /* a linux security monitor implementation, keep everything in */
 126 /* non-secure mode. */
 127         chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU);
 128         secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL |
 129                           secHw_BLK_MASK_KEY_SCAN |
 130                           secHw_BLK_MASK_TOUCH_SCREEN |
 131                           secHw_BLK_MASK_UART0 |
 132                           secHw_BLK_MASK_UART1 |
 133                           secHw_BLK_MASK_WATCHDOG |
 134                           secHw_BLK_MASK_SPUM |
 135                           secHw_BLK_MASK_DDR2 |
 136                           secHw_BLK_MASK_SPU |
 137                           secHw_BLK_MASK_PKA |
 138                           secHw_BLK_MASK_RNG |
 139                           secHw_BLK_MASK_RTC |
 140                           secHw_BLK_MASK_OTP |
 141                           secHw_BLK_MASK_BOOT |
 142                           secHw_BLK_MASK_MPU |
 143                           secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR);
 144
 145         /* Only the devices attached to the AMBA bus are enabled just before the bus is */
 146         /* scanned and the drivers are loaded. The clocks need to be on for the AMBA bus */
 147         /* driver to access these blocks. The bus is probed, and the drivers are loaded. */
 148         /* FIXME Need to remove enable of PIF once CLCD clock enable used properly in FPGA. */
 149         bus_clock = chipcHw_REG_BUS_CLOCK_GE
 150             | chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1;
 151
 152         chipcHw_busInterfaceClockEnable(bus_clock);
 153
 154         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 155                 struct amba_device *d = amba_devs[i];
 156                 amba_device_register(d, &iomem_resource);
 157         }
 158 }
 159
 160 /*
 161  * Where is the timer (VA)?
 162  */
 163 #define TIMER0_VA_BASE           MM_IO_BASE_TMR
 164 #define TIMER1_VA_BASE          (MM_IO_BASE_TMR + 0x20)
 165 #define TIMER2_VA_BASE          (MM_IO_BASE_TMR + 0x40)
 166 #define TIMER3_VA_BASE          (MM_IO_BASE_TMR + 0x60)
 167
 168 /* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically  150-166 MHz */
 169 #if defined(CONFIG_ARCH_FPGA11107)
 170 /* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
 171 /* slow down Linux's sense of time */
 172 #define TIMER0_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
 173 #define TIMER1_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
 174 #define TIMER3_FREQUENCY_MHZ  (tmrHw_HIGH_FREQUENCY_MHZ * 30)
 175 #define TIMER3_FREQUENCY_KHZ   (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
 176 #else
 177 #define TIMER0_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
 178 #define TIMER1_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
 179 #define TIMER3_FREQUENCY_MHZ  tmrHw_HIGH_FREQUENCY_MHZ
 180 #define TIMER3_FREQUENCY_KHZ  (tmrHw_HIGH_FREQUENCY_HZ / 1000)
 181 #endif
 182
 183 #define TICKS_PER_uSEC     TIMER0_FREQUENCY_MHZ
 184
 185 /*
 186  *  These are useconds NOT ticks.
 187  *
 188  */
 189 #define mSEC_1                          1000
 190 #define mSEC_5                          (mSEC_1 * 5)
 191 #define mSEC_10                         (mSEC_1 * 10)
 192 #define mSEC_25                         (mSEC_1 * 25)
 193 #define SEC_1                           (mSEC_1 * 1000)
 194
 195 /*
 196  * How long is the timer interval?
 197  */
 198 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
 199 #if TIMER_INTERVAL >= 0x100000
 200 #define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
 201 #define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
 202 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
 203 #elif TIMER_INTERVAL >= 0x10000
 204 #define TIMER_RELOAD    (TIMER_INTERVAL >> 4)   /* Divide by 16 */
 205 #define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
 206 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
 207 #else
 208 #define TIMER_RELOAD    (TIMER_INTERVAL)
 209 #define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
 210 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
 211 #endif
 212
 213 static void timer_set_mode(enum clock_event_mode mode,
 214                            struct clock_event_device *clk)
 215 {
 216         unsigned long ctrl;
 217
 218         switch (mode) {
 219         case CLOCK_EVT_MODE_PERIODIC:
 220                 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
 221
 222                 ctrl = TIMER_CTRL_PERIODIC;
 223                 ctrl |=
 224                     TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE |
 225                     TIMER_CTRL_ENABLE;
 226                 break;
 227         case CLOCK_EVT_MODE_ONESHOT:
 228                 /* period set, and timer enabled in 'next_event' hook */
 229                 ctrl = TIMER_CTRL_ONESHOT;
 230                 ctrl |= TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE;
 231                 break;
 232         case CLOCK_EVT_MODE_UNUSED:
 233         case CLOCK_EVT_MODE_SHUTDOWN:
 234         default:
 235                 ctrl = 0;
 236         }
 237
 238         writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
 239 }
 240
 241 static int timer_set_next_event(unsigned long evt,
 242                                 struct clock_event_device *unused)
 243 {
 244         unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
 245
 246         writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
 247         writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
 248
 249         return 0;
 250 }
 251
 252 static struct clock_event_device timer0_clockevent = {
 253         .name = "timer0",
 254         .shift = 32,
 255         .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 256         .set_mode = timer_set_mode,
 257         .set_next_event = timer_set_next_event,
 258 };
 259
 260 /*
 261  * IRQ handler for the timer
 262  */
 263 static irqreturn_t bcmring_timer_interrupt(int irq, void *dev_id)
 264 {
 265         struct clock_event_device *evt = &timer0_clockevent;
 266
 267         writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
 268
 269         evt->event_handler(evt);
 270
 271         return IRQ_HANDLED;
 272 }
 273
 274 static struct irqaction bcmring_timer_irq = {
 275         .name = "bcmring Timer Tick",
 276         .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 277         .handler = bcmring_timer_interrupt,
 278 };
 279
 280 static cycle_t bcmring_get_cycles_timer1(struct clocksource *cs)
 281 {
 282         return ~readl(TIMER1_VA_BASE + TIMER_VALUE);
 283 }
 284
 285 static cycle_t bcmring_get_cycles_timer3(struct clocksource *cs)
 286 {
 287         return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
 288 }
 289
 290 static struct clocksource clocksource_bcmring_timer1 = {
 291         .name = "timer1",
 292         .rating = 200,
 293         .read = bcmring_get_cycles_timer1,
 294         .mask = CLOCKSOURCE_MASK(32),
 295         .flags = CLOCK_SOURCE_IS_CONTINUOUS,
 296 };
 297
 298 static struct clocksource clocksource_bcmring_timer3 = {
 299         .name = "timer3",
 300         .rating = 100,
 301         .read = bcmring_get_cycles_timer3,
 302         .mask = CLOCKSOURCE_MASK(32),
 303         .flags = CLOCK_SOURCE_IS_CONTINUOUS,
 304 };
 305
 306 static int __init bcmring_clocksource_init(void)
 307 {
 308         /* setup timer1 as free-running clocksource */
 309         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 310         writel(0xffffffff, TIMER1_VA_BASE + TIMER_LOAD);
 311         writel(0xffffffff, TIMER1_VA_BASE + TIMER_VALUE);
 312         writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
 313                TIMER1_VA_BASE + TIMER_CTRL);
 314
 315         clocksource_register_khz(&clocksource_bcmring_timer1,
 316                                  TIMER1_FREQUENCY_MHZ * 1000);
 317
 318         /* setup timer3 as free-running clocksource */
 319         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 320         writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
 321         writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
 322         writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
 323                TIMER3_VA_BASE + TIMER_CTRL);
 324
 325         clocksource_register_khz(&clocksource_bcmring_timer3,
 326                                  TIMER3_FREQUENCY_KHZ);
 327
 328         return 0;
 329 }
 330
 331 /*
 332  * Set up timer interrupt, and return the current time in seconds.
 333  */
 334 void __init bcmring_init_timer(void)
 335 {
 336         printk(KERN_INFO "bcmring_init_timer\n");
 337         /*
 338          * Initialise to a known state (all timers off)
 339          */
 340         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 341         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 342         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 343         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 344
 345         /*
 346          * Make irqs happen for the system timer
 347          */
 348         setup_irq(IRQ_TIMER0, &bcmring_timer_irq);
 349
 350         bcmring_clocksource_init();
 351
 352         timer0_clockevent.mult =
 353             div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
 354         timer0_clockevent.max_delta_ns =
 355             clockevent_delta2ns(0xffffffff, &timer0_clockevent);
 356         timer0_clockevent.min_delta_ns =
 357             clockevent_delta2ns(0xf, &timer0_clockevent);
 358
 359         timer0_clockevent.cpumask = cpumask_of(0);
 360         clockevents_register_device(&timer0_clockevent);
 361 }
 362
 363 struct sys_timer bcmring_timer = {
 364         .init = bcmring_init_timer,
 365 };
 366
 367 void __init bcmring_init_early(void)
 368 {
 369         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 370 }