drivers/net/dsa/mv88e6123_61_65.c

   1 /*
   2  * net/dsa/mv88e6123_61_65.c - Marvell 88e6123/6161/6165 switch chip support
   3  * Copyright (c) 2008-2009 Marvell Semiconductor
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  */
  10
  11 #include <linux/list.h>
  12 #include <linux/netdevice.h>
  13 #include <linux/phy.h>
  14 #include <net/dsa.h>
  15 #include "mv88e6xxx.h"
  16
  17 static char *mv88e6123_61_65_probe(struct mii_bus *bus, int sw_addr)
  18 {
  19         int ret;
  20
  21         ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03);
  22         if (ret >= 0) {
  23                 if (ret == 0x1212)
  24                         return "Marvell 88E6123 (A1)";
  25                 if (ret == 0x1213)
  26                         return "Marvell 88E6123 (A2)";
  27                 if ((ret & 0xfff0) == 0x1210)
  28                         return "Marvell 88E6123";
  29
  30                 if (ret == 0x1612)
  31                         return "Marvell 88E6161 (A1)";
  32                 if (ret == 0x1613)
  33                         return "Marvell 88E6161 (A2)";
  34                 if ((ret & 0xfff0) == 0x1610)
  35                         return "Marvell 88E6161";
  36
  37                 if (ret == 0x1652)
  38                         return "Marvell 88E6165 (A1)";
  39                 if (ret == 0x1653)
  40                         return "Marvell 88e6165 (A2)";
  41                 if ((ret & 0xfff0) == 0x1650)
  42                         return "Marvell 88E6165";
  43         }
  44
  45         return NULL;
  46 }
  47
  48 static int mv88e6123_61_65_switch_reset(struct dsa_switch *ds)
  49 {
  50         int i;
  51         int ret;
  52
  53         /*
  54          * Set all ports to the disabled state.
  55          */
  56         for (i = 0; i < 8; i++) {
  57                 ret = REG_READ(REG_PORT(i), 0x04);
  58                 REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
  59         }
  60
  61         /*
  62          * Wait for transmit queues to drain.
  63          */
  64         msleep(2);
  65
  66         /*
  67          * Reset the switch.
  68          */
  69         REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
  70
  71         /*
  72          * Wait up to one second for reset to complete.
  73          */
  74         for (i = 0; i < 1000; i++) {
  75                 ret = REG_READ(REG_GLOBAL, 0x00);
  76                 if ((ret & 0xc800) == 0xc800)
  77                         break;
  78
  79                 msleep(1);
  80         }
  81         if (i == 1000)
  82                 return -ETIMEDOUT;
  83
  84         return 0;
  85 }
  86
  87 static int mv88e6123_61_65_setup_global(struct dsa_switch *ds)
  88 {
  89         int ret;
  90         int i;
  91
  92         /*
  93          * Disable the PHY polling unit (since there won't be any
  94          * external PHYs to poll), don't discard packets with
  95          * excessive collisions, and mask all interrupt sources.
  96          */
  97         REG_WRITE(REG_GLOBAL, 0x04, 0x0000);
  98
  99         /*
 100          * Set the default address aging time to 5 minutes, and
 101          * enable address learn messages to be sent to all message
 102          * ports.
 103          */
 104         REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);
 105
 106         /*
 107          * Configure the priority mapping registers.
 108          */
 109         ret = mv88e6xxx_config_prio(ds);
 110         if (ret < 0)
 111                 return ret;
 112
 113         /*
 114          * Configure the upstream port, and configure the upstream
 115          * port as the port to which ingress and egress monitor frames
 116          * are to be sent.
 117          */
 118         REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110));
 119
 120         /*
 121          * Disable remote management for now, and set the switch's
 122          * DSA device number.
 123          */
 124         REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f);
 125
 126         /*
 127          * Send all frames with destination addresses matching
 128          * 01:80:c2:00:00:2x to the CPU port.
 129          */
 130         REG_WRITE(REG_GLOBAL2, 0x02, 0xffff);
 131
 132         /*
 133          * Send all frames with destination addresses matching
 134          * 01:80:c2:00:00:0x to the CPU port.
 135          */
 136         REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);
 137
 138         /*
 139          * Disable the loopback filter, disable flow control
 140          * messages, disable flood broadcast override, disable
 141          * removing of provider tags, disable ATU age violation
 142          * interrupts, disable tag flow control, force flow
 143          * control priority to the highest, and send all special
 144          * multicast frames to the CPU at the highest priority.
 145          */
 146         REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);
 147
 148         /*
 149          * Program the DSA routing table.
 150          */
 151         for (i = 0; i < 32; i++) {
 152                 int nexthop;
 153
 154                 nexthop = 0x1f;
 155                 if (i != ds->index && i < ds->dst->pd->nr_chips)
 156                         nexthop = ds->pd->rtable[i] & 0x1f;
 157
 158                 REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop);
 159         }
 160
 161         /*
 162          * Clear all trunk masks.
 163          */
 164         for (i = 0; i < 8; i++)
 165                 REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0xff);
 166
 167         /*
 168          * Clear all trunk mappings.
 169          */
 170         for (i = 0; i < 16; i++)
 171                 REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11));
 172
 173         /*
 174          * Disable ingress rate limiting by resetting all ingress
 175          * rate limit registers to their initial state.
 176          */
 177         for (i = 0; i < 6; i++)
 178                 REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 | (i << 8));
 179
 180         /*
 181          * Initialise cross-chip port VLAN table to reset defaults.
 182          */
 183         REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000);
 184
 185         /*
 186          * Clear the priority override table.
 187          */
 188         for (i = 0; i < 16; i++)
 189                 REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 | (i << 8));
 190
 191         /* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */
 192
 193         return 0;
 194 }
 195
 196 static int mv88e6123_61_65_setup_port(struct dsa_switch *ds, int p)
 197 {
 198         int addr = REG_PORT(p);
 199         u16 val;
 200
 201         /*
 202          * MAC Forcing register: don't force link, speed, duplex
 203          * or flow control state to any particular values on physical
 204          * ports, but force the CPU port and all DSA ports to 1000 Mb/s
 205          * full duplex.
 206          */
 207         if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p))
 208                 REG_WRITE(addr, 0x01, 0x003e);
 209         else
 210                 REG_WRITE(addr, 0x01, 0x0003);
 211
 212         /*
 213          * Do not limit the period of time that this port can be
 214          * paused for by the remote end or the period of time that
 215          * this port can pause the remote end.
 216          */
 217         REG_WRITE(addr, 0x02, 0x0000);
 218
 219         /*
 220          * Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
 221          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
 222          * tunneling, determine priority by looking at 802.1p and IP
 223          * priority fields (IP prio has precedence), and set STP state
 224          * to Forwarding.
 225          *
 226          * If this is the CPU link, use DSA or EDSA tagging depending
 227          * on which tagging mode was configured.
 228          *
 229          * If this is a link to another switch, use DSA tagging mode.
 230          *
 231          * If this is the upstream port for this switch, enable
 232          * forwarding of unknown unicasts and multicasts.
 233          */
 234         val = 0x0433;
 235         if (dsa_is_cpu_port(ds, p)) {
 236                 if (ds->dst->tag_protocol == htons(ETH_P_EDSA))
 237                         val |= 0x3300;
 238                 else
 239                         val |= 0x0100;
 240         }
 241         if (ds->dsa_port_mask & (1 << p))
 242                 val |= 0x0100;
 243         if (p == dsa_upstream_port(ds))
 244                 val |= 0x000c;
 245         REG_WRITE(addr, 0x04, val);
 246
 247         /*
 248          * Port Control 1: disable trunking.  Also, if this is the
 249          * CPU port, enable learn messages to be sent to this port.
 250          */
 251         REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000);
 252
 253         /*
 254          * Port based VLAN map: give each port its own address
 255          * database, allow the CPU port to talk to each of the 'real'
 256          * ports, and allow each of the 'real' ports to only talk to
 257          * the upstream port.
 258          */
 259         val = (p & 0xf) << 12;
 260         if (dsa_is_cpu_port(ds, p))
 261                 val |= ds->phys_port_mask;
 262         else
 263                 val |= 1 << dsa_upstream_port(ds);
 264         REG_WRITE(addr, 0x06, val);
 265
 266         /*
 267          * Default VLAN ID and priority: don't set a default VLAN
 268          * ID, and set the default packet priority to zero.
 269          */
 270         REG_WRITE(addr, 0x07, 0x0000);
 271
 272         /*
 273          * Port Control 2: don't force a good FCS, set the maximum
 274          * frame size to 10240 bytes, don't let the switch add or
 275          * strip 802.1q tags, don't discard tagged or untagged frames
 276          * on this port, do a destination address lookup on all
 277          * received packets as usual, disable ARP mirroring and don't
 278          * send a copy of all transmitted/received frames on this port
 279          * to the CPU.
 280          */
 281         REG_WRITE(addr, 0x08, 0x2080);
 282
 283         /*
 284          * Egress rate control: disable egress rate control.
 285          */
 286         REG_WRITE(addr, 0x09, 0x0001);
 287
 288         /*
 289          * Egress rate control 2: disable egress rate control.
 290          */
 291         REG_WRITE(addr, 0x0a, 0x0000);
 292
 293         /*
 294          * Port Association Vector: when learning source addresses
 295          * of packets, add the address to the address database using
 296          * a port bitmap that has only the bit for this port set and
 297          * the other bits clear.
 298          */
 299         REG_WRITE(addr, 0x0b, 1 << p);
 300
 301         /*
 302          * Port ATU control: disable limiting the number of address
 303          * database entries that this port is allowed to use.
 304          */
 305         REG_WRITE(addr, 0x0c, 0x0000);
 306
 307         /*
 308          * Priorit Override: disable DA, SA and VTU priority override.
 309          */
 310         REG_WRITE(addr, 0x0d, 0x0000);
 311
 312         /*
 313          * Port Ethertype: use the Ethertype DSA Ethertype value.
 314          */
 315         REG_WRITE(addr, 0x0f, ETH_P_EDSA);
 316
 317         /*
 318          * Tag Remap: use an identity 802.1p prio -> switch prio
 319          * mapping.
 320          */
 321         REG_WRITE(addr, 0x18, 0x3210);
 322
 323         /*
 324          * Tag Remap 2: use an identity 802.1p prio -> switch prio
 325          * mapping.
 326          */
 327         REG_WRITE(addr, 0x19, 0x7654);
 328
 329         return 0;
 330 }
 331
 332 static int mv88e6123_61_65_setup(struct dsa_switch *ds)
 333 {
 334         struct mv88e6xxx_priv_state *ps = (void *)(ds + 1);
 335         int i;
 336         int ret;
 337
 338         mutex_init(&ps->smi_mutex);
 339         mutex_init(&ps->stats_mutex);
 340
 341         ret = mv88e6123_61_65_switch_reset(ds);
 342         if (ret < 0)
 343                 return ret;
 344
 345         /* @@@ initialise vtu and atu */
 346
 347         ret = mv88e6123_61_65_setup_global(ds);
 348         if (ret < 0)
 349                 return ret;
 350
 351         for (i = 0; i < 6; i++) {
 352                 ret = mv88e6123_61_65_setup_port(ds, i);
 353                 if (ret < 0)
 354                         return ret;
 355         }
 356
 357         return 0;
 358 }
 359
 360 static int mv88e6123_61_65_port_to_phy_addr(int port)
 361 {
 362         if (port >= 0 && port <= 4)
 363                 return port;
 364         return -1;
 365 }
 366
 367 static int
 368 mv88e6123_61_65_phy_read(struct dsa_switch *ds, int port, int regnum)
 369 {
 370         int addr = mv88e6123_61_65_port_to_phy_addr(port);
 371         return mv88e6xxx_phy_read(ds, addr, regnum);
 372 }
 373
 374 static int
 375 mv88e6123_61_65_phy_write(struct dsa_switch *ds,
 376                               int port, int regnum, u16 val)
 377 {
 378         int addr = mv88e6123_61_65_port_to_phy_addr(port);
 379         return mv88e6xxx_phy_write(ds, addr, regnum, val);
 380 }
 381
 382 static struct mv88e6xxx_hw_stat mv88e6123_61_65_hw_stats[] = {
 383         { "in_good_octets", 8, 0x00, },
 384         { "in_bad_octets", 4, 0x02, },
 385         { "in_unicast", 4, 0x04, },
 386         { "in_broadcasts", 4, 0x06, },
 387         { "in_multicasts", 4, 0x07, },
 388         { "in_pause", 4, 0x16, },
 389         { "in_undersize", 4, 0x18, },
 390         { "in_fragments", 4, 0x19, },
 391         { "in_oversize", 4, 0x1a, },
 392         { "in_jabber", 4, 0x1b, },
 393         { "in_rx_error", 4, 0x1c, },
 394         { "in_fcs_error", 4, 0x1d, },
 395         { "out_octets", 8, 0x0e, },
 396         { "out_unicast", 4, 0x10, },
 397         { "out_broadcasts", 4, 0x13, },
 398         { "out_multicasts", 4, 0x12, },
 399         { "out_pause", 4, 0x15, },
 400         { "excessive", 4, 0x11, },
 401         { "collisions", 4, 0x1e, },
 402         { "deferred", 4, 0x05, },
 403         { "single", 4, 0x14, },
 404         { "multiple", 4, 0x17, },
 405         { "out_fcs_error", 4, 0x03, },
 406         { "late", 4, 0x1f, },
 407         { "hist_64bytes", 4, 0x08, },
 408         { "hist_65_127bytes", 4, 0x09, },
 409         { "hist_128_255bytes", 4, 0x0a, },
 410         { "hist_256_511bytes", 4, 0x0b, },
 411         { "hist_512_1023bytes", 4, 0x0c, },
 412         { "hist_1024_max_bytes", 4, 0x0d, },
 413 };
 414
 415 static void
 416 mv88e6123_61_65_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
 417 {
 418         mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6123_61_65_hw_stats),
 419                               mv88e6123_61_65_hw_stats, port, data);
 420 }
 421
 422 static void
 423 mv88e6123_61_65_get_ethtool_stats(struct dsa_switch *ds,
 424                                   int port, uint64_t *data)
 425 {
 426         mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6123_61_65_hw_stats),
 427                                     mv88e6123_61_65_hw_stats, port, data);
 428 }
 429
 430 static int mv88e6123_61_65_get_sset_count(struct dsa_switch *ds)
 431 {
 432         return ARRAY_SIZE(mv88e6123_61_65_hw_stats);
 433 }
 434
 435 struct dsa_switch_driver mv88e6123_61_65_switch_driver = {
 436         .tag_protocol           = cpu_to_be16(ETH_P_EDSA),
 437         .priv_size              = sizeof(struct mv88e6xxx_priv_state),
 438         .probe                  = mv88e6123_61_65_probe,
 439         .setup                  = mv88e6123_61_65_setup,
 440         .set_addr               = mv88e6xxx_set_addr_indirect,
 441         .phy_read               = mv88e6123_61_65_phy_read,
 442         .phy_write              = mv88e6123_61_65_phy_write,
 443         .poll_link              = mv88e6xxx_poll_link,
 444         .get_strings            = mv88e6123_61_65_get_strings,
 445         .get_ethtool_stats      = mv88e6123_61_65_get_ethtool_stats,
 446         .get_sset_count         = mv88e6123_61_65_get_sset_count,
 447 };
 448
 449 MODULE_ALIAS("platform:mv88e6123");
 450 MODULE_ALIAS("platform:mv88e6161");
 451 MODULE_ALIAS("platform:mv88e6165");