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driver-core: remove sysdev.h usage.
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / arm / mach-versatile / core.c
blob3a4893b82ad1a219fcf25ac1c3dac010736c0855
1 /*
2 * linux/arch/arm/mach-versatile/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21 #include <linux/init.h>
22 #include <linux/device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_device.h>
25 #include <linux/interrupt.h>
26 #include <linux/irqdomain.h>
27 #include <linux/of_address.h>
28 #include <linux/of_platform.h>
29 #include <linux/amba/bus.h>
30 #include <linux/amba/clcd.h>
31 #include <linux/amba/pl061.h>
32 #include <linux/amba/mmci.h>
33 #include <linux/amba/pl022.h>
34 #include <linux/io.h>
35 #include <linux/gfp.h>
36 #include <linux/clkdev.h>
37 #include <linux/mtd/physmap.h>
38
39 #include <asm/system.h>
40 #include <asm/irq.h>
41 #include <asm/leds.h>
42 #include <asm/hardware/arm_timer.h>
43 #include <asm/hardware/icst.h>
44 #include <asm/hardware/vic.h>
45 #include <asm/mach-types.h>
46
47 #include <asm/mach/arch.h>
48 #include <asm/mach/irq.h>
49 #include <asm/mach/time.h>
50 #include <asm/mach/map.h>
51 #include <mach/hardware.h>
52 #include <mach/platform.h>
53 #include <asm/hardware/timer-sp.h>
54
55 #include <plat/clcd.h>
56 #include <plat/fpga-irq.h>
57 #include <plat/sched_clock.h>
58
59 #include "core.h"
60
61 /*
62 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
63 * is the (PA >> 12).
64 *
65 * Setup a VA for the Versatile Vectored Interrupt Controller.
66 */
67 #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
68 #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
69
70 static struct fpga_irq_data sic_irq = {
71 .base = VA_SIC_BASE,
72 .irq_start = IRQ_SIC_START,
73 .chip.name = "SIC",
74 };
75
76 #if 1
77 #define IRQ_MMCI0A IRQ_VICSOURCE22
78 #define IRQ_AACI IRQ_VICSOURCE24
79 #define IRQ_ETH IRQ_VICSOURCE25
80 #define PIC_MASK 0xFFD00000
81 #else
82 #define IRQ_MMCI0A IRQ_SIC_MMCI0A
83 #define IRQ_AACI IRQ_SIC_AACI
84 #define IRQ_ETH IRQ_SIC_ETH
85 #define PIC_MASK 0
86 #endif
87
88 /* Lookup table for finding a DT node that represents the vic instance */
89 static const struct of_device_id vic_of_match[] __initconst = {
90 { .compatible = "arm,versatile-vic", },
91 {}
92 };
93
94 static const struct of_device_id sic_of_match[] __initconst = {
95 { .compatible = "arm,versatile-sic", },
96 {}
97 };
98
99 void __init versatile_init_irq(void)
100 {
101 vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
102 irq_domain_generate_simple(vic_of_match, VERSATILE_VIC_BASE, IRQ_VIC_START);
103
104 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
105
106 fpga_irq_init(IRQ_VICSOURCE31, ~PIC_MASK, &sic_irq);
107 irq_domain_generate_simple(sic_of_match, VERSATILE_SIC_BASE, IRQ_SIC_START);
108
109 /*
110 * Interrupts on secondary controller from 0 to 8 are routed to
111 * source 31 on PIC.
112 * Interrupts from 21 to 31 are routed directly to the VIC on
113 * the corresponding number on primary controller. This is controlled
114 * by setting PIC_ENABLEx.
115 */
116 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
117 }
118
119 static struct map_desc versatile_io_desc[] __initdata = {
120 {
121 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
122 .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
123 .length = SZ_4K,
124 .type = MT_DEVICE
125 }, {
126 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
127 .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
128 .length = SZ_4K,
129 .type = MT_DEVICE
130 }, {
131 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
132 .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
133 .length = SZ_4K,
134 .type = MT_DEVICE
135 }, {
136 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
137 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
138 .length = SZ_4K * 9,
139 .type = MT_DEVICE
140 },
141 #ifdef CONFIG_MACH_VERSATILE_AB
142 {
143 .virtual = IO_ADDRESS(VERSATILE_GPIO0_BASE),
144 .pfn = __phys_to_pfn(VERSATILE_GPIO0_BASE),
145 .length = SZ_4K,
146 .type = MT_DEVICE
147 }, {
148 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
149 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
150 .length = SZ_64M,
151 .type = MT_DEVICE
152 },
153 #endif
154 #ifdef CONFIG_DEBUG_LL
155 {
156 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
157 .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
158 .length = SZ_4K,
159 .type = MT_DEVICE
160 },
161 #endif
162 #ifdef CONFIG_PCI
163 {
164 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
165 .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
166 .length = SZ_4K,
167 .type = MT_DEVICE
168 }, {
169 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
170 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
171 .length = VERSATILE_PCI_BASE_SIZE,
172 .type = MT_DEVICE
173 }, {
174 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
175 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
176 .length = VERSATILE_PCI_CFG_BASE_SIZE,
177 .type = MT_DEVICE
178 },
179 #if 0
180 {
181 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0,
182 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
183 .length = SZ_16M,
184 .type = MT_DEVICE
185 }, {
186 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1,
187 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
188 .length = SZ_16M,
189 .type = MT_DEVICE
190 }, {
191 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2,
192 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
193 .length = SZ_16M,
194 .type = MT_DEVICE
195 },
196 #endif
197 #endif
198 };
199
200 void __init versatile_map_io(void)
201 {
202 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
203 }
204
205
206 #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
207
208 static void versatile_flash_set_vpp(struct platform_device *pdev, int on)
209 {
210 u32 val;
211
212 val = __raw_readl(VERSATILE_FLASHCTRL);
213 if (on)
214 val |= VERSATILE_FLASHPROG_FLVPPEN;
215 else
216 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
217 __raw_writel(val, VERSATILE_FLASHCTRL);
218 }
219
220 static struct physmap_flash_data versatile_flash_data = {
221 .width = 4,
222 .set_vpp = versatile_flash_set_vpp,
223 };
224
225 static struct resource versatile_flash_resource = {
226 .start = VERSATILE_FLASH_BASE,
227 .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
228 .flags = IORESOURCE_MEM,
229 };
230
231 static struct platform_device versatile_flash_device = {
232 .name = "physmap-flash",
233 .id = 0,
234 .dev = {
235 .platform_data = &versatile_flash_data,
236 },
237 .num_resources = 1,
238 .resource = &versatile_flash_resource,
239 };
240
241 static struct resource smc91x_resources[] = {
242 [0] = {
243 .start = VERSATILE_ETH_BASE,
244 .end = VERSATILE_ETH_BASE + SZ_64K - 1,
245 .flags = IORESOURCE_MEM,
246 },
247 [1] = {
248 .start = IRQ_ETH,
249 .end = IRQ_ETH,
250 .flags = IORESOURCE_IRQ,
251 },
252 };
253
254 static struct platform_device smc91x_device = {
255 .name = "smc91x",
256 .id = 0,
257 .num_resources = ARRAY_SIZE(smc91x_resources),
258 .resource = smc91x_resources,
259 };
260
261 static struct resource versatile_i2c_resource = {
262 .start = VERSATILE_I2C_BASE,
263 .end = VERSATILE_I2C_BASE + SZ_4K - 1,
264 .flags = IORESOURCE_MEM,
265 };
266
267 static struct platform_device versatile_i2c_device = {
268 .name = "versatile-i2c",
269 .id = 0,
270 .num_resources = 1,
271 .resource = &versatile_i2c_resource,
272 };
273
274 static struct i2c_board_info versatile_i2c_board_info[] = {
275 {
276 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
277 },
278 };
279
280 static int __init versatile_i2c_init(void)
281 {
282 return i2c_register_board_info(0, versatile_i2c_board_info,
283 ARRAY_SIZE(versatile_i2c_board_info));
284 }
285 arch_initcall(versatile_i2c_init);
286
287 #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
288
289 unsigned int mmc_status(struct device *dev)
290 {
291 struct amba_device *adev = container_of(dev, struct amba_device, dev);
292 u32 mask;
293
294 if (adev->res.start == VERSATILE_MMCI0_BASE)
295 mask = 1;
296 else
297 mask = 2;
298
299 return readl(VERSATILE_SYSMCI) & mask;
300 }
301
302 static struct mmci_platform_data mmc0_plat_data = {
303 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
304 .status = mmc_status,
305 .gpio_wp = -1,
306 .gpio_cd = -1,
307 };
308
309 static struct resource char_lcd_resources[] = {
310 {
311 .start = VERSATILE_CHAR_LCD_BASE,
312 .end = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
313 .flags = IORESOURCE_MEM,
314 },
315 };
316
317 static struct platform_device char_lcd_device = {
318 .name = "arm-charlcd",
319 .id = -1,
320 .num_resources = ARRAY_SIZE(char_lcd_resources),
321 .resource = char_lcd_resources,
322 };
323
324 /*
325 * Clock handling
326 */
327 static const struct icst_params versatile_oscvco_params = {
328 .ref = 24000000,
329 .vco_max = ICST307_VCO_MAX,
330 .vco_min = ICST307_VCO_MIN,
331 .vd_min = 4 + 8,
332 .vd_max = 511 + 8,
333 .rd_min = 1 + 2,
334 .rd_max = 127 + 2,
335 .s2div = icst307_s2div,
336 .idx2s = icst307_idx2s,
337 };
338
339 static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
340 {
341 void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
342 u32 val;
343
344 val = readl(clk->vcoreg) & ~0x7ffff;
345 val |= vco.v | (vco.r << 9) | (vco.s << 16);
346
347 writel(0xa05f, sys_lock);
348 writel(val, clk->vcoreg);
349 writel(0, sys_lock);
350 }
351
352 static const struct clk_ops osc4_clk_ops = {
353 .round = icst_clk_round,
354 .set = icst_clk_set,
355 .setvco = versatile_oscvco_set,
356 };
357
358 static struct clk osc4_clk = {
359 .ops = &osc4_clk_ops,
360 .params = &versatile_oscvco_params,
361 };
362
363 /*
364 * These are fixed clocks.
365 */
366 static struct clk ref24_clk = {
367 .rate = 24000000,
368 };
369
370 static struct clk sp804_clk = {
371 .rate = 1000000,
372 };
373
374 static struct clk dummy_apb_pclk;
375
376 static struct clk_lookup lookups[] = {
377 { /* AMBA bus clock */
378 .con_id = "apb_pclk",
379 .clk = &dummy_apb_pclk,
380 }, { /* UART0 */
381 .dev_id = "dev:f1",
382 .clk = &ref24_clk,
383 }, { /* UART1 */
384 .dev_id = "dev:f2",
385 .clk = &ref24_clk,
386 }, { /* UART2 */
387 .dev_id = "dev:f3",
388 .clk = &ref24_clk,
389 }, { /* UART3 */
390 .dev_id = "fpga:09",
391 .clk = &ref24_clk,
392 }, { /* KMI0 */
393 .dev_id = "fpga:06",
394 .clk = &ref24_clk,
395 }, { /* KMI1 */
396 .dev_id = "fpga:07",
397 .clk = &ref24_clk,
398 }, { /* MMC0 */
399 .dev_id = "fpga:05",
400 .clk = &ref24_clk,
401 }, { /* MMC1 */
402 .dev_id = "fpga:0b",
403 .clk = &ref24_clk,
404 }, { /* SSP */
405 .dev_id = "dev:f4",
406 .clk = &ref24_clk,
407 }, { /* CLCD */
408 .dev_id = "dev:20",
409 .clk = &osc4_clk,
410 }, { /* SP804 timers */
411 .dev_id = "sp804",
412 .clk = &sp804_clk,
413 },
414 };
415
416 /*
417 * CLCD support.
418 */
419 #define SYS_CLCD_MODE_MASK (3 << 0)
420 #define SYS_CLCD_MODE_888 (0 << 0)
421 #define SYS_CLCD_MODE_5551 (1 << 0)
422 #define SYS_CLCD_MODE_565_RLSB (2 << 0)
423 #define SYS_CLCD_MODE_565_BLSB (3 << 0)
424 #define SYS_CLCD_NLCDIOON (1 << 2)
425 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
426 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
427 #define SYS_CLCD_ID_MASK (0x1f << 8)
428 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
429 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
430 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
431 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
432 #define SYS_CLCD_ID_VGA (0x1f << 8)
433
434 static bool is_sanyo_2_5_lcd;
435
436 /*
437 * Disable all display connectors on the interface module.
438 */
439 static void versatile_clcd_disable(struct clcd_fb *fb)
440 {
441 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
442 u32 val;
443
444 val = readl(sys_clcd);
445 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
446 writel(val, sys_clcd);
447
448 #ifdef CONFIG_MACH_VERSATILE_AB
449 /*
450 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
451 */
452 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
453 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
454 unsigned long ctrl;
455
456 ctrl = readl(versatile_ib2_ctrl);
457 ctrl &= ~0x01;
458 writel(ctrl, versatile_ib2_ctrl);
459 }
460 #endif
461 }
462
463 /*
464 * Enable the relevant connector on the interface module.
465 */
466 static void versatile_clcd_enable(struct clcd_fb *fb)
467 {
468 struct fb_var_screeninfo *var = &fb->fb.var;
469 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
470 u32 val;
471
472 val = readl(sys_clcd);
473 val &= ~SYS_CLCD_MODE_MASK;
474
475 switch (var->green.length) {
476 case 5:
477 val |= SYS_CLCD_MODE_5551;
478 break;
479 case 6:
480 if (var->red.offset == 0)
481 val |= SYS_CLCD_MODE_565_RLSB;
482 else
483 val |= SYS_CLCD_MODE_565_BLSB;
484 break;
485 case 8:
486 val |= SYS_CLCD_MODE_888;
487 break;
488 }
489
490 /*
491 * Set the MUX
492 */
493 writel(val, sys_clcd);
494
495 /*
496 * And now enable the PSUs
497 */
498 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
499 writel(val, sys_clcd);
500
501 #ifdef CONFIG_MACH_VERSATILE_AB
502 /*
503 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
504 */
505 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
506 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
507 unsigned long ctrl;
508
509 ctrl = readl(versatile_ib2_ctrl);
510 ctrl |= 0x01;
511 writel(ctrl, versatile_ib2_ctrl);
512 }
513 #endif
514 }
515
516 /*
517 * Detect which LCD panel is connected, and return the appropriate
518 * clcd_panel structure. Note: we do not have any information on
519 * the required timings for the 8.4in panel, so we presently assume
520 * VGA timings.
521 */
522 static int versatile_clcd_setup(struct clcd_fb *fb)
523 {
524 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
525 const char *panel_name;
526 u32 val;
527
528 is_sanyo_2_5_lcd = false;
529
530 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
531 if (val == SYS_CLCD_ID_SANYO_3_8)
532 panel_name = "Sanyo TM38QV67A02A";
533 else if (val == SYS_CLCD_ID_SANYO_2_5) {
534 panel_name = "Sanyo QVGA Portrait";
535 is_sanyo_2_5_lcd = true;
536 } else if (val == SYS_CLCD_ID_EPSON_2_2)
537 panel_name = "Epson L2F50113T00";
538 else if (val == SYS_CLCD_ID_VGA)
539 panel_name = "VGA";
540 else {
541 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
542 val);
543 panel_name = "VGA";
544 }
545
546 fb->panel = versatile_clcd_get_panel(panel_name);
547 if (!fb->panel)
548 return -EINVAL;
549
550 return versatile_clcd_setup_dma(fb, SZ_1M);
551 }
552
553 static void versatile_clcd_decode(struct clcd_fb *fb, struct clcd_regs *regs)
554 {
555 clcdfb_decode(fb, regs);
556
557 /* Always clear BGR for RGB565: we do the routing externally */
558 if (fb->fb.var.green.length == 6)
559 regs->cntl &= ~CNTL_BGR;
560 }
561
562 static struct clcd_board clcd_plat_data = {
563 .name = "Versatile",
564 .caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888,
565 .check = clcdfb_check,
566 .decode = versatile_clcd_decode,
567 .disable = versatile_clcd_disable,
568 .enable = versatile_clcd_enable,
569 .setup = versatile_clcd_setup,
570 .mmap = versatile_clcd_mmap_dma,
571 .remove = versatile_clcd_remove_dma,
572 };
573
574 static struct pl061_platform_data gpio0_plat_data = {
575 .gpio_base = 0,
576 .irq_base = IRQ_GPIO0_START,
577 };
578
579 static struct pl061_platform_data gpio1_plat_data = {
580 .gpio_base = 8,
581 .irq_base = IRQ_GPIO1_START,
582 };
583
584 static struct pl022_ssp_controller ssp0_plat_data = {
585 .bus_id = 0,
586 .enable_dma = 0,
587 .num_chipselect = 1,
588 };
589
590 #define AACI_IRQ { IRQ_AACI, NO_IRQ }
591 #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
592 #define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
593 #define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
594
595 /*
596 * These devices are connected directly to the multi-layer AHB switch
597 */
598 #define SMC_IRQ { NO_IRQ, NO_IRQ }
599 #define MPMC_IRQ { NO_IRQ, NO_IRQ }
600 #define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
601 #define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
602
603 /*
604 * These devices are connected via the core APB bridge
605 */
606 #define SCTL_IRQ { NO_IRQ, NO_IRQ }
607 #define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
608 #define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
609 #define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
610 #define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
611
612 /*
613 * These devices are connected via the DMA APB bridge
614 */
615 #define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
616 #define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
617 #define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
618 #define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
619 #define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
620
621 /* FPGA Primecells */
622 AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
623 AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
624 AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
625 AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
626
627 /* DevChip Primecells */
628 AMBA_DEVICE(smc, "dev:00", SMC, NULL);
629 AMBA_DEVICE(mpmc, "dev:10", MPMC, NULL);
630 AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
631 AMBA_DEVICE(dmac, "dev:30", DMAC, NULL);
632 AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
633 AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
634 AMBA_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data);
635 AMBA_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data);
636 AMBA_DEVICE(rtc, "dev:e8", RTC, NULL);
637 AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
638 AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
639 AMBA_DEVICE(uart1, "dev:f2", UART1, NULL);
640 AMBA_DEVICE(uart2, "dev:f3", UART2, NULL);
641 AMBA_DEVICE(ssp0, "dev:f4", SSP, &ssp0_plat_data);
642
643 static struct amba_device *amba_devs[] __initdata = {
644 &dmac_device,
645 &uart0_device,
646 &uart1_device,
647 &uart2_device,
648 &smc_device,
649 &mpmc_device,
650 &clcd_device,
651 &sctl_device,
652 &wdog_device,
653 &gpio0_device,
654 &gpio1_device,
655 &rtc_device,
656 &sci0_device,
657 &ssp0_device,
658 &aaci_device,
659 &mmc0_device,
660 &kmi0_device,
661 &kmi1_device,
662 };
663
664 #ifdef CONFIG_OF
665 /*
666 * Lookup table for attaching a specific name and platform_data pointer to
667 * devices as they get created by of_platform_populate(). Ideally this table
668 * would not exist, but the current clock implementation depends on some devices
669 * having a specific name.
670 */
671 struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = {
672 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", NULL),
673 OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI0_BASE, "fpga:06", NULL),
674 OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI1_BASE, "fpga:07", NULL),
675 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART3_BASE, "fpga:09", NULL),
676 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", NULL),
677
678 OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data),
679 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART0_BASE, "dev:f1", NULL),
680 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART1_BASE, "dev:f2", NULL),
681 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART2_BASE, "dev:f3", NULL),
682 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", NULL),
683
684 #if 0
685 /*
686 * These entries are unnecessary because no clocks referencing
687 * them. I've left them in for now as place holders in case
688 * any of them need to be added back, but they should be
689 * removed before actually committing this patch. --gcl
690 */
691 OF_DEV_AUXDATA("arm,primecell", VERSATILE_AACI_BASE, "fpga:04", NULL),
692 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI1_BASE, "fpga:0a", NULL),
693 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SMC_BASE, "dev:00", NULL),
694 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MPMC_BASE, "dev:10", NULL),
695 OF_DEV_AUXDATA("arm,primecell", VERSATILE_DMAC_BASE, "dev:30", NULL),
696
697 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCTL_BASE, "dev:e0", NULL),
698 OF_DEV_AUXDATA("arm,primecell", VERSATILE_WATCHDOG_BASE, "dev:e1", NULL),
699 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO0_BASE, "dev:e4", NULL),
700 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO1_BASE, "dev:e5", NULL),
701 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO2_BASE, "dev:e6", NULL),
702 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO3_BASE, "dev:e7", NULL),
703 OF_DEV_AUXDATA("arm,primecell", VERSATILE_RTC_BASE, "dev:e8", NULL),
704 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI_BASE, "dev:f0", NULL),
705 #endif
706 {}
707 };
708 #endif
709
710 #ifdef CONFIG_LEDS
711 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
712
713 static void versatile_leds_event(led_event_t ledevt)
714 {
715 unsigned long flags;
716 u32 val;
717
718 local_irq_save(flags);
719 val = readl(VA_LEDS_BASE);
720
721 switch (ledevt) {
722 case led_idle_start:
723 val = val & ~VERSATILE_SYS_LED0;
724 break;
725
726 case led_idle_end:
727 val = val | VERSATILE_SYS_LED0;
728 break;
729
730 case led_timer:
731 val = val ^ VERSATILE_SYS_LED1;
732 break;
733
734 case led_halted:
735 val = 0;
736 break;
737
738 default:
739 break;
740 }
741
742 writel(val, VA_LEDS_BASE);
743 local_irq_restore(flags);
744 }
745 #endif /* CONFIG_LEDS */
746
747 /* Early initializations */
748 void __init versatile_init_early(void)
749 {
750 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
751
752 osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET;
753 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
754
755 versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000);
756 }
757
758 void __init versatile_init(void)
759 {
760 int i;
761
762 platform_device_register(&versatile_flash_device);
763 platform_device_register(&versatile_i2c_device);
764 platform_device_register(&smc91x_device);
765 platform_device_register(&char_lcd_device);
766
767 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
768 struct amba_device *d = amba_devs[i];
769 amba_device_register(d, &iomem_resource);
770 }
771
772 #ifdef CONFIG_LEDS
773 leds_event = versatile_leds_event;
774 #endif
775 }
776
777 /*
778 * Where is the timer (VA)?
779 */
780 #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
781 #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
782 #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
783 #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
784
785 /*
786 * Set up timer interrupt, and return the current time in seconds.
787 */
788 static void __init versatile_timer_init(void)
789 {
790 u32 val;
791
792 /*
793 * set clock frequency:
794 * VERSATILE_REFCLK is 32KHz
795 * VERSATILE_TIMCLK is 1MHz
796 */
797 val = readl(__io_address(VERSATILE_SCTL_BASE));
798 writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
799 (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
800 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
801 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
802 __io_address(VERSATILE_SCTL_BASE));
803
804 /*
805 * Initialise to a known state (all timers off)
806 */
807 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
808 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
809 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
810 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
811
812 sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
813 sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1, "timer0");
814 }
815
816 struct sys_timer versatile_timer = {
817 .init = versatile_timer_init,
818 };
819
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree