1 /* linux/arch/arm/mach-s5p64x0/clock-s5p6450.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * S5P6450 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/device.h>
23 #include <mach/hardware.h>
25 #include <mach/regs-clock.h>
26 #include <mach/s5p64x0-clock.h>
28 #include <plat/cpu-freq.h>
29 #include <plat/clock.h>
32 #include <plat/s5p-clock.h>
33 #include <plat/clock-clksrc.h>
34 #include <plat/s5p6450.h>
36 static struct clksrc_clk clk_mout_dpll
= {
40 .sources
= &clk_src_dpll
,
41 .reg_src
= { .reg
= S5P64X0_CLK_SRC0
, .shift
= 5, .size
= 1 },
44 static u32 epll_div
[][5] = {
45 { 133000000, 27307, 55, 2, 2 },
46 { 100000000, 43691, 41, 2, 2 },
47 { 480000000, 0, 80, 2, 0 },
50 static int s5p6450_epll_set_rate(struct clk
*clk
, unsigned long rate
)
52 unsigned int epll_con
, epll_con_k
;
55 if (clk
->rate
== rate
) /* Return if nothing changed */
58 epll_con
= __raw_readl(S5P64X0_EPLL_CON
);
59 epll_con_k
= __raw_readl(S5P64X0_EPLL_CON_K
);
61 epll_con_k
&= ~(PLL90XX_KDIV_MASK
);
62 epll_con
&= ~(PLL90XX_MDIV_MASK
| PLL90XX_PDIV_MASK
| PLL90XX_SDIV_MASK
);
64 for (i
= 0; i
< ARRAY_SIZE(epll_div
); i
++) {
65 if (epll_div
[i
][0] == rate
) {
66 epll_con_k
|= (epll_div
[i
][1] << PLL90XX_KDIV_SHIFT
);
67 epll_con
|= (epll_div
[i
][2] << PLL90XX_MDIV_SHIFT
) |
68 (epll_div
[i
][3] << PLL90XX_PDIV_SHIFT
) |
69 (epll_div
[i
][4] << PLL90XX_SDIV_SHIFT
);
74 if (i
== ARRAY_SIZE(epll_div
)) {
75 printk(KERN_ERR
"%s: Invalid Clock EPLL Frequency\n", __func__
);
79 __raw_writel(epll_con
, S5P64X0_EPLL_CON
);
80 __raw_writel(epll_con_k
, S5P64X0_EPLL_CON_K
);
82 printk(KERN_WARNING
"EPLL Rate changes from %lu to %lu\n",
90 static struct clk_ops s5p6450_epll_ops
= {
91 .get_rate
= s5p_epll_get_rate
,
92 .set_rate
= s5p6450_epll_set_rate
,
95 static struct clksrc_clk clk_dout_epll
= {
98 .parent
= &clk_mout_epll
.clk
,
100 .reg_div
= { .reg
= S5P64X0_CLK_DIV1
, .shift
= 24, .size
= 4 },
103 static struct clksrc_clk clk_mout_hclk_sel
= {
105 .name
= "mout_hclk_sel",
107 .sources
= &clkset_hclk_low
,
108 .reg_src
= { .reg
= S5P64X0_OTHERS
, .shift
= 15, .size
= 1 },
111 static struct clk
*clkset_hclk_list
[] = {
112 &clk_mout_hclk_sel
.clk
,
116 static struct clksrc_sources clkset_hclk
= {
117 .sources
= clkset_hclk_list
,
118 .nr_sources
= ARRAY_SIZE(clkset_hclk_list
),
121 static struct clksrc_clk clk_hclk
= {
125 .sources
= &clkset_hclk
,
126 .reg_src
= { .reg
= S5P64X0_OTHERS
, .shift
= 14, .size
= 1 },
127 .reg_div
= { .reg
= S5P64X0_CLK_DIV0
, .shift
= 8, .size
= 4 },
130 static struct clksrc_clk clk_pclk
= {
133 .parent
= &clk_hclk
.clk
,
135 .reg_div
= { .reg
= S5P64X0_CLK_DIV0
, .shift
= 12, .size
= 4 },
137 static struct clksrc_clk clk_dout_pwm_ratio0
= {
139 .name
= "clk_dout_pwm_ratio0",
140 .parent
= &clk_mout_hclk_sel
.clk
,
142 .reg_div
= { .reg
= S5P64X0_CLK_DIV3
, .shift
= 16, .size
= 4 },
145 static struct clksrc_clk clk_pclk_to_wdt_pwm
= {
147 .name
= "clk_pclk_to_wdt_pwm",
148 .parent
= &clk_dout_pwm_ratio0
.clk
,
150 .reg_div
= { .reg
= S5P64X0_CLK_DIV3
, .shift
= 20, .size
= 4 },
153 static struct clksrc_clk clk_hclk_low
= {
155 .name
= "clk_hclk_low",
157 .sources
= &clkset_hclk_low
,
158 .reg_src
= { .reg
= S5P64X0_OTHERS
, .shift
= 6, .size
= 1 },
159 .reg_div
= { .reg
= S5P64X0_CLK_DIV3
, .shift
= 8, .size
= 4 },
162 static struct clksrc_clk clk_pclk_low
= {
164 .name
= "clk_pclk_low",
165 .parent
= &clk_hclk_low
.clk
,
167 .reg_div
= { .reg
= S5P64X0_CLK_DIV3
, .shift
= 12, .size
= 4 },
171 * The following clocks will be disabled during clock initialization. It is
172 * recommended to keep the following clocks disabled until the driver requests
173 * for enabling the clock.
175 static struct clk init_clocks_off
[] = {
178 .parent
= &clk_hclk_low
.clk
,
179 .enable
= s5p64x0_hclk0_ctrl
,
183 .devname
= "dma-pl330",
184 .parent
= &clk_hclk_low
.clk
,
185 .enable
= s5p64x0_hclk0_ctrl
,
186 .ctrlbit
= (1 << 12),
189 .devname
= "s3c-sdhci.0",
190 .parent
= &clk_hclk_low
.clk
,
191 .enable
= s5p64x0_hclk0_ctrl
,
192 .ctrlbit
= (1 << 17),
195 .devname
= "s3c-sdhci.1",
196 .parent
= &clk_hclk_low
.clk
,
197 .enable
= s5p64x0_hclk0_ctrl
,
198 .ctrlbit
= (1 << 18),
201 .devname
= "s3c-sdhci.2",
202 .parent
= &clk_hclk_low
.clk
,
203 .enable
= s5p64x0_hclk0_ctrl
,
204 .ctrlbit
= (1 << 19),
207 .parent
= &clk_hclk_low
.clk
,
208 .enable
= s5p64x0_hclk0_ctrl
,
209 .ctrlbit
= (1 << 20),
213 .enable
= s5p64x0_hclk1_ctrl
,
217 .parent
= &clk_pclk_low
.clk
,
218 .enable
= s5p64x0_pclk_ctrl
,
222 .parent
= &clk_pclk_low
.clk
,
223 .enable
= s5p64x0_pclk_ctrl
,
227 .parent
= &clk_pclk_low
.clk
,
228 .enable
= s5p64x0_pclk_ctrl
,
229 .ctrlbit
= (1 << 12),
232 .devname
= "s3c2440-i2c.0",
233 .parent
= &clk_pclk_low
.clk
,
234 .enable
= s5p64x0_pclk_ctrl
,
235 .ctrlbit
= (1 << 17),
238 .devname
= "s3c64xx-spi.0",
239 .parent
= &clk_pclk_low
.clk
,
240 .enable
= s5p64x0_pclk_ctrl
,
241 .ctrlbit
= (1 << 21),
244 .devname
= "s3c64xx-spi.1",
245 .parent
= &clk_pclk_low
.clk
,
246 .enable
= s5p64x0_pclk_ctrl
,
247 .ctrlbit
= (1 << 22),
250 .devname
= "samsung-i2s.0",
251 .parent
= &clk_pclk_low
.clk
,
252 .enable
= s5p64x0_pclk_ctrl
,
253 .ctrlbit
= (1 << 26),
256 .devname
= "samsung-i2s.1",
257 .parent
= &clk_pclk_low
.clk
,
258 .enable
= s5p64x0_pclk_ctrl
,
259 .ctrlbit
= (1 << 15),
262 .devname
= "samsung-i2s.2",
263 .parent
= &clk_pclk_low
.clk
,
264 .enable
= s5p64x0_pclk_ctrl
,
265 .ctrlbit
= (1 << 16),
268 .devname
= "s3c2440-i2c.1",
269 .parent
= &clk_pclk_low
.clk
,
270 .enable
= s5p64x0_pclk_ctrl
,
271 .ctrlbit
= (1 << 27),
274 .parent
= &clk_pclk
.clk
,
275 .enable
= s5p64x0_pclk_ctrl
,
276 .ctrlbit
= (1 << 30),
281 * The following clocks will be enabled during clock initialization.
283 static struct clk init_clocks
[] = {
286 .parent
= &clk_hclk
.clk
,
287 .enable
= s5p64x0_hclk0_ctrl
,
291 .parent
= &clk_hclk
.clk
,
292 .enable
= s5p64x0_hclk0_ctrl
,
293 .ctrlbit
= (1 << 21),
296 .devname
= "s3c6400-uart.0",
297 .parent
= &clk_pclk_low
.clk
,
298 .enable
= s5p64x0_pclk_ctrl
,
302 .devname
= "s3c6400-uart.1",
303 .parent
= &clk_pclk_low
.clk
,
304 .enable
= s5p64x0_pclk_ctrl
,
308 .devname
= "s3c6400-uart.2",
309 .parent
= &clk_pclk_low
.clk
,
310 .enable
= s5p64x0_pclk_ctrl
,
314 .devname
= "s3c6400-uart.3",
315 .parent
= &clk_pclk_low
.clk
,
316 .enable
= s5p64x0_pclk_ctrl
,
320 .parent
= &clk_pclk_to_wdt_pwm
.clk
,
321 .enable
= s5p64x0_pclk_ctrl
,
325 .parent
= &clk_pclk_low
.clk
,
326 .enable
= s5p64x0_pclk_ctrl
,
327 .ctrlbit
= (1 << 18),
331 static struct clk
*clkset_uart_list
[] = {
336 static struct clksrc_sources clkset_uart
= {
337 .sources
= clkset_uart_list
,
338 .nr_sources
= ARRAY_SIZE(clkset_uart_list
),
341 static struct clk
*clkset_mali_list
[] = {
347 static struct clksrc_sources clkset_mali
= {
348 .sources
= clkset_mali_list
,
349 .nr_sources
= ARRAY_SIZE(clkset_mali_list
),
352 static struct clk
*clkset_group2_list
[] = {
358 static struct clksrc_sources clkset_group2
= {
359 .sources
= clkset_group2_list
,
360 .nr_sources
= ARRAY_SIZE(clkset_group2_list
),
363 static struct clk
*clkset_dispcon_list
[] = {
370 static struct clksrc_sources clkset_dispcon
= {
371 .sources
= clkset_dispcon_list
,
372 .nr_sources
= ARRAY_SIZE(clkset_dispcon_list
),
375 static struct clk
*clkset_hsmmc44_list
[] = {
383 static struct clksrc_sources clkset_hsmmc44
= {
384 .sources
= clkset_hsmmc44_list
,
385 .nr_sources
= ARRAY_SIZE(clkset_hsmmc44_list
),
388 static struct clk
*clkset_sclk_audio0_list
[] = {
389 [0] = &clk_dout_epll
.clk
,
390 [1] = &clk_dout_mpll
.clk
,
391 [2] = &clk_ext_xtal_mux
,
396 static struct clksrc_sources clkset_sclk_audio0
= {
397 .sources
= clkset_sclk_audio0_list
,
398 .nr_sources
= ARRAY_SIZE(clkset_sclk_audio0_list
),
401 static struct clksrc_clk clk_sclk_audio0
= {
404 .enable
= s5p64x0_sclk_ctrl
,
406 .parent
= &clk_dout_epll
.clk
,
408 .sources
= &clkset_sclk_audio0
,
409 .reg_src
= { .reg
= S5P64X0_CLK_SRC1
, .shift
= 10, .size
= 3 },
410 .reg_div
= { .reg
= S5P64X0_CLK_DIV2
, .shift
= 8, .size
= 4 },
413 static struct clksrc_clk clksrcs
[] = {
417 .devname
= "s3c-sdhci.0",
418 .ctrlbit
= (1 << 24),
419 .enable
= s5p64x0_sclk_ctrl
,
421 .sources
= &clkset_group2
,
422 .reg_src
= { .reg
= S5P64X0_CLK_SRC0
, .shift
= 18, .size
= 2 },
423 .reg_div
= { .reg
= S5P64X0_CLK_DIV1
, .shift
= 0, .size
= 4 },
427 .devname
= "s3c-sdhci.1",
428 .ctrlbit
= (1 << 25),
429 .enable
= s5p64x0_sclk_ctrl
,
431 .sources
= &clkset_group2
,
432 .reg_src
= { .reg
= S5P64X0_CLK_SRC0
, .shift
= 20, .size
= 2 },
433 .reg_div
= { .reg
= S5P64X0_CLK_DIV1
, .shift
= 4, .size
= 4 },
437 .devname
= "s3c-sdhci.2",
438 .ctrlbit
= (1 << 26),
439 .enable
= s5p64x0_sclk_ctrl
,
441 .sources
= &clkset_group2
,
442 .reg_src
= { .reg
= S5P64X0_CLK_SRC0
, .shift
= 22, .size
= 2 },
443 .reg_div
= { .reg
= S5P64X0_CLK_DIV1
, .shift
= 8, .size
= 4 },
448 .enable
= s5p64x0_sclk_ctrl
,
450 .sources
= &clkset_uart
,
451 .reg_src
= { .reg
= S5P64X0_CLK_SRC0
, .shift
= 13, .size
= 1 },
452 .reg_div
= { .reg
= S5P64X0_CLK_DIV2
, .shift
= 16, .size
= 4 },
456 .devname
= "s3c64xx-spi.0",
457 .ctrlbit
= (1 << 20),
458 .enable
= s5p64x0_sclk_ctrl
,
460 .sources
= &clkset_group2
,
461 .reg_src
= { .reg
= S5P64X0_CLK_SRC0
, .shift
= 14, .size
= 2 },
462 .reg_div
= { .reg
= S5P64X0_CLK_DIV2
, .shift
= 0, .size
= 4 },
466 .devname
= "s3c64xx-spi.1",
467 .ctrlbit
= (1 << 21),
468 .enable
= s5p64x0_sclk_ctrl
,
470 .sources
= &clkset_group2
,
471 .reg_src
= { .reg
= S5P64X0_CLK_SRC0
, .shift
= 16, .size
= 2 },
472 .reg_div
= { .reg
= S5P64X0_CLK_DIV2
, .shift
= 4, .size
= 4 },
476 .ctrlbit
= (1 << 10),
477 .enable
= s5p64x0_sclk_ctrl
,
479 .sources
= &clkset_group2
,
480 .reg_src
= { .reg
= S5P64X0_CLK_SRC0
, .shift
= 26, .size
= 2 },
481 .reg_div
= { .reg
= S5P64X0_CLK_DIV1
, .shift
= 12, .size
= 4 },
486 .enable
= s5p64x0_sclk1_ctrl
,
488 .sources
= &clkset_mali
,
489 .reg_src
= { .reg
= S5P64X0_CLK_SRC1
, .shift
= 8, .size
= 2 },
490 .reg_div
= { .reg
= S5P64X0_CLK_DIV3
, .shift
= 4, .size
= 4 },
494 .ctrlbit
= (1 << 12),
495 .enable
= s5p64x0_sclk_ctrl
,
497 .sources
= &clkset_mali
,
498 .reg_src
= { .reg
= S5P64X0_CLK_SRC0
, .shift
= 30, .size
= 2 },
499 .reg_div
= { .reg
= S5P64X0_CLK_DIV2
, .shift
= 20, .size
= 4 },
504 .enable
= s5p64x0_sclk_ctrl
,
506 .sources
= &clkset_group2
,
507 .reg_src
= { .reg
= S5P64X0_CLK_SRC0
, .shift
= 10, .size
= 2 },
508 .reg_div
= { .reg
= S5P64X0_CLK_DIV1
, .shift
= 16, .size
= 4 },
511 .name
= "sclk_camif",
513 .enable
= s5p64x0_sclk_ctrl
,
515 .sources
= &clkset_group2
,
516 .reg_src
= { .reg
= S5P64X0_CLK_SRC0
, .shift
= 28, .size
= 2 },
517 .reg_div
= { .reg
= S5P64X0_CLK_DIV1
, .shift
= 20, .size
= 4 },
520 .name
= "sclk_dispcon",
522 .enable
= s5p64x0_sclk1_ctrl
,
524 .sources
= &clkset_dispcon
,
525 .reg_src
= { .reg
= S5P64X0_CLK_SRC1
, .shift
= 4, .size
= 2 },
526 .reg_div
= { .reg
= S5P64X0_CLK_DIV3
, .shift
= 0, .size
= 4 },
529 .name
= "sclk_hsmmc44",
530 .ctrlbit
= (1 << 30),
531 .enable
= s5p64x0_sclk_ctrl
,
533 .sources
= &clkset_hsmmc44
,
534 .reg_src
= { .reg
= S5P64X0_CLK_SRC0
, .shift
= 6, .size
= 3 },
535 .reg_div
= { .reg
= S5P64X0_CLK_DIV1
, .shift
= 28, .size
= 4 },
539 /* Clock initialization code */
540 static struct clksrc_clk
*sysclks
[] = {
548 &clk_dout_pwm_ratio0
,
549 &clk_pclk_to_wdt_pwm
,
557 static struct clk dummy_apb_pclk
= {
562 void __init_or_cpufreq
s5p6450_setup_clocks(void)
564 struct clk
*xtal_clk
;
569 unsigned long hclk_low
;
571 unsigned long pclk_low
;
579 /* Set S5P6450 functions for clk_fout_epll */
581 clk_fout_epll
.enable
= s5p_epll_enable
;
582 clk_fout_epll
.ops
= &s5p6450_epll_ops
;
584 clk_48m
.enable
= s5p64x0_clk48m_ctrl
;
586 xtal_clk
= clk_get(NULL
, "ext_xtal");
587 BUG_ON(IS_ERR(xtal_clk
));
589 xtal
= clk_get_rate(xtal_clk
);
592 apll
= s5p_get_pll45xx(xtal
, __raw_readl(S5P64X0_APLL_CON
), pll_4502
);
593 mpll
= s5p_get_pll45xx(xtal
, __raw_readl(S5P64X0_MPLL_CON
), pll_4502
);
594 epll
= s5p_get_pll90xx(xtal
, __raw_readl(S5P64X0_EPLL_CON
),
595 __raw_readl(S5P64X0_EPLL_CON_K
));
596 dpll
= s5p_get_pll46xx(xtal
, __raw_readl(S5P6450_DPLL_CON
),
597 __raw_readl(S5P6450_DPLL_CON_K
), pll_4650c
);
599 clk_fout_apll
.rate
= apll
;
600 clk_fout_mpll
.rate
= mpll
;
601 clk_fout_epll
.rate
= epll
;
602 clk_fout_dpll
.rate
= dpll
;
604 printk(KERN_INFO
"S5P6450: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
605 " E=%ld.%ldMHz, D=%ld.%ldMHz\n",
606 print_mhz(apll
), print_mhz(mpll
), print_mhz(epll
),
609 fclk
= clk_get_rate(&clk_armclk
.clk
);
610 hclk
= clk_get_rate(&clk_hclk
.clk
);
611 pclk
= clk_get_rate(&clk_pclk
.clk
);
612 hclk_low
= clk_get_rate(&clk_hclk_low
.clk
);
613 pclk_low
= clk_get_rate(&clk_pclk_low
.clk
);
615 printk(KERN_INFO
"S5P6450: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
616 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
617 print_mhz(hclk
), print_mhz(hclk_low
),
618 print_mhz(pclk
), print_mhz(pclk_low
));
624 for (ptr
= 0; ptr
< ARRAY_SIZE(clksrcs
); ptr
++)
625 s3c_set_clksrc(&clksrcs
[ptr
], true);
628 void __init
s5p6450_register_clocks(void)
632 for (ptr
= 0; ptr
< ARRAY_SIZE(sysclks
); ptr
++)
633 s3c_register_clksrc(sysclks
[ptr
], 1);
635 s3c_register_clksrc(clksrcs
, ARRAY_SIZE(clksrcs
));
636 s3c_register_clocks(init_clocks
, ARRAY_SIZE(init_clocks
));
638 s3c_register_clocks(init_clocks_off
, ARRAY_SIZE(init_clocks_off
));
639 s3c_disable_clocks(init_clocks_off
, ARRAY_SIZE(init_clocks_off
));
641 s3c24xx_register_clock(&dummy_apb_pclk
);