2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "2.0"
56 AHCI_MAX_SG
= 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY
= 0xffffffff,
58 AHCI_USE_CLUSTERING
= 0,
61 AHCI_CMD_SLOT_SZ
= AHCI_MAX_CMDS
* AHCI_CMD_SZ
,
63 AHCI_CMD_TBL_CDB
= 0x40,
64 AHCI_CMD_TBL_HDR_SZ
= 0x80,
65 AHCI_CMD_TBL_SZ
= AHCI_CMD_TBL_HDR_SZ
+ (AHCI_MAX_SG
* 16),
66 AHCI_CMD_TBL_AR_SZ
= AHCI_CMD_TBL_SZ
* AHCI_MAX_CMDS
,
67 AHCI_PORT_PRIV_DMA_SZ
= AHCI_CMD_SLOT_SZ
+ AHCI_CMD_TBL_AR_SZ
+
69 AHCI_IRQ_ON_SG
= (1 << 31),
70 AHCI_CMD_ATAPI
= (1 << 5),
71 AHCI_CMD_WRITE
= (1 << 6),
72 AHCI_CMD_PREFETCH
= (1 << 7),
73 AHCI_CMD_RESET
= (1 << 8),
74 AHCI_CMD_CLR_BUSY
= (1 << 10),
76 RX_FIS_D2H_REG
= 0x40, /* offset of D2H Register FIS data */
77 RX_FIS_UNK
= 0x60, /* offset of Unknown FIS data */
80 board_ahci_vt8251
= 1,
82 /* global controller registers */
83 HOST_CAP
= 0x00, /* host capabilities */
84 HOST_CTL
= 0x04, /* global host control */
85 HOST_IRQ_STAT
= 0x08, /* interrupt status */
86 HOST_PORTS_IMPL
= 0x0c, /* bitmap of implemented ports */
87 HOST_VERSION
= 0x10, /* AHCI spec. version compliancy */
90 HOST_RESET
= (1 << 0), /* reset controller; self-clear */
91 HOST_IRQ_EN
= (1 << 1), /* global IRQ enable */
92 HOST_AHCI_EN
= (1 << 31), /* AHCI enabled */
95 HOST_CAP_SSC
= (1 << 14), /* Slumber capable */
96 HOST_CAP_CLO
= (1 << 24), /* Command List Override support */
97 HOST_CAP_SSS
= (1 << 27), /* Staggered Spin-up */
98 HOST_CAP_NCQ
= (1 << 30), /* Native Command Queueing */
99 HOST_CAP_64
= (1 << 31), /* PCI DAC (64-bit DMA) support */
101 /* registers for each SATA port */
102 PORT_LST_ADDR
= 0x00, /* command list DMA addr */
103 PORT_LST_ADDR_HI
= 0x04, /* command list DMA addr hi */
104 PORT_FIS_ADDR
= 0x08, /* FIS rx buf addr */
105 PORT_FIS_ADDR_HI
= 0x0c, /* FIS rx buf addr hi */
106 PORT_IRQ_STAT
= 0x10, /* interrupt status */
107 PORT_IRQ_MASK
= 0x14, /* interrupt enable/disable mask */
108 PORT_CMD
= 0x18, /* port command */
109 PORT_TFDATA
= 0x20, /* taskfile data */
110 PORT_SIG
= 0x24, /* device TF signature */
111 PORT_CMD_ISSUE
= 0x38, /* command issue */
112 PORT_SCR
= 0x28, /* SATA phy register block */
113 PORT_SCR_STAT
= 0x28, /* SATA phy register: SStatus */
114 PORT_SCR_CTL
= 0x2c, /* SATA phy register: SControl */
115 PORT_SCR_ERR
= 0x30, /* SATA phy register: SError */
116 PORT_SCR_ACT
= 0x34, /* SATA phy register: SActive */
118 /* PORT_IRQ_{STAT,MASK} bits */
119 PORT_IRQ_COLD_PRES
= (1 << 31), /* cold presence detect */
120 PORT_IRQ_TF_ERR
= (1 << 30), /* task file error */
121 PORT_IRQ_HBUS_ERR
= (1 << 29), /* host bus fatal error */
122 PORT_IRQ_HBUS_DATA_ERR
= (1 << 28), /* host bus data error */
123 PORT_IRQ_IF_ERR
= (1 << 27), /* interface fatal error */
124 PORT_IRQ_IF_NONFATAL
= (1 << 26), /* interface non-fatal error */
125 PORT_IRQ_OVERFLOW
= (1 << 24), /* xfer exhausted available S/G */
126 PORT_IRQ_BAD_PMP
= (1 << 23), /* incorrect port multiplier */
128 PORT_IRQ_PHYRDY
= (1 << 22), /* PhyRdy changed */
129 PORT_IRQ_DEV_ILCK
= (1 << 7), /* device interlock */
130 PORT_IRQ_CONNECT
= (1 << 6), /* port connect change status */
131 PORT_IRQ_SG_DONE
= (1 << 5), /* descriptor processed */
132 PORT_IRQ_UNK_FIS
= (1 << 4), /* unknown FIS rx'd */
133 PORT_IRQ_SDB_FIS
= (1 << 3), /* Set Device Bits FIS rx'd */
134 PORT_IRQ_DMAS_FIS
= (1 << 2), /* DMA Setup FIS rx'd */
135 PORT_IRQ_PIOS_FIS
= (1 << 1), /* PIO Setup FIS rx'd */
136 PORT_IRQ_D2H_REG_FIS
= (1 << 0), /* D2H Register FIS rx'd */
138 PORT_IRQ_FREEZE
= PORT_IRQ_HBUS_ERR
|
143 PORT_IRQ_ERROR
= PORT_IRQ_FREEZE
|
145 PORT_IRQ_HBUS_DATA_ERR
,
146 DEF_PORT_IRQ
= PORT_IRQ_ERROR
| PORT_IRQ_SG_DONE
|
147 PORT_IRQ_SDB_FIS
| PORT_IRQ_DMAS_FIS
|
148 PORT_IRQ_PIOS_FIS
| PORT_IRQ_D2H_REG_FIS
,
151 PORT_CMD_ATAPI
= (1 << 24), /* Device is ATAPI */
152 PORT_CMD_LIST_ON
= (1 << 15), /* cmd list DMA engine running */
153 PORT_CMD_FIS_ON
= (1 << 14), /* FIS DMA engine running */
154 PORT_CMD_FIS_RX
= (1 << 4), /* Enable FIS receive DMA engine */
155 PORT_CMD_CLO
= (1 << 3), /* Command list override */
156 PORT_CMD_POWER_ON
= (1 << 2), /* Power up device */
157 PORT_CMD_SPIN_UP
= (1 << 1), /* Spin up device */
158 PORT_CMD_START
= (1 << 0), /* Enable port DMA engine */
160 PORT_CMD_ICC_MASK
= (0xf << 28), /* i/f ICC state mask */
161 PORT_CMD_ICC_ACTIVE
= (0x1 << 28), /* Put i/f in active state */
162 PORT_CMD_ICC_PARTIAL
= (0x2 << 28), /* Put i/f in partial state */
163 PORT_CMD_ICC_SLUMBER
= (0x6 << 28), /* Put i/f in slumber state */
165 /* hpriv->flags bits */
166 AHCI_FLAG_MSI
= (1 << 0),
169 AHCI_FLAG_RESET_NEEDS_CLO
= (1 << 24),
170 AHCI_FLAG_NO_NCQ
= (1 << 25),
173 struct ahci_cmd_hdr
{
188 struct ahci_host_priv
{
190 u32 cap
; /* cache of HOST_CAP register */
191 u32 port_map
; /* cache of HOST_PORTS_IMPL reg */
194 struct ahci_port_priv
{
195 struct ahci_cmd_hdr
*cmd_slot
;
196 dma_addr_t cmd_slot_dma
;
198 dma_addr_t cmd_tbl_dma
;
200 dma_addr_t rx_fis_dma
;
203 static u32
ahci_scr_read (struct ata_port
*ap
, unsigned int sc_reg
);
204 static void ahci_scr_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
);
205 static int ahci_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
206 static unsigned int ahci_qc_issue(struct ata_queued_cmd
*qc
);
207 static irqreturn_t
ahci_interrupt (int irq
, void *dev_instance
);
208 static void ahci_irq_clear(struct ata_port
*ap
);
209 static int ahci_port_start(struct ata_port
*ap
);
210 static void ahci_port_stop(struct ata_port
*ap
);
211 static void ahci_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
);
212 static void ahci_qc_prep(struct ata_queued_cmd
*qc
);
213 static u8
ahci_check_status(struct ata_port
*ap
);
214 static void ahci_freeze(struct ata_port
*ap
);
215 static void ahci_thaw(struct ata_port
*ap
);
216 static void ahci_error_handler(struct ata_port
*ap
);
217 static void ahci_post_internal_cmd(struct ata_queued_cmd
*qc
);
218 static int ahci_port_suspend(struct ata_port
*ap
, pm_message_t mesg
);
219 static int ahci_port_resume(struct ata_port
*ap
);
220 static int ahci_pci_device_suspend(struct pci_dev
*pdev
, pm_message_t mesg
);
221 static int ahci_pci_device_resume(struct pci_dev
*pdev
);
222 static void ahci_remove_one (struct pci_dev
*pdev
);
224 static struct scsi_host_template ahci_sht
= {
225 .module
= THIS_MODULE
,
227 .ioctl
= ata_scsi_ioctl
,
228 .queuecommand
= ata_scsi_queuecmd
,
229 .change_queue_depth
= ata_scsi_change_queue_depth
,
230 .can_queue
= AHCI_MAX_CMDS
- 1,
231 .this_id
= ATA_SHT_THIS_ID
,
232 .sg_tablesize
= AHCI_MAX_SG
,
233 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
234 .emulated
= ATA_SHT_EMULATED
,
235 .use_clustering
= AHCI_USE_CLUSTERING
,
236 .proc_name
= DRV_NAME
,
237 .dma_boundary
= AHCI_DMA_BOUNDARY
,
238 .slave_configure
= ata_scsi_slave_config
,
239 .slave_destroy
= ata_scsi_slave_destroy
,
240 .bios_param
= ata_std_bios_param
,
241 .suspend
= ata_scsi_device_suspend
,
242 .resume
= ata_scsi_device_resume
,
245 static const struct ata_port_operations ahci_ops
= {
246 .port_disable
= ata_port_disable
,
248 .check_status
= ahci_check_status
,
249 .check_altstatus
= ahci_check_status
,
250 .dev_select
= ata_noop_dev_select
,
252 .tf_read
= ahci_tf_read
,
254 .qc_prep
= ahci_qc_prep
,
255 .qc_issue
= ahci_qc_issue
,
257 .irq_handler
= ahci_interrupt
,
258 .irq_clear
= ahci_irq_clear
,
260 .scr_read
= ahci_scr_read
,
261 .scr_write
= ahci_scr_write
,
263 .freeze
= ahci_freeze
,
266 .error_handler
= ahci_error_handler
,
267 .post_internal_cmd
= ahci_post_internal_cmd
,
269 .port_suspend
= ahci_port_suspend
,
270 .port_resume
= ahci_port_resume
,
272 .port_start
= ahci_port_start
,
273 .port_stop
= ahci_port_stop
,
276 static const struct ata_port_info ahci_port_info
[] = {
280 .flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
281 ATA_FLAG_MMIO
| ATA_FLAG_PIO_DMA
|
282 ATA_FLAG_SKIP_D2H_BSY
,
283 .pio_mask
= 0x1f, /* pio0-4 */
284 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
285 .port_ops
= &ahci_ops
,
287 /* board_ahci_vt8251 */
290 .flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
291 ATA_FLAG_MMIO
| ATA_FLAG_PIO_DMA
|
292 ATA_FLAG_SKIP_D2H_BSY
|
293 AHCI_FLAG_RESET_NEEDS_CLO
| AHCI_FLAG_NO_NCQ
,
294 .pio_mask
= 0x1f, /* pio0-4 */
295 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
296 .port_ops
= &ahci_ops
,
300 static const struct pci_device_id ahci_pci_tbl
[] = {
302 { PCI_VDEVICE(INTEL
, 0x2652), board_ahci
}, /* ICH6 */
303 { PCI_VDEVICE(INTEL
, 0x2653), board_ahci
}, /* ICH6M */
304 { PCI_VDEVICE(INTEL
, 0x27c1), board_ahci
}, /* ICH7 */
305 { PCI_VDEVICE(INTEL
, 0x27c5), board_ahci
}, /* ICH7M */
306 { PCI_VDEVICE(INTEL
, 0x27c3), board_ahci
}, /* ICH7R */
307 { PCI_VDEVICE(AL
, 0x5288), board_ahci
}, /* ULi M5288 */
308 { PCI_VDEVICE(INTEL
, 0x2681), board_ahci
}, /* ESB2 */
309 { PCI_VDEVICE(INTEL
, 0x2682), board_ahci
}, /* ESB2 */
310 { PCI_VDEVICE(INTEL
, 0x2683), board_ahci
}, /* ESB2 */
311 { PCI_VDEVICE(INTEL
, 0x27c6), board_ahci
}, /* ICH7-M DH */
312 { PCI_VDEVICE(INTEL
, 0x2821), board_ahci
}, /* ICH8 */
313 { PCI_VDEVICE(INTEL
, 0x2822), board_ahci
}, /* ICH8 */
314 { PCI_VDEVICE(INTEL
, 0x2824), board_ahci
}, /* ICH8 */
315 { PCI_VDEVICE(INTEL
, 0x2829), board_ahci
}, /* ICH8M */
316 { PCI_VDEVICE(INTEL
, 0x282a), board_ahci
}, /* ICH8M */
319 { PCI_VDEVICE(JMICRON
, 0x2360), board_ahci
}, /* JMicron JMB360 */
320 { PCI_VDEVICE(JMICRON
, 0x2361), board_ahci
}, /* JMicron JMB361 */
321 { PCI_VDEVICE(JMICRON
, 0x2363), board_ahci
}, /* JMicron JMB363 */
322 { PCI_VDEVICE(JMICRON
, 0x2365), board_ahci
}, /* JMicron JMB365 */
323 { PCI_VDEVICE(JMICRON
, 0x2366), board_ahci
}, /* JMicron JMB366 */
326 { PCI_VDEVICE(ATI
, 0x4380), board_ahci
}, /* ATI SB600 non-raid */
327 { PCI_VDEVICE(ATI
, 0x4381), board_ahci
}, /* ATI SB600 raid */
330 { PCI_VDEVICE(VIA
, 0x3349), board_ahci_vt8251
}, /* VIA VT8251 */
333 { PCI_VDEVICE(NVIDIA
, 0x044c), board_ahci
}, /* MCP65 */
334 { PCI_VDEVICE(NVIDIA
, 0x044d), board_ahci
}, /* MCP65 */
335 { PCI_VDEVICE(NVIDIA
, 0x044e), board_ahci
}, /* MCP65 */
336 { PCI_VDEVICE(NVIDIA
, 0x044f), board_ahci
}, /* MCP65 */
339 { PCI_VDEVICE(SI
, 0x1184), board_ahci
}, /* SiS 966 */
340 { PCI_VDEVICE(SI
, 0x1185), board_ahci
}, /* SiS 966 */
341 { PCI_VDEVICE(SI
, 0x0186), board_ahci
}, /* SiS 968 */
343 { } /* terminate list */
347 static struct pci_driver ahci_pci_driver
= {
349 .id_table
= ahci_pci_tbl
,
350 .probe
= ahci_init_one
,
351 .suspend
= ahci_pci_device_suspend
,
352 .resume
= ahci_pci_device_resume
,
353 .remove
= ahci_remove_one
,
357 static inline unsigned long ahci_port_base_ul (unsigned long base
, unsigned int port
)
359 return base
+ 0x100 + (port
* 0x80);
362 static inline void __iomem
*ahci_port_base (void __iomem
*base
, unsigned int port
)
364 return (void __iomem
*) ahci_port_base_ul((unsigned long)base
, port
);
367 static u32
ahci_scr_read (struct ata_port
*ap
, unsigned int sc_reg_in
)
372 case SCR_STATUS
: sc_reg
= 0; break;
373 case SCR_CONTROL
: sc_reg
= 1; break;
374 case SCR_ERROR
: sc_reg
= 2; break;
375 case SCR_ACTIVE
: sc_reg
= 3; break;
380 return readl((void __iomem
*) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
384 static void ahci_scr_write (struct ata_port
*ap
, unsigned int sc_reg_in
,
390 case SCR_STATUS
: sc_reg
= 0; break;
391 case SCR_CONTROL
: sc_reg
= 1; break;
392 case SCR_ERROR
: sc_reg
= 2; break;
393 case SCR_ACTIVE
: sc_reg
= 3; break;
398 writel(val
, (void __iomem
*) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
401 static void ahci_start_engine(void __iomem
*port_mmio
)
406 tmp
= readl(port_mmio
+ PORT_CMD
);
407 tmp
|= PORT_CMD_START
;
408 writel(tmp
, port_mmio
+ PORT_CMD
);
409 readl(port_mmio
+ PORT_CMD
); /* flush */
412 static int ahci_stop_engine(void __iomem
*port_mmio
)
416 tmp
= readl(port_mmio
+ PORT_CMD
);
418 /* check if the HBA is idle */
419 if ((tmp
& (PORT_CMD_START
| PORT_CMD_LIST_ON
)) == 0)
422 /* setting HBA to idle */
423 tmp
&= ~PORT_CMD_START
;
424 writel(tmp
, port_mmio
+ PORT_CMD
);
426 /* wait for engine to stop. This could be as long as 500 msec */
427 tmp
= ata_wait_register(port_mmio
+ PORT_CMD
,
428 PORT_CMD_LIST_ON
, PORT_CMD_LIST_ON
, 1, 500);
429 if (tmp
& PORT_CMD_LIST_ON
)
435 static void ahci_start_fis_rx(void __iomem
*port_mmio
, u32 cap
,
436 dma_addr_t cmd_slot_dma
, dma_addr_t rx_fis_dma
)
440 /* set FIS registers */
441 if (cap
& HOST_CAP_64
)
442 writel((cmd_slot_dma
>> 16) >> 16, port_mmio
+ PORT_LST_ADDR_HI
);
443 writel(cmd_slot_dma
& 0xffffffff, port_mmio
+ PORT_LST_ADDR
);
445 if (cap
& HOST_CAP_64
)
446 writel((rx_fis_dma
>> 16) >> 16, port_mmio
+ PORT_FIS_ADDR_HI
);
447 writel(rx_fis_dma
& 0xffffffff, port_mmio
+ PORT_FIS_ADDR
);
449 /* enable FIS reception */
450 tmp
= readl(port_mmio
+ PORT_CMD
);
451 tmp
|= PORT_CMD_FIS_RX
;
452 writel(tmp
, port_mmio
+ PORT_CMD
);
455 readl(port_mmio
+ PORT_CMD
);
458 static int ahci_stop_fis_rx(void __iomem
*port_mmio
)
462 /* disable FIS reception */
463 tmp
= readl(port_mmio
+ PORT_CMD
);
464 tmp
&= ~PORT_CMD_FIS_RX
;
465 writel(tmp
, port_mmio
+ PORT_CMD
);
467 /* wait for completion, spec says 500ms, give it 1000 */
468 tmp
= ata_wait_register(port_mmio
+ PORT_CMD
, PORT_CMD_FIS_ON
,
469 PORT_CMD_FIS_ON
, 10, 1000);
470 if (tmp
& PORT_CMD_FIS_ON
)
476 static void ahci_power_up(void __iomem
*port_mmio
, u32 cap
)
480 cmd
= readl(port_mmio
+ PORT_CMD
) & ~PORT_CMD_ICC_MASK
;
483 if (cap
& HOST_CAP_SSS
) {
484 cmd
|= PORT_CMD_SPIN_UP
;
485 writel(cmd
, port_mmio
+ PORT_CMD
);
489 writel(cmd
| PORT_CMD_ICC_ACTIVE
, port_mmio
+ PORT_CMD
);
492 static void ahci_power_down(void __iomem
*port_mmio
, u32 cap
)
496 cmd
= readl(port_mmio
+ PORT_CMD
) & ~PORT_CMD_ICC_MASK
;
498 if (cap
& HOST_CAP_SSC
) {
499 /* enable transitions to slumber mode */
500 scontrol
= readl(port_mmio
+ PORT_SCR_CTL
);
501 if ((scontrol
& 0x0f00) > 0x100) {
503 writel(scontrol
, port_mmio
+ PORT_SCR_CTL
);
506 /* put device into slumber mode */
507 writel(cmd
| PORT_CMD_ICC_SLUMBER
, port_mmio
+ PORT_CMD
);
509 /* wait for the transition to complete */
510 ata_wait_register(port_mmio
+ PORT_CMD
, PORT_CMD_ICC_SLUMBER
,
511 PORT_CMD_ICC_SLUMBER
, 1, 50);
514 /* put device into listen mode */
515 if (cap
& HOST_CAP_SSS
) {
516 /* first set PxSCTL.DET to 0 */
517 scontrol
= readl(port_mmio
+ PORT_SCR_CTL
);
519 writel(scontrol
, port_mmio
+ PORT_SCR_CTL
);
521 /* then set PxCMD.SUD to 0 */
522 cmd
&= ~PORT_CMD_SPIN_UP
;
523 writel(cmd
, port_mmio
+ PORT_CMD
);
527 static void ahci_init_port(void __iomem
*port_mmio
, u32 cap
,
528 dma_addr_t cmd_slot_dma
, dma_addr_t rx_fis_dma
)
531 ahci_power_up(port_mmio
, cap
);
533 /* enable FIS reception */
534 ahci_start_fis_rx(port_mmio
, cap
, cmd_slot_dma
, rx_fis_dma
);
537 ahci_start_engine(port_mmio
);
540 static int ahci_deinit_port(void __iomem
*port_mmio
, u32 cap
, const char **emsg
)
545 rc
= ahci_stop_engine(port_mmio
);
547 *emsg
= "failed to stop engine";
551 /* disable FIS reception */
552 rc
= ahci_stop_fis_rx(port_mmio
);
554 *emsg
= "failed stop FIS RX";
558 /* put device into slumber mode */
559 ahci_power_down(port_mmio
, cap
);
564 static int ahci_reset_controller(void __iomem
*mmio
, struct pci_dev
*pdev
)
568 cap_save
= readl(mmio
+ HOST_CAP
);
569 cap_save
&= ( (1<<28) | (1<<17) );
570 cap_save
|= (1 << 27);
572 /* global controller reset */
573 tmp
= readl(mmio
+ HOST_CTL
);
574 if ((tmp
& HOST_RESET
) == 0) {
575 writel(tmp
| HOST_RESET
, mmio
+ HOST_CTL
);
576 readl(mmio
+ HOST_CTL
); /* flush */
579 /* reset must complete within 1 second, or
580 * the hardware should be considered fried.
584 tmp
= readl(mmio
+ HOST_CTL
);
585 if (tmp
& HOST_RESET
) {
586 dev_printk(KERN_ERR
, &pdev
->dev
,
587 "controller reset failed (0x%x)\n", tmp
);
591 writel(HOST_AHCI_EN
, mmio
+ HOST_CTL
);
592 (void) readl(mmio
+ HOST_CTL
); /* flush */
593 writel(cap_save
, mmio
+ HOST_CAP
);
594 writel(0xf, mmio
+ HOST_PORTS_IMPL
);
595 (void) readl(mmio
+ HOST_PORTS_IMPL
); /* flush */
597 if (pdev
->vendor
== PCI_VENDOR_ID_INTEL
) {
601 pci_read_config_word(pdev
, 0x92, &tmp16
);
603 pci_write_config_word(pdev
, 0x92, tmp16
);
609 static void ahci_init_controller(void __iomem
*mmio
, struct pci_dev
*pdev
,
610 int n_ports
, u32 cap
)
615 for (i
= 0; i
< n_ports
; i
++) {
616 void __iomem
*port_mmio
= ahci_port_base(mmio
, i
);
617 const char *emsg
= NULL
;
619 #if 0 /* BIOSen initialize this incorrectly */
620 if (!(hpriv
->port_map
& (1 << i
)))
624 /* make sure port is not active */
625 rc
= ahci_deinit_port(port_mmio
, cap
, &emsg
);
627 dev_printk(KERN_WARNING
, &pdev
->dev
,
628 "%s (%d)\n", emsg
, rc
);
631 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
632 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp
);
633 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
636 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
637 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp
);
639 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
641 writel(1 << i
, mmio
+ HOST_IRQ_STAT
);
644 tmp
= readl(mmio
+ HOST_CTL
);
645 VPRINTK("HOST_CTL 0x%x\n", tmp
);
646 writel(tmp
| HOST_IRQ_EN
, mmio
+ HOST_CTL
);
647 tmp
= readl(mmio
+ HOST_CTL
);
648 VPRINTK("HOST_CTL 0x%x\n", tmp
);
651 static unsigned int ahci_dev_classify(struct ata_port
*ap
)
653 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
654 struct ata_taskfile tf
;
657 tmp
= readl(port_mmio
+ PORT_SIG
);
658 tf
.lbah
= (tmp
>> 24) & 0xff;
659 tf
.lbam
= (tmp
>> 16) & 0xff;
660 tf
.lbal
= (tmp
>> 8) & 0xff;
661 tf
.nsect
= (tmp
) & 0xff;
663 return ata_dev_classify(&tf
);
666 static void ahci_fill_cmd_slot(struct ahci_port_priv
*pp
, unsigned int tag
,
669 dma_addr_t cmd_tbl_dma
;
671 cmd_tbl_dma
= pp
->cmd_tbl_dma
+ tag
* AHCI_CMD_TBL_SZ
;
673 pp
->cmd_slot
[tag
].opts
= cpu_to_le32(opts
);
674 pp
->cmd_slot
[tag
].status
= 0;
675 pp
->cmd_slot
[tag
].tbl_addr
= cpu_to_le32(cmd_tbl_dma
& 0xffffffff);
676 pp
->cmd_slot
[tag
].tbl_addr_hi
= cpu_to_le32((cmd_tbl_dma
>> 16) >> 16);
679 static int ahci_clo(struct ata_port
*ap
)
681 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
682 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
685 if (!(hpriv
->cap
& HOST_CAP_CLO
))
688 tmp
= readl(port_mmio
+ PORT_CMD
);
690 writel(tmp
, port_mmio
+ PORT_CMD
);
692 tmp
= ata_wait_register(port_mmio
+ PORT_CMD
,
693 PORT_CMD_CLO
, PORT_CMD_CLO
, 1, 500);
694 if (tmp
& PORT_CMD_CLO
)
700 static int ahci_prereset(struct ata_port
*ap
)
702 if ((ap
->flags
& AHCI_FLAG_RESET_NEEDS_CLO
) &&
703 (ata_busy_wait(ap
, ATA_BUSY
, 1000) & ATA_BUSY
)) {
704 /* ATA_BUSY hasn't cleared, so send a CLO */
708 return ata_std_prereset(ap
);
711 static int ahci_softreset(struct ata_port
*ap
, unsigned int *class)
713 struct ahci_port_priv
*pp
= ap
->private_data
;
714 void __iomem
*mmio
= ap
->host
->mmio_base
;
715 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
716 const u32 cmd_fis_len
= 5; /* five dwords */
717 const char *reason
= NULL
;
718 struct ata_taskfile tf
;
725 if (ata_port_offline(ap
)) {
726 DPRINTK("PHY reports no device\n");
727 *class = ATA_DEV_NONE
;
731 /* prepare for SRST (AHCI-1.1 10.4.1) */
732 rc
= ahci_stop_engine(port_mmio
);
734 reason
= "failed to stop engine";
738 /* check BUSY/DRQ, perform Command List Override if necessary */
739 ahci_tf_read(ap
, &tf
);
740 if (tf
.command
& (ATA_BUSY
| ATA_DRQ
)) {
743 if (rc
== -EOPNOTSUPP
) {
744 reason
= "port busy but CLO unavailable";
747 reason
= "port busy but CLO failed";
753 ahci_start_engine(port_mmio
);
755 ata_tf_init(ap
->device
, &tf
);
758 /* issue the first D2H Register FIS */
759 ahci_fill_cmd_slot(pp
, 0,
760 cmd_fis_len
| AHCI_CMD_RESET
| AHCI_CMD_CLR_BUSY
);
763 ata_tf_to_fis(&tf
, fis
, 0);
764 fis
[1] &= ~(1 << 7); /* turn off Command FIS bit */
766 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
768 tmp
= ata_wait_register(port_mmio
+ PORT_CMD_ISSUE
, 0x1, 0x1, 1, 500);
771 reason
= "1st FIS failed";
775 /* spec says at least 5us, but be generous and sleep for 1ms */
778 /* issue the second D2H Register FIS */
779 ahci_fill_cmd_slot(pp
, 0, cmd_fis_len
);
782 ata_tf_to_fis(&tf
, fis
, 0);
783 fis
[1] &= ~(1 << 7); /* turn off Command FIS bit */
785 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
786 readl(port_mmio
+ PORT_CMD_ISSUE
); /* flush */
788 /* spec mandates ">= 2ms" before checking status.
789 * We wait 150ms, because that was the magic delay used for
790 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
791 * between when the ATA command register is written, and then
792 * status is checked. Because waiting for "a while" before
793 * checking status is fine, post SRST, we perform this magic
794 * delay here as well.
798 *class = ATA_DEV_NONE
;
799 if (ata_port_online(ap
)) {
800 if (ata_busy_sleep(ap
, ATA_TMOUT_BOOT_QUICK
, ATA_TMOUT_BOOT
)) {
802 reason
= "device not ready";
805 *class = ahci_dev_classify(ap
);
808 DPRINTK("EXIT, class=%u\n", *class);
812 ahci_start_engine(port_mmio
);
814 ata_port_printk(ap
, KERN_ERR
, "softreset failed (%s)\n", reason
);
818 static int ahci_hardreset(struct ata_port
*ap
, unsigned int *class)
820 struct ahci_port_priv
*pp
= ap
->private_data
;
821 u8
*d2h_fis
= pp
->rx_fis
+ RX_FIS_D2H_REG
;
822 struct ata_taskfile tf
;
823 void __iomem
*mmio
= ap
->host
->mmio_base
;
824 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
829 ahci_stop_engine(port_mmio
);
831 /* clear D2H reception area to properly wait for D2H FIS */
832 ata_tf_init(ap
->device
, &tf
);
834 ata_tf_to_fis(&tf
, d2h_fis
, 0);
836 rc
= sata_std_hardreset(ap
, class);
838 ahci_start_engine(port_mmio
);
840 if (rc
== 0 && ata_port_online(ap
))
841 *class = ahci_dev_classify(ap
);
842 if (*class == ATA_DEV_UNKNOWN
)
843 *class = ATA_DEV_NONE
;
845 DPRINTK("EXIT, rc=%d, class=%u\n", rc
, *class);
849 static void ahci_postreset(struct ata_port
*ap
, unsigned int *class)
851 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
854 ata_std_postreset(ap
, class);
856 /* Make sure port's ATAPI bit is set appropriately */
857 new_tmp
= tmp
= readl(port_mmio
+ PORT_CMD
);
858 if (*class == ATA_DEV_ATAPI
)
859 new_tmp
|= PORT_CMD_ATAPI
;
861 new_tmp
&= ~PORT_CMD_ATAPI
;
862 if (new_tmp
!= tmp
) {
863 writel(new_tmp
, port_mmio
+ PORT_CMD
);
864 readl(port_mmio
+ PORT_CMD
); /* flush */
868 static u8
ahci_check_status(struct ata_port
*ap
)
870 void __iomem
*mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
872 return readl(mmio
+ PORT_TFDATA
) & 0xFF;
875 static void ahci_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
877 struct ahci_port_priv
*pp
= ap
->private_data
;
878 u8
*d2h_fis
= pp
->rx_fis
+ RX_FIS_D2H_REG
;
880 ata_tf_from_fis(d2h_fis
, tf
);
883 static unsigned int ahci_fill_sg(struct ata_queued_cmd
*qc
, void *cmd_tbl
)
885 struct scatterlist
*sg
;
886 struct ahci_sg
*ahci_sg
;
887 unsigned int n_sg
= 0;
892 * Next, the S/G list.
894 ahci_sg
= cmd_tbl
+ AHCI_CMD_TBL_HDR_SZ
;
895 ata_for_each_sg(sg
, qc
) {
896 dma_addr_t addr
= sg_dma_address(sg
);
897 u32 sg_len
= sg_dma_len(sg
);
899 ahci_sg
->addr
= cpu_to_le32(addr
& 0xffffffff);
900 ahci_sg
->addr_hi
= cpu_to_le32((addr
>> 16) >> 16);
901 ahci_sg
->flags_size
= cpu_to_le32(sg_len
- 1);
910 static void ahci_qc_prep(struct ata_queued_cmd
*qc
)
912 struct ata_port
*ap
= qc
->ap
;
913 struct ahci_port_priv
*pp
= ap
->private_data
;
914 int is_atapi
= is_atapi_taskfile(&qc
->tf
);
917 const u32 cmd_fis_len
= 5; /* five dwords */
921 * Fill in command table information. First, the header,
922 * a SATA Register - Host to Device command FIS.
924 cmd_tbl
= pp
->cmd_tbl
+ qc
->tag
* AHCI_CMD_TBL_SZ
;
926 ata_tf_to_fis(&qc
->tf
, cmd_tbl
, 0);
928 memset(cmd_tbl
+ AHCI_CMD_TBL_CDB
, 0, 32);
929 memcpy(cmd_tbl
+ AHCI_CMD_TBL_CDB
, qc
->cdb
, qc
->dev
->cdb_len
);
933 if (qc
->flags
& ATA_QCFLAG_DMAMAP
)
934 n_elem
= ahci_fill_sg(qc
, cmd_tbl
);
937 * Fill in command slot information.
939 opts
= cmd_fis_len
| n_elem
<< 16;
940 if (qc
->tf
.flags
& ATA_TFLAG_WRITE
)
941 opts
|= AHCI_CMD_WRITE
;
943 opts
|= AHCI_CMD_ATAPI
| AHCI_CMD_PREFETCH
;
945 ahci_fill_cmd_slot(pp
, qc
->tag
, opts
);
948 static void ahci_error_intr(struct ata_port
*ap
, u32 irq_stat
)
950 struct ahci_port_priv
*pp
= ap
->private_data
;
951 struct ata_eh_info
*ehi
= &ap
->eh_info
;
952 unsigned int err_mask
= 0, action
= 0;
953 struct ata_queued_cmd
*qc
;
956 ata_ehi_clear_desc(ehi
);
958 /* AHCI needs SError cleared; otherwise, it might lock up */
959 serror
= ahci_scr_read(ap
, SCR_ERROR
);
960 ahci_scr_write(ap
, SCR_ERROR
, serror
);
962 /* analyze @irq_stat */
963 ata_ehi_push_desc(ehi
, "irq_stat 0x%08x", irq_stat
);
965 if (irq_stat
& PORT_IRQ_TF_ERR
)
966 err_mask
|= AC_ERR_DEV
;
968 if (irq_stat
& (PORT_IRQ_HBUS_ERR
| PORT_IRQ_HBUS_DATA_ERR
)) {
969 err_mask
|= AC_ERR_HOST_BUS
;
970 action
|= ATA_EH_SOFTRESET
;
973 if (irq_stat
& PORT_IRQ_IF_ERR
) {
974 err_mask
|= AC_ERR_ATA_BUS
;
975 action
|= ATA_EH_SOFTRESET
;
976 ata_ehi_push_desc(ehi
, ", interface fatal error");
979 if (irq_stat
& (PORT_IRQ_CONNECT
| PORT_IRQ_PHYRDY
)) {
980 ata_ehi_hotplugged(ehi
);
981 ata_ehi_push_desc(ehi
, ", %s", irq_stat
& PORT_IRQ_CONNECT
?
982 "connection status changed" : "PHY RDY changed");
985 if (irq_stat
& PORT_IRQ_UNK_FIS
) {
986 u32
*unk
= (u32
*)(pp
->rx_fis
+ RX_FIS_UNK
);
988 err_mask
|= AC_ERR_HSM
;
989 action
|= ATA_EH_SOFTRESET
;
990 ata_ehi_push_desc(ehi
, ", unknown FIS %08x %08x %08x %08x",
991 unk
[0], unk
[1], unk
[2], unk
[3]);
994 /* okay, let's hand over to EH */
995 ehi
->serror
|= serror
;
996 ehi
->action
|= action
;
998 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
1000 qc
->err_mask
|= err_mask
;
1002 ehi
->err_mask
|= err_mask
;
1004 if (irq_stat
& PORT_IRQ_FREEZE
)
1005 ata_port_freeze(ap
);
1010 static void ahci_host_intr(struct ata_port
*ap
)
1012 void __iomem
*mmio
= ap
->host
->mmio_base
;
1013 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
1014 struct ata_eh_info
*ehi
= &ap
->eh_info
;
1015 u32 status
, qc_active
;
1018 status
= readl(port_mmio
+ PORT_IRQ_STAT
);
1019 writel(status
, port_mmio
+ PORT_IRQ_STAT
);
1021 if (unlikely(status
& PORT_IRQ_ERROR
)) {
1022 ahci_error_intr(ap
, status
);
1027 qc_active
= readl(port_mmio
+ PORT_SCR_ACT
);
1029 qc_active
= readl(port_mmio
+ PORT_CMD_ISSUE
);
1031 rc
= ata_qc_complete_multiple(ap
, qc_active
, NULL
);
1035 ehi
->err_mask
|= AC_ERR_HSM
;
1036 ehi
->action
|= ATA_EH_SOFTRESET
;
1037 ata_port_freeze(ap
);
1041 /* hmmm... a spurious interupt */
1043 /* some devices send D2H reg with I bit set during NCQ command phase */
1044 if (ap
->sactive
&& status
& PORT_IRQ_D2H_REG_FIS
)
1047 /* ignore interim PIO setup fis interrupts */
1048 if (ata_tag_valid(ap
->active_tag
) && (status
& PORT_IRQ_PIOS_FIS
))
1051 if (ata_ratelimit())
1052 ata_port_printk(ap
, KERN_INFO
, "spurious interrupt "
1053 "(irq_stat 0x%x active_tag %d sactive 0x%x)\n",
1054 status
, ap
->active_tag
, ap
->sactive
);
1057 static void ahci_irq_clear(struct ata_port
*ap
)
1062 static irqreturn_t
ahci_interrupt(int irq
, void *dev_instance
)
1064 struct ata_host
*host
= dev_instance
;
1065 struct ahci_host_priv
*hpriv
;
1066 unsigned int i
, handled
= 0;
1068 u32 irq_stat
, irq_ack
= 0;
1072 hpriv
= host
->private_data
;
1073 mmio
= host
->mmio_base
;
1075 /* sigh. 0xffffffff is a valid return from h/w */
1076 irq_stat
= readl(mmio
+ HOST_IRQ_STAT
);
1077 irq_stat
&= hpriv
->port_map
;
1081 spin_lock(&host
->lock
);
1083 for (i
= 0; i
< host
->n_ports
; i
++) {
1084 struct ata_port
*ap
;
1086 if (!(irq_stat
& (1 << i
)))
1089 ap
= host
->ports
[i
];
1092 VPRINTK("port %u\n", i
);
1094 VPRINTK("port %u (no irq)\n", i
);
1095 if (ata_ratelimit())
1096 dev_printk(KERN_WARNING
, host
->dev
,
1097 "interrupt on disabled port %u\n", i
);
1100 irq_ack
|= (1 << i
);
1104 writel(irq_ack
, mmio
+ HOST_IRQ_STAT
);
1108 spin_unlock(&host
->lock
);
1112 return IRQ_RETVAL(handled
);
1115 static unsigned int ahci_qc_issue(struct ata_queued_cmd
*qc
)
1117 struct ata_port
*ap
= qc
->ap
;
1118 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
1120 if (qc
->tf
.protocol
== ATA_PROT_NCQ
)
1121 writel(1 << qc
->tag
, port_mmio
+ PORT_SCR_ACT
);
1122 writel(1 << qc
->tag
, port_mmio
+ PORT_CMD_ISSUE
);
1123 readl(port_mmio
+ PORT_CMD_ISSUE
); /* flush */
1128 static void ahci_freeze(struct ata_port
*ap
)
1130 void __iomem
*mmio
= ap
->host
->mmio_base
;
1131 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
1134 writel(0, port_mmio
+ PORT_IRQ_MASK
);
1137 static void ahci_thaw(struct ata_port
*ap
)
1139 void __iomem
*mmio
= ap
->host
->mmio_base
;
1140 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
1144 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
1145 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
1146 writel(1 << ap
->id
, mmio
+ HOST_IRQ_STAT
);
1148 /* turn IRQ back on */
1149 writel(DEF_PORT_IRQ
, port_mmio
+ PORT_IRQ_MASK
);
1152 static void ahci_error_handler(struct ata_port
*ap
)
1154 void __iomem
*mmio
= ap
->host
->mmio_base
;
1155 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
1157 if (!(ap
->pflags
& ATA_PFLAG_FROZEN
)) {
1158 /* restart engine */
1159 ahci_stop_engine(port_mmio
);
1160 ahci_start_engine(port_mmio
);
1163 /* perform recovery */
1164 ata_do_eh(ap
, ahci_prereset
, ahci_softreset
, ahci_hardreset
,
1168 static void ahci_post_internal_cmd(struct ata_queued_cmd
*qc
)
1170 struct ata_port
*ap
= qc
->ap
;
1171 void __iomem
*mmio
= ap
->host
->mmio_base
;
1172 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
1174 if (qc
->flags
& ATA_QCFLAG_FAILED
)
1175 qc
->err_mask
|= AC_ERR_OTHER
;
1178 /* make DMA engine forget about the failed command */
1179 ahci_stop_engine(port_mmio
);
1180 ahci_start_engine(port_mmio
);
1184 static int ahci_port_suspend(struct ata_port
*ap
, pm_message_t mesg
)
1186 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1187 struct ahci_port_priv
*pp
= ap
->private_data
;
1188 void __iomem
*mmio
= ap
->host
->mmio_base
;
1189 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
1190 const char *emsg
= NULL
;
1193 rc
= ahci_deinit_port(port_mmio
, hpriv
->cap
, &emsg
);
1195 ata_port_printk(ap
, KERN_ERR
, "%s (%d)\n", emsg
, rc
);
1196 ahci_init_port(port_mmio
, hpriv
->cap
,
1197 pp
->cmd_slot_dma
, pp
->rx_fis_dma
);
1203 static int ahci_port_resume(struct ata_port
*ap
)
1205 struct ahci_port_priv
*pp
= ap
->private_data
;
1206 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1207 void __iomem
*mmio
= ap
->host
->mmio_base
;
1208 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
1210 ahci_init_port(port_mmio
, hpriv
->cap
, pp
->cmd_slot_dma
, pp
->rx_fis_dma
);
1215 static int ahci_pci_device_suspend(struct pci_dev
*pdev
, pm_message_t mesg
)
1217 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
1218 void __iomem
*mmio
= host
->mmio_base
;
1221 if (mesg
.event
== PM_EVENT_SUSPEND
) {
1222 /* AHCI spec rev1.1 section 8.3.3:
1223 * Software must disable interrupts prior to requesting a
1224 * transition of the HBA to D3 state.
1226 ctl
= readl(mmio
+ HOST_CTL
);
1227 ctl
&= ~HOST_IRQ_EN
;
1228 writel(ctl
, mmio
+ HOST_CTL
);
1229 readl(mmio
+ HOST_CTL
); /* flush */
1232 return ata_pci_device_suspend(pdev
, mesg
);
1235 static int ahci_pci_device_resume(struct pci_dev
*pdev
)
1237 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
1238 struct ahci_host_priv
*hpriv
= host
->private_data
;
1239 void __iomem
*mmio
= host
->mmio_base
;
1242 ata_pci_device_do_resume(pdev
);
1244 if (pdev
->dev
.power
.power_state
.event
== PM_EVENT_SUSPEND
) {
1245 rc
= ahci_reset_controller(mmio
, pdev
);
1249 ahci_init_controller(mmio
, pdev
, host
->n_ports
, hpriv
->cap
);
1252 ata_host_resume(host
);
1257 static int ahci_port_start(struct ata_port
*ap
)
1259 struct device
*dev
= ap
->host
->dev
;
1260 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1261 struct ahci_port_priv
*pp
;
1262 void __iomem
*mmio
= ap
->host
->mmio_base
;
1263 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
1268 pp
= kmalloc(sizeof(*pp
), GFP_KERNEL
);
1271 memset(pp
, 0, sizeof(*pp
));
1273 rc
= ata_pad_alloc(ap
, dev
);
1279 mem
= dma_alloc_coherent(dev
, AHCI_PORT_PRIV_DMA_SZ
, &mem_dma
, GFP_KERNEL
);
1281 ata_pad_free(ap
, dev
);
1285 memset(mem
, 0, AHCI_PORT_PRIV_DMA_SZ
);
1288 * First item in chunk of DMA memory: 32-slot command table,
1289 * 32 bytes each in size
1292 pp
->cmd_slot_dma
= mem_dma
;
1294 mem
+= AHCI_CMD_SLOT_SZ
;
1295 mem_dma
+= AHCI_CMD_SLOT_SZ
;
1298 * Second item: Received-FIS area
1301 pp
->rx_fis_dma
= mem_dma
;
1303 mem
+= AHCI_RX_FIS_SZ
;
1304 mem_dma
+= AHCI_RX_FIS_SZ
;
1307 * Third item: data area for storing a single command
1308 * and its scatter-gather table
1311 pp
->cmd_tbl_dma
= mem_dma
;
1313 ap
->private_data
= pp
;
1315 /* initialize port */
1316 ahci_init_port(port_mmio
, hpriv
->cap
, pp
->cmd_slot_dma
, pp
->rx_fis_dma
);
1321 static void ahci_port_stop(struct ata_port
*ap
)
1323 struct device
*dev
= ap
->host
->dev
;
1324 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1325 struct ahci_port_priv
*pp
= ap
->private_data
;
1326 void __iomem
*mmio
= ap
->host
->mmio_base
;
1327 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
1328 const char *emsg
= NULL
;
1331 /* de-initialize port */
1332 rc
= ahci_deinit_port(port_mmio
, hpriv
->cap
, &emsg
);
1334 ata_port_printk(ap
, KERN_WARNING
, "%s (%d)\n", emsg
, rc
);
1336 ap
->private_data
= NULL
;
1337 dma_free_coherent(dev
, AHCI_PORT_PRIV_DMA_SZ
,
1338 pp
->cmd_slot
, pp
->cmd_slot_dma
);
1339 ata_pad_free(ap
, dev
);
1343 static void ahci_setup_port(struct ata_ioports
*port
, unsigned long base
,
1344 unsigned int port_idx
)
1346 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base
, port_idx
);
1347 base
= ahci_port_base_ul(base
, port_idx
);
1348 VPRINTK("base now==0x%lx\n", base
);
1350 port
->cmd_addr
= base
;
1351 port
->scr_addr
= base
+ PORT_SCR
;
1356 static int ahci_host_init(struct ata_probe_ent
*probe_ent
)
1358 struct ahci_host_priv
*hpriv
= probe_ent
->private_data
;
1359 struct pci_dev
*pdev
= to_pci_dev(probe_ent
->dev
);
1360 void __iomem
*mmio
= probe_ent
->mmio_base
;
1361 unsigned int i
, using_dac
;
1364 rc
= ahci_reset_controller(mmio
, pdev
);
1368 hpriv
->cap
= readl(mmio
+ HOST_CAP
);
1369 hpriv
->port_map
= readl(mmio
+ HOST_PORTS_IMPL
);
1370 probe_ent
->n_ports
= (hpriv
->cap
& 0x1f) + 1;
1372 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1373 hpriv
->cap
, hpriv
->port_map
, probe_ent
->n_ports
);
1375 using_dac
= hpriv
->cap
& HOST_CAP_64
;
1377 !pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
1378 rc
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
1380 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
1382 dev_printk(KERN_ERR
, &pdev
->dev
,
1383 "64-bit DMA enable failed\n");
1388 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
1390 dev_printk(KERN_ERR
, &pdev
->dev
,
1391 "32-bit DMA enable failed\n");
1394 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
1396 dev_printk(KERN_ERR
, &pdev
->dev
,
1397 "32-bit consistent DMA enable failed\n");
1402 for (i
= 0; i
< probe_ent
->n_ports
; i
++)
1403 ahci_setup_port(&probe_ent
->port
[i
], (unsigned long) mmio
, i
);
1405 ahci_init_controller(mmio
, pdev
, probe_ent
->n_ports
, hpriv
->cap
);
1407 pci_set_master(pdev
);
1412 static void ahci_print_info(struct ata_probe_ent
*probe_ent
)
1414 struct ahci_host_priv
*hpriv
= probe_ent
->private_data
;
1415 struct pci_dev
*pdev
= to_pci_dev(probe_ent
->dev
);
1416 void __iomem
*mmio
= probe_ent
->mmio_base
;
1417 u32 vers
, cap
, impl
, speed
;
1418 const char *speed_s
;
1422 vers
= readl(mmio
+ HOST_VERSION
);
1424 impl
= hpriv
->port_map
;
1426 speed
= (cap
>> 20) & 0xf;
1429 else if (speed
== 2)
1434 pci_read_config_word(pdev
, 0x0a, &cc
);
1437 else if (cc
== 0x0106)
1439 else if (cc
== 0x0104)
1444 dev_printk(KERN_INFO
, &pdev
->dev
,
1445 "AHCI %02x%02x.%02x%02x "
1446 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1449 (vers
>> 24) & 0xff,
1450 (vers
>> 16) & 0xff,
1454 ((cap
>> 8) & 0x1f) + 1,
1460 dev_printk(KERN_INFO
, &pdev
->dev
,
1466 cap
& (1 << 31) ? "64bit " : "",
1467 cap
& (1 << 30) ? "ncq " : "",
1468 cap
& (1 << 28) ? "ilck " : "",
1469 cap
& (1 << 27) ? "stag " : "",
1470 cap
& (1 << 26) ? "pm " : "",
1471 cap
& (1 << 25) ? "led " : "",
1473 cap
& (1 << 24) ? "clo " : "",
1474 cap
& (1 << 19) ? "nz " : "",
1475 cap
& (1 << 18) ? "only " : "",
1476 cap
& (1 << 17) ? "pmp " : "",
1477 cap
& (1 << 15) ? "pio " : "",
1478 cap
& (1 << 14) ? "slum " : "",
1479 cap
& (1 << 13) ? "part " : ""
1483 static int ahci_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1485 static int printed_version
;
1486 struct ata_probe_ent
*probe_ent
= NULL
;
1487 struct ahci_host_priv
*hpriv
;
1489 void __iomem
*mmio_base
;
1490 unsigned int board_idx
= (unsigned int) ent
->driver_data
;
1491 int have_msi
, pci_dev_busy
= 0;
1496 WARN_ON(ATA_MAX_QUEUE
> AHCI_MAX_CMDS
);
1498 if (!printed_version
++)
1499 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
1501 /* JMicron-specific fixup: make sure we're in AHCI mode */
1502 /* This is protected from races with ata_jmicron by the pci probe
1504 if (pdev
->vendor
== PCI_VENDOR_ID_JMICRON
) {
1505 /* AHCI enable, AHCI on function 0 */
1506 pci_write_config_byte(pdev
, 0x41, 0xa1);
1507 /* Function 1 is the PATA controller */
1508 if (PCI_FUNC(pdev
->devfn
))
1512 rc
= pci_enable_device(pdev
);
1516 rc
= pci_request_regions(pdev
, DRV_NAME
);
1522 if (pci_enable_msi(pdev
) == 0)
1529 probe_ent
= kmalloc(sizeof(*probe_ent
), GFP_KERNEL
);
1530 if (probe_ent
== NULL
) {
1535 memset(probe_ent
, 0, sizeof(*probe_ent
));
1536 probe_ent
->dev
= pci_dev_to_dev(pdev
);
1537 INIT_LIST_HEAD(&probe_ent
->node
);
1539 mmio_base
= pci_iomap(pdev
, AHCI_PCI_BAR
, 0);
1540 if (mmio_base
== NULL
) {
1542 goto err_out_free_ent
;
1544 base
= (unsigned long) mmio_base
;
1546 hpriv
= kmalloc(sizeof(*hpriv
), GFP_KERNEL
);
1549 goto err_out_iounmap
;
1551 memset(hpriv
, 0, sizeof(*hpriv
));
1553 probe_ent
->sht
= ahci_port_info
[board_idx
].sht
;
1554 probe_ent
->port_flags
= ahci_port_info
[board_idx
].flags
;
1555 probe_ent
->pio_mask
= ahci_port_info
[board_idx
].pio_mask
;
1556 probe_ent
->udma_mask
= ahci_port_info
[board_idx
].udma_mask
;
1557 probe_ent
->port_ops
= ahci_port_info
[board_idx
].port_ops
;
1559 probe_ent
->irq
= pdev
->irq
;
1560 probe_ent
->irq_flags
= IRQF_SHARED
;
1561 probe_ent
->mmio_base
= mmio_base
;
1562 probe_ent
->private_data
= hpriv
;
1565 hpriv
->flags
|= AHCI_FLAG_MSI
;
1567 /* initialize adapter */
1568 rc
= ahci_host_init(probe_ent
);
1572 if (!(probe_ent
->port_flags
& AHCI_FLAG_NO_NCQ
) &&
1573 (hpriv
->cap
& HOST_CAP_NCQ
))
1574 probe_ent
->port_flags
|= ATA_FLAG_NCQ
;
1576 ahci_print_info(probe_ent
);
1578 /* FIXME: check ata_device_add return value */
1579 ata_device_add(probe_ent
);
1587 pci_iounmap(pdev
, mmio_base
);
1592 pci_disable_msi(pdev
);
1595 pci_release_regions(pdev
);
1598 pci_disable_device(pdev
);
1602 static void ahci_remove_one (struct pci_dev
*pdev
)
1604 struct device
*dev
= pci_dev_to_dev(pdev
);
1605 struct ata_host
*host
= dev_get_drvdata(dev
);
1606 struct ahci_host_priv
*hpriv
= host
->private_data
;
1610 for (i
= 0; i
< host
->n_ports
; i
++)
1611 ata_port_detach(host
->ports
[i
]);
1613 have_msi
= hpriv
->flags
& AHCI_FLAG_MSI
;
1614 free_irq(host
->irq
, host
);
1616 for (i
= 0; i
< host
->n_ports
; i
++) {
1617 struct ata_port
*ap
= host
->ports
[i
];
1619 ata_scsi_release(ap
->scsi_host
);
1620 scsi_host_put(ap
->scsi_host
);
1624 pci_iounmap(pdev
, host
->mmio_base
);
1628 pci_disable_msi(pdev
);
1631 pci_release_regions(pdev
);
1632 pci_disable_device(pdev
);
1633 dev_set_drvdata(dev
, NULL
);
1636 static int __init
ahci_init(void)
1638 return pci_register_driver(&ahci_pci_driver
);
1641 static void __exit
ahci_exit(void)
1643 pci_unregister_driver(&ahci_pci_driver
);
1647 MODULE_AUTHOR("Jeff Garzik");
1648 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1649 MODULE_LICENSE("GPL");
1650 MODULE_DEVICE_TABLE(pci
, ahci_pci_tbl
);
1651 MODULE_VERSION(DRV_VERSION
);
1653 module_init(ahci_init
);
1654 module_exit(ahci_exit
);