arch/arm/mach-shmobile/pm-sh7372.c

   1 /*
   2  * sh7372 Power management support
   3  *
   4  *  Copyright (C) 2011 Magnus Damm
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10
  11 #include <linux/pm.h>
  12 #include <linux/suspend.h>
  13 #include <linux/cpuidle.h>
  14 #include <linux/module.h>
  15 #include <linux/list.h>
  16 #include <linux/err.h>
  17 #include <linux/slab.h>
  18 #include <linux/pm_clock.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/delay.h>
  21 #include <linux/irq.h>
  22 #include <linux/bitrev.h>
  23 #include <linux/console.h>
  24 #include <asm/system.h>
  25 #include <asm/io.h>
  26 #include <asm/tlbflush.h>
  27 #include <asm/suspend.h>
  28 #include <mach/common.h>
  29 #include <mach/sh7372.h>
  30
  31 /* DBG */
  32 #define DBGREG1 0xe6100020
  33 #define DBGREG9 0xe6100040
  34
  35 /* CPGA */
  36 #define SYSTBCR 0xe6150024
  37 #define MSTPSR0 0xe6150030
  38 #define MSTPSR1 0xe6150038
  39 #define MSTPSR2 0xe6150040
  40 #define MSTPSR3 0xe6150048
  41 #define MSTPSR4 0xe615004c
  42 #define PLLC01STPCR 0xe61500c8
  43
  44 /* SYSC */
  45 #define SPDCR 0xe6180008
  46 #define SWUCR 0xe6180014
  47 #define SBAR 0xe6180020
  48 #define WUPRMSK 0xe6180028
  49 #define WUPSMSK 0xe618002c
  50 #define WUPSMSK2 0xe6180048
  51 #define PSTR 0xe6180080
  52 #define WUPSFAC 0xe6180098
  53 #define IRQCR 0xe618022c
  54 #define IRQCR2 0xe6180238
  55 #define IRQCR3 0xe6180244
  56 #define IRQCR4 0xe6180248
  57 #define PDNSEL 0xe6180254
  58
  59 /* INTC */
  60 #define ICR1A 0xe6900000
  61 #define ICR2A 0xe6900004
  62 #define ICR3A 0xe6900008
  63 #define ICR4A 0xe690000c
  64 #define INTMSK00A 0xe6900040
  65 #define INTMSK10A 0xe6900044
  66 #define INTMSK20A 0xe6900048
  67 #define INTMSK30A 0xe690004c
  68
  69 /* MFIS */
  70 #define SMFRAM 0xe6a70000
  71
  72 /* AP-System Core */
  73 #define APARMBAREA 0xe6f10020
  74
  75 #define PSTR_RETRIES 100
  76 #define PSTR_DELAY_US 10
  77
  78 #ifdef CONFIG_PM
  79
  80 static int pd_power_down(struct generic_pm_domain *genpd)
  81 {
  82         struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
  83         unsigned int mask = 1 << sh7372_pd->bit_shift;
  84
  85         if (sh7372_pd->suspend)
  86                 sh7372_pd->suspend();
  87
  88         if (sh7372_pd->stay_on)
  89                 return 0;
  90
  91         if (__raw_readl(PSTR) & mask) {
  92                 unsigned int retry_count;
  93
  94                 __raw_writel(mask, SPDCR);
  95
  96                 for (retry_count = PSTR_RETRIES; retry_count; retry_count--) {
  97                         if (!(__raw_readl(SPDCR) & mask))
  98                                 break;
  99                         cpu_relax();
 100                 }
 101         }
 102
 103         if (!sh7372_pd->no_debug)
 104                 pr_debug("sh7372 power domain down 0x%08x -> PSTR = 0x%08x\n",
 105                          mask, __raw_readl(PSTR));
 106
 107         return 0;
 108 }
 109
 110 static int __pd_power_up(struct sh7372_pm_domain *sh7372_pd, bool do_resume)
 111 {
 112         unsigned int mask = 1 << sh7372_pd->bit_shift;
 113         unsigned int retry_count;
 114         int ret = 0;
 115
 116         if (sh7372_pd->stay_on)
 117                 goto out;
 118
 119         if (__raw_readl(PSTR) & mask)
 120                 goto out;
 121
 122         __raw_writel(mask, SWUCR);
 123
 124         for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) {
 125                 if (!(__raw_readl(SWUCR) & mask))
 126                         break;
 127                 if (retry_count > PSTR_RETRIES)
 128                         udelay(PSTR_DELAY_US);
 129                 else
 130                         cpu_relax();
 131         }
 132         if (!retry_count)
 133                 ret = -EIO;
 134
 135         if (!sh7372_pd->no_debug)
 136                 pr_debug("sh7372 power domain up 0x%08x -> PSTR = 0x%08x\n",
 137                          mask, __raw_readl(PSTR));
 138
 139  out:
 140         if (ret == 0 && sh7372_pd->resume && do_resume)
 141                 sh7372_pd->resume();
 142
 143         return ret;
 144 }
 145
 146 static int pd_power_up(struct generic_pm_domain *genpd)
 147 {
 148          return __pd_power_up(to_sh7372_pd(genpd), true);
 149 }
 150
 151 static void sh7372_a4r_suspend(void)
 152 {
 153         sh7372_intcs_suspend();
 154         __raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */
 155 }
 156
 157 static bool pd_active_wakeup(struct device *dev)
 158 {
 159         return true;
 160 }
 161
 162 static bool sh7372_power_down_forbidden(struct dev_pm_domain *domain)
 163 {
 164         return false;
 165 }
 166
 167 struct dev_power_governor sh7372_always_on_gov = {
 168         .power_down_ok = sh7372_power_down_forbidden,
 169 };
 170
 171 void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd)
 172 {
 173         struct generic_pm_domain *genpd = &sh7372_pd->genpd;
 174
 175         pm_genpd_init(genpd, sh7372_pd->gov, false);
 176         genpd->stop_device = pm_clk_suspend;
 177         genpd->start_device = pm_clk_resume;
 178         genpd->dev_irq_safe = true;
 179         genpd->active_wakeup = pd_active_wakeup;
 180         genpd->power_off = pd_power_down;
 181         genpd->power_on = pd_power_up;
 182         __pd_power_up(sh7372_pd, false);
 183 }
 184
 185 void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd,
 186                                  struct platform_device *pdev)
 187 {
 188         struct device *dev = &pdev->dev;
 189
 190         pm_genpd_add_device(&sh7372_pd->genpd, dev);
 191         if (pm_clk_no_clocks(dev))
 192                 pm_clk_add(dev, NULL);
 193 }
 194
 195 void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd,
 196                              struct sh7372_pm_domain *sh7372_sd)
 197 {
 198         pm_genpd_add_subdomain(&sh7372_pd->genpd, &sh7372_sd->genpd);
 199 }
 200
 201 struct sh7372_pm_domain sh7372_a4lc = {
 202         .bit_shift = 1,
 203 };
 204
 205 struct sh7372_pm_domain sh7372_a4mp = {
 206         .bit_shift = 2,
 207 };
 208
 209 struct sh7372_pm_domain sh7372_d4 = {
 210         .bit_shift = 3,
 211 };
 212
 213 struct sh7372_pm_domain sh7372_a4r = {
 214         .bit_shift = 5,
 215         .gov = &sh7372_always_on_gov,
 216         .suspend = sh7372_a4r_suspend,
 217         .resume = sh7372_intcs_resume,
 218         .stay_on = true,
 219 };
 220
 221 struct sh7372_pm_domain sh7372_a3rv = {
 222         .bit_shift = 6,
 223 };
 224
 225 struct sh7372_pm_domain sh7372_a3ri = {
 226         .bit_shift = 8,
 227 };
 228
 229 struct sh7372_pm_domain sh7372_a3sp = {
 230         .bit_shift = 11,
 231         .gov = &sh7372_always_on_gov,
 232         .no_debug = true,
 233 };
 234
 235 static void sh7372_a3sp_init(void)
 236 {
 237         /* serial consoles make use of SCIF hardware located in A3SP,
 238          * keep such power domain on if "no_console_suspend" is set.
 239          */
 240         sh7372_a3sp.stay_on = !console_suspend_enabled;
 241 }
 242
 243 struct sh7372_pm_domain sh7372_a3sg = {
 244         .bit_shift = 13,
 245 };
 246
 247 #else /* !CONFIG_PM */
 248
 249 static inline void sh7372_a3sp_init(void) {}
 250
 251 #endif /* !CONFIG_PM */
 252
 253 #if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE)
 254 static int sh7372_do_idle_core_standby(unsigned long unused)
 255 {
 256         cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */
 257         return 0;
 258 }
 259
 260 static void sh7372_enter_core_standby(void)
 261 {
 262         /* set reset vector, translate 4k */
 263         __raw_writel(__pa(sh7372_resume_core_standby_a3sm), SBAR);
 264         __raw_writel(0, APARMBAREA);
 265
 266         /* enter sleep mode with SYSTBCR to 0x10 */
 267         __raw_writel(0x10, SYSTBCR);
 268         cpu_suspend(0, sh7372_do_idle_core_standby);
 269         __raw_writel(0, SYSTBCR);
 270
 271          /* disable reset vector translation */
 272         __raw_writel(0, SBAR);
 273 }
 274 #endif
 275
 276 #ifdef CONFIG_SUSPEND
 277 static void sh7372_enter_a3sm_common(int pllc0_on)
 278 {
 279         /* set reset vector, translate 4k */
 280         __raw_writel(__pa(sh7372_resume_core_standby_a3sm), SBAR);
 281         __raw_writel(0, APARMBAREA);
 282
 283         if (pllc0_on)
 284                 __raw_writel(0, PLLC01STPCR);
 285         else
 286                 __raw_writel(1 << 28, PLLC01STPCR);
 287
 288         __raw_writel(0, PDNSEL); /* power-down A3SM only, not A4S */
 289         __raw_readl(WUPSFAC); /* read wakeup int. factor before sleep */
 290         cpu_suspend(0, sh7372_do_idle_a3sm);
 291         __raw_readl(WUPSFAC); /* read wakeup int. factor after wakeup */
 292
 293          /* disable reset vector translation */
 294         __raw_writel(0, SBAR);
 295 }
 296
 297 static int sh7372_a3sm_valid(unsigned long *mskp, unsigned long *msk2p)
 298 {
 299         unsigned long mstpsr0, mstpsr1, mstpsr2, mstpsr3, mstpsr4;
 300         unsigned long msk, msk2;
 301
 302         /* check active clocks to determine potential wakeup sources */
 303
 304         mstpsr0 = __raw_readl(MSTPSR0);
 305         if ((mstpsr0 & 0x00000003) != 0x00000003) {
 306                 pr_debug("sh7372 mstpsr0 0x%08lx\n", mstpsr0);
 307                 return 0;
 308         }
 309
 310         mstpsr1 = __raw_readl(MSTPSR1);
 311         if ((mstpsr1 & 0xff079b7f) != 0xff079b7f) {
 312                 pr_debug("sh7372 mstpsr1 0x%08lx\n", mstpsr1);
 313                 return 0;
 314         }
 315
 316         mstpsr2 = __raw_readl(MSTPSR2);
 317         if ((mstpsr2 & 0x000741ff) != 0x000741ff) {
 318                 pr_debug("sh7372 mstpsr2 0x%08lx\n", mstpsr2);
 319                 return 0;
 320         }
 321
 322         mstpsr3 = __raw_readl(MSTPSR3);
 323         if ((mstpsr3 & 0x1a60f010) != 0x1a60f010) {
 324                 pr_debug("sh7372 mstpsr3 0x%08lx\n", mstpsr3);
 325                 return 0;
 326         }
 327
 328         mstpsr4 = __raw_readl(MSTPSR4);
 329         if ((mstpsr4 & 0x00008cf0) != 0x00008cf0) {
 330                 pr_debug("sh7372 mstpsr4 0x%08lx\n", mstpsr4);
 331                 return 0;
 332         }
 333
 334         msk = 0;
 335         msk2 = 0;
 336
 337         /* make bitmaps of limited number of wakeup sources */
 338
 339         if ((mstpsr2 & (1 << 23)) == 0) /* SPU2 */
 340                 msk |= 1 << 31;
 341
 342         if ((mstpsr2 & (1 << 12)) == 0) /* MFI_MFIM */
 343                 msk |= 1 << 21;
 344
 345         if ((mstpsr4 & (1 << 3)) == 0) /* KEYSC */
 346                 msk |= 1 << 2;
 347
 348         if ((mstpsr1 & (1 << 24)) == 0) /* CMT0 */
 349                 msk |= 1 << 1;
 350
 351         if ((mstpsr3 & (1 << 29)) == 0) /* CMT1 */
 352                 msk |= 1 << 1;
 353
 354         if ((mstpsr4 & (1 << 0)) == 0) /* CMT2 */
 355                 msk |= 1 << 1;
 356
 357         if ((mstpsr2 & (1 << 13)) == 0) /* MFI_MFIS */
 358                 msk2 |= 1 << 17;
 359
 360         *mskp = msk;
 361         *msk2p = msk2;
 362
 363         return 1;
 364 }
 365
 366 static void sh7372_icr_to_irqcr(unsigned long icr, u16 *irqcr1p, u16 *irqcr2p)
 367 {
 368         u16 tmp, irqcr1, irqcr2;
 369         int k;
 370
 371         irqcr1 = 0;
 372         irqcr2 = 0;
 373
 374         /* convert INTCA ICR register layout to SYSC IRQCR+IRQCR2 */
 375         for (k = 0; k <= 7; k++) {
 376                 tmp = (icr >> ((7 - k) * 4)) & 0xf;
 377                 irqcr1 |= (tmp & 0x03) << (k * 2);
 378                 irqcr2 |= (tmp >> 2) << (k * 2);
 379         }
 380
 381         *irqcr1p = irqcr1;
 382         *irqcr2p = irqcr2;
 383 }
 384
 385 static void sh7372_setup_a3sm(unsigned long msk, unsigned long msk2)
 386 {
 387         u16 irqcrx_low, irqcrx_high, irqcry_low, irqcry_high;
 388         unsigned long tmp;
 389
 390         /* read IRQ0A -> IRQ15A mask */
 391         tmp = bitrev8(__raw_readb(INTMSK00A));
 392         tmp |= bitrev8(__raw_readb(INTMSK10A)) << 8;
 393
 394         /* setup WUPSMSK from clocks and external IRQ mask */
 395         msk = (~msk & 0xc030000f) | (tmp << 4);
 396         __raw_writel(msk, WUPSMSK);
 397
 398         /* propage level/edge trigger for external IRQ 0->15 */
 399         sh7372_icr_to_irqcr(__raw_readl(ICR1A), &irqcrx_low, &irqcry_low);
 400         sh7372_icr_to_irqcr(__raw_readl(ICR2A), &irqcrx_high, &irqcry_high);
 401         __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR);
 402         __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR2);
 403
 404         /* read IRQ16A -> IRQ31A mask */
 405         tmp = bitrev8(__raw_readb(INTMSK20A));
 406         tmp |= bitrev8(__raw_readb(INTMSK30A)) << 8;
 407
 408         /* setup WUPSMSK2 from clocks and external IRQ mask */
 409         msk2 = (~msk2 & 0x00030000) | tmp;
 410         __raw_writel(msk2, WUPSMSK2);
 411
 412         /* propage level/edge trigger for external IRQ 16->31 */
 413         sh7372_icr_to_irqcr(__raw_readl(ICR3A), &irqcrx_low, &irqcry_low);
 414         sh7372_icr_to_irqcr(__raw_readl(ICR4A), &irqcrx_high, &irqcry_high);
 415         __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR3);
 416         __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR4);
 417 }
 418 #endif
 419
 420 #ifdef CONFIG_CPU_IDLE
 421
 422 static void sh7372_cpuidle_setup(struct cpuidle_driver *drv)
 423 {
 424         struct cpuidle_state *state = &drv->states[drv->state_count];
 425
 426         snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
 427         strncpy(state->desc, "Core Standby Mode", CPUIDLE_DESC_LEN);
 428         state->exit_latency = 10;
 429         state->target_residency = 20 + 10;
 430         state->flags = CPUIDLE_FLAG_TIME_VALID;
 431         shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_core_standby;
 432
 433         drv->state_count++;
 434 }
 435
 436 static void sh7372_cpuidle_init(void)
 437 {
 438         shmobile_cpuidle_setup = sh7372_cpuidle_setup;
 439 }
 440 #else
 441 static void sh7372_cpuidle_init(void) {}
 442 #endif
 443
 444 #ifdef CONFIG_SUSPEND
 445
 446 static int sh7372_enter_suspend(suspend_state_t suspend_state)
 447 {
 448         unsigned long msk, msk2;
 449
 450         /* check active clocks to determine potential wakeup sources */
 451         if (sh7372_a3sm_valid(&msk, &msk2)) {
 452
 453                 /* convert INTC mask and sense to SYSC mask and sense */
 454                 sh7372_setup_a3sm(msk, msk2);
 455
 456                 /* enter A3SM sleep with PLLC0 off */
 457                 pr_debug("entering A3SM\n");
 458                 sh7372_enter_a3sm_common(0);
 459         } else {
 460                 /* default to Core Standby that supports all wakeup sources */
 461                 pr_debug("entering Core Standby\n");
 462                 sh7372_enter_core_standby();
 463         }
 464         return 0;
 465 }
 466
 467 static void sh7372_suspend_init(void)
 468 {
 469         shmobile_suspend_ops.enter = sh7372_enter_suspend;
 470 }
 471 #else
 472 static void sh7372_suspend_init(void) {}
 473 #endif
 474
 475 void __init sh7372_pm_init(void)
 476 {
 477         /* enable DBG hardware block to kick SYSC */
 478         __raw_writel(0x0000a500, DBGREG9);
 479         __raw_writel(0x0000a501, DBGREG9);
 480         __raw_writel(0x00000000, DBGREG1);
 481
 482         /* do not convert A3SM, A3SP, A3SG, A4R power down into A4S */
 483         __raw_writel(0, PDNSEL);
 484
 485         sh7372_a3sp_init();
 486
 487         sh7372_suspend_init();
 488         sh7372_cpuidle_init();
 489 }