arch/arm/mach-shmobile/clock-sh73a0.c

   1 /*
   2  * sh73a0 clock framework support
   3  *
   4  * Copyright (C) 2010 Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19 #include <linux/init.h>
  20 #include <linux/kernel.h>
  21 #include <linux/io.h>
  22 #include <linux/sh_clk.h>
  23 #include <linux/clkdev.h>
  24 #include <mach/common.h>
  25
  26 #define FRQCRA          0xe6150000
  27 #define FRQCRB          0xe6150004
  28 #define FRQCRD          0xe61500e4
  29 #define VCLKCR1         0xe6150008
  30 #define VCLKCR2         0xe615000C
  31 #define VCLKCR3         0xe615001C
  32 #define ZBCKCR          0xe6150010
  33 #define FLCKCR          0xe6150014
  34 #define SD0CKCR         0xe6150074
  35 #define SD1CKCR         0xe6150078
  36 #define SD2CKCR         0xe615007C
  37 #define FSIACKCR        0xe6150018
  38 #define FSIBCKCR        0xe6150090
  39 #define SUBCKCR         0xe6150080
  40 #define SPUACKCR        0xe6150084
  41 #define SPUVCKCR        0xe6150094
  42 #define MSUCKCR         0xe6150088
  43 #define HSICKCR         0xe615008C
  44 #define MFCK1CR         0xe6150098
  45 #define MFCK2CR         0xe615009C
  46 #define DSITCKCR        0xe6150060
  47 #define DSI0PCKCR       0xe6150064
  48 #define DSI1PCKCR       0xe6150068
  49 #define DSI0PHYCR       0xe615006C
  50 #define DSI1PHYCR       0xe6150070
  51 #define PLLECR          0xe61500d0
  52 #define PLL0CR          0xe61500d8
  53 #define PLL1CR          0xe6150028
  54 #define PLL2CR          0xe615002c
  55 #define PLL3CR          0xe61500dc
  56 #define SMSTPCR0        0xe6150130
  57 #define SMSTPCR1        0xe6150134
  58 #define SMSTPCR2        0xe6150138
  59 #define SMSTPCR3        0xe615013c
  60 #define SMSTPCR4        0xe6150140
  61 #define SMSTPCR5        0xe6150144
  62 #define CKSCR           0xe61500c0
  63
  64 /* Fixed 32 KHz root clock from EXTALR pin */
  65 static struct clk r_clk = {
  66         .rate           = 32768,
  67 };
  68
  69 /*
  70  * 26MHz default rate for the EXTAL1 root input clock.
  71  * If needed, reset this with clk_set_rate() from the platform code.
  72  */
  73 struct clk sh73a0_extal1_clk = {
  74         .rate           = 26000000,
  75 };
  76
  77 /*
  78  * 48MHz default rate for the EXTAL2 root input clock.
  79  * If needed, reset this with clk_set_rate() from the platform code.
  80  */
  81 struct clk sh73a0_extal2_clk = {
  82         .rate           = 48000000,
  83 };
  84
  85 /* A fixed divide-by-2 block */
  86 static unsigned long div2_recalc(struct clk *clk)
  87 {
  88         return clk->parent->rate / 2;
  89 }
  90
  91 static struct clk_ops div2_clk_ops = {
  92         .recalc         = div2_recalc,
  93 };
  94
  95 /* Divide extal1 by two */
  96 static struct clk extal1_div2_clk = {
  97         .ops            = &div2_clk_ops,
  98         .parent         = &sh73a0_extal1_clk,
  99 };
 100
 101 /* Divide extal2 by two */
 102 static struct clk extal2_div2_clk = {
 103         .ops            = &div2_clk_ops,
 104         .parent         = &sh73a0_extal2_clk,
 105 };
 106
 107 static struct clk_ops main_clk_ops = {
 108         .recalc         = followparent_recalc,
 109 };
 110
 111 /* Main clock */
 112 static struct clk main_clk = {
 113         .ops            = &main_clk_ops,
 114 };
 115
 116 /* Divide Main clock by two */
 117 static struct clk main_div2_clk = {
 118         .ops            = &div2_clk_ops,
 119         .parent         = &main_clk,
 120 };
 121
 122 /* PLL0, PLL1, PLL2, PLL3 */
 123 static unsigned long pll_recalc(struct clk *clk)
 124 {
 125         unsigned long mult = 1;
 126
 127         if (__raw_readl(PLLECR) & (1 << clk->enable_bit)) {
 128                 mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1);
 129                 /* handle CFG bit for PLL1 and PLL2 */
 130                 switch (clk->enable_bit) {
 131                 case 1:
 132                 case 2:
 133                         if (__raw_readl(clk->enable_reg) & (1 << 20))
 134                                 mult *= 2;
 135                 }
 136         }
 137
 138         return clk->parent->rate * mult;
 139 }
 140
 141 static struct clk_ops pll_clk_ops = {
 142         .recalc         = pll_recalc,
 143 };
 144
 145 static struct clk pll0_clk = {
 146         .ops            = &pll_clk_ops,
 147         .flags          = CLK_ENABLE_ON_INIT,
 148         .parent         = &main_clk,
 149         .enable_reg     = (void __iomem *)PLL0CR,
 150         .enable_bit     = 0,
 151 };
 152
 153 static struct clk pll1_clk = {
 154         .ops            = &pll_clk_ops,
 155         .flags          = CLK_ENABLE_ON_INIT,
 156         .parent         = &main_clk,
 157         .enable_reg     = (void __iomem *)PLL1CR,
 158         .enable_bit     = 1,
 159 };
 160
 161 static struct clk pll2_clk = {
 162         .ops            = &pll_clk_ops,
 163         .flags          = CLK_ENABLE_ON_INIT,
 164         .parent         = &main_clk,
 165         .enable_reg     = (void __iomem *)PLL2CR,
 166         .enable_bit     = 2,
 167 };
 168
 169 static struct clk pll3_clk = {
 170         .ops            = &pll_clk_ops,
 171         .flags          = CLK_ENABLE_ON_INIT,
 172         .parent         = &main_clk,
 173         .enable_reg     = (void __iomem *)PLL3CR,
 174         .enable_bit     = 3,
 175 };
 176
 177 /* Divide PLL1 by two */
 178 static struct clk pll1_div2_clk = {
 179         .ops            = &div2_clk_ops,
 180         .parent         = &pll1_clk,
 181 };
 182
 183 static struct clk *main_clks[] = {
 184         &r_clk,
 185         &sh73a0_extal1_clk,
 186         &sh73a0_extal2_clk,
 187         &extal1_div2_clk,
 188         &extal2_div2_clk,
 189         &main_clk,
 190         &main_div2_clk,
 191         &pll0_clk,
 192         &pll1_clk,
 193         &pll2_clk,
 194         &pll3_clk,
 195         &pll1_div2_clk,
 196 };
 197
 198 static void div4_kick(struct clk *clk)
 199 {
 200         unsigned long value;
 201
 202         /* set KICK bit in FRQCRB to update hardware setting */
 203         value = __raw_readl(FRQCRB);
 204         value |= (1 << 31);
 205         __raw_writel(value, FRQCRB);
 206 }
 207
 208 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
 209                           24, 0, 36, 48, 7 };
 210
 211 static struct clk_div_mult_table div4_div_mult_table = {
 212         .divisors = divisors,
 213         .nr_divisors = ARRAY_SIZE(divisors),
 214 };
 215
 216 static struct clk_div4_table div4_table = {
 217         .div_mult_table = &div4_div_mult_table,
 218         .kick = div4_kick,
 219 };
 220
 221 enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
 222         DIV4_Z, DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, DIV4_NR };
 223
 224 #define DIV4(_reg, _bit, _mask, _flags) \
 225         SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags)
 226
 227 static struct clk div4_clks[DIV4_NR] = {
 228         [DIV4_I] = DIV4(FRQCRA, 20, 0xfff, CLK_ENABLE_ON_INIT),
 229         [DIV4_ZG] = DIV4(FRQCRA, 16, 0xbff, CLK_ENABLE_ON_INIT),
 230         [DIV4_M3] = DIV4(FRQCRA, 12, 0xfff, CLK_ENABLE_ON_INIT),
 231         [DIV4_B] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT),
 232         [DIV4_M1] = DIV4(FRQCRA, 4, 0xfff, 0),
 233         [DIV4_M2] = DIV4(FRQCRA, 0, 0xfff, 0),
 234         [DIV4_Z] = DIV4(FRQCRB, 24, 0xbff, 0),
 235         [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xfff, 0),
 236         [DIV4_ZT] = DIV4(FRQCRB, 16, 0xfff, 0),
 237         [DIV4_ZX] = DIV4(FRQCRB, 12, 0xfff, 0),
 238         [DIV4_HP] = DIV4(FRQCRB, 4, 0xfff, 0),
 239 };
 240
 241 enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
 242         DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
 243         DIV6_FSIA, DIV6_FSIB, DIV6_SUB,
 244         DIV6_SPUA, DIV6_SPUV, DIV6_MSU,
 245         DIV6_HSI,  DIV6_MFG1, DIV6_MFG2,
 246         DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
 247         DIV6_NR };
 248
 249 static struct clk div6_clks[DIV6_NR] = {
 250         [DIV6_VCK1] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR1, 0),
 251         [DIV6_VCK2] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR2, 0),
 252         [DIV6_VCK3] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR3, 0),
 253         [DIV6_ZB1] = SH_CLK_DIV6(&pll1_div2_clk, ZBCKCR, CLK_ENABLE_ON_INIT),
 254         [DIV6_FLCTL] = SH_CLK_DIV6(&pll1_div2_clk, FLCKCR, 0),
 255         [DIV6_SDHI0] = SH_CLK_DIV6(&pll1_div2_clk, SD0CKCR, 0),
 256         [DIV6_SDHI1] = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0),
 257         [DIV6_SDHI2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
 258         [DIV6_FSIA] = SH_CLK_DIV6(&pll1_div2_clk, FSIACKCR, 0),
 259         [DIV6_FSIB] = SH_CLK_DIV6(&pll1_div2_clk, FSIBCKCR, 0),
 260         [DIV6_SUB] = SH_CLK_DIV6(&sh73a0_extal2_clk, SUBCKCR, 0),
 261         [DIV6_SPUA] = SH_CLK_DIV6(&pll1_div2_clk, SPUACKCR, 0),
 262         [DIV6_SPUV] = SH_CLK_DIV6(&pll1_div2_clk, SPUVCKCR, 0),
 263         [DIV6_MSU] = SH_CLK_DIV6(&pll1_div2_clk, MSUCKCR, 0),
 264         [DIV6_HSI] = SH_CLK_DIV6(&pll1_div2_clk, HSICKCR, 0),
 265         [DIV6_MFG1] = SH_CLK_DIV6(&pll1_div2_clk, MFCK1CR, 0),
 266         [DIV6_MFG2] = SH_CLK_DIV6(&pll1_div2_clk, MFCK2CR, 0),
 267         [DIV6_DSIT] = SH_CLK_DIV6(&pll1_div2_clk, DSITCKCR, 0),
 268         [DIV6_DSI0P] = SH_CLK_DIV6(&pll1_div2_clk, DSI0PCKCR, 0),
 269         [DIV6_DSI1P] = SH_CLK_DIV6(&pll1_div2_clk, DSI1PCKCR, 0),
 270 };
 271
 272 enum { MSTP001,
 273         MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
 274         MSTP219,
 275         MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
 276         MSTP331, MSTP329, MSTP325, MSTP323, MSTP318,
 277         MSTP314, MSTP313, MSTP312, MSTP311,
 278         MSTP303, MSTP302, MSTP301, MSTP300,
 279         MSTP411, MSTP410, MSTP403,
 280         MSTP_NR };
 281
 282 #define MSTP(_parent, _reg, _bit, _flags) \
 283         SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
 284
 285 static struct clk mstp_clks[MSTP_NR] = {
 286         [MSTP001] = MSTP(&div4_clks[DIV4_HP], SMSTPCR0, 1, 0), /* IIC2 */
 287         [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* CEU1 */
 288         [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* CSI2-RX1 */
 289         [MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU0 */
 290         [MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2-RX0 */
 291         [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
 292         [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX0 */
 293         [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */
 294         [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
 295         [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */
 296         [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
 297         [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
 298         [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
 299         [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
 300         [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
 301         [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
 302         [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
 303         [MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */
 304         [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
 305         [MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IrDA */
 306         [MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
 307         [MSTP318] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 18, 0), /* SY-DMAC */
 308         [MSTP314] = MSTP(&div6_clks[DIV6_SDHI0], SMSTPCR3, 14, 0), /* SDHI0 */
 309         [MSTP313] = MSTP(&div6_clks[DIV6_SDHI1], SMSTPCR3, 13, 0), /* SDHI1 */
 310         [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */
 311         [MSTP311] = MSTP(&div6_clks[DIV6_SDHI2], SMSTPCR3, 11, 0), /* SDHI2 */
 312         [MSTP303] = MSTP(&main_div2_clk, SMSTPCR3, 3, 0), /* TPU1 */
 313         [MSTP302] = MSTP(&main_div2_clk, SMSTPCR3, 2, 0), /* TPU2 */
 314         [MSTP301] = MSTP(&main_div2_clk, SMSTPCR3, 1, 0), /* TPU3 */
 315         [MSTP300] = MSTP(&main_div2_clk, SMSTPCR3, 0, 0), /* TPU4 */
 316         [MSTP411] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */
 317         [MSTP410] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */
 318         [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
 319 };
 320
 321 static struct clk_lookup lookups[] = {
 322         /* main clocks */
 323         CLKDEV_CON_ID("r_clk", &r_clk),
 324
 325         /* DIV6 clocks */
 326         CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
 327         CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
 328         CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
 329         CLKDEV_CON_ID("sdhi0_clk", &div6_clks[DIV6_SDHI0]),
 330         CLKDEV_CON_ID("sdhi1_clk", &div6_clks[DIV6_SDHI1]),
 331         CLKDEV_CON_ID("sdhi2_clk", &div6_clks[DIV6_SDHI2]),
 332         CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
 333         CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
 334         CLKDEV_ICK_ID("dsi0p_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
 335         CLKDEV_ICK_ID("dsi1p_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
 336
 337         /* MSTP32 clocks */
 338         CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
 339         CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP129]), /* CEU1 */
 340         CLKDEV_DEV_ID("sh-mobile-csi2.1", &mstp_clks[MSTP128]), /* CSI2-RX1 */
 341         CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU0 */
 342         CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2-RX0 */
 343         CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
 344         CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
 345         CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
 346         CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
 347         CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
 348         CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
 349         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
 350         CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
 351         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
 352         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
 353         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
 354         CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
 355         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
 356         CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
 357         CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
 358         CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
 359         CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
 360         CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP318]), /* SY-DMAC */
 361         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
 362         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
 363         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
 364         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */
 365         CLKDEV_DEV_ID("leds-renesas-tpu.12", &mstp_clks[MSTP303]), /* TPU1 */
 366         CLKDEV_DEV_ID("leds-renesas-tpu.21", &mstp_clks[MSTP302]), /* TPU2 */
 367         CLKDEV_DEV_ID("leds-renesas-tpu.30", &mstp_clks[MSTP301]), /* TPU3 */
 368         CLKDEV_DEV_ID("leds-renesas-tpu.41", &mstp_clks[MSTP300]), /* TPU4 */
 369         CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */
 370         CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */
 371         CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
 372 };
 373
 374 void __init sh73a0_clock_init(void)
 375 {
 376         int k, ret = 0;
 377
 378         /* Set SDHI clocks to a known state */
 379         __raw_writel(0x108, SD0CKCR);
 380         __raw_writel(0x108, SD1CKCR);
 381         __raw_writel(0x108, SD2CKCR);
 382
 383         /* detect main clock parent */
 384         switch ((__raw_readl(CKSCR) >> 28) & 0x03) {
 385         case 0:
 386                 main_clk.parent = &sh73a0_extal1_clk;
 387                 break;
 388         case 1:
 389                 main_clk.parent = &extal1_div2_clk;
 390                 break;
 391         case 2:
 392                 main_clk.parent = &sh73a0_extal2_clk;
 393                 break;
 394         case 3:
 395                 main_clk.parent = &extal2_div2_clk;
 396                 break;
 397         }
 398
 399         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
 400                 ret = clk_register(main_clks[k]);
 401
 402         if (!ret)
 403                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 404
 405         if (!ret)
 406                 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
 407
 408         if (!ret)
 409                 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
 410
 411         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 412
 413         if (!ret)
 414                 clk_init();
 415         else
 416                 panic("failed to setup sh73a0 clocks\n");
 417 }