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staging: ti dspbridge: remove unused code
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / tidspbridge / core / tiomap3430.c
blobd1fa560ae98b78a49c8befbf47772bc61452e04f
1 /*
2 * tiomap.c
3 *
4 * DSP-BIOS Bridge driver support functions for TI OMAP processors.
5 *
6 * Processor Manager Driver for TI OMAP3430 EVM.
7 *
8 * Copyright (C) 2005-2006 Texas Instruments, Inc.
9 *
10 * This package is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
16 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
17 */
18
19 /* ----------------------------------- Host OS */
20 #include <dspbridge/host_os.h>
21 #include <linux/mm.h>
22 #include <linux/mmzone.h>
23 #include <plat/control.h>
24
25 /* ----------------------------------- DSP/BIOS Bridge */
26 #include <dspbridge/std.h>
27 #include <dspbridge/dbdefs.h>
28
29 /* ----------------------------------- Trace & Debug */
30 #include <dspbridge/dbc.h>
31
32 /* ----------------------------------- OS Adaptation Layer */
33 #include <dspbridge/cfg.h>
34 #include <dspbridge/drv.h>
35 #include <dspbridge/sync.h>
36
37 /* ------------------------------------ Hardware Abstraction Layer */
38 #include <hw_defs.h>
39 #include <hw_mmu.h>
40
41 /* ----------------------------------- Link Driver */
42 #include <dspbridge/dspdefs.h>
43 #include <dspbridge/dspchnl.h>
44 #include <dspbridge/dspdeh.h>
45 #include <dspbridge/dspio.h>
46 #include <dspbridge/dspmsg.h>
47 #include <dspbridge/pwr.h>
48 #include <dspbridge/io_sm.h>
49
50 /* ----------------------------------- Platform Manager */
51 #include <dspbridge/dev.h>
52 #include <dspbridge/dspapi.h>
53 #include <dspbridge/dmm.h>
54 #include <dspbridge/wdt.h>
55
56 /* ----------------------------------- Local */
57 #include "_tiomap.h"
58 #include "_tiomap_pwr.h"
59 #include "tiomap_io.h"
60
61 /* Offset in shared mem to write to in order to synchronize start with DSP */
62 #define SHMSYNCOFFSET 4 /* GPP byte offset */
63
64 #define BUFFERSIZE 1024
65
66 #define TIHELEN_ACKTIMEOUT 10000
67
68 #define MMU_SECTION_ADDR_MASK 0xFFF00000
69 #define MMU_SSECTION_ADDR_MASK 0xFF000000
70 #define MMU_LARGE_PAGE_MASK 0xFFFF0000
71 #define MMU_SMALL_PAGE_MASK 0xFFFFF000
72 #define OMAP3_IVA2_BOOTADDR_MASK 0xFFFFFC00
73 #define PAGES_II_LVL_TABLE 512
74 #define PHYS_TO_PAGE(phys) pfn_to_page((phys) >> PAGE_SHIFT)
75
76 #define MMU_GFLUSH 0x60
77
78 /* Forward Declarations: */
79 static int bridge_brd_monitor(struct bridge_dev_context *dev_context);
80 static int bridge_brd_read(struct bridge_dev_context *dev_context,
81 OUT u8 *pbHostBuf,
82 u32 dwDSPAddr, u32 ul_num_bytes,
83 u32 ulMemType);
84 static int bridge_brd_start(struct bridge_dev_context *dev_context,
85 u32 dwDSPAddr);
86 static int bridge_brd_status(struct bridge_dev_context *dev_context,
87 int *pdwState);
88 static int bridge_brd_stop(struct bridge_dev_context *dev_context);
89 static int bridge_brd_write(struct bridge_dev_context *dev_context,
90 IN u8 *pbHostBuf,
91 u32 dwDSPAddr, u32 ul_num_bytes,
92 u32 ulMemType);
93 static int bridge_brd_set_state(struct bridge_dev_context *hDevContext,
94 u32 ulBrdState);
95 static int bridge_brd_mem_copy(struct bridge_dev_context *hDevContext,
96 u32 ulDspDestAddr, u32 ulDspSrcAddr,
97 u32 ul_num_bytes, u32 ulMemType);
98 static int bridge_brd_mem_write(struct bridge_dev_context *dev_context,
99 IN u8 *pbHostBuf, u32 dwDSPAddr,
100 u32 ul_num_bytes, u32 ulMemType);
101 static int bridge_brd_mem_map(struct bridge_dev_context *hDevContext,
102 u32 ul_mpu_addr, u32 ulVirtAddr,
103 u32 ul_num_bytes, u32 ul_map_attr,
104 struct page **mapped_pages);
105 static int bridge_brd_mem_un_map(struct bridge_dev_context *hDevContext,
106 u32 ulVirtAddr, u32 ul_num_bytes);
107 static int bridge_dev_create(OUT struct bridge_dev_context
108 **ppDevContext,
109 struct dev_object *hdev_obj,
110 IN struct cfg_hostres *pConfig);
111 static int bridge_dev_ctrl(struct bridge_dev_context *dev_context,
112 u32 dw_cmd, IN OUT void *pargs);
113 static int bridge_dev_destroy(struct bridge_dev_context *dev_context);
114 static u32 user_va2_pa(struct mm_struct *mm, u32 address);
115 static int pte_update(struct bridge_dev_context *hDevContext, u32 pa,
116 u32 va, u32 size,
117 struct hw_mmu_map_attrs_t *map_attrs);
118 static int pte_set(struct pg_table_attrs *pt, u32 pa, u32 va,
119 u32 size, struct hw_mmu_map_attrs_t *attrs);
120 static int mem_map_vmalloc(struct bridge_dev_context *hDevContext,
121 u32 ul_mpu_addr, u32 ulVirtAddr,
122 u32 ul_num_bytes,
123 struct hw_mmu_map_attrs_t *hw_attrs);
124
125 bool wait_for_start(struct bridge_dev_context *dev_context, u32 dw_sync_addr);
126
127 /* ----------------------------------- Globals */
128
129 /* Attributes of L2 page tables for DSP MMU */
130 struct page_info {
131 u32 num_entries; /* Number of valid PTEs in the L2 PT */
132 };
133
134 /* Attributes used to manage the DSP MMU page tables */
135 struct pg_table_attrs {
136 spinlock_t pg_lock; /* Critical section object handle */
137
138 u32 l1_base_pa; /* Physical address of the L1 PT */
139 u32 l1_base_va; /* Virtual address of the L1 PT */
140 u32 l1_size; /* Size of the L1 PT */
141 u32 l1_tbl_alloc_pa;
142 /* Physical address of Allocated mem for L1 table. May not be aligned */
143 u32 l1_tbl_alloc_va;
144 /* Virtual address of Allocated mem for L1 table. May not be aligned */
145 u32 l1_tbl_alloc_sz;
146 /* Size of consistent memory allocated for L1 table.
147 * May not be aligned */
148
149 u32 l2_base_pa; /* Physical address of the L2 PT */
150 u32 l2_base_va; /* Virtual address of the L2 PT */
151 u32 l2_size; /* Size of the L2 PT */
152 u32 l2_tbl_alloc_pa;
153 /* Physical address of Allocated mem for L2 table. May not be aligned */
154 u32 l2_tbl_alloc_va;
155 /* Virtual address of Allocated mem for L2 table. May not be aligned */
156 u32 l2_tbl_alloc_sz;
157 /* Size of consistent memory allocated for L2 table.
158 * May not be aligned */
159
160 u32 l2_num_pages; /* Number of allocated L2 PT */
161 /* Array [l2_num_pages] of L2 PT info structs */
162 struct page_info *pg_info;
163 };
164
165 /*
166 * This Bridge driver's function interface table.
167 */
168 static struct bridge_drv_interface drv_interface_fxns = {
169 /* Bridge API ver. for which this bridge driver is built. */
170 BRD_API_MAJOR_VERSION,
171 BRD_API_MINOR_VERSION,
172 bridge_dev_create,
173 bridge_dev_destroy,
174 bridge_dev_ctrl,
175 bridge_brd_monitor,
176 bridge_brd_start,
177 bridge_brd_stop,
178 bridge_brd_status,
179 bridge_brd_read,
180 bridge_brd_write,
181 bridge_brd_set_state,
182 bridge_brd_mem_copy,
183 bridge_brd_mem_write,
184 bridge_brd_mem_map,
185 bridge_brd_mem_un_map,
186 /* The following CHNL functions are provided by chnl_io.lib: */
187 bridge_chnl_create,
188 bridge_chnl_destroy,
189 bridge_chnl_open,
190 bridge_chnl_close,
191 bridge_chnl_add_io_req,
192 bridge_chnl_get_ioc,
193 bridge_chnl_cancel_io,
194 bridge_chnl_flush_io,
195 bridge_chnl_get_info,
196 bridge_chnl_get_mgr_info,
197 bridge_chnl_idle,
198 bridge_chnl_register_notify,
199 /* The following DEH functions are provided by tihelen_ue_deh.c */
200 bridge_deh_create,
201 bridge_deh_destroy,
202 bridge_deh_notify,
203 bridge_deh_register_notify,
204 bridge_deh_get_info,
205 /* The following IO functions are provided by chnl_io.lib: */
206 bridge_io_create,
207 bridge_io_destroy,
208 bridge_io_on_loaded,
209 bridge_io_get_proc_load,
210 /* The following msg_ctrl functions are provided by chnl_io.lib: */
211 bridge_msg_create,
212 bridge_msg_create_queue,
213 bridge_msg_delete,
214 bridge_msg_delete_queue,
215 bridge_msg_get,
216 bridge_msg_put,
217 bridge_msg_register_notify,
218 bridge_msg_set_queue_id,
219 };
220
221 static inline void tlb_flush_all(const void __iomem *base)
222 {
223 __raw_writeb(__raw_readb(base + MMU_GFLUSH) | 1, base + MMU_GFLUSH);
224 }
225
226 static inline void flush_all(struct bridge_dev_context *dev_context)
227 {
228 if (dev_context->dw_brd_state == BRD_DSP_HIBERNATION ||
229 dev_context->dw_brd_state == BRD_HIBERNATION)
230 wake_dsp(dev_context, NULL);
231
232 tlb_flush_all(dev_context->dw_dsp_mmu_base);
233 }
234
235 static void bad_page_dump(u32 pa, struct page *pg)
236 {
237 pr_emerg("DSPBRIDGE: MAP function: COUNT 0 FOR PA 0x%x\n", pa);
238 pr_emerg("Bad page state in process '%s'\n"
239 "page:%p flags:0x%0*lx mapping:%p mapcount:%d count:%d\n"
240 "Backtrace:\n",
241 current->comm, pg, (int)(2 * sizeof(unsigned long)),
242 (unsigned long)pg->flags, pg->mapping,
243 page_mapcount(pg), page_count(pg));
244 dump_stack();
245 }
246
247 /*
248 * ======== bridge_drv_entry ========
249 * purpose:
250 * Bridge Driver entry point.
251 */
252 void bridge_drv_entry(OUT struct bridge_drv_interface **ppDrvInterface,
253 IN CONST char *driver_file_name)
254 {
255
256 DBC_REQUIRE(driver_file_name != NULL);
257
258 io_sm_init(); /* Initialization of io_sm module */
259
260 if (strcmp(driver_file_name, "UMA") == 0)
261 *ppDrvInterface = &drv_interface_fxns;
262 else
263 dev_dbg(bridge, "%s Unknown Bridge file name", __func__);
264
265 }
266
267 /*
268 * ======== bridge_brd_monitor ========
269 * purpose:
270 * This bridge_brd_monitor puts DSP into a Loadable state.
271 * i.e Application can load and start the device.
272 *
273 * Preconditions:
274 * Device in 'OFF' state.
275 */
276 static int bridge_brd_monitor(struct bridge_dev_context *hDevContext)
277 {
278 int status = 0;
279 struct bridge_dev_context *dev_context = hDevContext;
280 u32 temp;
281 struct dspbridge_platform_data *pdata =
282 omap_dspbridge_dev->dev.platform_data;
283
284 temp = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
285 OMAP_POWERSTATEST_MASK;
286 if (!(temp & 0x02)) {
287 /* IVA2 is not in ON state */
288 /* Read and set PM_PWSTCTRL_IVA2 to ON */
289 (*pdata->dsp_prm_rmw_bits)(OMAP_POWERSTATEST_MASK,
290 PWRDM_POWER_ON, OMAP3430_IVA2_MOD, OMAP2_PM_PWSTCTRL);
291 /* Set the SW supervised state transition */
292 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP,
293 OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
294
295 /* Wait until the state has moved to ON */
296 while ((*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
297 OMAP_INTRANSITION_MASK)
298 ;
299 /* Disable Automatic transition */
300 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_DISABLE_AUTO,
301 OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
302 }
303 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
304 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
305 dsp_clk_enable(DSP_CLK_IVA2);
306
307 if (DSP_SUCCEEDED(status)) {
308 /* set the device state to IDLE */
309 dev_context->dw_brd_state = BRD_IDLE;
310 }
311 return status;
312 }
313
314 /*
315 * ======== bridge_brd_read ========
316 * purpose:
317 * Reads buffers for DSP memory.
318 */
319 static int bridge_brd_read(struct bridge_dev_context *hDevContext,
320 OUT u8 *pbHostBuf, u32 dwDSPAddr,
321 u32 ul_num_bytes, u32 ulMemType)
322 {
323 int status = 0;
324 struct bridge_dev_context *dev_context = hDevContext;
325 u32 offset;
326 u32 dsp_base_addr = hDevContext->dw_dsp_base_addr;
327
328 if (dwDSPAddr < dev_context->dw_dsp_start_add) {
329 status = -EPERM;
330 return status;
331 }
332 /* change here to account for the 3 bands of the DSP internal memory */
333 if ((dwDSPAddr - dev_context->dw_dsp_start_add) <
334 dev_context->dw_internal_size) {
335 offset = dwDSPAddr - dev_context->dw_dsp_start_add;
336 } else {
337 status = read_ext_dsp_data(dev_context, pbHostBuf, dwDSPAddr,
338 ul_num_bytes, ulMemType);
339 return status;
340 }
341 /* copy the data from DSP memory, */
342 memcpy(pbHostBuf, (void *)(dsp_base_addr + offset), ul_num_bytes);
343 return status;
344 }
345
346 /*
347 * ======== bridge_brd_set_state ========
348 * purpose:
349 * This routine updates the Board status.
350 */
351 static int bridge_brd_set_state(struct bridge_dev_context *hDevContext,
352 u32 ulBrdState)
353 {
354 int status = 0;
355 struct bridge_dev_context *dev_context = hDevContext;
356
357 dev_context->dw_brd_state = ulBrdState;
358 return status;
359 }
360
361 /*
362 * ======== bridge_brd_start ========
363 * purpose:
364 * Initializes DSP MMU and Starts DSP.
365 *
366 * Preconditions:
367 * a) DSP domain is 'ACTIVE'.
368 * b) DSP_RST1 is asserted.
369 * b) DSP_RST2 is released.
370 */
371 static int bridge_brd_start(struct bridge_dev_context *hDevContext,
372 u32 dwDSPAddr)
373 {
374 int status = 0;
375 struct bridge_dev_context *dev_context = hDevContext;
376 u32 dw_sync_addr = 0;
377 u32 ul_shm_base; /* Gpp Phys SM base addr(byte) */
378 u32 ul_shm_base_virt; /* Dsp Virt SM base addr */
379 u32 ul_tlb_base_virt; /* Base of MMU TLB entry */
380 /* Offset of shm_base_virt from tlb_base_virt */
381 u32 ul_shm_offset_virt;
382 s32 entry_ndx;
383 s32 itmp_entry_ndx = 0; /* DSP-MMU TLB entry base address */
384 struct cfg_hostres *resources = NULL;
385 u32 temp;
386 u32 ul_dsp_clk_rate;
387 u32 ul_dsp_clk_addr;
388 u32 ul_bios_gp_timer;
389 u32 clk_cmd;
390 struct io_mgr *hio_mgr;
391 u32 ul_load_monitor_timer;
392 struct dspbridge_platform_data *pdata =
393 omap_dspbridge_dev->dev.platform_data;
394
395 /* The device context contains all the mmu setup info from when the
396 * last dsp base image was loaded. The first entry is always
397 * SHMMEM base. */
398 /* Get SHM_BEG - convert to byte address */
399 (void)dev_get_symbol(dev_context->hdev_obj, SHMBASENAME,
400 &ul_shm_base_virt);
401 ul_shm_base_virt *= DSPWORDSIZE;
402 DBC_ASSERT(ul_shm_base_virt != 0);
403 /* DSP Virtual address */
404 ul_tlb_base_virt = dev_context->atlb_entry[0].ul_dsp_va;
405 DBC_ASSERT(ul_tlb_base_virt <= ul_shm_base_virt);
406 ul_shm_offset_virt =
407 ul_shm_base_virt - (ul_tlb_base_virt * DSPWORDSIZE);
408 /* Kernel logical address */
409 ul_shm_base = dev_context->atlb_entry[0].ul_gpp_va + ul_shm_offset_virt;
410
411 DBC_ASSERT(ul_shm_base != 0);
412 /* 2nd wd is used as sync field */
413 dw_sync_addr = ul_shm_base + SHMSYNCOFFSET;
414 /* Write a signature into the shm base + offset; this will
415 * get cleared when the DSP program starts. */
416 if ((ul_shm_base_virt == 0) || (ul_shm_base == 0)) {
417 pr_err("%s: Illegal SM base\n", __func__);
418 status = -EPERM;
419 } else
420 *((volatile u32 *)dw_sync_addr) = 0xffffffff;
421
422 if (DSP_SUCCEEDED(status)) {
423 resources = dev_context->resources;
424 if (!resources)
425 status = -EPERM;
426
427 /* Assert RST1 i.e only the RST only for DSP megacell */
428 if (DSP_SUCCEEDED(status)) {
429 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK,
430 OMAP3430_RST1_IVA2_MASK, OMAP3430_IVA2_MOD,
431 OMAP2_RM_RSTCTRL);
432 /* Mask address with 1K for compatibility */
433 __raw_writel(dwDSPAddr & OMAP3_IVA2_BOOTADDR_MASK,
434 OMAP343X_CTRL_REGADDR(
435 OMAP343X_CONTROL_IVA2_BOOTADDR));
436 /*
437 * Set bootmode to self loop if dsp_debug flag is true
438 */
439 __raw_writel((dsp_debug) ? OMAP3_IVA2_BOOTMOD_IDLE : 0,
440 OMAP343X_CTRL_REGADDR(
441 OMAP343X_CONTROL_IVA2_BOOTMOD));
442 }
443 }
444 if (DSP_SUCCEEDED(status)) {
445 /* Reset and Unreset the RST2, so that BOOTADDR is copied to
446 * IVA2 SYSC register */
447 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK,
448 OMAP3430_RST2_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
449 udelay(100);
450 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
451 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
452 udelay(100);
453
454 /* Disbale the DSP MMU */
455 hw_mmu_disable(resources->dw_dmmu_base);
456 /* Disable TWL */
457 hw_mmu_twl_disable(resources->dw_dmmu_base);
458
459 /* Only make TLB entry if both addresses are non-zero */
460 for (entry_ndx = 0; entry_ndx < BRDIOCTL_NUMOFMMUTLB;
461 entry_ndx++) {
462 struct bridge_ioctl_extproc *e = &dev_context->atlb_entry[entry_ndx];
463 struct hw_mmu_map_attrs_t map_attrs = {
464 .endianism = e->endianism,
465 .element_size = e->elem_size,
466 .mixed_size = e->mixed_mode,
467 };
468
469 if (!e->ul_gpp_pa || !e->ul_dsp_va)
470 continue;
471
472 dev_dbg(bridge,
473 "MMU %d, pa: 0x%x, va: 0x%x, size: 0x%x",
474 itmp_entry_ndx,
475 e->ul_gpp_pa,
476 e->ul_dsp_va,
477 e->ul_size);
478
479 hw_mmu_tlb_add(dev_context->dw_dsp_mmu_base,
480 e->ul_gpp_pa,
481 e->ul_dsp_va,
482 e->ul_size,
483 itmp_entry_ndx,
484 &map_attrs, 1, 1);
485
486 itmp_entry_ndx++;
487 }
488 }
489
490 /* Lock the above TLB entries and get the BIOS and load monitor timer
491 * information */
492 if (DSP_SUCCEEDED(status)) {
493 hw_mmu_num_locked_set(resources->dw_dmmu_base, itmp_entry_ndx);
494 hw_mmu_victim_num_set(resources->dw_dmmu_base, itmp_entry_ndx);
495 hw_mmu_ttb_set(resources->dw_dmmu_base,
496 dev_context->pt_attrs->l1_base_pa);
497 hw_mmu_twl_enable(resources->dw_dmmu_base);
498 /* Enable the SmartIdle and AutoIdle bit for MMU_SYSCONFIG */
499
500 temp = __raw_readl((resources->dw_dmmu_base) + 0x10);
501 temp = (temp & 0xFFFFFFEF) | 0x11;
502 __raw_writel(temp, (resources->dw_dmmu_base) + 0x10);
503
504 /* Let the DSP MMU run */
505 hw_mmu_enable(resources->dw_dmmu_base);
506
507 /* Enable the BIOS clock */
508 (void)dev_get_symbol(dev_context->hdev_obj,
509 BRIDGEINIT_BIOSGPTIMER, &ul_bios_gp_timer);
510 (void)dev_get_symbol(dev_context->hdev_obj,
511 BRIDGEINIT_LOADMON_GPTIMER,
512 &ul_load_monitor_timer);
513 }
514
515 if (DSP_SUCCEEDED(status)) {
516 if (ul_load_monitor_timer != 0xFFFF) {
517 clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) |
518 ul_load_monitor_timer;
519 dsp_peripheral_clk_ctrl(dev_context, &clk_cmd);
520 } else {
521 dev_dbg(bridge, "Not able to get the symbol for Load "
522 "Monitor Timer\n");
523 }
524 }
525
526 if (DSP_SUCCEEDED(status)) {
527 if (ul_bios_gp_timer != 0xFFFF) {
528 clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) |
529 ul_bios_gp_timer;
530 dsp_peripheral_clk_ctrl(dev_context, &clk_cmd);
531 } else {
532 dev_dbg(bridge,
533 "Not able to get the symbol for BIOS Timer\n");
534 }
535 }
536
537 if (DSP_SUCCEEDED(status)) {
538 /* Set the DSP clock rate */
539 (void)dev_get_symbol(dev_context->hdev_obj,
540 "_BRIDGEINIT_DSP_FREQ", &ul_dsp_clk_addr);
541 /*Set Autoidle Mode for IVA2 PLL */
542 (*pdata->dsp_cm_write)(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
543 OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL);
544
545 if ((unsigned int *)ul_dsp_clk_addr != NULL) {
546 /* Get the clock rate */
547 ul_dsp_clk_rate = dsp_clk_get_iva2_rate();
548 dev_dbg(bridge, "%s: DSP clock rate (KHZ): 0x%x \n",
549 __func__, ul_dsp_clk_rate);
550 (void)bridge_brd_write(dev_context,
551 (u8 *) &ul_dsp_clk_rate,
552 ul_dsp_clk_addr, sizeof(u32), 0);
553 }
554 /*
555 * Enable Mailbox events and also drain any pending
556 * stale messages.
557 */
558 dev_context->mbox = omap_mbox_get("dsp");
559 if (IS_ERR(dev_context->mbox)) {
560 dev_context->mbox = NULL;
561 pr_err("%s: Failed to get dsp mailbox handle\n",
562 __func__);
563 status = -EPERM;
564 }
565
566 }
567 if (DSP_SUCCEEDED(status)) {
568 dev_context->mbox->rxq->callback = (int (*)(void *))io_mbox_msg;
569
570 /*PM_IVA2GRPSEL_PER = 0xC0;*/
571 temp = (u32) *((reg_uword32 *)
572 ((u32) (resources->dw_per_pm_base) + 0xA8));
573 temp = (temp & 0xFFFFFF30) | 0xC0;
574 *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) =
575 (u32) temp;
576
577 /*PM_MPUGRPSEL_PER &= 0xFFFFFF3F; */
578 temp = (u32) *((reg_uword32 *)
579 ((u32) (resources->dw_per_pm_base) + 0xA4));
580 temp = (temp & 0xFFFFFF3F);
581 *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) =
582 (u32) temp;
583 /*CM_SLEEPDEP_PER |= 0x04; */
584 temp = (u32) *((reg_uword32 *)
585 ((u32) (resources->dw_per_base) + 0x44));
586 temp = (temp & 0xFFFFFFFB) | 0x04;
587 *((reg_uword32 *) ((u32) (resources->dw_per_base) + 0x44)) =
588 (u32) temp;
589
590 /*CM_CLKSTCTRL_IVA2 = 0x00000003 -To Allow automatic transitions */
591 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_ENABLE_AUTO,
592 OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
593
594 /* Let DSP go */
595 dev_dbg(bridge, "%s Unreset\n", __func__);
596 /* Enable DSP MMU Interrupts */
597 hw_mmu_event_enable(resources->dw_dmmu_base,
598 HW_MMU_ALL_INTERRUPTS);
599 /* release the RST1, DSP starts executing now .. */
600 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK, 0,
601 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
602
603 dev_dbg(bridge, "Waiting for Sync @ 0x%x\n", dw_sync_addr);
604 dev_dbg(bridge, "DSP c_int00 Address = 0x%x\n", dwDSPAddr);
605 if (dsp_debug)
606 while (*((volatile u16 *)dw_sync_addr))
607 ;;
608
609 /* Wait for DSP to clear word in shared memory */
610 /* Read the Location */
611 if (!wait_for_start(dev_context, dw_sync_addr))
612 status = -ETIMEDOUT;
613
614 /* Start wdt */
615 dsp_wdt_sm_set((void *)ul_shm_base);
616 dsp_wdt_enable(true);
617
618 status = dev_get_io_mgr(dev_context->hdev_obj, &hio_mgr);
619 if (hio_mgr) {
620 io_sh_msetting(hio_mgr, SHM_OPPINFO, NULL);
621 /* Write the synchronization bit to indicate the
622 * completion of OPP table update to DSP
623 */
624 *((volatile u32 *)dw_sync_addr) = 0XCAFECAFE;
625
626 /* update board state */
627 dev_context->dw_brd_state = BRD_RUNNING;
628 /* (void)chnlsm_enable_interrupt(dev_context); */
629 } else {
630 dev_context->dw_brd_state = BRD_UNKNOWN;
631 }
632 }
633 return status;
634 }
635
636 /*
637 * ======== bridge_brd_stop ========
638 * purpose:
639 * Puts DSP in self loop.
640 *
641 * Preconditions :
642 * a) None
643 */
644 static int bridge_brd_stop(struct bridge_dev_context *hDevContext)
645 {
646 int status = 0;
647 struct bridge_dev_context *dev_context = hDevContext;
648 struct pg_table_attrs *pt_attrs;
649 u32 dsp_pwr_state;
650 int clk_status;
651 struct dspbridge_platform_data *pdata =
652 omap_dspbridge_dev->dev.platform_data;
653
654 if (dev_context->dw_brd_state == BRD_STOPPED)
655 return status;
656
657 /* as per TRM, it is advised to first drive the IVA2 to 'Standby' mode,
658 * before turning off the clocks.. This is to ensure that there are no
659 * pending L3 or other transactons from IVA2 */
660 dsp_pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
661 OMAP_POWERSTATEST_MASK;
662 if (dsp_pwr_state != PWRDM_POWER_OFF) {
663 sm_interrupt_dsp(dev_context, MBX_PM_DSPIDLE);
664 mdelay(10);
665
666 clk_status = dsp_clk_disable(DSP_CLK_IVA2);
667
668 /* IVA2 is not in OFF state */
669 /* Set PM_PWSTCTRL_IVA2 to OFF */
670 (*pdata->dsp_prm_rmw_bits)(OMAP_POWERSTATEST_MASK,
671 PWRDM_POWER_OFF, OMAP3430_IVA2_MOD, OMAP2_PM_PWSTCTRL);
672 /* Set the SW supervised state transition for Sleep */
673 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_FORCE_SLEEP,
674 OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
675 } else {
676 clk_status = dsp_clk_disable(DSP_CLK_IVA2);
677 }
678 udelay(10);
679 /* Release the Ext Base virtual Address as the next DSP Program
680 * may have a different load address */
681 if (dev_context->dw_dsp_ext_base_addr)
682 dev_context->dw_dsp_ext_base_addr = 0;
683
684 dev_context->dw_brd_state = BRD_STOPPED; /* update board state */
685
686 dsp_wdt_enable(false);
687
688 /* This is a good place to clear the MMU page tables as well */
689 if (dev_context->pt_attrs) {
690 pt_attrs = dev_context->pt_attrs;
691 memset((u8 *) pt_attrs->l1_base_va, 0x00, pt_attrs->l1_size);
692 memset((u8 *) pt_attrs->l2_base_va, 0x00, pt_attrs->l2_size);
693 memset((u8 *) pt_attrs->pg_info, 0x00,
694 (pt_attrs->l2_num_pages * sizeof(struct page_info)));
695 }
696 /* Disable the mailbox interrupts */
697 if (dev_context->mbox) {
698 omap_mbox_disable_irq(dev_context->mbox, IRQ_RX);
699 omap_mbox_put(dev_context->mbox);
700 dev_context->mbox = NULL;
701 }
702 /* Reset IVA2 clocks*/
703 (*pdata->dsp_prm_write)(OMAP3430_RST1_IVA2_MASK | OMAP3430_RST2_IVA2_MASK |
704 OMAP3430_RST3_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
705
706 return status;
707 }
708
709 /*
710 * ======== bridge_brd_delete ========
711 * purpose:
712 * Puts DSP in Low power mode
713 *
714 * Preconditions :
715 * a) None
716 */
717 static int bridge_brd_delete(struct bridge_dev_context *hDevContext)
718 {
719 int status = 0;
720 struct bridge_dev_context *dev_context = hDevContext;
721 struct pg_table_attrs *pt_attrs;
722 int clk_status;
723 struct dspbridge_platform_data *pdata =
724 omap_dspbridge_dev->dev.platform_data;
725
726 if (dev_context->dw_brd_state == BRD_STOPPED)
727 return status;
728
729 /* as per TRM, it is advised to first drive
730 * the IVA2 to 'Standby' mode, before turning off the clocks.. This is
731 * to ensure that there are no pending L3 or other transactons from
732 * IVA2 */
733 status = sleep_dsp(dev_context, PWR_EMERGENCYDEEPSLEEP, NULL);
734 clk_status = dsp_clk_disable(DSP_CLK_IVA2);
735
736 /* Release the Ext Base virtual Address as the next DSP Program
737 * may have a different load address */
738 if (dev_context->dw_dsp_ext_base_addr)
739 dev_context->dw_dsp_ext_base_addr = 0;
740
741 dev_context->dw_brd_state = BRD_STOPPED; /* update board state */
742
743 /* This is a good place to clear the MMU page tables as well */
744 if (dev_context->pt_attrs) {
745 pt_attrs = dev_context->pt_attrs;
746 memset((u8 *) pt_attrs->l1_base_va, 0x00, pt_attrs->l1_size);
747 memset((u8 *) pt_attrs->l2_base_va, 0x00, pt_attrs->l2_size);
748 memset((u8 *) pt_attrs->pg_info, 0x00,
749 (pt_attrs->l2_num_pages * sizeof(struct page_info)));
750 }
751 /* Disable the mail box interrupts */
752 if (dev_context->mbox) {
753 omap_mbox_disable_irq(dev_context->mbox, IRQ_RX);
754 omap_mbox_put(dev_context->mbox);
755 dev_context->mbox = NULL;
756 }
757 /* Reset IVA2 clocks*/
758 (*pdata->dsp_prm_write)(OMAP3430_RST1_IVA2_MASK | OMAP3430_RST2_IVA2_MASK |
759 OMAP3430_RST3_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
760
761 return status;
762 }
763
764 /*
765 * ======== bridge_brd_status ========
766 * Returns the board status.
767 */
768 static int bridge_brd_status(struct bridge_dev_context *hDevContext,
769 int *pdwState)
770 {
771 struct bridge_dev_context *dev_context = hDevContext;
772 *pdwState = dev_context->dw_brd_state;
773 return 0;
774 }
775
776 /*
777 * ======== bridge_brd_write ========
778 * Copies the buffers to DSP internal or external memory.
779 */
780 static int bridge_brd_write(struct bridge_dev_context *hDevContext,
781 IN u8 *pbHostBuf, u32 dwDSPAddr,
782 u32 ul_num_bytes, u32 ulMemType)
783 {
784 int status = 0;
785 struct bridge_dev_context *dev_context = hDevContext;
786
787 if (dwDSPAddr < dev_context->dw_dsp_start_add) {
788 status = -EPERM;
789 return status;
790 }
791 if ((dwDSPAddr - dev_context->dw_dsp_start_add) <
792 dev_context->dw_internal_size) {
793 status = write_dsp_data(hDevContext, pbHostBuf, dwDSPAddr,
794 ul_num_bytes, ulMemType);
795 } else {
796 status = write_ext_dsp_data(dev_context, pbHostBuf, dwDSPAddr,
797 ul_num_bytes, ulMemType, false);
798 }
799
800 return status;
801 }
802
803 /*
804 * ======== bridge_dev_create ========
805 * Creates a driver object. Puts DSP in self loop.
806 */
807 static int bridge_dev_create(OUT struct bridge_dev_context
808 **ppDevContext,
809 struct dev_object *hdev_obj,
810 IN struct cfg_hostres *pConfig)
811 {
812 int status = 0;
813 struct bridge_dev_context *dev_context = NULL;
814 s32 entry_ndx;
815 struct cfg_hostres *resources = pConfig;
816 struct pg_table_attrs *pt_attrs;
817 u32 pg_tbl_pa;
818 u32 pg_tbl_va;
819 u32 align_size;
820 struct drv_data *drv_datap = dev_get_drvdata(bridge);
821
822 /* Allocate and initialize a data structure to contain the bridge driver
823 * state, which becomes the context for later calls into this driver */
824 dev_context = kzalloc(sizeof(struct bridge_dev_context), GFP_KERNEL);
825 if (!dev_context) {
826 status = -ENOMEM;
827 goto func_end;
828 }
829
830 dev_context->dw_dsp_start_add = (u32) OMAP_GEM_BASE;
831 dev_context->dw_self_loop = (u32) NULL;
832 dev_context->dsp_per_clks = 0;
833 dev_context->dw_internal_size = OMAP_DSP_SIZE;
834 /* Clear dev context MMU table entries.
835 * These get set on bridge_io_on_loaded() call after program loaded. */
836 for (entry_ndx = 0; entry_ndx < BRDIOCTL_NUMOFMMUTLB; entry_ndx++) {
837 dev_context->atlb_entry[entry_ndx].ul_gpp_pa =
838 dev_context->atlb_entry[entry_ndx].ul_dsp_va = 0;
839 }
840 dev_context->dw_dsp_base_addr = (u32) MEM_LINEAR_ADDRESS((void *)
841 (pConfig->
842 dw_mem_base
843 [3]),
844 pConfig->
845 dw_mem_length
846 [3]);
847 if (!dev_context->dw_dsp_base_addr)
848 status = -EPERM;
849
850 pt_attrs = kzalloc(sizeof(struct pg_table_attrs), GFP_KERNEL);
851 if (pt_attrs != NULL) {
852 /* Assuming that we use only DSP's memory map
853 * until 0x4000:0000 , we would need only 1024
854 * L1 enties i.e L1 size = 4K */
855 pt_attrs->l1_size = 0x1000;
856 align_size = pt_attrs->l1_size;
857 /* Align sizes are expected to be power of 2 */
858 /* we like to get aligned on L1 table size */
859 pg_tbl_va = (u32) mem_alloc_phys_mem(pt_attrs->l1_size,
860 align_size, &pg_tbl_pa);
861
862 /* Check if the PA is aligned for us */
863 if ((pg_tbl_pa) & (align_size - 1)) {
864 /* PA not aligned to page table size ,
865 * try with more allocation and align */
866 mem_free_phys_mem((void *)pg_tbl_va, pg_tbl_pa,
867 pt_attrs->l1_size);
868 /* we like to get aligned on L1 table size */
869 pg_tbl_va =
870 (u32) mem_alloc_phys_mem((pt_attrs->l1_size) * 2,
871 align_size, &pg_tbl_pa);
872 /* We should be able to get aligned table now */
873 pt_attrs->l1_tbl_alloc_pa = pg_tbl_pa;
874 pt_attrs->l1_tbl_alloc_va = pg_tbl_va;
875 pt_attrs->l1_tbl_alloc_sz = pt_attrs->l1_size * 2;
876 /* Align the PA to the next 'align' boundary */
877 pt_attrs->l1_base_pa =
878 ((pg_tbl_pa) +
879 (align_size - 1)) & (~(align_size - 1));
880 pt_attrs->l1_base_va =
881 pg_tbl_va + (pt_attrs->l1_base_pa - pg_tbl_pa);
882 } else {
883 /* We got aligned PA, cool */
884 pt_attrs->l1_tbl_alloc_pa = pg_tbl_pa;
885 pt_attrs->l1_tbl_alloc_va = pg_tbl_va;
886 pt_attrs->l1_tbl_alloc_sz = pt_attrs->l1_size;
887 pt_attrs->l1_base_pa = pg_tbl_pa;
888 pt_attrs->l1_base_va = pg_tbl_va;
889 }
890 if (pt_attrs->l1_base_va)
891 memset((u8 *) pt_attrs->l1_base_va, 0x00,
892 pt_attrs->l1_size);
893
894 /* number of L2 page tables = DMM pool used + SHMMEM +EXTMEM +
895 * L4 pages */
896 pt_attrs->l2_num_pages = ((DMMPOOLSIZE >> 20) + 6);
897 pt_attrs->l2_size = HW_MMU_COARSE_PAGE_SIZE *
898 pt_attrs->l2_num_pages;
899 align_size = 4; /* Make it u32 aligned */
900 /* we like to get aligned on L1 table size */
901 pg_tbl_va = (u32) mem_alloc_phys_mem(pt_attrs->l2_size,
902 align_size, &pg_tbl_pa);
903 pt_attrs->l2_tbl_alloc_pa = pg_tbl_pa;
904 pt_attrs->l2_tbl_alloc_va = pg_tbl_va;
905 pt_attrs->l2_tbl_alloc_sz = pt_attrs->l2_size;
906 pt_attrs->l2_base_pa = pg_tbl_pa;
907 pt_attrs->l2_base_va = pg_tbl_va;
908
909 if (pt_attrs->l2_base_va)
910 memset((u8 *) pt_attrs->l2_base_va, 0x00,
911 pt_attrs->l2_size);
912
913 pt_attrs->pg_info = kzalloc(pt_attrs->l2_num_pages *
914 sizeof(struct page_info), GFP_KERNEL);
915 dev_dbg(bridge,
916 "L1 pa %x, va %x, size %x\n L2 pa %x, va "
917 "%x, size %x\n", pt_attrs->l1_base_pa,
918 pt_attrs->l1_base_va, pt_attrs->l1_size,
919 pt_attrs->l2_base_pa, pt_attrs->l2_base_va,
920 pt_attrs->l2_size);
921 dev_dbg(bridge, "pt_attrs %p L2 NumPages %x pg_info %p\n",
922 pt_attrs, pt_attrs->l2_num_pages, pt_attrs->pg_info);
923 }
924 if ((pt_attrs != NULL) && (pt_attrs->l1_base_va != 0) &&
925 (pt_attrs->l2_base_va != 0) && (pt_attrs->pg_info != NULL))
926 dev_context->pt_attrs = pt_attrs;
927 else
928 status = -ENOMEM;
929
930 if (DSP_SUCCEEDED(status)) {
931 spin_lock_init(&pt_attrs->pg_lock);
932 dev_context->tc_word_swap_on = drv_datap->tc_wordswapon;
933
934 /* Set the Clock Divisor for the DSP module */
935 udelay(5);
936 /* MMU address is obtained from the host
937 * resources struct */
938 dev_context->dw_dsp_mmu_base = resources->dw_dmmu_base;
939 }
940 if (DSP_SUCCEEDED(status)) {
941 dev_context->hdev_obj = hdev_obj;
942 /* Store current board state. */
943 dev_context->dw_brd_state = BRD_STOPPED;
944 dev_context->resources = resources;
945 /* Return ptr to our device state to the DSP API for storage */
946 *ppDevContext = dev_context;
947 } else {
948 if (pt_attrs != NULL) {
949 kfree(pt_attrs->pg_info);
950
951 if (pt_attrs->l2_tbl_alloc_va) {
952 mem_free_phys_mem((void *)
953 pt_attrs->l2_tbl_alloc_va,
954 pt_attrs->l2_tbl_alloc_pa,
955 pt_attrs->l2_tbl_alloc_sz);
956 }
957 if (pt_attrs->l1_tbl_alloc_va) {
958 mem_free_phys_mem((void *)
959 pt_attrs->l1_tbl_alloc_va,
960 pt_attrs->l1_tbl_alloc_pa,
961 pt_attrs->l1_tbl_alloc_sz);
962 }
963 }
964 kfree(pt_attrs);
965 kfree(dev_context);
966 }
967 func_end:
968 return status;
969 }
970
971 /*
972 * ======== bridge_dev_ctrl ========
973 * Receives device specific commands.
974 */
975 static int bridge_dev_ctrl(struct bridge_dev_context *dev_context,
976 u32 dw_cmd, IN OUT void *pargs)
977 {
978 int status = 0;
979 struct bridge_ioctl_extproc *pa_ext_proc =
980 (struct bridge_ioctl_extproc *)pargs;
981 s32 ndx;
982
983 switch (dw_cmd) {
984 case BRDIOCTL_CHNLREAD:
985 break;
986 case BRDIOCTL_CHNLWRITE:
987 break;
988 case BRDIOCTL_SETMMUCONFIG:
989 /* store away dsp-mmu setup values for later use */
990 for (ndx = 0; ndx < BRDIOCTL_NUMOFMMUTLB; ndx++, pa_ext_proc++)
991 dev_context->atlb_entry[ndx] = *pa_ext_proc;
992 break;
993 case BRDIOCTL_DEEPSLEEP:
994 case BRDIOCTL_EMERGENCYSLEEP:
995 /* Currently only DSP Idle is supported Need to update for
996 * later releases */
997 status = sleep_dsp(dev_context, PWR_DEEPSLEEP, pargs);
998 break;
999 case BRDIOCTL_WAKEUP:
1000 status = wake_dsp(dev_context, pargs);
1001 break;
1002 case BRDIOCTL_CLK_CTRL:
1003 status = 0;
1004 /* Looking For Baseport Fix for Clocks */
1005 status = dsp_peripheral_clk_ctrl(dev_context, pargs);
1006 break;
1007 case BRDIOCTL_PWR_HIBERNATE:
1008 status = handle_hibernation_from_dsp(dev_context);
1009 break;
1010 case BRDIOCTL_PRESCALE_NOTIFY:
1011 status = pre_scale_dsp(dev_context, pargs);
1012 break;
1013 case BRDIOCTL_POSTSCALE_NOTIFY:
1014 status = post_scale_dsp(dev_context, pargs);
1015 break;
1016 case BRDIOCTL_CONSTRAINT_REQUEST:
1017 status = handle_constraints_set(dev_context, pargs);
1018 break;
1019 default:
1020 status = -EPERM;
1021 break;
1022 }
1023 return status;
1024 }
1025
1026 /*
1027 * ======== bridge_dev_destroy ========
1028 * Destroys the driver object.
1029 */
1030 static int bridge_dev_destroy(struct bridge_dev_context *hDevContext)
1031 {
1032 struct pg_table_attrs *pt_attrs;
1033 int status = 0;
1034 struct bridge_dev_context *dev_context = (struct bridge_dev_context *)
1035 hDevContext;
1036 struct cfg_hostres *host_res;
1037 u32 shm_size;
1038 struct drv_data *drv_datap = dev_get_drvdata(bridge);
1039
1040 /* It should never happen */
1041 if (!hDevContext)
1042 return -EFAULT;
1043
1044 /* first put the device to stop state */
1045 bridge_brd_delete(dev_context);
1046 if (dev_context->pt_attrs) {
1047 pt_attrs = dev_context->pt_attrs;
1048 kfree(pt_attrs->pg_info);
1049
1050 if (pt_attrs->l2_tbl_alloc_va) {
1051 mem_free_phys_mem((void *)pt_attrs->l2_tbl_alloc_va,
1052 pt_attrs->l2_tbl_alloc_pa,
1053 pt_attrs->l2_tbl_alloc_sz);
1054 }
1055 if (pt_attrs->l1_tbl_alloc_va) {
1056 mem_free_phys_mem((void *)pt_attrs->l1_tbl_alloc_va,
1057 pt_attrs->l1_tbl_alloc_pa,
1058 pt_attrs->l1_tbl_alloc_sz);
1059 }
1060 kfree(pt_attrs);
1061
1062 }
1063
1064 if (dev_context->resources) {
1065 host_res = dev_context->resources;
1066 shm_size = drv_datap->shm_size;
1067 if (shm_size >= 0x10000) {
1068 if ((host_res->dw_mem_base[1]) &&
1069 (host_res->dw_mem_phys[1])) {
1070 mem_free_phys_mem((void *)
1071 host_res->dw_mem_base
1072 [1],
1073 host_res->dw_mem_phys
1074 [1], shm_size);
1075 }
1076 } else {
1077 dev_dbg(bridge, "%s: Error getting shm size "
1078 "from registry: %x. Not calling "
1079 "mem_free_phys_mem\n", __func__,
1080 status);
1081 }
1082 host_res->dw_mem_base[1] = 0;
1083 host_res->dw_mem_phys[1] = 0;
1084
1085 if (host_res->dw_mem_base[0])
1086 iounmap((void *)host_res->dw_mem_base[0]);
1087 if (host_res->dw_mem_base[2])
1088 iounmap((void *)host_res->dw_mem_base[2]);
1089 if (host_res->dw_mem_base[3])
1090 iounmap((void *)host_res->dw_mem_base[3]);
1091 if (host_res->dw_mem_base[4])
1092 iounmap((void *)host_res->dw_mem_base[4]);
1093 if (host_res->dw_dmmu_base)
1094 iounmap(host_res->dw_dmmu_base);
1095 if (host_res->dw_per_base)
1096 iounmap(host_res->dw_per_base);
1097 if (host_res->dw_per_pm_base)
1098 iounmap((void *)host_res->dw_per_pm_base);
1099 if (host_res->dw_core_pm_base)
1100 iounmap((void *)host_res->dw_core_pm_base);
1101 if (host_res->dw_sys_ctrl_base)
1102 iounmap(host_res->dw_sys_ctrl_base);
1103
1104 host_res->dw_mem_base[0] = (u32) NULL;
1105 host_res->dw_mem_base[2] = (u32) NULL;
1106 host_res->dw_mem_base[3] = (u32) NULL;
1107 host_res->dw_mem_base[4] = (u32) NULL;
1108 host_res->dw_dmmu_base = NULL;
1109 host_res->dw_sys_ctrl_base = NULL;
1110
1111 kfree(host_res);
1112 }
1113
1114 /* Free the driver's device context: */
1115 kfree(drv_datap->base_img);
1116 kfree(drv_datap);
1117 dev_set_drvdata(bridge, NULL);
1118 kfree((void *)hDevContext);
1119 return status;
1120 }
1121
1122 static int bridge_brd_mem_copy(struct bridge_dev_context *hDevContext,
1123 u32 ulDspDestAddr, u32 ulDspSrcAddr,
1124 u32 ul_num_bytes, u32 ulMemType)
1125 {
1126 int status = 0;
1127 u32 src_addr = ulDspSrcAddr;
1128 u32 dest_addr = ulDspDestAddr;
1129 u32 copy_bytes = 0;
1130 u32 total_bytes = ul_num_bytes;
1131 u8 host_buf[BUFFERSIZE];
1132 struct bridge_dev_context *dev_context = hDevContext;
1133 while ((total_bytes > 0) && DSP_SUCCEEDED(status)) {
1134 copy_bytes =
1135 total_bytes > BUFFERSIZE ? BUFFERSIZE : total_bytes;
1136 /* Read from External memory */
1137 status = read_ext_dsp_data(hDevContext, host_buf, src_addr,
1138 copy_bytes, ulMemType);
1139 if (DSP_SUCCEEDED(status)) {
1140 if (dest_addr < (dev_context->dw_dsp_start_add +
1141 dev_context->dw_internal_size)) {
1142 /* Write to Internal memory */
1143 status = write_dsp_data(hDevContext, host_buf,
1144 dest_addr, copy_bytes,
1145 ulMemType);
1146 } else {
1147 /* Write to External memory */
1148 status =
1149 write_ext_dsp_data(hDevContext, host_buf,
1150 dest_addr, copy_bytes,
1151 ulMemType, false);
1152 }
1153 }
1154 total_bytes -= copy_bytes;
1155 src_addr += copy_bytes;
1156 dest_addr += copy_bytes;
1157 }
1158 return status;
1159 }
1160
1161 /* Mem Write does not halt the DSP to write unlike bridge_brd_write */
1162 static int bridge_brd_mem_write(struct bridge_dev_context *hDevContext,
1163 IN u8 *pbHostBuf, u32 dwDSPAddr,
1164 u32 ul_num_bytes, u32 ulMemType)
1165 {
1166 int status = 0;
1167 struct bridge_dev_context *dev_context = hDevContext;
1168 u32 ul_remain_bytes = 0;
1169 u32 ul_bytes = 0;
1170 ul_remain_bytes = ul_num_bytes;
1171 while (ul_remain_bytes > 0 && DSP_SUCCEEDED(status)) {
1172 ul_bytes =
1173 ul_remain_bytes > BUFFERSIZE ? BUFFERSIZE : ul_remain_bytes;
1174 if (dwDSPAddr < (dev_context->dw_dsp_start_add +
1175 dev_context->dw_internal_size)) {
1176 status =
1177 write_dsp_data(hDevContext, pbHostBuf, dwDSPAddr,
1178 ul_bytes, ulMemType);
1179 } else {
1180 status = write_ext_dsp_data(hDevContext, pbHostBuf,
1181 dwDSPAddr, ul_bytes,
1182 ulMemType, true);
1183 }
1184 ul_remain_bytes -= ul_bytes;
1185 dwDSPAddr += ul_bytes;
1186 pbHostBuf = pbHostBuf + ul_bytes;
1187 }
1188 return status;
1189 }
1190
1191 /*
1192 * ======== bridge_brd_mem_map ========
1193 * This function maps MPU buffer to the DSP address space. It performs
1194 * linear to physical address translation if required. It translates each
1195 * page since linear addresses can be physically non-contiguous
1196 * All address & size arguments are assumed to be page aligned (in proc.c)
1197 *
1198 * TODO: Disable MMU while updating the page tables (but that'll stall DSP)
1199 */
1200 static int bridge_brd_mem_map(struct bridge_dev_context *hDevContext,
1201 u32 ul_mpu_addr, u32 ulVirtAddr,
1202 u32 ul_num_bytes, u32 ul_map_attr,
1203 struct page **mapped_pages)
1204 {
1205 u32 attrs;
1206 int status = 0;
1207 struct bridge_dev_context *dev_context = hDevContext;
1208 struct hw_mmu_map_attrs_t hw_attrs;
1209 struct vm_area_struct *vma;
1210 struct mm_struct *mm = current->mm;
1211 u32 write = 0;
1212 u32 num_usr_pgs = 0;
1213 struct page *mapped_page, *pg;
1214 s32 pg_num;
1215 u32 va = ulVirtAddr;
1216 struct task_struct *curr_task = current;
1217 u32 pg_i = 0;
1218 u32 mpu_addr, pa;
1219
1220 dev_dbg(bridge,
1221 "%s hDevCtxt %p, pa %x, va %x, size %x, ul_map_attr %x\n",
1222 __func__, hDevContext, ul_mpu_addr, ulVirtAddr, ul_num_bytes,
1223 ul_map_attr);
1224 if (ul_num_bytes == 0)
1225 return -EINVAL;
1226
1227 if (ul_map_attr & DSP_MAP_DIR_MASK) {
1228 attrs = ul_map_attr;
1229 } else {
1230 /* Assign default attributes */
1231 attrs = ul_map_attr | (DSP_MAPVIRTUALADDR | DSP_MAPELEMSIZE16);
1232 }
1233 /* Take mapping properties */
1234 if (attrs & DSP_MAPBIGENDIAN)
1235 hw_attrs.endianism = HW_BIG_ENDIAN;
1236 else
1237 hw_attrs.endianism = HW_LITTLE_ENDIAN;
1238
1239 hw_attrs.mixed_size = (enum hw_mmu_mixed_size_t)
1240 ((attrs & DSP_MAPMIXEDELEMSIZE) >> 2);
1241 /* Ignore element_size if mixed_size is enabled */
1242 if (hw_attrs.mixed_size == 0) {
1243 if (attrs & DSP_MAPELEMSIZE8) {
1244 /* Size is 8 bit */
1245 hw_attrs.element_size = HW_ELEM_SIZE8BIT;
1246 } else if (attrs & DSP_MAPELEMSIZE16) {
1247 /* Size is 16 bit */
1248 hw_attrs.element_size = HW_ELEM_SIZE16BIT;
1249 } else if (attrs & DSP_MAPELEMSIZE32) {
1250 /* Size is 32 bit */
1251 hw_attrs.element_size = HW_ELEM_SIZE32BIT;
1252 } else if (attrs & DSP_MAPELEMSIZE64) {
1253 /* Size is 64 bit */
1254 hw_attrs.element_size = HW_ELEM_SIZE64BIT;
1255 } else {
1256 /*
1257 * Mixedsize isn't enabled, so size can't be
1258 * zero here
1259 */
1260 return -EINVAL;
1261 }
1262 }
1263 if (attrs & DSP_MAPDONOTLOCK)
1264 hw_attrs.donotlockmpupage = 1;
1265 else
1266 hw_attrs.donotlockmpupage = 0;
1267
1268 if (attrs & DSP_MAPVMALLOCADDR) {
1269 return mem_map_vmalloc(hDevContext, ul_mpu_addr, ulVirtAddr,
1270 ul_num_bytes, &hw_attrs);
1271 }
1272 /*
1273 * Do OS-specific user-va to pa translation.
1274 * Combine physically contiguous regions to reduce TLBs.
1275 * Pass the translated pa to pte_update.
1276 */
1277 if ((attrs & DSP_MAPPHYSICALADDR)) {
1278 status = pte_update(dev_context, ul_mpu_addr, ulVirtAddr,
1279 ul_num_bytes, &hw_attrs);
1280 goto func_cont;
1281 }
1282
1283 /*
1284 * Important Note: ul_mpu_addr is mapped from user application process
1285 * to current process - it must lie completely within the current
1286 * virtual memory address space in order to be of use to us here!
1287 */
1288 down_read(&mm->mmap_sem);
1289 vma = find_vma(mm, ul_mpu_addr);
1290 if (vma)
1291 dev_dbg(bridge,
1292 "VMAfor UserBuf: ul_mpu_addr=%x, ul_num_bytes=%x, "
1293 "vm_start=%lx, vm_end=%lx, vm_flags=%lx\n", ul_mpu_addr,
1294 ul_num_bytes, vma->vm_start, vma->vm_end,
1295 vma->vm_flags);
1296
1297 /*
1298 * It is observed that under some circumstances, the user buffer is
1299 * spread across several VMAs. So loop through and check if the entire
1300 * user buffer is covered
1301 */
1302 while ((vma) && (ul_mpu_addr + ul_num_bytes > vma->vm_end)) {
1303 /* jump to the next VMA region */
1304 vma = find_vma(mm, vma->vm_end + 1);
1305 dev_dbg(bridge,
1306 "VMA for UserBuf ul_mpu_addr=%x ul_num_bytes=%x, "
1307 "vm_start=%lx, vm_end=%lx, vm_flags=%lx\n", ul_mpu_addr,
1308 ul_num_bytes, vma->vm_start, vma->vm_end,
1309 vma->vm_flags);
1310 }
1311 if (!vma) {
1312 pr_err("%s: Failed to get VMA region for 0x%x (%d)\n",
1313 __func__, ul_mpu_addr, ul_num_bytes);
1314 status = -EINVAL;
1315 up_read(&mm->mmap_sem);
1316 goto func_cont;
1317 }
1318
1319 if (vma->vm_flags & VM_IO) {
1320 num_usr_pgs = ul_num_bytes / PG_SIZE4K;
1321 mpu_addr = ul_mpu_addr;
1322
1323 /* Get the physical addresses for user buffer */
1324 for (pg_i = 0; pg_i < num_usr_pgs; pg_i++) {
1325 pa = user_va2_pa(mm, mpu_addr);
1326 if (!pa) {
1327 status = -EPERM;
1328 pr_err("DSPBRIDGE: VM_IO mapping physical"
1329 "address is invalid\n");
1330 break;
1331 }
1332 if (pfn_valid(__phys_to_pfn(pa))) {
1333 pg = PHYS_TO_PAGE(pa);
1334 get_page(pg);
1335 if (page_count(pg) < 1) {
1336 pr_err("Bad page in VM_IO buffer\n");
1337 bad_page_dump(pa, pg);
1338 }
1339 }
1340 status = pte_set(dev_context->pt_attrs, pa,
1341 va, HW_PAGE_SIZE4KB, &hw_attrs);
1342 if (DSP_FAILED(status))
1343 break;
1344
1345 va += HW_PAGE_SIZE4KB;
1346 mpu_addr += HW_PAGE_SIZE4KB;
1347 pa += HW_PAGE_SIZE4KB;
1348 }
1349 } else {
1350 num_usr_pgs = ul_num_bytes / PG_SIZE4K;
1351 if (vma->vm_flags & (VM_WRITE | VM_MAYWRITE))
1352 write = 1;
1353
1354 for (pg_i = 0; pg_i < num_usr_pgs; pg_i++) {
1355 pg_num = get_user_pages(curr_task, mm, ul_mpu_addr, 1,
1356 write, 1, &mapped_page, NULL);
1357 if (pg_num > 0) {
1358 if (page_count(mapped_page) < 1) {
1359 pr_err("Bad page count after doing"
1360 "get_user_pages on"
1361 "user buffer\n");
1362 bad_page_dump(page_to_phys(mapped_page),
1363 mapped_page);
1364 }
1365 status = pte_set(dev_context->pt_attrs,
1366 page_to_phys(mapped_page), va,
1367 HW_PAGE_SIZE4KB, &hw_attrs);
1368 if (DSP_FAILED(status))
1369 break;
1370
1371 if (mapped_pages)
1372 mapped_pages[pg_i] = mapped_page;
1373
1374 va += HW_PAGE_SIZE4KB;
1375 ul_mpu_addr += HW_PAGE_SIZE4KB;
1376 } else {
1377 pr_err("DSPBRIDGE: get_user_pages FAILED,"
1378 "MPU addr = 0x%x,"
1379 "vma->vm_flags = 0x%lx,"
1380 "get_user_pages Err"
1381 "Value = %d, Buffer"
1382 "size=0x%x\n", ul_mpu_addr,
1383 vma->vm_flags, pg_num, ul_num_bytes);
1384 status = -EPERM;
1385 break;
1386 }
1387 }
1388 }
1389 up_read(&mm->mmap_sem);
1390 func_cont:
1391 if (DSP_SUCCEEDED(status)) {
1392 status = 0;
1393 } else {
1394 /*
1395 * Roll out the mapped pages incase it failed in middle of
1396 * mapping
1397 */
1398 if (pg_i) {
1399 bridge_brd_mem_un_map(dev_context, ulVirtAddr,
1400 (pg_i * PG_SIZE4K));
1401 }
1402 status = -EPERM;
1403 }
1404 /*
1405 * In any case, flush the TLB
1406 * This is called from here instead from pte_update to avoid unnecessary
1407 * repetition while mapping non-contiguous physical regions of a virtual
1408 * region
1409 */
1410 flush_all(dev_context);
1411 dev_dbg(bridge, "%s status %x\n", __func__, status);
1412 return status;
1413 }
1414
1415 /*
1416 * ======== bridge_brd_mem_un_map ========
1417 * Invalidate the PTEs for the DSP VA block to be unmapped.
1418 *
1419 * PTEs of a mapped memory block are contiguous in any page table
1420 * So, instead of looking up the PTE address for every 4K block,
1421 * we clear consecutive PTEs until we unmap all the bytes
1422 */
1423 static int bridge_brd_mem_un_map(struct bridge_dev_context *hDevContext,
1424 u32 ulVirtAddr, u32 ul_num_bytes)
1425 {
1426 u32 l1_base_va;
1427 u32 l2_base_va;
1428 u32 l2_base_pa;
1429 u32 l2_page_num;
1430 u32 pte_val;
1431 u32 pte_size;
1432 u32 pte_count;
1433 u32 pte_addr_l1;
1434 u32 pte_addr_l2 = 0;
1435 u32 rem_bytes;
1436 u32 rem_bytes_l2;
1437 u32 va_curr;
1438 struct page *pg = NULL;
1439 int status = 0;
1440 struct bridge_dev_context *dev_context = hDevContext;
1441 struct pg_table_attrs *pt = dev_context->pt_attrs;
1442 u32 temp;
1443 u32 paddr;
1444 u32 numof4k_pages = 0;
1445
1446 va_curr = ulVirtAddr;
1447 rem_bytes = ul_num_bytes;
1448 rem_bytes_l2 = 0;
1449 l1_base_va = pt->l1_base_va;
1450 pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va_curr);
1451 dev_dbg(bridge, "%s hDevContext %p, va %x, NumBytes %x l1_base_va %x, "
1452 "pte_addr_l1 %x\n", __func__, hDevContext, ulVirtAddr,
1453 ul_num_bytes, l1_base_va, pte_addr_l1);
1454
1455 while (rem_bytes && (DSP_SUCCEEDED(status))) {
1456 u32 va_curr_orig = va_curr;
1457 /* Find whether the L1 PTE points to a valid L2 PT */
1458 pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va_curr);
1459 pte_val = *(u32 *) pte_addr_l1;
1460 pte_size = hw_mmu_pte_size_l1(pte_val);
1461
1462 if (pte_size != HW_MMU_COARSE_PAGE_SIZE)
1463 goto skip_coarse_page;
1464
1465 /*
1466 * Get the L2 PA from the L1 PTE, and find
1467 * corresponding L2 VA
1468 */
1469 l2_base_pa = hw_mmu_pte_coarse_l1(pte_val);
1470 l2_base_va = l2_base_pa - pt->l2_base_pa + pt->l2_base_va;
1471 l2_page_num =
1472 (l2_base_pa - pt->l2_base_pa) / HW_MMU_COARSE_PAGE_SIZE;
1473 /*
1474 * Find the L2 PTE address from which we will start
1475 * clearing, the number of PTEs to be cleared on this
1476 * page, and the size of VA space that needs to be
1477 * cleared on this L2 page
1478 */
1479 pte_addr_l2 = hw_mmu_pte_addr_l2(l2_base_va, va_curr);
1480 pte_count = pte_addr_l2 & (HW_MMU_COARSE_PAGE_SIZE - 1);
1481 pte_count = (HW_MMU_COARSE_PAGE_SIZE - pte_count) / sizeof(u32);
1482 if (rem_bytes < (pte_count * PG_SIZE4K))
1483 pte_count = rem_bytes / PG_SIZE4K;
1484 rem_bytes_l2 = pte_count * PG_SIZE4K;
1485
1486 /*
1487 * Unmap the VA space on this L2 PT. A quicker way
1488 * would be to clear pte_count entries starting from
1489 * pte_addr_l2. However, below code checks that we don't
1490 * clear invalid entries or less than 64KB for a 64KB
1491 * entry. Similar checking is done for L1 PTEs too
1492 * below
1493 */
1494 while (rem_bytes_l2 && (DSP_SUCCEEDED(status))) {
1495 pte_val = *(u32 *) pte_addr_l2;
1496 pte_size = hw_mmu_pte_size_l2(pte_val);
1497 /* va_curr aligned to pte_size? */
1498 if (pte_size == 0 || rem_bytes_l2 < pte_size ||
1499 va_curr & (pte_size - 1)) {
1500 status = -EPERM;
1501 break;
1502 }
1503
1504 /* Collect Physical addresses from VA */
1505 paddr = (pte_val & ~(pte_size - 1));
1506 if (pte_size == HW_PAGE_SIZE64KB)
1507 numof4k_pages = 16;
1508 else
1509 numof4k_pages = 1;
1510 temp = 0;
1511 while (temp++ < numof4k_pages) {
1512 if (!pfn_valid(__phys_to_pfn(paddr))) {
1513 paddr += HW_PAGE_SIZE4KB;
1514 continue;
1515 }
1516 pg = PHYS_TO_PAGE(paddr);
1517 if (page_count(pg) < 1) {
1518 pr_info("DSPBRIDGE: UNMAP function: "
1519 "COUNT 0 FOR PA 0x%x, size = "
1520 "0x%x\n", paddr, ul_num_bytes);
1521 bad_page_dump(paddr, pg);
1522 } else {
1523 SetPageDirty(pg);
1524 page_cache_release(pg);
1525 }
1526 paddr += HW_PAGE_SIZE4KB;
1527 }
1528 if (hw_mmu_pte_clear(pte_addr_l2, va_curr, pte_size)
1529 == RET_FAIL) {
1530 status = -EPERM;
1531 goto EXIT_LOOP;
1532 }
1533
1534 status = 0;
1535 rem_bytes_l2 -= pte_size;
1536 va_curr += pte_size;
1537 pte_addr_l2 += (pte_size >> 12) * sizeof(u32);
1538 }
1539 spin_lock(&pt->pg_lock);
1540 if (rem_bytes_l2 == 0) {
1541 pt->pg_info[l2_page_num].num_entries -= pte_count;
1542 if (pt->pg_info[l2_page_num].num_entries == 0) {
1543 /*
1544 * Clear the L1 PTE pointing to the L2 PT
1545 */
1546 if (hw_mmu_pte_clear(l1_base_va, va_curr_orig,
1547 HW_MMU_COARSE_PAGE_SIZE) ==
1548 RET_OK)
1549 status = 0;
1550 else {
1551 status = -EPERM;
1552 spin_unlock(&pt->pg_lock);
1553 goto EXIT_LOOP;
1554 }
1555 }
1556 rem_bytes -= pte_count * PG_SIZE4K;
1557 } else
1558 status = -EPERM;
1559
1560 spin_unlock(&pt->pg_lock);
1561 continue;
1562 skip_coarse_page:
1563 /* va_curr aligned to pte_size? */
1564 /* pte_size = 1 MB or 16 MB */
1565 if (pte_size == 0 || rem_bytes < pte_size ||
1566 va_curr & (pte_size - 1)) {
1567 status = -EPERM;
1568 break;
1569 }
1570
1571 if (pte_size == HW_PAGE_SIZE1MB)
1572 numof4k_pages = 256;
1573 else
1574 numof4k_pages = 4096;
1575 temp = 0;
1576 /* Collect Physical addresses from VA */
1577 paddr = (pte_val & ~(pte_size - 1));
1578 while (temp++ < numof4k_pages) {
1579 if (pfn_valid(__phys_to_pfn(paddr))) {
1580 pg = PHYS_TO_PAGE(paddr);
1581 if (page_count(pg) < 1) {
1582 pr_info("DSPBRIDGE: UNMAP function: "
1583 "COUNT 0 FOR PA 0x%x, size = "
1584 "0x%x\n", paddr, ul_num_bytes);
1585 bad_page_dump(paddr, pg);
1586 } else {
1587 SetPageDirty(pg);
1588 page_cache_release(pg);
1589 }
1590 }
1591 paddr += HW_PAGE_SIZE4KB;
1592 }
1593 if (hw_mmu_pte_clear(l1_base_va, va_curr, pte_size) == RET_OK) {
1594 status = 0;
1595 rem_bytes -= pte_size;
1596 va_curr += pte_size;
1597 } else {
1598 status = -EPERM;
1599 goto EXIT_LOOP;
1600 }
1601 }
1602 /*
1603 * It is better to flush the TLB here, so that any stale old entries
1604 * get flushed
1605 */
1606 EXIT_LOOP:
1607 flush_all(dev_context);
1608 dev_dbg(bridge,
1609 "%s: va_curr %x, pte_addr_l1 %x pte_addr_l2 %x rem_bytes %x,"
1610 " rem_bytes_l2 %x status %x\n", __func__, va_curr, pte_addr_l1,
1611 pte_addr_l2, rem_bytes, rem_bytes_l2, status);
1612 return status;
1613 }
1614
1615 /*
1616 * ======== user_va2_pa ========
1617 * Purpose:
1618 * This function walks through the page tables to convert a userland
1619 * virtual address to physical address
1620 */
1621 static u32 user_va2_pa(struct mm_struct *mm, u32 address)
1622 {
1623 pgd_t *pgd;
1624 pmd_t *pmd;
1625 pte_t *ptep, pte;
1626
1627 pgd = pgd_offset(mm, address);
1628 if (!(pgd_none(*pgd) || pgd_bad(*pgd))) {
1629 pmd = pmd_offset(pgd, address);
1630 if (!(pmd_none(*pmd) || pmd_bad(*pmd))) {
1631 ptep = pte_offset_map(pmd, address);
1632 if (ptep) {
1633 pte = *ptep;
1634 if (pte_present(pte))
1635 return pte & PAGE_MASK;
1636 }
1637 }
1638 }
1639
1640 return 0;
1641 }
1642
1643 /*
1644 * ======== pte_update ========
1645 * This function calculates the optimum page-aligned addresses and sizes
1646 * Caller must pass page-aligned values
1647 */
1648 static int pte_update(struct bridge_dev_context *hDevContext, u32 pa,
1649 u32 va, u32 size,
1650 struct hw_mmu_map_attrs_t *map_attrs)
1651 {
1652 u32 i;
1653 u32 all_bits;
1654 u32 pa_curr = pa;
1655 u32 va_curr = va;
1656 u32 num_bytes = size;
1657 struct bridge_dev_context *dev_context = hDevContext;
1658 int status = 0;
1659 u32 page_size[] = { HW_PAGE_SIZE16MB, HW_PAGE_SIZE1MB,
1660 HW_PAGE_SIZE64KB, HW_PAGE_SIZE4KB
1661 };
1662
1663 while (num_bytes && DSP_SUCCEEDED(status)) {
1664 /* To find the max. page size with which both PA & VA are
1665 * aligned */
1666 all_bits = pa_curr | va_curr;
1667
1668 for (i = 0; i < 4; i++) {
1669 if ((num_bytes >= page_size[i]) && ((all_bits &
1670 (page_size[i] -
1671 1)) == 0)) {
1672 status =
1673 pte_set(dev_context->pt_attrs, pa_curr,
1674 va_curr, page_size[i], map_attrs);
1675 pa_curr += page_size[i];
1676 va_curr += page_size[i];
1677 num_bytes -= page_size[i];
1678 /* Don't try smaller sizes. Hopefully we have
1679 * reached an address aligned to a bigger page
1680 * size */
1681 break;
1682 }
1683 }
1684 }
1685
1686 return status;
1687 }
1688
1689 /*
1690 * ======== pte_set ========
1691 * This function calculates PTE address (MPU virtual) to be updated
1692 * It also manages the L2 page tables
1693 */
1694 static int pte_set(struct pg_table_attrs *pt, u32 pa, u32 va,
1695 u32 size, struct hw_mmu_map_attrs_t *attrs)
1696 {
1697 u32 i;
1698 u32 pte_val;
1699 u32 pte_addr_l1;
1700 u32 pte_size;
1701 /* Base address of the PT that will be updated */
1702 u32 pg_tbl_va;
1703 u32 l1_base_va;
1704 /* Compiler warns that the next three variables might be used
1705 * uninitialized in this function. Doesn't seem so. Working around,
1706 * anyways. */
1707 u32 l2_base_va = 0;
1708 u32 l2_base_pa = 0;
1709 u32 l2_page_num = 0;
1710 int status = 0;
1711
1712 l1_base_va = pt->l1_base_va;
1713 pg_tbl_va = l1_base_va;
1714 if ((size == HW_PAGE_SIZE64KB) || (size == HW_PAGE_SIZE4KB)) {
1715 /* Find whether the L1 PTE points to a valid L2 PT */
1716 pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va);
1717 if (pte_addr_l1 <= (pt->l1_base_va + pt->l1_size)) {
1718 pte_val = *(u32 *) pte_addr_l1;
1719 pte_size = hw_mmu_pte_size_l1(pte_val);
1720 } else {
1721 return -EPERM;
1722 }
1723 spin_lock(&pt->pg_lock);
1724 if (pte_size == HW_MMU_COARSE_PAGE_SIZE) {
1725 /* Get the L2 PA from the L1 PTE, and find
1726 * corresponding L2 VA */
1727 l2_base_pa = hw_mmu_pte_coarse_l1(pte_val);
1728 l2_base_va =
1729 l2_base_pa - pt->l2_base_pa + pt->l2_base_va;
1730 l2_page_num =
1731 (l2_base_pa -
1732 pt->l2_base_pa) / HW_MMU_COARSE_PAGE_SIZE;
1733 } else if (pte_size == 0) {
1734 /* L1 PTE is invalid. Allocate a L2 PT and
1735 * point the L1 PTE to it */
1736 /* Find a free L2 PT. */
1737 for (i = 0; (i < pt->l2_num_pages) &&
1738 (pt->pg_info[i].num_entries != 0); i++)
1739 ;;
1740 if (i < pt->l2_num_pages) {
1741 l2_page_num = i;
1742 l2_base_pa = pt->l2_base_pa + (l2_page_num *
1743 HW_MMU_COARSE_PAGE_SIZE);
1744 l2_base_va = pt->l2_base_va + (l2_page_num *
1745 HW_MMU_COARSE_PAGE_SIZE);
1746 /* Endianness attributes are ignored for
1747 * HW_MMU_COARSE_PAGE_SIZE */
1748 status =
1749 hw_mmu_pte_set(l1_base_va, l2_base_pa, va,
1750 HW_MMU_COARSE_PAGE_SIZE,
1751 attrs);
1752 } else {
1753 status = -ENOMEM;
1754 }
1755 } else {
1756 /* Found valid L1 PTE of another size.
1757 * Should not overwrite it. */
1758 status = -EPERM;
1759 }
1760 if (DSP_SUCCEEDED(status)) {
1761 pg_tbl_va = l2_base_va;
1762 if (size == HW_PAGE_SIZE64KB)
1763 pt->pg_info[l2_page_num].num_entries += 16;
1764 else
1765 pt->pg_info[l2_page_num].num_entries++;
1766 dev_dbg(bridge, "PTE: L2 BaseVa %x, BasePa %x, PageNum "
1767 "%x, num_entries %x\n", l2_base_va,
1768 l2_base_pa, l2_page_num,
1769 pt->pg_info[l2_page_num].num_entries);
1770 }
1771 spin_unlock(&pt->pg_lock);
1772 }
1773 if (DSP_SUCCEEDED(status)) {
1774 dev_dbg(bridge, "PTE: pg_tbl_va %x, pa %x, va %x, size %x\n",
1775 pg_tbl_va, pa, va, size);
1776 dev_dbg(bridge, "PTE: endianism %x, element_size %x, "
1777 "mixed_size %x\n", attrs->endianism,
1778 attrs->element_size, attrs->mixed_size);
1779 status = hw_mmu_pte_set(pg_tbl_va, pa, va, size, attrs);
1780 }
1781
1782 return status;
1783 }
1784
1785 /* Memory map kernel VA -- memory allocated with vmalloc */
1786 static int mem_map_vmalloc(struct bridge_dev_context *dev_context,
1787 u32 ul_mpu_addr, u32 ulVirtAddr,
1788 u32 ul_num_bytes,
1789 struct hw_mmu_map_attrs_t *hw_attrs)
1790 {
1791 int status = 0;
1792 struct page *page[1];
1793 u32 i;
1794 u32 pa_curr;
1795 u32 pa_next;
1796 u32 va_curr;
1797 u32 size_curr;
1798 u32 num_pages;
1799 u32 pa;
1800 u32 num_of4k_pages;
1801 u32 temp = 0;
1802
1803 /*
1804 * Do Kernel va to pa translation.
1805 * Combine physically contiguous regions to reduce TLBs.
1806 * Pass the translated pa to pte_update.
1807 */
1808 num_pages = ul_num_bytes / PAGE_SIZE; /* PAGE_SIZE = OS page size */
1809 i = 0;
1810 va_curr = ul_mpu_addr;
1811 page[0] = vmalloc_to_page((void *)va_curr);
1812 pa_next = page_to_phys(page[0]);
1813 while (DSP_SUCCEEDED(status) && (i < num_pages)) {
1814 /*
1815 * Reuse pa_next from the previous iteraion to avoid
1816 * an extra va2pa call
1817 */
1818 pa_curr = pa_next;
1819 size_curr = PAGE_SIZE;
1820 /*
1821 * If the next page is physically contiguous,
1822 * map it with the current one by increasing
1823 * the size of the region to be mapped
1824 */
1825 while (++i < num_pages) {
1826 page[0] =
1827 vmalloc_to_page((void *)(va_curr + size_curr));
1828 pa_next = page_to_phys(page[0]);
1829
1830 if (pa_next == (pa_curr + size_curr))
1831 size_curr += PAGE_SIZE;
1832 else
1833 break;
1834
1835 }
1836 if (pa_next == 0) {
1837 status = -ENOMEM;
1838 break;
1839 }
1840 pa = pa_curr;
1841 num_of4k_pages = size_curr / HW_PAGE_SIZE4KB;
1842 while (temp++ < num_of4k_pages) {
1843 get_page(PHYS_TO_PAGE(pa));
1844 pa += HW_PAGE_SIZE4KB;
1845 }
1846 status = pte_update(dev_context, pa_curr, ulVirtAddr +
1847 (va_curr - ul_mpu_addr), size_curr,
1848 hw_attrs);
1849 va_curr += size_curr;
1850 }
1851 if (DSP_SUCCEEDED(status))
1852 status = 0;
1853 else
1854 status = -EPERM;
1855
1856 /*
1857 * In any case, flush the TLB
1858 * This is called from here instead from pte_update to avoid unnecessary
1859 * repetition while mapping non-contiguous physical regions of a virtual
1860 * region
1861 */
1862 flush_all(dev_context);
1863 dev_dbg(bridge, "%s status %x\n", __func__, status);
1864 return status;
1865 }
1866
1867 /*
1868 * ======== wait_for_start ========
1869 * Wait for the singal from DSP that it has started, or time out.
1870 */
1871 bool wait_for_start(struct bridge_dev_context *dev_context, u32 dw_sync_addr)
1872 {
1873 u16 timeout = TIHELEN_ACKTIMEOUT;
1874
1875 /* Wait for response from board */
1876 while (*((volatile u16 *)dw_sync_addr) && --timeout)
1877 udelay(10);
1878
1879 /* If timed out: return FALSE */
1880 if (!timeout) {
1881 pr_err("%s: Timed out waiting DSP to Start\n", __func__);
1882 return FALSE;
1883 }
1884 return TRUE;
1885 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree