2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/ioport.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/spi/spi.h>
28 #include <linux/workqueue.h>
29 #include <linux/delay.h>
30 #include <linux/clk.h>
34 #include <asm/delay.h>
37 #include <mach/regs-ssp.h>
39 #include <mach/pxa2xx_spi.h>
41 MODULE_AUTHOR("Stephen Street");
42 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
43 MODULE_LICENSE("GPL");
44 MODULE_ALIAS("platform:pxa2xx-spi");
48 #define RX_THRESH_DFLT 8
49 #define TX_THRESH_DFLT 8
50 #define TIMOUT_DFLT 1000
52 #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
53 #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
54 #define IS_DMA_ALIGNED(x) ((((u32)(x)) & 0x07) == 0)
55 #define MAX_DMA_LEN 8191
58 * for testing SSCR1 changes that require SSP restart, basically
59 * everything except the service and interrupt enables, the pxa270 developer
60 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
61 * list, but the PXA255 dev man says all bits without really meaning the
62 * service and interrupt enables
64 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
65 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
66 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
67 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
68 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
69 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
71 #define DEFINE_SSP_REG(reg, off) \
72 static inline u32 read_##reg(void const __iomem *p) \
73 { return __raw_readl(p + (off)); } \
75 static inline void write_##reg(u32 v, void __iomem *p) \
76 { __raw_writel(v, p + (off)); }
78 DEFINE_SSP_REG(SSCR0
, 0x00)
79 DEFINE_SSP_REG(SSCR1
, 0x04)
80 DEFINE_SSP_REG(SSSR
, 0x08)
81 DEFINE_SSP_REG(SSITR
, 0x0c)
82 DEFINE_SSP_REG(SSDR
, 0x10)
83 DEFINE_SSP_REG(SSTO
, 0x28)
84 DEFINE_SSP_REG(SSPSP
, 0x2c)
86 #define START_STATE ((void*)0)
87 #define RUNNING_STATE ((void*)1)
88 #define DONE_STATE ((void*)2)
89 #define ERROR_STATE ((void*)-1)
91 #define QUEUE_RUNNING 0
92 #define QUEUE_STOPPED 1
95 /* Driver model hookup */
96 struct platform_device
*pdev
;
99 struct ssp_device
*ssp
;
101 /* SPI framework hookup */
102 enum pxa_ssp_type ssp_type
;
103 struct spi_master
*master
;
106 struct pxa2xx_spi_master
*master_info
;
108 /* DMA setup stuff */
113 /* SSP register addresses */
114 void __iomem
*ioaddr
;
123 /* Driver message queue */
124 struct workqueue_struct
*workqueue
;
125 struct work_struct pump_messages
;
127 struct list_head queue
;
131 /* Message Transfer pump */
132 struct tasklet_struct pump_transfers
;
134 /* Current message transfer state info */
135 struct spi_message
* cur_msg
;
136 struct spi_transfer
* cur_transfer
;
137 struct chip_data
*cur_chip
;
150 int (*write
)(struct driver_data
*drv_data
);
151 int (*read
)(struct driver_data
*drv_data
);
152 irqreturn_t (*transfer_handler
)(struct driver_data
*drv_data
);
153 void (*cs_control
)(u32 command
);
169 int (*write
)(struct driver_data
*drv_data
);
170 int (*read
)(struct driver_data
*drv_data
);
171 void (*cs_control
)(u32 command
);
174 static void pump_messages(struct work_struct
*work
);
176 static int flush(struct driver_data
*drv_data
)
178 unsigned long limit
= loops_per_jiffy
<< 1;
180 void __iomem
*reg
= drv_data
->ioaddr
;
183 while (read_SSSR(reg
) & SSSR_RNE
) {
186 } while ((read_SSSR(reg
) & SSSR_BSY
) && limit
--);
187 write_SSSR(SSSR_ROR
, reg
);
192 static void null_cs_control(u32 command
)
196 static int null_writer(struct driver_data
*drv_data
)
198 void __iomem
*reg
= drv_data
->ioaddr
;
199 u8 n_bytes
= drv_data
->n_bytes
;
201 if (((read_SSSR(reg
) & 0x00000f00) == 0x00000f00)
202 || (drv_data
->tx
== drv_data
->tx_end
))
206 drv_data
->tx
+= n_bytes
;
211 static int null_reader(struct driver_data
*drv_data
)
213 void __iomem
*reg
= drv_data
->ioaddr
;
214 u8 n_bytes
= drv_data
->n_bytes
;
216 while ((read_SSSR(reg
) & SSSR_RNE
)
217 && (drv_data
->rx
< drv_data
->rx_end
)) {
219 drv_data
->rx
+= n_bytes
;
222 return drv_data
->rx
== drv_data
->rx_end
;
225 static int u8_writer(struct driver_data
*drv_data
)
227 void __iomem
*reg
= drv_data
->ioaddr
;
229 if (((read_SSSR(reg
) & 0x00000f00) == 0x00000f00)
230 || (drv_data
->tx
== drv_data
->tx_end
))
233 write_SSDR(*(u8
*)(drv_data
->tx
), reg
);
239 static int u8_reader(struct driver_data
*drv_data
)
241 void __iomem
*reg
= drv_data
->ioaddr
;
243 while ((read_SSSR(reg
) & SSSR_RNE
)
244 && (drv_data
->rx
< drv_data
->rx_end
)) {
245 *(u8
*)(drv_data
->rx
) = read_SSDR(reg
);
249 return drv_data
->rx
== drv_data
->rx_end
;
252 static int u16_writer(struct driver_data
*drv_data
)
254 void __iomem
*reg
= drv_data
->ioaddr
;
256 if (((read_SSSR(reg
) & 0x00000f00) == 0x00000f00)
257 || (drv_data
->tx
== drv_data
->tx_end
))
260 write_SSDR(*(u16
*)(drv_data
->tx
), reg
);
266 static int u16_reader(struct driver_data
*drv_data
)
268 void __iomem
*reg
= drv_data
->ioaddr
;
270 while ((read_SSSR(reg
) & SSSR_RNE
)
271 && (drv_data
->rx
< drv_data
->rx_end
)) {
272 *(u16
*)(drv_data
->rx
) = read_SSDR(reg
);
276 return drv_data
->rx
== drv_data
->rx_end
;
279 static int u32_writer(struct driver_data
*drv_data
)
281 void __iomem
*reg
= drv_data
->ioaddr
;
283 if (((read_SSSR(reg
) & 0x00000f00) == 0x00000f00)
284 || (drv_data
->tx
== drv_data
->tx_end
))
287 write_SSDR(*(u32
*)(drv_data
->tx
), reg
);
293 static int u32_reader(struct driver_data
*drv_data
)
295 void __iomem
*reg
= drv_data
->ioaddr
;
297 while ((read_SSSR(reg
) & SSSR_RNE
)
298 && (drv_data
->rx
< drv_data
->rx_end
)) {
299 *(u32
*)(drv_data
->rx
) = read_SSDR(reg
);
303 return drv_data
->rx
== drv_data
->rx_end
;
306 static void *next_transfer(struct driver_data
*drv_data
)
308 struct spi_message
*msg
= drv_data
->cur_msg
;
309 struct spi_transfer
*trans
= drv_data
->cur_transfer
;
311 /* Move to next transfer */
312 if (trans
->transfer_list
.next
!= &msg
->transfers
) {
313 drv_data
->cur_transfer
=
314 list_entry(trans
->transfer_list
.next
,
317 return RUNNING_STATE
;
322 static int map_dma_buffers(struct driver_data
*drv_data
)
324 struct spi_message
*msg
= drv_data
->cur_msg
;
325 struct device
*dev
= &msg
->spi
->dev
;
327 if (!drv_data
->cur_chip
->enable_dma
)
330 if (msg
->is_dma_mapped
)
331 return drv_data
->rx_dma
&& drv_data
->tx_dma
;
333 if (!IS_DMA_ALIGNED(drv_data
->rx
) || !IS_DMA_ALIGNED(drv_data
->tx
))
336 /* Modify setup if rx buffer is null */
337 if (drv_data
->rx
== NULL
) {
338 *drv_data
->null_dma_buf
= 0;
339 drv_data
->rx
= drv_data
->null_dma_buf
;
340 drv_data
->rx_map_len
= 4;
342 drv_data
->rx_map_len
= drv_data
->len
;
345 /* Modify setup if tx buffer is null */
346 if (drv_data
->tx
== NULL
) {
347 *drv_data
->null_dma_buf
= 0;
348 drv_data
->tx
= drv_data
->null_dma_buf
;
349 drv_data
->tx_map_len
= 4;
351 drv_data
->tx_map_len
= drv_data
->len
;
353 /* Stream map the tx buffer. Always do DMA_TO_DEVICE first
354 * so we flush the cache *before* invalidating it, in case
355 * the tx and rx buffers overlap.
357 drv_data
->tx_dma
= dma_map_single(dev
, drv_data
->tx
,
358 drv_data
->tx_map_len
, DMA_TO_DEVICE
);
359 if (dma_mapping_error(dev
, drv_data
->tx_dma
))
362 /* Stream map the rx buffer */
363 drv_data
->rx_dma
= dma_map_single(dev
, drv_data
->rx
,
364 drv_data
->rx_map_len
, DMA_FROM_DEVICE
);
365 if (dma_mapping_error(dev
, drv_data
->rx_dma
)) {
366 dma_unmap_single(dev
, drv_data
->tx_dma
,
367 drv_data
->tx_map_len
, DMA_TO_DEVICE
);
374 static void unmap_dma_buffers(struct driver_data
*drv_data
)
378 if (!drv_data
->dma_mapped
)
381 if (!drv_data
->cur_msg
->is_dma_mapped
) {
382 dev
= &drv_data
->cur_msg
->spi
->dev
;
383 dma_unmap_single(dev
, drv_data
->rx_dma
,
384 drv_data
->rx_map_len
, DMA_FROM_DEVICE
);
385 dma_unmap_single(dev
, drv_data
->tx_dma
,
386 drv_data
->tx_map_len
, DMA_TO_DEVICE
);
389 drv_data
->dma_mapped
= 0;
392 /* caller already set message->status; dma and pio irqs are blocked */
393 static void giveback(struct driver_data
*drv_data
)
395 struct spi_transfer
* last_transfer
;
397 struct spi_message
*msg
;
399 spin_lock_irqsave(&drv_data
->lock
, flags
);
400 msg
= drv_data
->cur_msg
;
401 drv_data
->cur_msg
= NULL
;
402 drv_data
->cur_transfer
= NULL
;
403 drv_data
->cur_chip
= NULL
;
404 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
405 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
407 last_transfer
= list_entry(msg
->transfers
.prev
,
411 /* Delay if requested before any change in chip select */
412 if (last_transfer
->delay_usecs
)
413 udelay(last_transfer
->delay_usecs
);
415 /* Drop chip select UNLESS cs_change is true or we are returning
416 * a message with an error, or next message is for another chip
418 if (!last_transfer
->cs_change
)
419 drv_data
->cs_control(PXA2XX_CS_DEASSERT
);
421 struct spi_message
*next_msg
;
423 /* Holding of cs was hinted, but we need to make sure
424 * the next message is for the same chip. Don't waste
425 * time with the following tests unless this was hinted.
427 * We cannot postpone this until pump_messages, because
428 * after calling msg->complete (below) the driver that
429 * sent the current message could be unloaded, which
430 * could invalidate the cs_control() callback...
433 /* get a pointer to the next message, if any */
434 spin_lock_irqsave(&drv_data
->lock
, flags
);
435 if (list_empty(&drv_data
->queue
))
438 next_msg
= list_entry(drv_data
->queue
.next
,
439 struct spi_message
, queue
);
440 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
442 /* see if the next and current messages point
445 if (next_msg
&& next_msg
->spi
!= msg
->spi
)
447 if (!next_msg
|| msg
->state
== ERROR_STATE
)
448 drv_data
->cs_control(PXA2XX_CS_DEASSERT
);
453 msg
->complete(msg
->context
);
456 static int wait_ssp_rx_stall(void const __iomem
*ioaddr
)
458 unsigned long limit
= loops_per_jiffy
<< 1;
460 while ((read_SSSR(ioaddr
) & SSSR_BSY
) && limit
--)
466 static int wait_dma_channel_stop(int channel
)
468 unsigned long limit
= loops_per_jiffy
<< 1;
470 while (!(DCSR(channel
) & DCSR_STOPSTATE
) && limit
--)
476 static void dma_error_stop(struct driver_data
*drv_data
, const char *msg
)
478 void __iomem
*reg
= drv_data
->ioaddr
;
481 DCSR(drv_data
->rx_channel
) = RESET_DMA_CHANNEL
;
482 DCSR(drv_data
->tx_channel
) = RESET_DMA_CHANNEL
;
483 write_SSSR(drv_data
->clear_sr
, reg
);
484 write_SSCR1(read_SSCR1(reg
) & ~drv_data
->dma_cr1
, reg
);
485 if (drv_data
->ssp_type
!= PXA25x_SSP
)
488 write_SSCR0(read_SSCR0(reg
) & ~SSCR0_SSE
, reg
);
490 unmap_dma_buffers(drv_data
);
492 dev_err(&drv_data
->pdev
->dev
, "%s\n", msg
);
494 drv_data
->cur_msg
->state
= ERROR_STATE
;
495 tasklet_schedule(&drv_data
->pump_transfers
);
498 static void dma_transfer_complete(struct driver_data
*drv_data
)
500 void __iomem
*reg
= drv_data
->ioaddr
;
501 struct spi_message
*msg
= drv_data
->cur_msg
;
503 /* Clear and disable interrupts on SSP and DMA channels*/
504 write_SSCR1(read_SSCR1(reg
) & ~drv_data
->dma_cr1
, reg
);
505 write_SSSR(drv_data
->clear_sr
, reg
);
506 DCSR(drv_data
->tx_channel
) = RESET_DMA_CHANNEL
;
507 DCSR(drv_data
->rx_channel
) = RESET_DMA_CHANNEL
;
509 if (wait_dma_channel_stop(drv_data
->rx_channel
) == 0)
510 dev_err(&drv_data
->pdev
->dev
,
511 "dma_handler: dma rx channel stop failed\n");
513 if (wait_ssp_rx_stall(drv_data
->ioaddr
) == 0)
514 dev_err(&drv_data
->pdev
->dev
,
515 "dma_transfer: ssp rx stall failed\n");
517 unmap_dma_buffers(drv_data
);
519 /* update the buffer pointer for the amount completed in dma */
520 drv_data
->rx
+= drv_data
->len
-
521 (DCMD(drv_data
->rx_channel
) & DCMD_LENGTH
);
523 /* read trailing data from fifo, it does not matter how many
524 * bytes are in the fifo just read until buffer is full
525 * or fifo is empty, which ever occurs first */
526 drv_data
->read(drv_data
);
528 /* return count of what was actually read */
529 msg
->actual_length
+= drv_data
->len
-
530 (drv_data
->rx_end
- drv_data
->rx
);
532 /* Transfer delays and chip select release are
533 * handled in pump_transfers or giveback
536 /* Move to next transfer */
537 msg
->state
= next_transfer(drv_data
);
539 /* Schedule transfer tasklet */
540 tasklet_schedule(&drv_data
->pump_transfers
);
543 static void dma_handler(int channel
, void *data
)
545 struct driver_data
*drv_data
= data
;
546 u32 irq_status
= DCSR(channel
) & DMA_INT_MASK
;
548 if (irq_status
& DCSR_BUSERR
) {
550 if (channel
== drv_data
->tx_channel
)
551 dma_error_stop(drv_data
,
553 "bad bus address on tx channel");
555 dma_error_stop(drv_data
,
557 "bad bus address on rx channel");
561 /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
562 if ((channel
== drv_data
->tx_channel
)
563 && (irq_status
& DCSR_ENDINTR
)
564 && (drv_data
->ssp_type
== PXA25x_SSP
)) {
566 /* Wait for rx to stall */
567 if (wait_ssp_rx_stall(drv_data
->ioaddr
) == 0)
568 dev_err(&drv_data
->pdev
->dev
,
569 "dma_handler: ssp rx stall failed\n");
571 /* finish this transfer, start the next */
572 dma_transfer_complete(drv_data
);
576 static irqreturn_t
dma_transfer(struct driver_data
*drv_data
)
579 void __iomem
*reg
= drv_data
->ioaddr
;
581 irq_status
= read_SSSR(reg
) & drv_data
->mask_sr
;
582 if (irq_status
& SSSR_ROR
) {
583 dma_error_stop(drv_data
, "dma_transfer: fifo overrun");
587 /* Check for false positive timeout */
588 if ((irq_status
& SSSR_TINT
)
589 && (DCSR(drv_data
->tx_channel
) & DCSR_RUN
)) {
590 write_SSSR(SSSR_TINT
, reg
);
594 if (irq_status
& SSSR_TINT
|| drv_data
->rx
== drv_data
->rx_end
) {
596 /* Clear and disable timeout interrupt, do the rest in
597 * dma_transfer_complete */
598 if (drv_data
->ssp_type
!= PXA25x_SSP
)
601 /* finish this transfer, start the next */
602 dma_transfer_complete(drv_data
);
607 /* Opps problem detected */
611 static void int_error_stop(struct driver_data
*drv_data
, const char* msg
)
613 void __iomem
*reg
= drv_data
->ioaddr
;
615 /* Stop and reset SSP */
616 write_SSSR(drv_data
->clear_sr
, reg
);
617 write_SSCR1(read_SSCR1(reg
) & ~drv_data
->int_cr1
, reg
);
618 if (drv_data
->ssp_type
!= PXA25x_SSP
)
621 write_SSCR0(read_SSCR0(reg
) & ~SSCR0_SSE
, reg
);
623 dev_err(&drv_data
->pdev
->dev
, "%s\n", msg
);
625 drv_data
->cur_msg
->state
= ERROR_STATE
;
626 tasklet_schedule(&drv_data
->pump_transfers
);
629 static void int_transfer_complete(struct driver_data
*drv_data
)
631 void __iomem
*reg
= drv_data
->ioaddr
;
634 write_SSSR(drv_data
->clear_sr
, reg
);
635 write_SSCR1(read_SSCR1(reg
) & ~drv_data
->int_cr1
, reg
);
636 if (drv_data
->ssp_type
!= PXA25x_SSP
)
639 /* Update total byte transfered return count actual bytes read */
640 drv_data
->cur_msg
->actual_length
+= drv_data
->len
-
641 (drv_data
->rx_end
- drv_data
->rx
);
643 /* Transfer delays and chip select release are
644 * handled in pump_transfers or giveback
647 /* Move to next transfer */
648 drv_data
->cur_msg
->state
= next_transfer(drv_data
);
650 /* Schedule transfer tasklet */
651 tasklet_schedule(&drv_data
->pump_transfers
);
654 static irqreturn_t
interrupt_transfer(struct driver_data
*drv_data
)
656 void __iomem
*reg
= drv_data
->ioaddr
;
658 u32 irq_mask
= (read_SSCR1(reg
) & SSCR1_TIE
) ?
659 drv_data
->mask_sr
: drv_data
->mask_sr
& ~SSSR_TFS
;
661 u32 irq_status
= read_SSSR(reg
) & irq_mask
;
663 if (irq_status
& SSSR_ROR
) {
664 int_error_stop(drv_data
, "interrupt_transfer: fifo overrun");
668 if (irq_status
& SSSR_TINT
) {
669 write_SSSR(SSSR_TINT
, reg
);
670 if (drv_data
->read(drv_data
)) {
671 int_transfer_complete(drv_data
);
676 /* Drain rx fifo, Fill tx fifo and prevent overruns */
678 if (drv_data
->read(drv_data
)) {
679 int_transfer_complete(drv_data
);
682 } while (drv_data
->write(drv_data
));
684 if (drv_data
->read(drv_data
)) {
685 int_transfer_complete(drv_data
);
689 if (drv_data
->tx
== drv_data
->tx_end
) {
690 write_SSCR1(read_SSCR1(reg
) & ~SSCR1_TIE
, reg
);
691 /* PXA25x_SSP has no timeout, read trailing bytes */
692 if (drv_data
->ssp_type
== PXA25x_SSP
) {
693 if (!wait_ssp_rx_stall(reg
))
695 int_error_stop(drv_data
, "interrupt_transfer: "
699 if (!drv_data
->read(drv_data
))
701 int_error_stop(drv_data
,
702 "interrupt_transfer: "
703 "trailing byte read failed");
706 int_transfer_complete(drv_data
);
710 /* We did something */
714 static irqreturn_t
ssp_int(int irq
, void *dev_id
)
716 struct driver_data
*drv_data
= dev_id
;
717 void __iomem
*reg
= drv_data
->ioaddr
;
719 if (!drv_data
->cur_msg
) {
721 write_SSCR0(read_SSCR0(reg
) & ~SSCR0_SSE
, reg
);
722 write_SSCR1(read_SSCR1(reg
) & ~drv_data
->int_cr1
, reg
);
723 if (drv_data
->ssp_type
!= PXA25x_SSP
)
725 write_SSSR(drv_data
->clear_sr
, reg
);
727 dev_err(&drv_data
->pdev
->dev
, "bad message state "
728 "in interrupt handler\n");
734 return drv_data
->transfer_handler(drv_data
);
737 static int set_dma_burst_and_threshold(struct chip_data
*chip
,
738 struct spi_device
*spi
,
739 u8 bits_per_word
, u32
*burst_code
,
742 struct pxa2xx_spi_chip
*chip_info
=
743 (struct pxa2xx_spi_chip
*)spi
->controller_data
;
750 /* Set the threshold (in registers) to equal the same amount of data
751 * as represented by burst size (in bytes). The computation below
752 * is (burst_size rounded up to nearest 8 byte, word or long word)
753 * divided by (bytes/register); the tx threshold is the inverse of
754 * the rx, so that there will always be enough data in the rx fifo
755 * to satisfy a burst, and there will always be enough space in the
756 * tx fifo to accept a burst (a tx burst will overwrite the fifo if
757 * there is not enough space), there must always remain enough empty
758 * space in the rx fifo for any data loaded to the tx fifo.
759 * Whenever burst_size (in bytes) equals bits/word, the fifo threshold
760 * will be 8, or half the fifo;
761 * The threshold can only be set to 2, 4 or 8, but not 16, because
762 * to burst 16 to the tx fifo, the fifo would have to be empty;
763 * however, the minimum fifo trigger level is 1, and the tx will
764 * request service when the fifo is at this level, with only 15 spaces.
767 /* find bytes/word */
768 if (bits_per_word
<= 8)
770 else if (bits_per_word
<= 16)
775 /* use struct pxa2xx_spi_chip->dma_burst_size if available */
777 req_burst_size
= chip_info
->dma_burst_size
;
779 switch (chip
->dma_burst_size
) {
781 /* if the default burst size is not set,
783 chip
->dma_burst_size
= DCMD_BURST8
;
795 if (req_burst_size
<= 8) {
796 *burst_code
= DCMD_BURST8
;
798 } else if (req_burst_size
<= 16) {
799 if (bytes_per_word
== 1) {
800 /* don't burst more than 1/2 the fifo */
801 *burst_code
= DCMD_BURST8
;
805 *burst_code
= DCMD_BURST16
;
809 if (bytes_per_word
== 1) {
810 /* don't burst more than 1/2 the fifo */
811 *burst_code
= DCMD_BURST8
;
814 } else if (bytes_per_word
== 2) {
815 /* don't burst more than 1/2 the fifo */
816 *burst_code
= DCMD_BURST16
;
820 *burst_code
= DCMD_BURST32
;
825 thresh_words
= burst_bytes
/ bytes_per_word
;
827 /* thresh_words will be between 2 and 8 */
828 *threshold
= (SSCR1_RxTresh(thresh_words
) & SSCR1_RFT
)
829 | (SSCR1_TxTresh(16-thresh_words
) & SSCR1_TFT
);
834 static unsigned int ssp_get_clk_div(struct ssp_device
*ssp
, int rate
)
836 unsigned long ssp_clk
= clk_get_rate(ssp
->clk
);
838 if (ssp
->type
== PXA25x_SSP
)
839 return ((ssp_clk
/ (2 * rate
) - 1) & 0xff) << 8;
841 return ((ssp_clk
/ rate
- 1) & 0xfff) << 8;
844 static void pump_transfers(unsigned long data
)
846 struct driver_data
*drv_data
= (struct driver_data
*)data
;
847 struct spi_message
*message
= NULL
;
848 struct spi_transfer
*transfer
= NULL
;
849 struct spi_transfer
*previous
= NULL
;
850 struct chip_data
*chip
= NULL
;
851 struct ssp_device
*ssp
= drv_data
->ssp
;
852 void __iomem
*reg
= drv_data
->ioaddr
;
858 u32 dma_thresh
= drv_data
->cur_chip
->dma_threshold
;
859 u32 dma_burst
= drv_data
->cur_chip
->dma_burst_size
;
861 /* Get current state information */
862 message
= drv_data
->cur_msg
;
863 transfer
= drv_data
->cur_transfer
;
864 chip
= drv_data
->cur_chip
;
866 /* Handle for abort */
867 if (message
->state
== ERROR_STATE
) {
868 message
->status
= -EIO
;
873 /* Handle end of message */
874 if (message
->state
== DONE_STATE
) {
880 /* Delay if requested at end of transfer before CS change */
881 if (message
->state
== RUNNING_STATE
) {
882 previous
= list_entry(transfer
->transfer_list
.prev
,
885 if (previous
->delay_usecs
)
886 udelay(previous
->delay_usecs
);
888 /* Drop chip select only if cs_change is requested */
889 if (previous
->cs_change
)
890 drv_data
->cs_control(PXA2XX_CS_DEASSERT
);
893 /* Check for transfers that need multiple DMA segments */
894 if (transfer
->len
> MAX_DMA_LEN
&& chip
->enable_dma
) {
896 /* reject already-mapped transfers; PIO won't always work */
897 if (message
->is_dma_mapped
898 || transfer
->rx_dma
|| transfer
->tx_dma
) {
899 dev_err(&drv_data
->pdev
->dev
,
900 "pump_transfers: mapped transfer length "
901 "of %u is greater than %d\n",
902 transfer
->len
, MAX_DMA_LEN
);
903 message
->status
= -EINVAL
;
908 /* warn ... we force this to PIO mode */
909 if (printk_ratelimit())
910 dev_warn(&message
->spi
->dev
, "pump_transfers: "
911 "DMA disabled for transfer length %ld "
913 (long)drv_data
->len
, MAX_DMA_LEN
);
916 /* Setup the transfer state based on the type of transfer */
917 if (flush(drv_data
) == 0) {
918 dev_err(&drv_data
->pdev
->dev
, "pump_transfers: flush failed\n");
919 message
->status
= -EIO
;
923 drv_data
->n_bytes
= chip
->n_bytes
;
924 drv_data
->dma_width
= chip
->dma_width
;
925 drv_data
->cs_control
= chip
->cs_control
;
926 drv_data
->tx
= (void *)transfer
->tx_buf
;
927 drv_data
->tx_end
= drv_data
->tx
+ transfer
->len
;
928 drv_data
->rx
= transfer
->rx_buf
;
929 drv_data
->rx_end
= drv_data
->rx
+ transfer
->len
;
930 drv_data
->rx_dma
= transfer
->rx_dma
;
931 drv_data
->tx_dma
= transfer
->tx_dma
;
932 drv_data
->len
= transfer
->len
& DCMD_LENGTH
;
933 drv_data
->write
= drv_data
->tx
? chip
->write
: null_writer
;
934 drv_data
->read
= drv_data
->rx
? chip
->read
: null_reader
;
936 /* Change speed and bit per word on a per transfer */
938 if (transfer
->speed_hz
|| transfer
->bits_per_word
) {
940 bits
= chip
->bits_per_word
;
941 speed
= chip
->speed_hz
;
943 if (transfer
->speed_hz
)
944 speed
= transfer
->speed_hz
;
946 if (transfer
->bits_per_word
)
947 bits
= transfer
->bits_per_word
;
949 clk_div
= ssp_get_clk_div(ssp
, speed
);
952 drv_data
->n_bytes
= 1;
953 drv_data
->dma_width
= DCMD_WIDTH1
;
954 drv_data
->read
= drv_data
->read
!= null_reader
?
955 u8_reader
: null_reader
;
956 drv_data
->write
= drv_data
->write
!= null_writer
?
957 u8_writer
: null_writer
;
958 } else if (bits
<= 16) {
959 drv_data
->n_bytes
= 2;
960 drv_data
->dma_width
= DCMD_WIDTH2
;
961 drv_data
->read
= drv_data
->read
!= null_reader
?
962 u16_reader
: null_reader
;
963 drv_data
->write
= drv_data
->write
!= null_writer
?
964 u16_writer
: null_writer
;
965 } else if (bits
<= 32) {
966 drv_data
->n_bytes
= 4;
967 drv_data
->dma_width
= DCMD_WIDTH4
;
968 drv_data
->read
= drv_data
->read
!= null_reader
?
969 u32_reader
: null_reader
;
970 drv_data
->write
= drv_data
->write
!= null_writer
?
971 u32_writer
: null_writer
;
973 /* if bits/word is changed in dma mode, then must check the
974 * thresholds and burst also */
975 if (chip
->enable_dma
) {
976 if (set_dma_burst_and_threshold(chip
, message
->spi
,
979 if (printk_ratelimit())
980 dev_warn(&message
->spi
->dev
,
982 "DMA burst size reduced to "
983 "match bits_per_word\n");
988 | SSCR0_DataSize(bits
> 16 ? bits
- 16 : bits
)
990 | (bits
> 16 ? SSCR0_EDSS
: 0);
993 message
->state
= RUNNING_STATE
;
995 /* Try to map dma buffer and do a dma transfer if successful, but
996 * only if the length is non-zero and less than MAX_DMA_LEN.
998 * Zero-length non-descriptor DMA is illegal on PXA2xx; force use
999 * of PIO instead. Care is needed above because the transfer may
1000 * have have been passed with buffers that are already dma mapped.
1001 * A zero-length transfer in PIO mode will not try to write/read
1002 * to/from the buffers
1004 * REVISIT large transfers are exactly where we most want to be
1005 * using DMA. If this happens much, split those transfers into
1006 * multiple DMA segments rather than forcing PIO.
1008 drv_data
->dma_mapped
= 0;
1009 if (drv_data
->len
> 0 && drv_data
->len
<= MAX_DMA_LEN
)
1010 drv_data
->dma_mapped
= map_dma_buffers(drv_data
);
1011 if (drv_data
->dma_mapped
) {
1013 /* Ensure we have the correct interrupt handler */
1014 drv_data
->transfer_handler
= dma_transfer
;
1016 /* Setup rx DMA Channel */
1017 DCSR(drv_data
->rx_channel
) = RESET_DMA_CHANNEL
;
1018 DSADR(drv_data
->rx_channel
) = drv_data
->ssdr_physical
;
1019 DTADR(drv_data
->rx_channel
) = drv_data
->rx_dma
;
1020 if (drv_data
->rx
== drv_data
->null_dma_buf
)
1021 /* No target address increment */
1022 DCMD(drv_data
->rx_channel
) = DCMD_FLOWSRC
1023 | drv_data
->dma_width
1027 DCMD(drv_data
->rx_channel
) = DCMD_INCTRGADDR
1029 | drv_data
->dma_width
1033 /* Setup tx DMA Channel */
1034 DCSR(drv_data
->tx_channel
) = RESET_DMA_CHANNEL
;
1035 DSADR(drv_data
->tx_channel
) = drv_data
->tx_dma
;
1036 DTADR(drv_data
->tx_channel
) = drv_data
->ssdr_physical
;
1037 if (drv_data
->tx
== drv_data
->null_dma_buf
)
1038 /* No source address increment */
1039 DCMD(drv_data
->tx_channel
) = DCMD_FLOWTRG
1040 | drv_data
->dma_width
1044 DCMD(drv_data
->tx_channel
) = DCMD_INCSRCADDR
1046 | drv_data
->dma_width
1050 /* Enable dma end irqs on SSP to detect end of transfer */
1051 if (drv_data
->ssp_type
== PXA25x_SSP
)
1052 DCMD(drv_data
->tx_channel
) |= DCMD_ENDIRQEN
;
1054 /* Clear status and start DMA engine */
1055 cr1
= chip
->cr1
| dma_thresh
| drv_data
->dma_cr1
;
1056 write_SSSR(drv_data
->clear_sr
, reg
);
1057 DCSR(drv_data
->rx_channel
) |= DCSR_RUN
;
1058 DCSR(drv_data
->tx_channel
) |= DCSR_RUN
;
1060 /* Ensure we have the correct interrupt handler */
1061 drv_data
->transfer_handler
= interrupt_transfer
;
1064 cr1
= chip
->cr1
| chip
->threshold
| drv_data
->int_cr1
;
1065 write_SSSR(drv_data
->clear_sr
, reg
);
1068 /* see if we need to reload the config registers */
1069 if ((read_SSCR0(reg
) != cr0
)
1070 || (read_SSCR1(reg
) & SSCR1_CHANGE_MASK
) !=
1071 (cr1
& SSCR1_CHANGE_MASK
)) {
1073 /* stop the SSP, and update the other bits */
1074 write_SSCR0(cr0
& ~SSCR0_SSE
, reg
);
1075 if (drv_data
->ssp_type
!= PXA25x_SSP
)
1076 write_SSTO(chip
->timeout
, reg
);
1077 /* first set CR1 without interrupt and service enables */
1078 write_SSCR1(cr1
& SSCR1_CHANGE_MASK
, reg
);
1079 /* restart the SSP */
1080 write_SSCR0(cr0
, reg
);
1083 if (drv_data
->ssp_type
!= PXA25x_SSP
)
1084 write_SSTO(chip
->timeout
, reg
);
1087 /* FIXME, need to handle cs polarity,
1088 * this driver uses struct pxa2xx_spi_chip.cs_control to
1089 * specify a CS handling function, and it ignores most
1090 * struct spi_device.mode[s], including SPI_CS_HIGH */
1091 drv_data
->cs_control(PXA2XX_CS_ASSERT
);
1093 /* after chip select, release the data by enabling service
1094 * requests and interrupts, without changing any mode bits */
1095 write_SSCR1(cr1
, reg
);
1098 static void pump_messages(struct work_struct
*work
)
1100 struct driver_data
*drv_data
=
1101 container_of(work
, struct driver_data
, pump_messages
);
1102 unsigned long flags
;
1104 /* Lock queue and check for queue work */
1105 spin_lock_irqsave(&drv_data
->lock
, flags
);
1106 if (list_empty(&drv_data
->queue
) || drv_data
->run
== QUEUE_STOPPED
) {
1108 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1112 /* Make sure we are not already running a message */
1113 if (drv_data
->cur_msg
) {
1114 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1118 /* Extract head of queue */
1119 drv_data
->cur_msg
= list_entry(drv_data
->queue
.next
,
1120 struct spi_message
, queue
);
1121 list_del_init(&drv_data
->cur_msg
->queue
);
1123 /* Initial message state*/
1124 drv_data
->cur_msg
->state
= START_STATE
;
1125 drv_data
->cur_transfer
= list_entry(drv_data
->cur_msg
->transfers
.next
,
1126 struct spi_transfer
,
1129 /* prepare to setup the SSP, in pump_transfers, using the per
1130 * chip configuration */
1131 drv_data
->cur_chip
= spi_get_ctldata(drv_data
->cur_msg
->spi
);
1133 /* Mark as busy and launch transfers */
1134 tasklet_schedule(&drv_data
->pump_transfers
);
1137 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1140 static int transfer(struct spi_device
*spi
, struct spi_message
*msg
)
1142 struct driver_data
*drv_data
= spi_master_get_devdata(spi
->master
);
1143 unsigned long flags
;
1145 spin_lock_irqsave(&drv_data
->lock
, flags
);
1147 if (drv_data
->run
== QUEUE_STOPPED
) {
1148 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1152 msg
->actual_length
= 0;
1153 msg
->status
= -EINPROGRESS
;
1154 msg
->state
= START_STATE
;
1156 list_add_tail(&msg
->queue
, &drv_data
->queue
);
1158 if (drv_data
->run
== QUEUE_RUNNING
&& !drv_data
->busy
)
1159 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
1161 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1166 /* the spi->mode bits understood by this driver: */
1167 #define MODEBITS (SPI_CPOL | SPI_CPHA)
1169 static int setup(struct spi_device
*spi
)
1171 struct pxa2xx_spi_chip
*chip_info
= NULL
;
1172 struct chip_data
*chip
;
1173 struct driver_data
*drv_data
= spi_master_get_devdata(spi
->master
);
1174 struct ssp_device
*ssp
= drv_data
->ssp
;
1175 unsigned int clk_div
;
1176 uint tx_thres
= TX_THRESH_DFLT
;
1177 uint rx_thres
= RX_THRESH_DFLT
;
1179 if (!spi
->bits_per_word
)
1180 spi
->bits_per_word
= 8;
1182 if (drv_data
->ssp_type
!= PXA25x_SSP
1183 && (spi
->bits_per_word
< 4 || spi
->bits_per_word
> 32)) {
1184 dev_err(&spi
->dev
, "failed setup: ssp_type=%d, bits/wrd=%d "
1185 "b/w not 4-32 for type non-PXA25x_SSP\n",
1186 drv_data
->ssp_type
, spi
->bits_per_word
);
1189 else if (drv_data
->ssp_type
== PXA25x_SSP
1190 && (spi
->bits_per_word
< 4
1191 || spi
->bits_per_word
> 16)) {
1192 dev_err(&spi
->dev
, "failed setup: ssp_type=%d, bits/wrd=%d "
1193 "b/w not 4-16 for type PXA25x_SSP\n",
1194 drv_data
->ssp_type
, spi
->bits_per_word
);
1198 if (spi
->mode
& ~MODEBITS
) {
1199 dev_dbg(&spi
->dev
, "setup: unsupported mode bits %x\n",
1200 spi
->mode
& ~MODEBITS
);
1204 /* Only alloc on first setup */
1205 chip
= spi_get_ctldata(spi
);
1207 chip
= kzalloc(sizeof(struct chip_data
), GFP_KERNEL
);
1210 "failed setup: can't allocate chip data\n");
1214 chip
->cs_control
= null_cs_control
;
1215 chip
->enable_dma
= 0;
1216 chip
->timeout
= TIMOUT_DFLT
;
1217 chip
->dma_burst_size
= drv_data
->master_info
->enable_dma
?
1221 /* protocol drivers may change the chip settings, so...
1222 * if chip_info exists, use it */
1223 chip_info
= spi
->controller_data
;
1225 /* chip_info isn't always needed */
1228 if (chip_info
->cs_control
)
1229 chip
->cs_control
= chip_info
->cs_control
;
1230 if (chip_info
->timeout
)
1231 chip
->timeout
= chip_info
->timeout
;
1232 if (chip_info
->tx_threshold
)
1233 tx_thres
= chip_info
->tx_threshold
;
1234 if (chip_info
->rx_threshold
)
1235 rx_thres
= chip_info
->rx_threshold
;
1236 chip
->enable_dma
= drv_data
->master_info
->enable_dma
;
1237 chip
->dma_threshold
= 0;
1238 if (chip_info
->enable_loopback
)
1239 chip
->cr1
= SSCR1_LBM
;
1242 chip
->threshold
= (SSCR1_RxTresh(rx_thres
) & SSCR1_RFT
) |
1243 (SSCR1_TxTresh(tx_thres
) & SSCR1_TFT
);
1245 /* set dma burst and threshold outside of chip_info path so that if
1246 * chip_info goes away after setting chip->enable_dma, the
1247 * burst and threshold can still respond to changes in bits_per_word */
1248 if (chip
->enable_dma
) {
1249 /* set up legal burst and threshold for dma */
1250 if (set_dma_burst_and_threshold(chip
, spi
, spi
->bits_per_word
,
1251 &chip
->dma_burst_size
,
1252 &chip
->dma_threshold
)) {
1253 dev_warn(&spi
->dev
, "in setup: DMA burst size reduced "
1254 "to match bits_per_word\n");
1258 clk_div
= ssp_get_clk_div(ssp
, spi
->max_speed_hz
);
1259 chip
->speed_hz
= spi
->max_speed_hz
;
1263 | SSCR0_DataSize(spi
->bits_per_word
> 16 ?
1264 spi
->bits_per_word
- 16 : spi
->bits_per_word
)
1266 | (spi
->bits_per_word
> 16 ? SSCR0_EDSS
: 0);
1267 chip
->cr1
&= ~(SSCR1_SPO
| SSCR1_SPH
);
1268 chip
->cr1
|= (((spi
->mode
& SPI_CPHA
) != 0) ? SSCR1_SPH
: 0)
1269 | (((spi
->mode
& SPI_CPOL
) != 0) ? SSCR1_SPO
: 0);
1271 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1272 if (drv_data
->ssp_type
!= PXA25x_SSP
)
1273 dev_dbg(&spi
->dev
, "%d bits/word, %ld Hz, mode %d, %s\n",
1275 clk_get_rate(ssp
->clk
)
1276 / (1 + ((chip
->cr0
& SSCR0_SCR
) >> 8)),
1278 chip
->enable_dma
? "DMA" : "PIO");
1280 dev_dbg(&spi
->dev
, "%d bits/word, %ld Hz, mode %d, %s\n",
1282 clk_get_rate(ssp
->clk
) / 2
1283 / (1 + ((chip
->cr0
& SSCR0_SCR
) >> 8)),
1285 chip
->enable_dma
? "DMA" : "PIO");
1287 if (spi
->bits_per_word
<= 8) {
1289 chip
->dma_width
= DCMD_WIDTH1
;
1290 chip
->read
= u8_reader
;
1291 chip
->write
= u8_writer
;
1292 } else if (spi
->bits_per_word
<= 16) {
1294 chip
->dma_width
= DCMD_WIDTH2
;
1295 chip
->read
= u16_reader
;
1296 chip
->write
= u16_writer
;
1297 } else if (spi
->bits_per_word
<= 32) {
1298 chip
->cr0
|= SSCR0_EDSS
;
1300 chip
->dma_width
= DCMD_WIDTH4
;
1301 chip
->read
= u32_reader
;
1302 chip
->write
= u32_writer
;
1304 dev_err(&spi
->dev
, "invalid wordsize\n");
1307 chip
->bits_per_word
= spi
->bits_per_word
;
1309 spi_set_ctldata(spi
, chip
);
1314 static void cleanup(struct spi_device
*spi
)
1316 struct chip_data
*chip
= spi_get_ctldata(spi
);
1321 static int __init
init_queue(struct driver_data
*drv_data
)
1323 INIT_LIST_HEAD(&drv_data
->queue
);
1324 spin_lock_init(&drv_data
->lock
);
1326 drv_data
->run
= QUEUE_STOPPED
;
1329 tasklet_init(&drv_data
->pump_transfers
,
1330 pump_transfers
, (unsigned long)drv_data
);
1332 INIT_WORK(&drv_data
->pump_messages
, pump_messages
);
1333 drv_data
->workqueue
= create_singlethread_workqueue(
1334 dev_name(drv_data
->master
->dev
.parent
));
1335 if (drv_data
->workqueue
== NULL
)
1341 static int start_queue(struct driver_data
*drv_data
)
1343 unsigned long flags
;
1345 spin_lock_irqsave(&drv_data
->lock
, flags
);
1347 if (drv_data
->run
== QUEUE_RUNNING
|| drv_data
->busy
) {
1348 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1352 drv_data
->run
= QUEUE_RUNNING
;
1353 drv_data
->cur_msg
= NULL
;
1354 drv_data
->cur_transfer
= NULL
;
1355 drv_data
->cur_chip
= NULL
;
1356 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1358 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
1363 static int stop_queue(struct driver_data
*drv_data
)
1365 unsigned long flags
;
1366 unsigned limit
= 500;
1369 spin_lock_irqsave(&drv_data
->lock
, flags
);
1371 /* This is a bit lame, but is optimized for the common execution path.
1372 * A wait_queue on the drv_data->busy could be used, but then the common
1373 * execution path (pump_messages) would be required to call wake_up or
1374 * friends on every SPI message. Do this instead */
1375 drv_data
->run
= QUEUE_STOPPED
;
1376 while (!list_empty(&drv_data
->queue
) && drv_data
->busy
&& limit
--) {
1377 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1379 spin_lock_irqsave(&drv_data
->lock
, flags
);
1382 if (!list_empty(&drv_data
->queue
) || drv_data
->busy
)
1385 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1390 static int destroy_queue(struct driver_data
*drv_data
)
1394 status
= stop_queue(drv_data
);
1395 /* we are unloading the module or failing to load (only two calls
1396 * to this routine), and neither call can handle a return value.
1397 * However, destroy_workqueue calls flush_workqueue, and that will
1398 * block until all work is done. If the reason that stop_queue
1399 * timed out is that the work will never finish, then it does no
1400 * good to call destroy_workqueue, so return anyway. */
1404 destroy_workqueue(drv_data
->workqueue
);
1409 static int __init
pxa2xx_spi_probe(struct platform_device
*pdev
)
1411 struct device
*dev
= &pdev
->dev
;
1412 struct pxa2xx_spi_master
*platform_info
;
1413 struct spi_master
*master
;
1414 struct driver_data
*drv_data
;
1415 struct ssp_device
*ssp
;
1418 platform_info
= dev
->platform_data
;
1420 ssp
= ssp_request(pdev
->id
, pdev
->name
);
1422 dev_err(&pdev
->dev
, "failed to request SSP%d\n", pdev
->id
);
1426 /* Allocate master with space for drv_data and null dma buffer */
1427 master
= spi_alloc_master(dev
, sizeof(struct driver_data
) + 16);
1429 dev_err(&pdev
->dev
, "cannot alloc spi_master\n");
1433 drv_data
= spi_master_get_devdata(master
);
1434 drv_data
->master
= master
;
1435 drv_data
->master_info
= platform_info
;
1436 drv_data
->pdev
= pdev
;
1437 drv_data
->ssp
= ssp
;
1439 master
->bus_num
= pdev
->id
;
1440 master
->num_chipselect
= platform_info
->num_chipselect
;
1441 master
->cleanup
= cleanup
;
1442 master
->setup
= setup
;
1443 master
->transfer
= transfer
;
1445 drv_data
->ssp_type
= ssp
->type
;
1446 drv_data
->null_dma_buf
= (u32
*)ALIGN((u32
)(drv_data
+
1447 sizeof(struct driver_data
)), 8);
1449 drv_data
->ioaddr
= ssp
->mmio_base
;
1450 drv_data
->ssdr_physical
= ssp
->phys_base
+ SSDR
;
1451 if (ssp
->type
== PXA25x_SSP
) {
1452 drv_data
->int_cr1
= SSCR1_TIE
| SSCR1_RIE
;
1453 drv_data
->dma_cr1
= 0;
1454 drv_data
->clear_sr
= SSSR_ROR
;
1455 drv_data
->mask_sr
= SSSR_RFS
| SSSR_TFS
| SSSR_ROR
;
1457 drv_data
->int_cr1
= SSCR1_TIE
| SSCR1_RIE
| SSCR1_TINTE
;
1458 drv_data
->dma_cr1
= SSCR1_TSRE
| SSCR1_RSRE
| SSCR1_TINTE
;
1459 drv_data
->clear_sr
= SSSR_ROR
| SSSR_TINT
;
1460 drv_data
->mask_sr
= SSSR_TINT
| SSSR_RFS
| SSSR_TFS
| SSSR_ROR
;
1463 status
= request_irq(ssp
->irq
, ssp_int
, 0, dev_name(dev
), drv_data
);
1465 dev_err(&pdev
->dev
, "cannot get IRQ %d\n", ssp
->irq
);
1466 goto out_error_master_alloc
;
1469 /* Setup DMA if requested */
1470 drv_data
->tx_channel
= -1;
1471 drv_data
->rx_channel
= -1;
1472 if (platform_info
->enable_dma
) {
1474 /* Get two DMA channels (rx and tx) */
1475 drv_data
->rx_channel
= pxa_request_dma("pxa2xx_spi_ssp_rx",
1479 if (drv_data
->rx_channel
< 0) {
1480 dev_err(dev
, "problem (%d) requesting rx channel\n",
1481 drv_data
->rx_channel
);
1483 goto out_error_irq_alloc
;
1485 drv_data
->tx_channel
= pxa_request_dma("pxa2xx_spi_ssp_tx",
1489 if (drv_data
->tx_channel
< 0) {
1490 dev_err(dev
, "problem (%d) requesting tx channel\n",
1491 drv_data
->tx_channel
);
1493 goto out_error_dma_alloc
;
1496 DRCMR(ssp
->drcmr_rx
) = DRCMR_MAPVLD
| drv_data
->rx_channel
;
1497 DRCMR(ssp
->drcmr_tx
) = DRCMR_MAPVLD
| drv_data
->tx_channel
;
1500 /* Enable SOC clock */
1501 clk_enable(ssp
->clk
);
1503 /* Load default SSP configuration */
1504 write_SSCR0(0, drv_data
->ioaddr
);
1505 write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT
) |
1506 SSCR1_TxTresh(TX_THRESH_DFLT
),
1508 write_SSCR0(SSCR0_SerClkDiv(2)
1510 | SSCR0_DataSize(8),
1512 if (drv_data
->ssp_type
!= PXA25x_SSP
)
1513 write_SSTO(0, drv_data
->ioaddr
);
1514 write_SSPSP(0, drv_data
->ioaddr
);
1516 /* Initial and start queue */
1517 status
= init_queue(drv_data
);
1519 dev_err(&pdev
->dev
, "problem initializing queue\n");
1520 goto out_error_clock_enabled
;
1522 status
= start_queue(drv_data
);
1524 dev_err(&pdev
->dev
, "problem starting queue\n");
1525 goto out_error_clock_enabled
;
1528 /* Register with the SPI framework */
1529 platform_set_drvdata(pdev
, drv_data
);
1530 status
= spi_register_master(master
);
1532 dev_err(&pdev
->dev
, "problem registering spi master\n");
1533 goto out_error_queue_alloc
;
1538 out_error_queue_alloc
:
1539 destroy_queue(drv_data
);
1541 out_error_clock_enabled
:
1542 clk_disable(ssp
->clk
);
1544 out_error_dma_alloc
:
1545 if (drv_data
->tx_channel
!= -1)
1546 pxa_free_dma(drv_data
->tx_channel
);
1547 if (drv_data
->rx_channel
!= -1)
1548 pxa_free_dma(drv_data
->rx_channel
);
1550 out_error_irq_alloc
:
1551 free_irq(ssp
->irq
, drv_data
);
1553 out_error_master_alloc
:
1554 spi_master_put(master
);
1559 static int pxa2xx_spi_remove(struct platform_device
*pdev
)
1561 struct driver_data
*drv_data
= platform_get_drvdata(pdev
);
1562 struct ssp_device
*ssp
;
1567 ssp
= drv_data
->ssp
;
1569 /* Remove the queue */
1570 status
= destroy_queue(drv_data
);
1572 /* the kernel does not check the return status of this
1573 * this routine (mod->exit, within the kernel). Therefore
1574 * nothing is gained by returning from here, the module is
1575 * going away regardless, and we should not leave any more
1576 * resources allocated than necessary. We cannot free the
1577 * message memory in drv_data->queue, but we can release the
1578 * resources below. I think the kernel should honor -EBUSY
1580 dev_err(&pdev
->dev
, "pxa2xx_spi_remove: workqueue will not "
1581 "complete, message memory not freed\n");
1583 /* Disable the SSP at the peripheral and SOC level */
1584 write_SSCR0(0, drv_data
->ioaddr
);
1585 clk_disable(ssp
->clk
);
1588 if (drv_data
->master_info
->enable_dma
) {
1589 DRCMR(ssp
->drcmr_rx
) = 0;
1590 DRCMR(ssp
->drcmr_tx
) = 0;
1591 pxa_free_dma(drv_data
->tx_channel
);
1592 pxa_free_dma(drv_data
->rx_channel
);
1596 free_irq(ssp
->irq
, drv_data
);
1601 /* Disconnect from the SPI framework */
1602 spi_unregister_master(drv_data
->master
);
1604 /* Prevent double remove */
1605 platform_set_drvdata(pdev
, NULL
);
1610 static void pxa2xx_spi_shutdown(struct platform_device
*pdev
)
1614 if ((status
= pxa2xx_spi_remove(pdev
)) != 0)
1615 dev_err(&pdev
->dev
, "shutdown failed with %d\n", status
);
1620 static int pxa2xx_spi_suspend(struct platform_device
*pdev
, pm_message_t state
)
1622 struct driver_data
*drv_data
= platform_get_drvdata(pdev
);
1623 struct ssp_device
*ssp
= drv_data
->ssp
;
1626 status
= stop_queue(drv_data
);
1629 write_SSCR0(0, drv_data
->ioaddr
);
1630 clk_disable(ssp
->clk
);
1635 static int pxa2xx_spi_resume(struct platform_device
*pdev
)
1637 struct driver_data
*drv_data
= platform_get_drvdata(pdev
);
1638 struct ssp_device
*ssp
= drv_data
->ssp
;
1641 /* Enable the SSP clock */
1642 clk_enable(ssp
->clk
);
1644 /* Start the queue running */
1645 status
= start_queue(drv_data
);
1647 dev_err(&pdev
->dev
, "problem starting queue (%d)\n", status
);
1654 #define pxa2xx_spi_suspend NULL
1655 #define pxa2xx_spi_resume NULL
1656 #endif /* CONFIG_PM */
1658 static struct platform_driver driver
= {
1660 .name
= "pxa2xx-spi",
1661 .owner
= THIS_MODULE
,
1663 .remove
= pxa2xx_spi_remove
,
1664 .shutdown
= pxa2xx_spi_shutdown
,
1665 .suspend
= pxa2xx_spi_suspend
,
1666 .resume
= pxa2xx_spi_resume
,
1669 static int __init
pxa2xx_spi_init(void)
1671 return platform_driver_probe(&driver
, pxa2xx_spi_probe
);
1673 module_init(pxa2xx_spi_init
);
1675 static void __exit
pxa2xx_spi_exit(void)
1677 platform_driver_unregister(&driver
);
1679 module_exit(pxa2xx_spi_exit
);