drivers/scsi/qla2xxx/qla_fw.h

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2008 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7 #ifndef __QLA_FW_H
   8 #define __QLA_FW_H
   9
  10 #define MBS_CHECKSUM_ERROR      0x4010
  11 #define MBS_INVALID_PRODUCT_KEY 0x4020
  12
  13 /*
  14  * Firmware Options.
  15  */
  16 #define FO1_ENABLE_PUREX        BIT_10
  17 #define FO1_DISABLE_LED_CTRL    BIT_6
  18 #define FO1_ENABLE_8016         BIT_0
  19 #define FO2_ENABLE_SEL_CLASS2   BIT_5
  20 #define FO3_NO_ABTS_ON_LINKDOWN BIT_14
  21 #define FO3_HOLD_STS_IOCB       BIT_12
  22
  23 /*
  24  * Port Database structure definition for ISP 24xx.
  25  */
  26 #define PDO_FORCE_ADISC         BIT_1
  27 #define PDO_FORCE_PLOGI         BIT_0
  28
  29
  30 #define PORT_DATABASE_24XX_SIZE         64
  31 struct port_database_24xx {
  32         uint16_t flags;
  33 #define PDF_TASK_RETRY_ID       BIT_14
  34 #define PDF_FC_TAPE             BIT_7
  35 #define PDF_ACK0_CAPABLE        BIT_6
  36 #define PDF_FCP2_CONF           BIT_5
  37 #define PDF_CLASS_2             BIT_4
  38 #define PDF_HARD_ADDR           BIT_1
  39
  40         uint8_t current_login_state;
  41         uint8_t last_login_state;
  42 #define PDS_PLOGI_PENDING       0x03
  43 #define PDS_PLOGI_COMPLETE      0x04
  44 #define PDS_PRLI_PENDING        0x05
  45 #define PDS_PRLI_COMPLETE       0x06
  46 #define PDS_PORT_UNAVAILABLE    0x07
  47 #define PDS_PRLO_PENDING        0x09
  48 #define PDS_LOGO_PENDING        0x11
  49 #define PDS_PRLI2_PENDING       0x12
  50
  51         uint8_t hard_address[3];
  52         uint8_t reserved_1;
  53
  54         uint8_t port_id[3];
  55         uint8_t sequence_id;
  56
  57         uint16_t port_timer;
  58
  59         uint16_t nport_handle;                  /* N_PORT handle. */
  60
  61         uint16_t receive_data_size;
  62         uint16_t reserved_2;
  63
  64         uint8_t prli_svc_param_word_0[2];       /* Big endian */
  65                                                 /* Bits 15-0 of word 0 */
  66         uint8_t prli_svc_param_word_3[2];       /* Big endian */
  67                                                 /* Bits 15-0 of word 3 */
  68
  69         uint8_t port_name[WWN_SIZE];
  70         uint8_t node_name[WWN_SIZE];
  71
  72         uint8_t reserved_3[24];
  73 };
  74
  75 struct vp_database_24xx {
  76         uint16_t vp_status;
  77         uint8_t  options;
  78         uint8_t  id;
  79         uint8_t  port_name[WWN_SIZE];
  80         uint8_t  node_name[WWN_SIZE];
  81         uint16_t port_id_low;
  82         uint16_t port_id_high;
  83 };
  84
  85 struct nvram_24xx {
  86         /* NVRAM header. */
  87         uint8_t id[4];
  88         uint16_t nvram_version;
  89         uint16_t reserved_0;
  90
  91         /* Firmware Initialization Control Block. */
  92         uint16_t version;
  93         uint16_t reserved_1;
  94         uint16_t frame_payload_size;
  95         uint16_t execution_throttle;
  96         uint16_t exchange_count;
  97         uint16_t hard_address;
  98
  99         uint8_t port_name[WWN_SIZE];
 100         uint8_t node_name[WWN_SIZE];
 101
 102         uint16_t login_retry_count;
 103         uint16_t link_down_on_nos;
 104         uint16_t interrupt_delay_timer;
 105         uint16_t login_timeout;
 106
 107         uint32_t firmware_options_1;
 108         uint32_t firmware_options_2;
 109         uint32_t firmware_options_3;
 110
 111         /* Offset 56. */
 112
 113         /*
 114          * BIT 0     = Control Enable
 115          * BIT 1-15  =
 116          *
 117          * BIT 0-7   = Reserved
 118          * BIT 8-10  = Output Swing 1G
 119          * BIT 11-13 = Output Emphasis 1G
 120          * BIT 14-15 = Reserved
 121          *
 122          * BIT 0-7   = Reserved
 123          * BIT 8-10  = Output Swing 2G
 124          * BIT 11-13 = Output Emphasis 2G
 125          * BIT 14-15 = Reserved
 126          *
 127          * BIT 0-7   = Reserved
 128          * BIT 8-10  = Output Swing 4G
 129          * BIT 11-13 = Output Emphasis 4G
 130          * BIT 14-15 = Reserved
 131          */
 132         uint16_t seriallink_options[4];
 133
 134         uint16_t reserved_2[16];
 135
 136         /* Offset 96. */
 137         uint16_t reserved_3[16];
 138
 139         /* PCIe table entries. */
 140         uint16_t reserved_4[16];
 141
 142         /* Offset 160. */
 143         uint16_t reserved_5[16];
 144
 145         /* Offset 192. */
 146         uint16_t reserved_6[16];
 147
 148         /* Offset 224. */
 149         uint16_t reserved_7[16];
 150
 151         /*
 152          * BIT 0  = Enable spinup delay
 153          * BIT 1  = Disable BIOS
 154          * BIT 2  = Enable Memory Map BIOS
 155          * BIT 3  = Enable Selectable Boot
 156          * BIT 4  = Disable RISC code load
 157          * BIT 5  = Disable Serdes
 158          * BIT 6  =
 159          * BIT 7  =
 160          *
 161          * BIT 8  =
 162          * BIT 9  =
 163          * BIT 10 = Enable lip full login
 164          * BIT 11 = Enable target reset
 165          * BIT 12 =
 166          * BIT 13 =
 167          * BIT 14 =
 168          * BIT 15 = Enable alternate WWN
 169          *
 170          * BIT 16-31 =
 171          */
 172         uint32_t host_p;
 173
 174         uint8_t alternate_port_name[WWN_SIZE];
 175         uint8_t alternate_node_name[WWN_SIZE];
 176
 177         uint8_t boot_port_name[WWN_SIZE];
 178         uint16_t boot_lun_number;
 179         uint16_t reserved_8;
 180
 181         uint8_t alt1_boot_port_name[WWN_SIZE];
 182         uint16_t alt1_boot_lun_number;
 183         uint16_t reserved_9;
 184
 185         uint8_t alt2_boot_port_name[WWN_SIZE];
 186         uint16_t alt2_boot_lun_number;
 187         uint16_t reserved_10;
 188
 189         uint8_t alt3_boot_port_name[WWN_SIZE];
 190         uint16_t alt3_boot_lun_number;
 191         uint16_t reserved_11;
 192
 193         /*
 194          * BIT 0 = Selective Login
 195          * BIT 1 = Alt-Boot Enable
 196          * BIT 2 = Reserved
 197          * BIT 3 = Boot Order List
 198          * BIT 4 = Reserved
 199          * BIT 5 = Selective LUN
 200          * BIT 6 = Reserved
 201          * BIT 7-31 =
 202          */
 203         uint32_t efi_parameters;
 204
 205         uint8_t reset_delay;
 206         uint8_t reserved_12;
 207         uint16_t reserved_13;
 208
 209         uint16_t boot_id_number;
 210         uint16_t reserved_14;
 211
 212         uint16_t max_luns_per_target;
 213         uint16_t reserved_15;
 214
 215         uint16_t port_down_retry_count;
 216         uint16_t link_down_timeout;
 217
 218         /* FCode parameters. */
 219         uint16_t fcode_parameter;
 220
 221         uint16_t reserved_16[3];
 222
 223         /* Offset 352. */
 224         uint8_t prev_drv_ver_major;
 225         uint8_t prev_drv_ver_submajob;
 226         uint8_t prev_drv_ver_minor;
 227         uint8_t prev_drv_ver_subminor;
 228
 229         uint16_t prev_bios_ver_major;
 230         uint16_t prev_bios_ver_minor;
 231
 232         uint16_t prev_efi_ver_major;
 233         uint16_t prev_efi_ver_minor;
 234
 235         uint16_t prev_fw_ver_major;
 236         uint8_t prev_fw_ver_minor;
 237         uint8_t prev_fw_ver_subminor;
 238
 239         uint16_t reserved_17[8];
 240
 241         /* Offset 384. */
 242         uint16_t reserved_18[16];
 243
 244         /* Offset 416. */
 245         uint16_t reserved_19[16];
 246
 247         /* Offset 448. */
 248         uint16_t reserved_20[16];
 249
 250         /* Offset 480. */
 251         uint8_t model_name[16];
 252
 253         uint16_t reserved_21[2];
 254
 255         /* Offset 500. */
 256         /* HW Parameter Block. */
 257         uint16_t pcie_table_sig;
 258         uint16_t pcie_table_offset;
 259
 260         uint16_t subsystem_vendor_id;
 261         uint16_t subsystem_device_id;
 262
 263         uint32_t checksum;
 264 };
 265
 266 /*
 267  * ISP Initialization Control Block.
 268  * Little endian except where noted.
 269  */
 270 #define ICB_VERSION 1
 271 struct init_cb_24xx {
 272         uint16_t version;
 273         uint16_t reserved_1;
 274
 275         uint16_t frame_payload_size;
 276         uint16_t execution_throttle;
 277         uint16_t exchange_count;
 278
 279         uint16_t hard_address;
 280
 281         uint8_t port_name[WWN_SIZE];            /* Big endian. */
 282         uint8_t node_name[WWN_SIZE];            /* Big endian. */
 283
 284         uint16_t response_q_inpointer;
 285         uint16_t request_q_outpointer;
 286
 287         uint16_t login_retry_count;
 288
 289         uint16_t prio_request_q_outpointer;
 290
 291         uint16_t response_q_length;
 292         uint16_t request_q_length;
 293
 294         uint16_t link_down_on_nos;              /* Milliseconds. */
 295
 296         uint16_t prio_request_q_length;
 297
 298         uint32_t request_q_address[2];
 299         uint32_t response_q_address[2];
 300         uint32_t prio_request_q_address[2];
 301
 302         uint16_t msix;
 303         uint8_t reserved_2[6];
 304
 305         uint16_t atio_q_inpointer;
 306         uint16_t atio_q_length;
 307         uint32_t atio_q_address[2];
 308
 309         uint16_t interrupt_delay_timer;         /* 100us increments. */
 310         uint16_t login_timeout;
 311
 312         /*
 313          * BIT 0  = Enable Hard Loop Id
 314          * BIT 1  = Enable Fairness
 315          * BIT 2  = Enable Full-Duplex
 316          * BIT 3  = Reserved
 317          * BIT 4  = Enable Target Mode
 318          * BIT 5  = Disable Initiator Mode
 319          * BIT 6  = Reserved
 320          * BIT 7  = Reserved
 321          *
 322          * BIT 8  = Reserved
 323          * BIT 9  = Non Participating LIP
 324          * BIT 10 = Descending Loop ID Search
 325          * BIT 11 = Acquire Loop ID in LIPA
 326          * BIT 12 = Reserved
 327          * BIT 13 = Full Login after LIP
 328          * BIT 14 = Node Name Option
 329          * BIT 15-31 = Reserved
 330          */
 331         uint32_t firmware_options_1;
 332
 333         /*
 334          * BIT 0  = Operation Mode bit 0
 335          * BIT 1  = Operation Mode bit 1
 336          * BIT 2  = Operation Mode bit 2
 337          * BIT 3  = Operation Mode bit 3
 338          * BIT 4  = Connection Options bit 0
 339          * BIT 5  = Connection Options bit 1
 340          * BIT 6  = Connection Options bit 2
 341          * BIT 7  = Enable Non part on LIHA failure
 342          *
 343          * BIT 8  = Enable Class 2
 344          * BIT 9  = Enable ACK0
 345          * BIT 10 = Reserved
 346          * BIT 11 = Enable FC-SP Security
 347          * BIT 12 = FC Tape Enable
 348          * BIT 13 = Reserved
 349          * BIT 14 = Enable Target PRLI Control
 350          * BIT 15-31 = Reserved
 351          */
 352         uint32_t firmware_options_2;
 353
 354         /*
 355          * BIT 0  = Reserved
 356          * BIT 1  = Soft ID only
 357          * BIT 2  = Reserved
 358          * BIT 3  = Reserved
 359          * BIT 4  = FCP RSP Payload bit 0
 360          * BIT 5  = FCP RSP Payload bit 1
 361          * BIT 6  = Enable Receive Out-of-Order data frame handling
 362          * BIT 7  = Disable Automatic PLOGI on Local Loop
 363          *
 364          * BIT 8  = Reserved
 365          * BIT 9  = Enable Out-of-Order FCP_XFER_RDY relative offset handling
 366          * BIT 10 = Reserved
 367          * BIT 11 = Reserved
 368          * BIT 12 = Reserved
 369          * BIT 13 = Data Rate bit 0
 370          * BIT 14 = Data Rate bit 1
 371          * BIT 15 = Data Rate bit 2
 372          * BIT 16 = Enable 75 ohm Termination Select
 373          * BIT 17-31 = Reserved
 374          */
 375         uint32_t firmware_options_3;
 376         uint16_t qos;
 377         uint16_t rid;
 378         uint8_t  reserved_3[20];
 379 };
 380
 381 /*
 382  * ISP queue - command entry structure definition.
 383  */
 384 #define COMMAND_TYPE_6  0x48            /* Command Type 6 entry */
 385 struct cmd_type_6 {
 386         uint8_t entry_type;             /* Entry type. */
 387         uint8_t entry_count;            /* Entry count. */
 388         uint8_t sys_define;             /* System defined. */
 389         uint8_t entry_status;           /* Entry Status. */
 390
 391         uint32_t handle;                /* System handle. */
 392
 393         uint16_t nport_handle;          /* N_PORT handle. */
 394         uint16_t timeout;               /* Command timeout. */
 395
 396         uint16_t dseg_count;            /* Data segment count. */
 397
 398         uint16_t fcp_rsp_dsd_len;       /* FCP_RSP DSD length. */
 399
 400         struct scsi_lun lun;            /* FCP LUN (BE). */
 401
 402         uint16_t control_flags;         /* Control flags. */
 403 #define CF_DATA_SEG_DESCR_ENABLE        BIT_2
 404 #define CF_READ_DATA                    BIT_1
 405 #define CF_WRITE_DATA                   BIT_0
 406
 407         uint16_t fcp_cmnd_dseg_len;             /* Data segment length. */
 408         uint32_t fcp_cmnd_dseg_address[2];      /* Data segment address. */
 409
 410         uint32_t fcp_rsp_dseg_address[2];       /* Data segment address. */
 411
 412         uint32_t byte_count;            /* Total byte count. */
 413
 414         uint8_t port_id[3];             /* PortID of destination port. */
 415         uint8_t vp_index;
 416
 417         uint32_t fcp_data_dseg_address[2];      /* Data segment address. */
 418         uint16_t fcp_data_dseg_len;             /* Data segment length. */
 419         uint16_t reserved_1;                    /* MUST be set to 0. */
 420 };
 421
 422 #define COMMAND_TYPE_7  0x18            /* Command Type 7 entry */
 423 struct cmd_type_7 {
 424         uint8_t entry_type;             /* Entry type. */
 425         uint8_t entry_count;            /* Entry count. */
 426         uint8_t sys_define;             /* System defined. */
 427         uint8_t entry_status;           /* Entry Status. */
 428
 429         uint32_t handle;                /* System handle. */
 430
 431         uint16_t nport_handle;          /* N_PORT handle. */
 432         uint16_t timeout;               /* Command timeout. */
 433 #define FW_MAX_TIMEOUT          0x1999
 434
 435         uint16_t dseg_count;            /* Data segment count. */
 436         uint16_t reserved_1;
 437
 438         struct scsi_lun lun;            /* FCP LUN (BE). */
 439
 440         uint16_t task_mgmt_flags;       /* Task management flags. */
 441 #define TMF_CLEAR_ACA           BIT_14
 442 #define TMF_TARGET_RESET        BIT_13
 443 #define TMF_LUN_RESET           BIT_12
 444 #define TMF_CLEAR_TASK_SET      BIT_10
 445 #define TMF_ABORT_TASK_SET      BIT_9
 446 #define TMF_DSD_LIST_ENABLE     BIT_2
 447 #define TMF_READ_DATA           BIT_1
 448 #define TMF_WRITE_DATA          BIT_0
 449
 450         uint8_t task;
 451 #define TSK_SIMPLE              0
 452 #define TSK_HEAD_OF_QUEUE       1
 453 #define TSK_ORDERED             2
 454 #define TSK_ACA                 4
 455 #define TSK_UNTAGGED            5
 456
 457         uint8_t crn;
 458
 459         uint8_t fcp_cdb[MAX_CMDSZ];     /* SCSI command words. */
 460         uint32_t byte_count;            /* Total byte count. */
 461
 462         uint8_t port_id[3];             /* PortID of destination port. */
 463         uint8_t vp_index;
 464
 465         uint32_t dseg_0_address[2];     /* Data segment 0 address. */
 466         uint32_t dseg_0_len;            /* Data segment 0 length. */
 467 };
 468
 469 /*
 470  * ISP queue - status entry structure definition.
 471  */
 472 #define STATUS_TYPE     0x03            /* Status entry. */
 473 struct sts_entry_24xx {
 474         uint8_t entry_type;             /* Entry type. */
 475         uint8_t entry_count;            /* Entry count. */
 476         uint8_t sys_define;             /* System defined. */
 477         uint8_t entry_status;           /* Entry Status. */
 478
 479         uint32_t handle;                /* System handle. */
 480
 481         uint16_t comp_status;           /* Completion status. */
 482         uint16_t ox_id;                 /* OX_ID used by the firmware. */
 483
 484         uint32_t residual_len;          /* FW calc residual transfer length. */
 485
 486         uint16_t reserved_1;
 487         uint16_t state_flags;           /* State flags. */
 488 #define SF_TRANSFERRED_DATA     BIT_11
 489 #define SF_FCP_RSP_DMA          BIT_0
 490
 491         uint16_t reserved_2;
 492         uint16_t scsi_status;           /* SCSI status. */
 493 #define SS_CONFIRMATION_REQ             BIT_12
 494
 495         uint32_t rsp_residual_count;    /* FCP RSP residual count. */
 496
 497         uint32_t sense_len;             /* FCP SENSE length. */
 498         uint32_t rsp_data_len;          /* FCP response data length. */
 499
 500         uint8_t data[28];               /* FCP response/sense information. */
 501 };
 502
 503 /*
 504  * Status entry completion status
 505  */
 506 #define CS_DATA_REASSEMBLY_ERROR 0x11   /* Data Reassembly Error.. */
 507 #define CS_ABTS_BY_TARGET       0x13    /* Target send ABTS to abort IOCB. */
 508 #define CS_FW_RESOURCE          0x2C    /* Firmware Resource Unavailable. */
 509 #define CS_TASK_MGMT_OVERRUN    0x30    /* Task management overrun (8+). */
 510 #define CS_ABORT_BY_TARGET      0x47    /* Abort By Target. */
 511
 512 /*
 513  * ISP queue - marker entry structure definition.
 514  */
 515 #define MARKER_TYPE     0x04            /* Marker entry. */
 516 struct mrk_entry_24xx {
 517         uint8_t entry_type;             /* Entry type. */
 518         uint8_t entry_count;            /* Entry count. */
 519         uint8_t handle_count;           /* Handle count. */
 520         uint8_t entry_status;           /* Entry Status. */
 521
 522         uint32_t handle;                /* System handle. */
 523
 524         uint16_t nport_handle;          /* N_PORT handle. */
 525
 526         uint8_t modifier;               /* Modifier (7-0). */
 527 #define MK_SYNC_ID_LUN  0               /* Synchronize ID/LUN */
 528 #define MK_SYNC_ID      1               /* Synchronize ID */
 529 #define MK_SYNC_ALL     2               /* Synchronize all ID/LUN */
 530         uint8_t reserved_1;
 531
 532         uint8_t reserved_2;
 533         uint8_t vp_index;
 534
 535         uint16_t reserved_3;
 536
 537         uint8_t lun[8];                 /* FCP LUN (BE). */
 538         uint8_t reserved_4[40];
 539 };
 540
 541 /*
 542  * ISP queue - CT Pass-Through entry structure definition.
 543  */
 544 #define CT_IOCB_TYPE            0x29    /* CT Pass-Through IOCB entry */
 545 struct ct_entry_24xx {
 546         uint8_t entry_type;             /* Entry type. */
 547         uint8_t entry_count;            /* Entry count. */
 548         uint8_t sys_define;             /* System Defined. */
 549         uint8_t entry_status;           /* Entry Status. */
 550
 551         uint32_t handle;                /* System handle. */
 552
 553         uint16_t comp_status;           /* Completion status. */
 554
 555         uint16_t nport_handle;          /* N_PORT handle. */
 556
 557         uint16_t cmd_dsd_count;
 558
 559         uint8_t vp_index;
 560         uint8_t reserved_1;
 561
 562         uint16_t timeout;               /* Command timeout. */
 563         uint16_t reserved_2;
 564
 565         uint16_t rsp_dsd_count;
 566
 567         uint8_t reserved_3[10];
 568
 569         uint32_t rsp_byte_count;
 570         uint32_t cmd_byte_count;
 571
 572         uint32_t dseg_0_address[2];     /* Data segment 0 address. */
 573         uint32_t dseg_0_len;            /* Data segment 0 length. */
 574         uint32_t dseg_1_address[2];     /* Data segment 1 address. */
 575         uint32_t dseg_1_len;            /* Data segment 1 length. */
 576 };
 577
 578 /*
 579  * ISP queue - ELS Pass-Through entry structure definition.
 580  */
 581 #define ELS_IOCB_TYPE           0x53    /* ELS Pass-Through IOCB entry */
 582 struct els_entry_24xx {
 583         uint8_t entry_type;             /* Entry type. */
 584         uint8_t entry_count;            /* Entry count. */
 585         uint8_t sys_define;             /* System Defined. */
 586         uint8_t entry_status;           /* Entry Status. */
 587
 588         uint32_t handle;                /* System handle. */
 589
 590         uint16_t reserved_1;
 591
 592         uint16_t nport_handle;          /* N_PORT handle. */
 593
 594         uint16_t tx_dsd_count;
 595
 596         uint8_t vp_index;
 597         uint8_t sof_type;
 598 #define EST_SOFI3               (1 << 4)
 599 #define EST_SOFI2               (3 << 4)
 600
 601         uint32_t rx_xchg_address;       /* Receive exchange address. */
 602         uint16_t rx_dsd_count;
 603
 604         uint8_t opcode;
 605         uint8_t reserved_2;
 606
 607         uint8_t port_id[3];
 608         uint8_t reserved_3;
 609
 610         uint16_t reserved_4;
 611
 612         uint16_t control_flags;         /* Control flags. */
 613 #define ECF_PAYLOAD_DESCR_MASK  (BIT_15|BIT_14|BIT_13)
 614 #define EPD_ELS_COMMAND         (0 << 13)
 615 #define EPD_ELS_ACC             (1 << 13)
 616 #define EPD_ELS_RJT             (2 << 13)
 617 #define EPD_RX_XCHG             (3 << 13)
 618 #define ECF_CLR_PASSTHRU_PEND   BIT_12
 619 #define ECF_INCL_FRAME_HDR      BIT_11
 620
 621         uint32_t rx_byte_count;
 622         uint32_t tx_byte_count;
 623
 624         uint32_t tx_address[2];         /* Data segment 0 address. */
 625         uint32_t tx_len;                /* Data segment 0 length. */
 626         uint32_t rx_address[2];         /* Data segment 1 address. */
 627         uint32_t rx_len;                /* Data segment 1 length. */
 628 };
 629
 630 /*
 631  * ISP queue - Mailbox Command entry structure definition.
 632  */
 633 #define MBX_IOCB_TYPE   0x39
 634 struct mbx_entry_24xx {
 635         uint8_t entry_type;             /* Entry type. */
 636         uint8_t entry_count;            /* Entry count. */
 637         uint8_t handle_count;           /* Handle count. */
 638         uint8_t entry_status;           /* Entry Status. */
 639
 640         uint32_t handle;                /* System handle. */
 641
 642         uint16_t mbx[28];
 643 };
 644
 645
 646 #define LOGINOUT_PORT_IOCB_TYPE 0x52    /* Login/Logout Port entry. */
 647 struct logio_entry_24xx {
 648         uint8_t entry_type;             /* Entry type. */
 649         uint8_t entry_count;            /* Entry count. */
 650         uint8_t sys_define;             /* System defined. */
 651         uint8_t entry_status;           /* Entry Status. */
 652
 653         uint32_t handle;                /* System handle. */
 654
 655         uint16_t comp_status;           /* Completion status. */
 656 #define CS_LOGIO_ERROR          0x31    /* Login/Logout IOCB error. */
 657
 658         uint16_t nport_handle;          /* N_PORT handle. */
 659
 660         uint16_t control_flags;         /* Control flags. */
 661                                         /* Modifiers. */
 662 #define LCF_INCLUDE_SNS         BIT_10  /* Include SNS (FFFFFC) during LOGO. */
 663 #define LCF_FCP2_OVERRIDE       BIT_9   /* Set/Reset word 3 of PRLI. */
 664 #define LCF_CLASS_2             BIT_8   /* Enable class 2 during PLOGI. */
 665 #define LCF_FREE_NPORT          BIT_7   /* Release NPORT handle after LOGO. */
 666 #define LCF_EXPL_LOGO           BIT_6   /* Perform an explicit LOGO. */
 667 #define LCF_SKIP_PRLI           BIT_5   /* Skip PRLI after PLOGI. */
 668 #define LCF_IMPL_LOGO_ALL       BIT_5   /* Implicit LOGO to all ports. */
 669 #define LCF_COND_PLOGI          BIT_4   /* PLOGI only if not logged-in. */
 670 #define LCF_IMPL_LOGO           BIT_4   /* Perform an implicit LOGO. */
 671 #define LCF_IMPL_PRLO           BIT_4   /* Perform an implicit PRLO. */
 672                                         /* Commands. */
 673 #define LCF_COMMAND_PLOGI       0x00    /* PLOGI. */
 674 #define LCF_COMMAND_PRLI        0x01    /* PRLI. */
 675 #define LCF_COMMAND_PDISC       0x02    /* PDISC. */
 676 #define LCF_COMMAND_ADISC       0x03    /* ADISC. */
 677 #define LCF_COMMAND_LOGO        0x08    /* LOGO. */
 678 #define LCF_COMMAND_PRLO        0x09    /* PRLO. */
 679 #define LCF_COMMAND_TPRLO       0x0A    /* TPRLO. */
 680
 681         uint8_t vp_index;
 682         uint8_t reserved_1;
 683
 684         uint8_t port_id[3];             /* PortID of destination port. */
 685
 686         uint8_t rsp_size;               /* Response size in 32bit words. */
 687
 688         uint32_t io_parameter[11];      /* General I/O parameters. */
 689 #define LSC_SCODE_NOLINK        0x01
 690 #define LSC_SCODE_NOIOCB        0x02
 691 #define LSC_SCODE_NOXCB         0x03
 692 #define LSC_SCODE_CMD_FAILED    0x04
 693 #define LSC_SCODE_NOFABRIC      0x05
 694 #define LSC_SCODE_FW_NOT_READY  0x07
 695 #define LSC_SCODE_NOT_LOGGED_IN 0x09
 696 #define LSC_SCODE_NOPCB         0x0A
 697
 698 #define LSC_SCODE_ELS_REJECT    0x18
 699 #define LSC_SCODE_CMD_PARAM_ERR 0x19
 700 #define LSC_SCODE_PORTID_USED   0x1A
 701 #define LSC_SCODE_NPORT_USED    0x1B
 702 #define LSC_SCODE_NONPORT       0x1C
 703 #define LSC_SCODE_LOGGED_IN     0x1D
 704 #define LSC_SCODE_NOFLOGI_ACC   0x1F
 705 };
 706
 707 #define TSK_MGMT_IOCB_TYPE      0x14
 708 struct tsk_mgmt_entry {
 709         uint8_t entry_type;             /* Entry type. */
 710         uint8_t entry_count;            /* Entry count. */
 711         uint8_t handle_count;           /* Handle count. */
 712         uint8_t entry_status;           /* Entry Status. */
 713
 714         uint32_t handle;                /* System handle. */
 715
 716         uint16_t nport_handle;          /* N_PORT handle. */
 717
 718         uint16_t reserved_1;
 719
 720         uint16_t delay;                 /* Activity delay in seconds. */
 721
 722         uint16_t timeout;               /* Command timeout. */
 723
 724         struct scsi_lun lun;            /* FCP LUN (BE). */
 725
 726         uint32_t control_flags;         /* Control Flags. */
 727 #define TCF_NOTMCMD_TO_TARGET   BIT_31
 728 #define TCF_LUN_RESET           BIT_4
 729 #define TCF_ABORT_TASK_SET      BIT_3
 730 #define TCF_CLEAR_TASK_SET      BIT_2
 731 #define TCF_TARGET_RESET        BIT_1
 732 #define TCF_CLEAR_ACA           BIT_0
 733
 734         uint8_t reserved_2[20];
 735
 736         uint8_t port_id[3];             /* PortID of destination port. */
 737         uint8_t vp_index;
 738
 739         uint8_t reserved_3[12];
 740 };
 741
 742 #define ABORT_IOCB_TYPE 0x33
 743 struct abort_entry_24xx {
 744         uint8_t entry_type;             /* Entry type. */
 745         uint8_t entry_count;            /* Entry count. */
 746         uint8_t handle_count;           /* Handle count. */
 747         uint8_t entry_status;           /* Entry Status. */
 748
 749         uint32_t handle;                /* System handle. */
 750
 751         uint16_t nport_handle;          /* N_PORT handle. */
 752                                         /* or Completion status. */
 753
 754         uint16_t options;               /* Options. */
 755 #define AOF_NO_ABTS             BIT_0   /* Do not send any ABTS. */
 756
 757         uint32_t handle_to_abort;       /* System handle to abort. */
 758
 759         uint16_t req_que_no;
 760         uint8_t reserved_1[30];
 761
 762         uint8_t port_id[3];             /* PortID of destination port. */
 763         uint8_t vp_index;
 764
 765         uint8_t reserved_2[12];
 766 };
 767
 768 /*
 769  * ISP I/O Register Set structure definitions.
 770  */
 771 struct device_reg_24xx {
 772         uint32_t flash_addr;            /* Flash/NVRAM BIOS address. */
 773 #define FARX_DATA_FLAG  BIT_31
 774 #define FARX_ACCESS_FLASH_CONF  0x7FFD0000
 775 #define FARX_ACCESS_FLASH_DATA  0x7FF00000
 776 #define FARX_ACCESS_NVRAM_CONF  0x7FFF0000
 777 #define FARX_ACCESS_NVRAM_DATA  0x7FFE0000
 778
 779 #define FA_NVRAM_FUNC0_ADDR     0x80
 780 #define FA_NVRAM_FUNC1_ADDR     0x180
 781
 782 #define FA_NVRAM_VPD_SIZE       0x200
 783 #define FA_NVRAM_VPD0_ADDR      0x00
 784 #define FA_NVRAM_VPD1_ADDR      0x100
 785
 786 #define FA_BOOT_CODE_ADDR       0x00000
 787                                         /*
 788                                          * RISC code begins at offset 512KB
 789                                          * within flash. Consisting of two
 790                                          * contiguous RISC code segments.
 791                                          */
 792 #define FA_RISC_CODE_ADDR       0x20000
 793 #define FA_RISC_CODE_SEGMENTS   2
 794
 795 #define FA_FLASH_DESCR_ADDR_24  0x11000
 796 #define FA_FLASH_LAYOUT_ADDR_24 0x11400
 797 #define FA_NPIV_CONF0_ADDR_24   0x16000
 798 #define FA_NPIV_CONF1_ADDR_24   0x17000
 799
 800 #define FA_FW_AREA_ADDR         0x40000
 801 #define FA_VPD_NVRAM_ADDR       0x48000
 802 #define FA_FEATURE_ADDR         0x4C000
 803 #define FA_FLASH_DESCR_ADDR     0x50000
 804 #define FA_FLASH_LAYOUT_ADDR    0x50400
 805 #define FA_HW_EVENT0_ADDR       0x54000
 806 #define FA_HW_EVENT1_ADDR       0x54400
 807 #define FA_HW_EVENT_SIZE        0x200
 808 #define FA_HW_EVENT_ENTRY_SIZE  4
 809 #define FA_NPIV_CONF0_ADDR      0x5C000
 810 #define FA_NPIV_CONF1_ADDR      0x5D000
 811
 812 /*
 813  * Flash Error Log Event Codes.
 814  */
 815 #define HW_EVENT_RESET_ERR      0xF00B
 816 #define HW_EVENT_ISP_ERR        0xF020
 817 #define HW_EVENT_PARITY_ERR     0xF022
 818 #define HW_EVENT_NVRAM_CHKSUM_ERR       0xF023
 819 #define HW_EVENT_FLASH_FW_ERR   0xF024
 820
 821         uint32_t flash_data;            /* Flash/NVRAM BIOS data. */
 822
 823         uint32_t ctrl_status;           /* Control/Status. */
 824 #define CSRX_FLASH_ACCESS_ERROR BIT_18  /* Flash/NVRAM Access Error. */
 825 #define CSRX_DMA_ACTIVE         BIT_17  /* DMA Active status. */
 826 #define CSRX_DMA_SHUTDOWN       BIT_16  /* DMA Shutdown control status. */
 827 #define CSRX_FUNCTION           BIT_15  /* Function number. */
 828                                         /* PCI-X Bus Mode. */
 829 #define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8)
 830 #define PBM_PCI_33MHZ           (0 << 8)
 831 #define PBM_PCIX_M1_66MHZ       (1 << 8)
 832 #define PBM_PCIX_M1_100MHZ      (2 << 8)
 833 #define PBM_PCIX_M1_133MHZ      (3 << 8)
 834 #define PBM_PCIX_M2_66MHZ       (5 << 8)
 835 #define PBM_PCIX_M2_100MHZ      (6 << 8)
 836 #define PBM_PCIX_M2_133MHZ      (7 << 8)
 837 #define PBM_PCI_66MHZ           (8 << 8)
 838                                         /* Max Write Burst byte count. */
 839 #define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4)
 840 #define MWB_512_BYTES           (0 << 4)
 841 #define MWB_1024_BYTES          (1 << 4)
 842 #define MWB_2048_BYTES          (2 << 4)
 843 #define MWB_4096_BYTES          (3 << 4)
 844
 845 #define CSRX_64BIT_SLOT         BIT_2   /* PCI 64-Bit Bus Slot. */
 846 #define CSRX_FLASH_ENABLE       BIT_1   /* Flash BIOS Read/Write enable. */
 847 #define CSRX_ISP_SOFT_RESET     BIT_0   /* ISP soft reset. */
 848
 849         uint32_t ictrl;                 /* Interrupt control. */
 850 #define ICRX_EN_RISC_INT        BIT_3   /* Enable RISC interrupts on PCI. */
 851
 852         uint32_t istatus;               /* Interrupt status. */
 853 #define ISRX_RISC_INT           BIT_3   /* RISC interrupt. */
 854
 855         uint32_t unused_1[2];           /* Gap. */
 856
 857                                         /* Request Queue. */
 858         uint32_t req_q_in;              /*  In-Pointer. */
 859         uint32_t req_q_out;             /*  Out-Pointer. */
 860                                         /* Response Queue. */
 861         uint32_t rsp_q_in;              /*  In-Pointer. */
 862         uint32_t rsp_q_out;             /*  Out-Pointer. */
 863                                         /* Priority Request Queue. */
 864         uint32_t preq_q_in;             /*  In-Pointer. */
 865         uint32_t preq_q_out;            /*  Out-Pointer. */
 866
 867         uint32_t unused_2[2];           /* Gap. */
 868
 869                                         /* ATIO Queue. */
 870         uint32_t atio_q_in;             /*  In-Pointer. */
 871         uint32_t atio_q_out;            /*  Out-Pointer. */
 872
 873         uint32_t host_status;
 874 #define HSRX_RISC_INT           BIT_15  /* RISC to Host interrupt. */
 875 #define HSRX_RISC_PAUSED        BIT_8   /* RISC Paused. */
 876
 877         uint32_t hccr;                  /* Host command & control register. */
 878                                         /* HCCR statuses. */
 879 #define HCCRX_HOST_INT          BIT_6   /* Host to RISC interrupt bit. */
 880 #define HCCRX_RISC_RESET        BIT_5   /* RISC Reset mode bit. */
 881                                         /* HCCR commands. */
 882                                         /* NOOP. */
 883 #define HCCRX_NOOP              0x00000000
 884                                         /* Set RISC Reset. */
 885 #define HCCRX_SET_RISC_RESET    0x10000000
 886                                         /* Clear RISC Reset. */
 887 #define HCCRX_CLR_RISC_RESET    0x20000000
 888                                         /* Set RISC Pause. */
 889 #define HCCRX_SET_RISC_PAUSE    0x30000000
 890                                         /* Releases RISC Pause. */
 891 #define HCCRX_REL_RISC_PAUSE    0x40000000
 892                                         /* Set HOST to RISC interrupt. */
 893 #define HCCRX_SET_HOST_INT      0x50000000
 894                                         /* Clear HOST to RISC interrupt. */
 895 #define HCCRX_CLR_HOST_INT      0x60000000
 896                                         /* Clear RISC to PCI interrupt. */
 897 #define HCCRX_CLR_RISC_INT      0xA0000000
 898
 899         uint32_t gpiod;                 /* GPIO Data register. */
 900
 901                                         /* LED update mask. */
 902 #define GPDX_LED_UPDATE_MASK    (BIT_20|BIT_19|BIT_18)
 903                                         /* Data update mask. */
 904 #define GPDX_DATA_UPDATE_MASK   (BIT_17|BIT_16)
 905                                         /* Data update mask. */
 906 #define GPDX_DATA_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)
 907                                         /* LED control mask. */
 908 #define GPDX_LED_COLOR_MASK     (BIT_4|BIT_3|BIT_2)
 909                                         /* LED bit values. Color names as
 910                                          * referenced in fw spec.
 911                                          */
 912 #define GPDX_LED_YELLOW_ON      BIT_2
 913 #define GPDX_LED_GREEN_ON       BIT_3
 914 #define GPDX_LED_AMBER_ON       BIT_4
 915                                         /* Data in/out. */
 916 #define GPDX_DATA_INOUT         (BIT_1|BIT_0)
 917
 918         uint32_t gpioe;                 /* GPIO Enable register. */
 919                                         /* Enable update mask. */
 920 #define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16)
 921                                         /* Enable update mask. */
 922 #define GPEX_ENABLE_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)
 923                                         /* Enable. */
 924 #define GPEX_ENABLE             (BIT_1|BIT_0)
 925
 926         uint32_t iobase_addr;           /* I/O Bus Base Address register. */
 927
 928         uint32_t unused_3[10];          /* Gap. */
 929
 930         uint16_t mailbox0;
 931         uint16_t mailbox1;
 932         uint16_t mailbox2;
 933         uint16_t mailbox3;
 934         uint16_t mailbox4;
 935         uint16_t mailbox5;
 936         uint16_t mailbox6;
 937         uint16_t mailbox7;
 938         uint16_t mailbox8;
 939         uint16_t mailbox9;
 940         uint16_t mailbox10;
 941         uint16_t mailbox11;
 942         uint16_t mailbox12;
 943         uint16_t mailbox13;
 944         uint16_t mailbox14;
 945         uint16_t mailbox15;
 946         uint16_t mailbox16;
 947         uint16_t mailbox17;
 948         uint16_t mailbox18;
 949         uint16_t mailbox19;
 950         uint16_t mailbox20;
 951         uint16_t mailbox21;
 952         uint16_t mailbox22;
 953         uint16_t mailbox23;
 954         uint16_t mailbox24;
 955         uint16_t mailbox25;
 956         uint16_t mailbox26;
 957         uint16_t mailbox27;
 958         uint16_t mailbox28;
 959         uint16_t mailbox29;
 960         uint16_t mailbox30;
 961         uint16_t mailbox31;
 962
 963         uint32_t iobase_window;
 964         uint32_t iobase_c4;
 965         uint32_t iobase_c8;
 966         uint32_t unused_4_1[6];         /* Gap. */
 967         uint32_t iobase_q;
 968         uint32_t unused_5[2];           /* Gap. */
 969         uint32_t iobase_select;
 970         uint32_t unused_6[2];           /* Gap. */
 971         uint32_t iobase_sdata;
 972 };
 973
 974 /* Trace Control *************************************************************/
 975
 976 #define TC_AEN_DISABLE          0
 977
 978 #define TC_EFT_ENABLE           4
 979 #define TC_EFT_DISABLE          5
 980
 981 #define TC_FCE_ENABLE           8
 982 #define TC_FCE_OPTIONS          0
 983 #define TC_FCE_DEFAULT_RX_SIZE  2112
 984 #define TC_FCE_DEFAULT_TX_SIZE  2112
 985 #define TC_FCE_DISABLE          9
 986 #define TC_FCE_DISABLE_TRACE    BIT_0
 987
 988 /* MID Support ***************************************************************/
 989
 990 #define MIN_MULTI_ID_FABRIC     64      /* Must be power-of-2. */
 991 #define MAX_MULTI_ID_FABRIC     256     /* ... */
 992
 993 #define for_each_mapped_vp_idx(_ha, _idx)               \
 994         for (_idx = find_next_bit((_ha)->vp_idx_map,    \
 995                 (_ha)->max_npiv_vports + 1, 1);         \
 996             _idx <= (_ha)->max_npiv_vports;             \
 997             _idx = find_next_bit((_ha)->vp_idx_map,     \
 998                 (_ha)->max_npiv_vports + 1, _idx + 1))  \
 999
1000 struct mid_conf_entry_24xx {
1001         uint16_t reserved_1;
1002
1003         /*
1004          * BIT 0  = Enable Hard Loop Id
1005          * BIT 1  = Acquire Loop ID in LIPA
1006          * BIT 2  = ID not Acquired
1007          * BIT 3  = Enable VP
1008          * BIT 4  = Enable Initiator Mode
1009          * BIT 5  = Disable Target Mode
1010          * BIT 6-7 = Reserved
1011          */
1012         uint8_t options;
1013
1014         uint8_t hard_address;
1015
1016         uint8_t port_name[WWN_SIZE];
1017         uint8_t node_name[WWN_SIZE];
1018 };
1019
1020 struct mid_init_cb_24xx {
1021         struct init_cb_24xx init_cb;
1022
1023         uint16_t count;
1024         uint16_t options;
1025
1026         struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC];
1027 };
1028
1029
1030 struct mid_db_entry_24xx {
1031         uint16_t status;
1032 #define MDBS_NON_PARTIC         BIT_3
1033 #define MDBS_ID_ACQUIRED        BIT_1
1034 #define MDBS_ENABLED            BIT_0
1035
1036         uint8_t options;
1037         uint8_t hard_address;
1038
1039         uint8_t port_name[WWN_SIZE];
1040         uint8_t node_name[WWN_SIZE];
1041
1042         uint8_t port_id[3];
1043         uint8_t reserved_1;
1044 };
1045
1046 /*
1047  * Virtual Port Control IOCB
1048  */
1049 #define VP_CTRL_IOCB_TYPE       0x30    /* Vitual Port Control entry. */
1050 struct vp_ctrl_entry_24xx {
1051         uint8_t entry_type;             /* Entry type. */
1052         uint8_t entry_count;            /* Entry count. */
1053         uint8_t sys_define;             /* System defined. */
1054         uint8_t entry_status;           /* Entry Status. */
1055
1056         uint32_t handle;                /* System handle. */
1057
1058         uint16_t vp_idx_failed;
1059
1060         uint16_t comp_status;           /* Completion status. */
1061 #define CS_VCE_IOCB_ERROR       0x01    /* Error processing IOCB */
1062 #define CS_VCE_ACQ_ID_ERROR     0x02    /* Error while acquireing ID. */
1063 #define CS_VCE_BUSY             0x05    /* Firmware not ready to accept cmd. */
1064
1065         uint16_t command;
1066 #define VCE_COMMAND_ENABLE_VPS  0x00    /* Enable VPs. */
1067 #define VCE_COMMAND_DISABLE_VPS 0x08    /* Disable VPs. */
1068 #define VCE_COMMAND_DISABLE_VPS_REINIT  0x09 /* Disable VPs and reinit link. */
1069 #define VCE_COMMAND_DISABLE_VPS_LOGO    0x0a /* Disable VPs and LOGO ports. */
1070 #define VCE_COMMAND_DISABLE_VPS_LOGO_ALL        0x0b /* Disable VPs and LOGO ports. */
1071
1072         uint16_t vp_count;
1073
1074         uint8_t vp_idx_map[16];
1075         uint16_t flags;
1076         uint16_t id;
1077         uint16_t reserved_4;
1078         uint16_t hopct;
1079         uint8_t reserved_5[24];
1080 };
1081
1082 /*
1083  * Modify Virtual Port Configuration IOCB
1084  */
1085 #define VP_CONFIG_IOCB_TYPE     0x31    /* Vitual Port Config entry. */
1086 struct vp_config_entry_24xx {
1087         uint8_t entry_type;             /* Entry type. */
1088         uint8_t entry_count;            /* Entry count. */
1089         uint8_t handle_count;
1090         uint8_t entry_status;           /* Entry Status. */
1091
1092         uint32_t handle;                /* System handle. */
1093
1094         uint16_t flags;
1095 #define CS_VF_BIND_VPORTS_TO_VF         BIT_0
1096 #define CS_VF_SET_QOS_OF_VPORTS         BIT_1
1097 #define CS_VF_SET_HOPS_OF_VPORTS        BIT_2
1098
1099         uint16_t comp_status;           /* Completion status. */
1100 #define CS_VCT_STS_ERROR        0x01    /* Specified VPs were not disabled. */
1101 #define CS_VCT_CNT_ERROR        0x02    /* Invalid VP count. */
1102 #define CS_VCT_ERROR            0x03    /* Unknown error. */
1103 #define CS_VCT_IDX_ERROR        0x02    /* Invalid VP index. */
1104 #define CS_VCT_BUSY             0x05    /* Firmware not ready to accept cmd. */
1105
1106         uint8_t command;
1107 #define VCT_COMMAND_MOD_VPS     0x00    /* Modify VP configurations. */
1108 #define VCT_COMMAND_MOD_ENABLE_VPS 0x01 /* Modify configuration & enable VPs. */
1109
1110         uint8_t vp_count;
1111
1112         uint8_t vp_index1;
1113         uint8_t vp_index2;
1114
1115         uint8_t options_idx1;
1116         uint8_t hard_address_idx1;
1117         uint16_t reserved_vp1;
1118         uint8_t port_name_idx1[WWN_SIZE];
1119         uint8_t node_name_idx1[WWN_SIZE];
1120
1121         uint8_t options_idx2;
1122         uint8_t hard_address_idx2;
1123         uint16_t reserved_vp2;
1124         uint8_t port_name_idx2[WWN_SIZE];
1125         uint8_t node_name_idx2[WWN_SIZE];
1126         uint16_t id;
1127         uint16_t reserved_4;
1128         uint16_t hopct;
1129         uint8_t reserved_5[2];
1130 };
1131
1132 #define VP_RPT_ID_IOCB_TYPE     0x32    /* Report ID Acquisition entry. */
1133 struct vp_rpt_id_entry_24xx {
1134         uint8_t entry_type;             /* Entry type. */
1135         uint8_t entry_count;            /* Entry count. */
1136         uint8_t sys_define;             /* System defined. */
1137         uint8_t entry_status;           /* Entry Status. */
1138
1139         uint32_t handle;                /* System handle. */
1140
1141         uint16_t vp_count;              /* Format 0 -- | VP setup | VP acq |. */
1142                                         /* Format 1 -- | VP count |. */
1143         uint16_t vp_idx;                /* Format 0 -- Reserved. */
1144                                         /* Format 1 -- VP status and index. */
1145
1146         uint8_t port_id[3];
1147         uint8_t format;
1148
1149         uint8_t vp_idx_map[16];
1150
1151         uint8_t reserved_4[32];
1152 };
1153
1154 #define VF_EVFP_IOCB_TYPE       0x26    /* Exchange Virtual Fabric Parameters entry. */
1155 struct vf_evfp_entry_24xx {
1156         uint8_t entry_type;             /* Entry type. */
1157         uint8_t entry_count;            /* Entry count. */
1158         uint8_t sys_define;             /* System defined. */
1159         uint8_t entry_status;           /* Entry Status. */
1160
1161         uint32_t handle;                /* System handle. */
1162         uint16_t comp_status;           /* Completion status. */
1163         uint16_t timeout;               /* timeout */
1164         uint16_t adim_tagging_mode;
1165
1166         uint16_t vfport_id;
1167         uint32_t exch_addr;
1168
1169         uint16_t nport_handle;          /* N_PORT handle. */
1170         uint16_t control_flags;
1171         uint32_t io_parameter_0;
1172         uint32_t io_parameter_1;
1173         uint32_t tx_address[2];         /* Data segment 0 address. */
1174         uint32_t tx_len;                /* Data segment 0 length. */
1175         uint32_t rx_address[2];         /* Data segment 1 address. */
1176         uint32_t rx_len;                /* Data segment 1 length. */
1177 };
1178
1179 /* END MID Support ***********************************************************/
1180
1181 /* Flash Description Table ***************************************************/
1182
1183 struct qla_fdt_layout {
1184         uint8_t sig[4];
1185         uint16_t version;
1186         uint16_t len;
1187         uint16_t checksum;
1188         uint8_t unused1[2];
1189         uint8_t model[16];
1190         uint16_t man_id;
1191         uint16_t id;
1192         uint8_t flags;
1193         uint8_t erase_cmd;
1194         uint8_t alt_erase_cmd;
1195         uint8_t wrt_enable_cmd;
1196         uint8_t wrt_enable_bits;
1197         uint8_t wrt_sts_reg_cmd;
1198         uint8_t unprotect_sec_cmd;
1199         uint8_t read_man_id_cmd;
1200         uint32_t block_size;
1201         uint32_t alt_block_size;
1202         uint32_t flash_size;
1203         uint32_t wrt_enable_data;
1204         uint8_t read_id_addr_len;
1205         uint8_t wrt_disable_bits;
1206         uint8_t read_dev_id_len;
1207         uint8_t chip_erase_cmd;
1208         uint16_t read_timeout;
1209         uint8_t protect_sec_cmd;
1210         uint8_t unused2[65];
1211 };
1212
1213 /* Flash Layout Table ********************************************************/
1214
1215 struct qla_flt_location {
1216         uint8_t sig[4];
1217         uint16_t start_lo;
1218         uint16_t start_hi;
1219         uint8_t version;
1220         uint8_t unused[5];
1221         uint16_t checksum;
1222 };
1223
1224 struct qla_flt_header {
1225         uint16_t version;
1226         uint16_t length;
1227         uint16_t checksum;
1228         uint16_t unused;
1229 };
1230
1231 #define FLT_REG_FW              0x01
1232 #define FLT_REG_BOOT_CODE       0x07
1233 #define FLT_REG_VPD_0           0x14
1234 #define FLT_REG_NVRAM_0         0x15
1235 #define FLT_REG_VPD_1           0x16
1236 #define FLT_REG_NVRAM_1         0x17
1237 #define FLT_REG_FDT             0x1a
1238 #define FLT_REG_FLT             0x1c
1239 #define FLT_REG_HW_EVENT_0      0x1d
1240 #define FLT_REG_HW_EVENT_1      0x1f
1241 #define FLT_REG_NPIV_CONF_0     0x29
1242 #define FLT_REG_NPIV_CONF_1     0x2a
1243 #define FLT_REG_GOLD_FW         0x2f
1244
1245 struct qla_flt_region {
1246         uint32_t code;
1247         uint32_t size;
1248         uint32_t start;
1249         uint32_t end;
1250 };
1251
1252 /* Flash NPIV Configuration Table ********************************************/
1253
1254 struct qla_npiv_header {
1255         uint8_t sig[2];
1256         uint16_t version;
1257         uint16_t entries;
1258         uint16_t unused[4];
1259         uint16_t checksum;
1260 };
1261
1262 struct qla_npiv_entry {
1263         uint16_t flags;
1264         uint16_t vf_id;
1265         uint8_t q_qos;
1266         uint8_t f_qos;
1267         uint16_t unused1;
1268         uint8_t port_name[WWN_SIZE];
1269         uint8_t node_name[WWN_SIZE];
1270 };
1271
1272 /* 84XX Support **************************************************************/
1273
1274 #define MBA_ISP84XX_ALERT       0x800f  /* Alert Notification. */
1275 #define A84_PANIC_RECOVERY      0x1
1276 #define A84_OP_LOGIN_COMPLETE   0x2
1277 #define A84_DIAG_LOGIN_COMPLETE 0x3
1278 #define A84_GOLD_LOGIN_COMPLETE 0x4
1279
1280 #define MBC_ISP84XX_RESET       0x3a    /* Reset. */
1281
1282 #define FSTATE_REMOTE_FC_DOWN   BIT_0
1283 #define FSTATE_NSL_LINK_DOWN    BIT_1
1284 #define FSTATE_IS_DIAG_FW       BIT_2
1285 #define FSTATE_LOGGED_IN        BIT_3
1286 #define FSTATE_WAITING_FOR_VERIFY       BIT_4
1287
1288 #define VERIFY_CHIP_IOCB_TYPE   0x1B
1289 struct verify_chip_entry_84xx {
1290         uint8_t entry_type;
1291         uint8_t entry_count;
1292         uint8_t sys_defined;
1293         uint8_t entry_status;
1294
1295         uint32_t handle;
1296
1297         uint16_t options;
1298 #define VCO_DONT_UPDATE_FW      BIT_0
1299 #define VCO_FORCE_UPDATE        BIT_1
1300 #define VCO_DONT_RESET_UPDATE   BIT_2
1301 #define VCO_DIAG_FW             BIT_3
1302 #define VCO_END_OF_DATA         BIT_14
1303 #define VCO_ENABLE_DSD          BIT_15
1304
1305         uint16_t reserved_1;
1306
1307         uint16_t data_seg_cnt;
1308         uint16_t reserved_2[3];
1309
1310         uint32_t fw_ver;
1311         uint32_t exchange_address;
1312
1313         uint32_t reserved_3[3];
1314         uint32_t fw_size;
1315         uint32_t fw_seq_size;
1316         uint32_t relative_offset;
1317
1318         uint32_t dseg_address[2];
1319         uint32_t dseg_length;
1320 };
1321
1322 struct verify_chip_rsp_84xx {
1323         uint8_t entry_type;
1324         uint8_t entry_count;
1325         uint8_t sys_defined;
1326         uint8_t entry_status;
1327
1328         uint32_t handle;
1329
1330         uint16_t comp_status;
1331 #define CS_VCS_CHIP_FAILURE     0x3
1332 #define CS_VCS_BAD_EXCHANGE     0x8
1333 #define CS_VCS_SEQ_COMPLETEi    0x40
1334
1335         uint16_t failure_code;
1336 #define VFC_CHECKSUM_ERROR      0x1
1337 #define VFC_INVALID_LEN         0x2
1338 #define VFC_ALREADY_IN_PROGRESS 0x8
1339
1340         uint16_t reserved_1[4];
1341
1342         uint32_t fw_ver;
1343         uint32_t exchange_address;
1344
1345         uint32_t reserved_2[6];
1346 };
1347
1348 #define ACCESS_CHIP_IOCB_TYPE   0x2B
1349 struct access_chip_84xx {
1350         uint8_t entry_type;
1351         uint8_t entry_count;
1352         uint8_t sys_defined;
1353         uint8_t entry_status;
1354
1355         uint32_t handle;
1356
1357         uint16_t options;
1358 #define ACO_DUMP_MEMORY         0x0
1359 #define ACO_LOAD_MEMORY         0x1
1360 #define ACO_CHANGE_CONFIG_PARAM 0x2
1361 #define ACO_REQUEST_INFO        0x3
1362
1363         uint16_t reserved1;
1364
1365         uint16_t dseg_count;
1366         uint16_t reserved2[3];
1367
1368         uint32_t parameter1;
1369         uint32_t parameter2;
1370         uint32_t parameter3;
1371
1372         uint32_t reserved3[3];
1373         uint32_t total_byte_cnt;
1374         uint32_t reserved4;
1375
1376         uint32_t dseg_address[2];
1377         uint32_t dseg_length;
1378 };
1379
1380 struct access_chip_rsp_84xx {
1381         uint8_t entry_type;
1382         uint8_t entry_count;
1383         uint8_t sys_defined;
1384         uint8_t entry_status;
1385
1386         uint32_t handle;
1387
1388         uint16_t comp_status;
1389         uint16_t failure_code;
1390         uint32_t residual_count;
1391
1392         uint32_t reserved[12];
1393 };
1394
1395 /* 81XX Support **************************************************************/
1396
1397 #define MBA_DCBX_START          0x8016
1398 #define MBA_DCBX_COMPLETE       0x8030
1399 #define MBA_FCF_CONF_ERR        0x8031
1400 #define MBA_DCBX_PARAM_UPDATE   0x8032
1401 #define MBA_IDC_COMPLETE        0x8100
1402 #define MBA_IDC_NOTIFY          0x8101
1403 #define MBA_IDC_TIME_EXT        0x8102
1404
1405 #define MBC_IDC_ACK             0x101
1406 #define MBC_RESTART_MPI_FW      0x3d
1407 #define MBC_FLASH_ACCESS_CTRL   0x3e    /* Control flash access. */
1408 #define MBC_GET_XGMAC_STATS     0x7a
1409 #define MBC_GET_DCBX_PARAMS     0x51
1410
1411 /* Flash access control option field bit definitions */
1412 #define FAC_OPT_FORCE_SEMAPHORE         BIT_15
1413 #define FAC_OPT_REQUESTOR_ID            BIT_14
1414 #define FAC_OPT_CMD_SUBCODE             0xff
1415
1416 /* Flash access control command subcodes */
1417 #define FAC_OPT_CMD_WRITE_PROTECT       0x00
1418 #define FAC_OPT_CMD_WRITE_ENABLE        0x01
1419 #define FAC_OPT_CMD_ERASE_SECTOR        0x02
1420 #define FAC_OPT_CMD_LOCK_SEMAPHORE      0x03
1421 #define FAC_OPT_CMD_UNLOCK_SEMAPHORE    0x04
1422 #define FAC_OPT_CMD_GET_SECTOR_SIZE     0x05
1423
1424 struct nvram_81xx {
1425         /* NVRAM header. */
1426         uint8_t id[4];
1427         uint16_t nvram_version;
1428         uint16_t reserved_0;
1429
1430         /* Firmware Initialization Control Block. */
1431         uint16_t version;
1432         uint16_t reserved_1;
1433         uint16_t frame_payload_size;
1434         uint16_t execution_throttle;
1435         uint16_t exchange_count;
1436         uint16_t reserved_2;
1437
1438         uint8_t port_name[WWN_SIZE];
1439         uint8_t node_name[WWN_SIZE];
1440
1441         uint16_t login_retry_count;
1442         uint16_t reserved_3;
1443         uint16_t interrupt_delay_timer;
1444         uint16_t login_timeout;
1445
1446         uint32_t firmware_options_1;
1447         uint32_t firmware_options_2;
1448         uint32_t firmware_options_3;
1449
1450         uint16_t reserved_4[4];
1451
1452         /* Offset 64. */
1453         uint8_t enode_mac[6];
1454         uint16_t reserved_5[5];
1455
1456         /* Offset 80. */
1457         uint16_t reserved_6[24];
1458
1459         /* Offset 128. */
1460         uint16_t ex_version;
1461         uint8_t prio_fcf_matching_flags;
1462         uint8_t reserved_6_1[3];
1463         uint16_t pri_fcf_vlan_id;
1464         uint8_t pri_fcf_fabric_name[8];
1465         uint16_t reserved_6_2[7];
1466         uint8_t spma_mac_addr[6];
1467         uint16_t reserved_6_3[14];
1468
1469         /* Offset 192. */
1470         uint16_t reserved_7[32];
1471
1472         /*
1473          * BIT 0  = Enable spinup delay
1474          * BIT 1  = Disable BIOS
1475          * BIT 2  = Enable Memory Map BIOS
1476          * BIT 3  = Enable Selectable Boot
1477          * BIT 4  = Disable RISC code load
1478          * BIT 5  = Disable Serdes
1479          * BIT 6  = Opt boot mode
1480          * BIT 7  = Interrupt enable
1481          *
1482          * BIT 8  = EV Control enable
1483          * BIT 9  = Enable lip reset
1484          * BIT 10 = Enable lip full login
1485          * BIT 11 = Enable target reset
1486          * BIT 12 = Stop firmware
1487          * BIT 13 = Enable nodename option
1488          * BIT 14 = Default WWPN valid
1489          * BIT 15 = Enable alternate WWN
1490          *
1491          * BIT 16 = CLP LUN string
1492          * BIT 17 = CLP Target string
1493          * BIT 18 = CLP BIOS enable string
1494          * BIT 19 = CLP Serdes string
1495          * BIT 20 = CLP WWPN string
1496          * BIT 21 = CLP WWNN string
1497          * BIT 22 =
1498          * BIT 23 =
1499          * BIT 24 = Keep WWPN
1500          * BIT 25 = Temp WWPN
1501          * BIT 26-31 =
1502          */
1503         uint32_t host_p;
1504
1505         uint8_t alternate_port_name[WWN_SIZE];
1506         uint8_t alternate_node_name[WWN_SIZE];
1507
1508         uint8_t boot_port_name[WWN_SIZE];
1509         uint16_t boot_lun_number;
1510         uint16_t reserved_8;
1511
1512         uint8_t alt1_boot_port_name[WWN_SIZE];
1513         uint16_t alt1_boot_lun_number;
1514         uint16_t reserved_9;
1515
1516         uint8_t alt2_boot_port_name[WWN_SIZE];
1517         uint16_t alt2_boot_lun_number;
1518         uint16_t reserved_10;
1519
1520         uint8_t alt3_boot_port_name[WWN_SIZE];
1521         uint16_t alt3_boot_lun_number;
1522         uint16_t reserved_11;
1523
1524         /*
1525          * BIT 0 = Selective Login
1526          * BIT 1 = Alt-Boot Enable
1527          * BIT 2 = Reserved
1528          * BIT 3 = Boot Order List
1529          * BIT 4 = Reserved
1530          * BIT 5 = Selective LUN
1531          * BIT 6 = Reserved
1532          * BIT 7-31 =
1533          */
1534         uint32_t efi_parameters;
1535
1536         uint8_t reset_delay;
1537         uint8_t reserved_12;
1538         uint16_t reserved_13;
1539
1540         uint16_t boot_id_number;
1541         uint16_t reserved_14;
1542
1543         uint16_t max_luns_per_target;
1544         uint16_t reserved_15;
1545
1546         uint16_t port_down_retry_count;
1547         uint16_t link_down_timeout;
1548
1549         /* FCode parameters. */
1550         uint16_t fcode_parameter;
1551
1552         uint16_t reserved_16[3];
1553
1554         /* Offset 352. */
1555         uint8_t reserved_17[4];
1556         uint16_t reserved_18[5];
1557         uint8_t reserved_19[2];
1558         uint16_t reserved_20[8];
1559
1560         /* Offset 384. */
1561         uint8_t reserved_21[16];
1562         uint16_t reserved_22[8];
1563
1564         /* Offset 416. */
1565         uint16_t reserved_23[32];
1566
1567         /* Offset 480. */
1568         uint8_t model_name[16];
1569
1570         /* Offset 496. */
1571         uint16_t feature_mask_l;
1572         uint16_t feature_mask_h;
1573         uint16_t reserved_24[2];
1574
1575         uint16_t subsystem_vendor_id;
1576         uint16_t subsystem_device_id;
1577
1578         uint32_t checksum;
1579 };
1580
1581 /*
1582  * ISP Initialization Control Block.
1583  * Little endian except where noted.
1584  */
1585 #define ICB_VERSION 1
1586 struct init_cb_81xx {
1587         uint16_t version;
1588         uint16_t reserved_1;
1589
1590         uint16_t frame_payload_size;
1591         uint16_t execution_throttle;
1592         uint16_t exchange_count;
1593
1594         uint16_t reserved_2;
1595
1596         uint8_t port_name[WWN_SIZE];            /* Big endian. */
1597         uint8_t node_name[WWN_SIZE];            /* Big endian. */
1598
1599         uint16_t response_q_inpointer;
1600         uint16_t request_q_outpointer;
1601
1602         uint16_t login_retry_count;
1603
1604         uint16_t prio_request_q_outpointer;
1605
1606         uint16_t response_q_length;
1607         uint16_t request_q_length;
1608
1609         uint16_t reserved_3;
1610
1611         uint16_t prio_request_q_length;
1612
1613         uint32_t request_q_address[2];
1614         uint32_t response_q_address[2];
1615         uint32_t prio_request_q_address[2];
1616
1617         uint8_t reserved_4[8];
1618
1619         uint16_t atio_q_inpointer;
1620         uint16_t atio_q_length;
1621         uint32_t atio_q_address[2];
1622
1623         uint16_t interrupt_delay_timer;         /* 100us increments. */
1624         uint16_t login_timeout;
1625
1626         /*
1627          * BIT 0-3 = Reserved
1628          * BIT 4  = Enable Target Mode
1629          * BIT 5  = Disable Initiator Mode
1630          * BIT 6  = Reserved
1631          * BIT 7  = Reserved
1632          *
1633          * BIT 8-13 = Reserved
1634          * BIT 14 = Node Name Option
1635          * BIT 15-31 = Reserved
1636          */
1637         uint32_t firmware_options_1;
1638
1639         /*
1640          * BIT 0  = Operation Mode bit 0
1641          * BIT 1  = Operation Mode bit 1
1642          * BIT 2  = Operation Mode bit 2
1643          * BIT 3  = Operation Mode bit 3
1644          * BIT 4-7 = Reserved
1645          *
1646          * BIT 8  = Enable Class 2
1647          * BIT 9  = Enable ACK0
1648          * BIT 10 = Reserved
1649          * BIT 11 = Enable FC-SP Security
1650          * BIT 12 = FC Tape Enable
1651          * BIT 13 = Reserved
1652          * BIT 14 = Enable Target PRLI Control
1653          * BIT 15-31 = Reserved
1654          */
1655         uint32_t firmware_options_2;
1656
1657         /*
1658          * BIT 0-3 = Reserved
1659          * BIT 4  = FCP RSP Payload bit 0
1660          * BIT 5  = FCP RSP Payload bit 1
1661          * BIT 6  = Enable Receive Out-of-Order data frame handling
1662          * BIT 7  = Reserved
1663          *
1664          * BIT 8  = Reserved
1665          * BIT 9  = Enable Out-of-Order FCP_XFER_RDY relative offset handling
1666          * BIT 10-16 = Reserved
1667          * BIT 17 = Enable multiple FCFs
1668          * BIT 18-20 = MAC addressing mode
1669          * BIT 21-25 = Ethernet data rate
1670          * BIT 26 = Enable ethernet header rx IOCB for ATIO q
1671          * BIT 27 = Enable ethernet header rx IOCB for response q
1672          * BIT 28 = SPMA selection bit 0
1673          * BIT 28 = SPMA selection bit 1
1674          * BIT 30-31 = Reserved
1675          */
1676         uint32_t firmware_options_3;
1677
1678         uint8_t  reserved_5[8];
1679
1680         uint8_t enode_mac[6];
1681
1682         uint8_t reserved_6[10];
1683 };
1684
1685 struct mid_init_cb_81xx {
1686         struct init_cb_81xx init_cb;
1687
1688         uint16_t count;
1689         uint16_t options;
1690
1691         struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC];
1692 };
1693
1694 struct ex_init_cb_81xx {
1695         uint16_t ex_version;
1696         uint8_t prio_fcf_matching_flags;
1697         uint8_t reserved_1[3];
1698         uint16_t pri_fcf_vlan_id;
1699         uint8_t pri_fcf_fabric_name[8];
1700         uint16_t reserved_2[7];
1701         uint8_t spma_mac_addr[6];
1702         uint16_t reserved_3[14];
1703 };
1704
1705 #define FARX_ACCESS_FLASH_CONF_81XX     0x7FFD0000
1706 #define FARX_ACCESS_FLASH_DATA_81XX     0x7F800000
1707
1708 /* 81XX Flash locations -- occupies second 2MB region. */
1709 #define FA_BOOT_CODE_ADDR_81    0x80000
1710 #define FA_RISC_CODE_ADDR_81    0xA0000
1711 #define FA_FW_AREA_ADDR_81      0xC0000
1712 #define FA_VPD_NVRAM_ADDR_81    0xD0000
1713 #define FA_VPD0_ADDR_81         0xD0000
1714 #define FA_VPD1_ADDR_81         0xD0400
1715 #define FA_NVRAM0_ADDR_81       0xD0080
1716 #define FA_NVRAM1_ADDR_81       0xD0180
1717 #define FA_FEATURE_ADDR_81      0xD4000
1718 #define FA_FLASH_DESCR_ADDR_81  0xD8000
1719 #define FA_FLASH_LAYOUT_ADDR_81 0xD8400
1720 #define FA_HW_EVENT0_ADDR_81    0xDC000
1721 #define FA_HW_EVENT1_ADDR_81    0xDC400
1722 #define FA_NPIV_CONF0_ADDR_81   0xD1000
1723 #define FA_NPIV_CONF1_ADDR_81   0xD2000
1724
1725 #endif