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x86: trivial clean up for irq_vectors.h
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / tulip / de4x5.c
blobf9491bd787d1ac06c0032a2524b5cc52b31c7f60
1 /* de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500
2 ethernet driver for Linux.
3
4 Copyright 1994, 1995 Digital Equipment Corporation.
5
6 Testing resources for this driver have been made available
7 in part by NASA Ames Research Center (mjacob@nas.nasa.gov).
8
9 The author may be reached at davies@maniac.ultranet.com.
10
11 This program is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published by the
13 Free Software Foundation; either version 2 of the License, or (at your
14 option) any later version.
15
16 THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27 You should have received a copy of the GNU General Public License along
28 with this program; if not, write to the Free Software Foundation, Inc.,
29 675 Mass Ave, Cambridge, MA 02139, USA.
30
31 Originally, this driver was written for the Digital Equipment
32 Corporation series of EtherWORKS ethernet cards:
33
34 DE425 TP/COAX EISA
35 DE434 TP PCI
36 DE435 TP/COAX/AUI PCI
37 DE450 TP/COAX/AUI PCI
38 DE500 10/100 PCI Fasternet
39
40 but it will now attempt to support all cards which conform to the
41 Digital Semiconductor SROM Specification. The driver currently
42 recognises the following chips:
43
44 DC21040 (no SROM)
45 DC21041[A]
46 DC21140[A]
47 DC21142
48 DC21143
49
50 So far the driver is known to work with the following cards:
51
52 KINGSTON
53 Linksys
54 ZNYX342
55 SMC8432
56 SMC9332 (w/new SROM)
57 ZNYX31[45]
58 ZNYX346 10/100 4 port (can act as a 10/100 bridge!)
59
60 The driver has been tested on a relatively busy network using the DE425,
61 DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
62 16M of data to a DECstation 5000/200 as follows:
63
64 TCP UDP
65 TX RX TX RX
66 DE425 1030k 997k 1170k 1128k
67 DE434 1063k 995k 1170k 1125k
68 DE435 1063k 995k 1170k 1125k
69 DE500 1063k 998k 1170k 1125k in 10Mb/s mode
70
71 All values are typical (in kBytes/sec) from a sample of 4 for each
72 measurement. Their error is +/-20k on a quiet (private) network and also
73 depend on what load the CPU has.
74
75 =========================================================================
76 This driver has been written substantially from scratch, although its
77 inheritance of style and stack interface from 'ewrk3.c' and in turn from
78 Donald Becker's 'lance.c' should be obvious. With the module autoload of
79 every usable DECchip board, I pinched Donald's 'next_module' field to
80 link my modules together.
81
82 Upto 15 EISA cards can be supported under this driver, limited primarily
83 by the available IRQ lines. I have checked different configurations of
84 multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a
85 problem yet (provided you have at least depca.c v0.38) ...
86
87 PCI support has been added to allow the driver to work with the DE434,
88 DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due
89 to the differences in the EISA and PCI CSR address offsets from the base
90 address.
91
92 The ability to load this driver as a loadable module has been included
93 and used extensively during the driver development (to save those long
94 reboot sequences). Loadable module support under PCI and EISA has been
95 achieved by letting the driver autoprobe as if it were compiled into the
96 kernel. Do make sure you're not sharing interrupts with anything that
97 cannot accommodate interrupt sharing!
98
99 To utilise this ability, you have to do 8 things:
100
101 0) have a copy of the loadable modules code installed on your system.
102 1) copy de4x5.c from the /linux/drivers/net directory to your favourite
103 temporary directory.
104 2) for fixed autoprobes (not recommended), edit the source code near
105 line 5594 to reflect the I/O address you're using, or assign these when
106 loading by:
107
108 insmod de4x5 io=0xghh where g = bus number
109 hh = device number
110
111 NB: autoprobing for modules is now supported by default. You may just
112 use:
113
114 insmod de4x5
115
116 to load all available boards. For a specific board, still use
117 the 'io=?' above.
118 3) compile de4x5.c, but include -DMODULE in the command line to ensure
119 that the correct bits are compiled (see end of source code).
120 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
121 kernel with the de4x5 configuration turned off and reboot.
122 5) insmod de4x5 [io=0xghh]
123 6) run the net startup bits for your new eth?? interface(s) manually
124 (usually /etc/rc.inet[12] at boot time).
125 7) enjoy!
126
127 To unload a module, turn off the associated interface(s)
128 'ifconfig eth?? down' then 'rmmod de4x5'.
129
130 Automedia detection is included so that in principal you can disconnect
131 from, e.g. TP, reconnect to BNC and things will still work (after a
132 pause whilst the driver figures out where its media went). My tests
133 using ping showed that it appears to work....
134
135 By default, the driver will now autodetect any DECchip based card.
136 Should you have a need to restrict the driver to DIGITAL only cards, you
137 can compile with a DEC_ONLY define, or if loading as a module, use the
138 'dec_only=1' parameter.
139
140 I've changed the timing routines to use the kernel timer and scheduling
141 functions so that the hangs and other assorted problems that occurred
142 while autosensing the media should be gone. A bonus for the DC21040
143 auto media sense algorithm is that it can now use one that is more in
144 line with the rest (the DC21040 chip doesn't have a hardware timer).
145 The downside is the 1 'jiffies' (10ms) resolution.
146
147 IEEE 802.3u MII interface code has been added in anticipation that some
148 products may use it in the future.
149
150 The SMC9332 card has a non-compliant SROM which needs fixing - I have
151 patched this driver to detect it because the SROM format used complies
152 to a previous DEC-STD format.
153
154 I have removed the buffer copies needed for receive on Intels. I cannot
155 remove them for Alphas since the Tulip hardware only does longword
156 aligned DMA transfers and the Alphas get alignment traps with non
157 longword aligned data copies (which makes them really slow). No comment.
158
159 I have added SROM decoding routines to make this driver work with any
160 card that supports the Digital Semiconductor SROM spec. This will help
161 all cards running the dc2114x series chips in particular. Cards using
162 the dc2104x chips should run correctly with the basic driver. I'm in
163 debt to <mjacob@feral.com> for the testing and feedback that helped get
164 this feature working. So far we have tested KINGSTON, SMC8432, SMC9332
165 (with the latest SROM complying with the SROM spec V3: their first was
166 broken), ZNYX342 and LinkSys. ZYNX314 (dual 21041 MAC) and ZNYX 315
167 (quad 21041 MAC) cards also appear to work despite their incorrectly
168 wired IRQs.
169
170 I have added a temporary fix for interrupt problems when some SCSI cards
171 share the same interrupt as the DECchip based cards. The problem occurs
172 because the SCSI card wants to grab the interrupt as a fast interrupt
173 (runs the service routine with interrupts turned off) vs. this card
174 which really needs to run the service routine with interrupts turned on.
175 This driver will now add the interrupt service routine as a fast
176 interrupt if it is bounced from the slow interrupt. THIS IS NOT A
177 RECOMMENDED WAY TO RUN THE DRIVER and has been done for a limited time
178 until people sort out their compatibility issues and the kernel
179 interrupt service code is fixed. YOU SHOULD SEPARATE OUT THE FAST
180 INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not
181 run on the same interrupt. PCMCIA/CardBus is another can of worms...
182
183 Finally, I think I have really fixed the module loading problem with
184 more than one DECchip based card. As a side effect, I don't mess with
185 the device structure any more which means that if more than 1 card in
186 2.0.x is installed (4 in 2.1.x), the user will have to edit
187 linux/drivers/net/Space.c to make room for them. Hence, module loading
188 is the preferred way to use this driver, since it doesn't have this
189 limitation.
190
191 Where SROM media detection is used and full duplex is specified in the
192 SROM, the feature is ignored unless lp->params.fdx is set at compile
193 time OR during a module load (insmod de4x5 args='eth??:fdx' [see
194 below]). This is because there is no way to automatically detect full
195 duplex links except through autonegotiation. When I include the
196 autonegotiation feature in the SROM autoconf code, this detection will
197 occur automatically for that case.
198
199 Command line arguments are now allowed, similar to passing arguments
200 through LILO. This will allow a per adapter board set up of full duplex
201 and media. The only lexical constraints are: the board name (dev->name)
202 appears in the list before its parameters. The list of parameters ends
203 either at the end of the parameter list or with another board name. The
204 following parameters are allowed:
205
206 fdx for full duplex
207 autosense to set the media/speed; with the following
208 sub-parameters:
209 TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO
210
211 Case sensitivity is important for the sub-parameters. They *must* be
212 upper case. Examples:
213
214 insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
215
216 For a compiled in driver, at or above line 548, place e.g.
217 #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
218
219 Yes, I know full duplex isn't permissible on BNC or AUI; they're just
220 examples. By default, full duplex is turned off and AUTO is the default
221 autosense setting. In reality, I expect only the full duplex option to
222 be used. Note the use of single quotes in the two examples above and the
223 lack of commas to separate items. ALSO, you must get the requested media
224 correct in relation to what the adapter SROM says it has. There's no way
225 to determine this in advance other than by trial and error and common
226 sense, e.g. call a BNC connectored port 'BNC', not '10Mb'.
227
228 Changed the bus probing. EISA used to be done first, followed by PCI.
229 Most people probably don't even know what a de425 is today and the EISA
230 probe has messed up some SCSI cards in the past, so now PCI is always
231 probed first followed by EISA if a) the architecture allows EISA and
232 either b) there have been no PCI cards detected or c) an EISA probe is
233 forced by the user. To force a probe include "force_eisa" in your
234 insmod "args" line; for built-in kernels either change the driver to do
235 this automatically or include #define DE4X5_FORCE_EISA on or before
236 line 1040 in the driver.
237
238 TO DO:
239 ------
240
241 Revision History
242 ----------------
243
244 Version Date Description
245
246 0.1 17-Nov-94 Initial writing. ALPHA code release.
247 0.2 13-Jan-95 Added PCI support for DE435's.
248 0.21 19-Jan-95 Added auto media detection.
249 0.22 10-Feb-95 Fix interrupt handler call <chris@cosy.sbg.ac.at>.
250 Fix recognition bug reported by <bkm@star.rl.ac.uk>.
251 Add request/release_region code.
252 Add loadable modules support for PCI.
253 Clean up loadable modules support.
254 0.23 28-Feb-95 Added DC21041 and DC21140 support.
255 Fix missed frame counter value and initialisation.
256 Fixed EISA probe.
257 0.24 11-Apr-95 Change delay routine to use <linux/udelay>.
258 Change TX_BUFFS_AVAIL macro.
259 Change media autodetection to allow manual setting.
260 Completed DE500 (DC21140) support.
261 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm.
262 0.242 10-May-95 Minor changes.
263 0.30 12-Jun-95 Timer fix for DC21140.
264 Portability changes.
265 Add ALPHA changes from <jestabro@ant.tay1.dec.com>.
266 Add DE500 semi automatic autosense.
267 Add Link Fail interrupt TP failure detection.
268 Add timer based link change detection.
269 Plugged a memory leak in de4x5_queue_pkt().
270 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1.
271 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from a
272 suggestion by <heiko@colossus.escape.de>.
273 0.33 8-Aug-95 Add shared interrupt support (not released yet).
274 0.331 21-Aug-95 Fix de4x5_open() with fast CPUs.
275 Fix de4x5_interrupt().
276 Fix dc21140_autoconf() mess.
277 No shared interrupt support.
278 0.332 11-Sep-95 Added MII management interface routines.
279 0.40 5-Mar-96 Fix setup frame timeout <maartenb@hpkuipc.cern.ch>.
280 Add kernel timer code (h/w is too flaky).
281 Add MII based PHY autosense.
282 Add new multicasting code.
283 Add new autosense algorithms for media/mode
284 selection using kernel scheduling/timing.
285 Re-formatted.
286 Made changes suggested by <jeff@router.patch.net>:
287 Change driver to detect all DECchip based cards
288 with DEC_ONLY restriction a special case.
289 Changed driver to autoprobe as a module. No irq
290 checking is done now - assume BIOS is good!
291 Added SMC9332 detection <manabe@Roy.dsl.tutics.ac.jp>
292 0.41 21-Mar-96 Don't check for get_hw_addr checksum unless DEC card
293 only <niles@axp745gsfc.nasa.gov>
294 Fix for multiple PCI cards reported by <jos@xos.nl>
295 Duh, put the IRQF_SHARED flag into request_interrupt().
296 Fix SMC ethernet address in enet_det[].
297 Print chip name instead of "UNKNOWN" during boot.
298 0.42 26-Apr-96 Fix MII write TA bit error.
299 Fix bug in dc21040 and dc21041 autosense code.
300 Remove buffer copies on receive for Intels.
301 Change sk_buff handling during media disconnects to
302 eliminate DUP packets.
303 Add dynamic TX thresholding.
304 Change all chips to use perfect multicast filtering.
305 Fix alloc_device() bug <jari@markkus2.fimr.fi>
306 0.43 21-Jun-96 Fix unconnected media TX retry bug.
307 Add Accton to the list of broken cards.
308 Fix TX under-run bug for non DC21140 chips.
309 Fix boot command probe bug in alloc_device() as
310 reported by <koen.gadeyne@barco.com> and
311 <orava@nether.tky.hut.fi>.
312 Add cache locks to prevent a race condition as
313 reported by <csd@microplex.com> and
314 <baba@beckman.uiuc.edu>.
315 Upgraded alloc_device() code.
316 0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion
317 with <csd@microplex.com>
318 0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips.
319 Fix EISA probe bugs reported by <os2@kpi.kharkov.ua>
320 and <michael@compurex.com>.
321 0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media
322 with a loopback packet.
323 0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported
324 by <bhat@mundook.cs.mu.OZ.AU>
325 0.45 8-Dec-96 Include endian functions for PPC use, from work
326 by <cort@cs.nmt.edu> and <g.thomas@opengroup.org>.
327 0.451 28-Dec-96 Added fix to allow autoprobe for modules after
328 suggestion from <mjacob@feral.com>.
329 0.5 30-Jan-97 Added SROM decoding functions.
330 Updated debug flags.
331 Fix sleep/wakeup calls for PCI cards, bug reported
332 by <cross@gweep.lkg.dec.com>.
333 Added multi-MAC, one SROM feature from discussion
334 with <mjacob@feral.com>.
335 Added full module autoprobe capability.
336 Added attempt to use an SMC9332 with broken SROM.
337 Added fix for ZYNX multi-mac cards that didn't
338 get their IRQs wired correctly.
339 0.51 13-Feb-97 Added endian fixes for the SROM accesses from
340 <paubert@iram.es>
341 Fix init_connection() to remove extra device reset.
342 Fix MAC/PHY reset ordering in dc21140m_autoconf().
343 Fix initialisation problem with lp->timeout in
344 typeX_infoblock() from <paubert@iram.es>.
345 Fix MII PHY reset problem from work done by
346 <paubert@iram.es>.
347 0.52 26-Apr-97 Some changes may not credit the right people -
348 a disk crash meant I lost some mail.
349 Change RX interrupt routine to drop rather than
350 defer packets to avoid hang reported by
351 <g.thomas@opengroup.org>.
352 Fix srom_exec() to return for COMPACT and type 1
353 infoblocks.
354 Added DC21142 and DC21143 functions.
355 Added byte counters from <phil@tazenda.demon.co.uk>
356 Added IRQF_DISABLED temporary fix from
357 <mjacob@feral.com>.
358 0.53 12-Nov-97 Fix the *_probe() to include 'eth??' name during
359 module load: bug reported by
360 <Piete.Brooks@cl.cam.ac.uk>
361 Fix multi-MAC, one SROM, to work with 2114x chips:
362 bug reported by <cmetz@inner.net>.
363 Make above search independent of BIOS device scan
364 direction.
365 Completed DC2114[23] autosense functions.
366 0.531 21-Dec-97 Fix DE500-XA 100Mb/s bug reported by
367 <robin@intercore.com
368 Fix type1_infoblock() bug introduced in 0.53, from
369 problem reports by
370 <parmee@postecss.ncrfran.france.ncr.com> and
371 <jo@ice.dillingen.baynet.de>.
372 Added argument list to set up each board from either
373 a module's command line or a compiled in #define.
374 Added generic MII PHY functionality to deal with
375 newer PHY chips.
376 Fix the mess in 2.1.67.
377 0.532 5-Jan-98 Fix bug in mii_get_phy() reported by
378 <redhat@cococo.net>.
379 Fix bug in pci_probe() for 64 bit systems reported
380 by <belliott@accessone.com>.
381 0.533 9-Jan-98 Fix more 64 bit bugs reported by <jal@cs.brown.edu>.
382 0.534 24-Jan-98 Fix last (?) endian bug from <geert@linux-m68k.org>
383 0.535 21-Feb-98 Fix Ethernet Address PROM reset bug for DC21040.
384 0.536 21-Mar-98 Change pci_probe() to use the pci_dev structure.
385 **Incompatible with 2.0.x from here.**
386 0.540 5-Jul-98 Atomicize assertion of dev->interrupt for SMP
387 from <lma@varesearch.com>
388 Add TP, AUI and BNC cases to 21140m_autoconf() for
389 case where a 21140 under SROM control uses, e.g. AUI
390 from problem report by <delchini@lpnp09.in2p3.fr>
391 Add MII parallel detection to 2114x_autoconf() for
392 case where no autonegotiation partner exists from
393 problem report by <mlapsley@ndirect.co.uk>.
394 Add ability to force connection type directly even
395 when using SROM control from problem report by
396 <earl@exis.net>.
397 Updated the PCI interface to conform with the latest
398 version. I hope nothing is broken...
399 Add TX done interrupt modification from suggestion
400 by <Austin.Donnelly@cl.cam.ac.uk>.
401 Fix is_anc_capable() bug reported by
402 <Austin.Donnelly@cl.cam.ac.uk>.
403 Fix type[13]_infoblock() bug: during MII search, PHY
404 lp->rst not run because lp->ibn not initialised -
405 from report & fix by <paubert@iram.es>.
406 Fix probe bug with EISA & PCI cards present from
407 report by <eirik@netcom.com>.
408 0.541 24-Aug-98 Fix compiler problems associated with i386-string
409 ops from multiple bug reports and temporary fix
410 from <paubert@iram.es>.
411 Fix pci_probe() to correctly emulate the old
412 pcibios_find_class() function.
413 Add an_exception() for old ZYNX346 and fix compile
414 warning on PPC & SPARC, from <ecd@skynet.be>.
415 Fix lastPCI to correctly work with compiled in
416 kernels and modules from bug report by
417 <Zlatko.Calusic@CARNet.hr> et al.
418 0.542 15-Sep-98 Fix dc2114x_autoconf() to stop multiple messages
419 when media is unconnected.
420 Change dev->interrupt to lp->interrupt to ensure
421 alignment for Alpha's and avoid their unaligned
422 access traps. This flag is merely for log messages:
423 should do something more definitive though...
424 0.543 30-Dec-98 Add SMP spin locking.
425 0.544 8-May-99 Fix for buggy SROM in Motorola embedded boards using
426 a 21143 by <mmporter@home.com>.
427 Change PCI/EISA bus probing order.
428 0.545 28-Nov-99 Further Moto SROM bug fix from
429 <mporter@eng.mcd.mot.com>
430 Remove double checking for DEBUG_RX in de4x5_dbg_rx()
431 from report by <geert@linux-m68k.org>
432 0.546 22-Feb-01 Fixes Alpha XP1000 oops. The srom_search function
433 was causing a page fault when initializing the
434 variable 'pb', on a non de4x5 PCI device, in this
435 case a PCI bridge (DEC chip 21152). The value of
436 'pb' is now only initialized if a de4x5 chip is
437 present.
438 <france@handhelds.org>
439 0.547 08-Nov-01 Use library crc32 functions by <Matt_Domsch@dell.com>
440 0.548 30-Aug-03 Big 2.6 cleanup. Ported to PCI/EISA probing and
441 generic DMA APIs. Fixed DE425 support on Alpha.
442 <maz@wild-wind.fr.eu.org>
443 =========================================================================
444 */
445
446 #include <linux/module.h>
447 #include <linux/kernel.h>
448 #include <linux/string.h>
449 #include <linux/interrupt.h>
450 #include <linux/ptrace.h>
451 #include <linux/errno.h>
452 #include <linux/ioport.h>
453 #include <linux/slab.h>
454 #include <linux/pci.h>
455 #include <linux/eisa.h>
456 #include <linux/delay.h>
457 #include <linux/init.h>
458 #include <linux/spinlock.h>
459 #include <linux/crc32.h>
460 #include <linux/netdevice.h>
461 #include <linux/etherdevice.h>
462 #include <linux/skbuff.h>
463 #include <linux/time.h>
464 #include <linux/types.h>
465 #include <linux/unistd.h>
466 #include <linux/ctype.h>
467 #include <linux/dma-mapping.h>
468 #include <linux/moduleparam.h>
469 #include <linux/bitops.h>
470
471 #include <asm/io.h>
472 #include <asm/dma.h>
473 #include <asm/byteorder.h>
474 #include <asm/unaligned.h>
475 #include <asm/uaccess.h>
476 #ifdef CONFIG_PPC_PMAC
477 #include <asm/machdep.h>
478 #endif /* CONFIG_PPC_PMAC */
479
480 #include "de4x5.h"
481
482 static const char version[] __devinitconst =
483 KERN_INFO "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n";
484
485 #define c_char const char
486
487 /*
488 ** MII Information
489 */
490 struct phy_table {
491 int reset; /* Hard reset required? */
492 int id; /* IEEE OUI */
493 int ta; /* One cycle TA time - 802.3u is confusing here */
494 struct { /* Non autonegotiation (parallel) speed det. */
495 int reg;
496 int mask;
497 int value;
498 } spd;
499 };
500
501 struct mii_phy {
502 int reset; /* Hard reset required? */
503 int id; /* IEEE OUI */
504 int ta; /* One cycle TA time */
505 struct { /* Non autonegotiation (parallel) speed det. */
506 int reg;
507 int mask;
508 int value;
509 } spd;
510 int addr; /* MII address for the PHY */
511 u_char *gep; /* Start of GEP sequence block in SROM */
512 u_char *rst; /* Start of reset sequence in SROM */
513 u_int mc; /* Media Capabilities */
514 u_int ana; /* NWay Advertisement */
515 u_int fdx; /* Full DupleX capabilities for each media */
516 u_int ttm; /* Transmit Threshold Mode for each media */
517 u_int mci; /* 21142 MII Connector Interrupt info */
518 };
519
520 #define DE4X5_MAX_PHY 8 /* Allow upto 8 attached PHY devices per board */
521
522 struct sia_phy {
523 u_char mc; /* Media Code */
524 u_char ext; /* csr13-15 valid when set */
525 int csr13; /* SIA Connectivity Register */
526 int csr14; /* SIA TX/RX Register */
527 int csr15; /* SIA General Register */
528 int gepc; /* SIA GEP Control Information */
529 int gep; /* SIA GEP Data */
530 };
531
532 /*
533 ** Define the know universe of PHY devices that can be
534 ** recognised by this driver.
535 */
536 static struct phy_table phy_info[] = {
537 {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}}, /* National TX */
538 {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}}, /* Broadcom T4 */
539 {0, SEEQ_T4 , 1, {0x12, 0x10, 0x10}}, /* SEEQ T4 */
540 {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}}, /* Cypress T4 */
541 {0, 0x7810 , 1, {0x14, 0x0800, 0x0800}} /* Level One LTX970 */
542 };
543
544 /*
545 ** These GENERIC values assumes that the PHY devices follow 802.3u and
546 ** allow parallel detection to set the link partner ability register.
547 ** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
548 */
549 #define GENERIC_REG 0x05 /* Autoneg. Link Partner Advertisement Reg. */
550 #define GENERIC_MASK MII_ANLPA_100M /* All 100Mb/s Technologies */
551 #define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4 */
552
553 /*
554 ** Define special SROM detection cases
555 */
556 static c_char enet_det[][ETH_ALEN] = {
557 {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
558 {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
559 };
560
561 #define SMC 1
562 #define ACCTON 2
563
564 /*
565 ** SROM Repair definitions. If a broken SROM is detected a card may
566 ** use this information to help figure out what to do. This is a
567 ** "stab in the dark" and so far for SMC9332's only.
568 */
569 static c_char srom_repair_info[][100] = {
570 {0x00,0x1e,0x00,0x00,0x00,0x08, /* SMC9332 */
571 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
572 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
573 0x00,0x18,}
574 };
575
576
577 #ifdef DE4X5_DEBUG
578 static int de4x5_debug = DE4X5_DEBUG;
579 #else
580 /*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/
581 static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION);
582 #endif
583
584 /*
585 ** Allow per adapter set up. For modules this is simply a command line
586 ** parameter, e.g.:
587 ** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
588 **
589 ** For a compiled in driver, place e.g.
590 ** #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
591 ** here
592 */
593 #ifdef DE4X5_PARM
594 static char *args = DE4X5_PARM;
595 #else
596 static char *args;
597 #endif
598
599 struct parameters {
600 bool fdx;
601 int autosense;
602 };
603
604 #define DE4X5_AUTOSENSE_MS 250 /* msec autosense tick (DE500) */
605
606 #define DE4X5_NDA 0xffe0 /* No Device (I/O) Address */
607
608 /*
609 ** Ethernet PROM defines
610 */
611 #define PROBE_LENGTH 32
612 #define ETH_PROM_SIG 0xAA5500FFUL
613
614 /*
615 ** Ethernet Info
616 */
617 #define PKT_BUF_SZ 1536 /* Buffer size for each Tx/Rx buffer */
618 #define IEEE802_3_SZ 1518 /* Packet + CRC */
619 #define MAX_PKT_SZ 1514 /* Maximum ethernet packet length */
620 #define MAX_DAT_SZ 1500 /* Maximum ethernet data length */
621 #define MIN_DAT_SZ 1 /* Minimum ethernet data length */
622 #define PKT_HDR_LEN 14 /* Addresses and data length info */
623 #define FAKE_FRAME_LEN (MAX_PKT_SZ + 1)
624 #define QUEUE_PKT_TIMEOUT (3*HZ) /* 3 second timeout */
625
626
627 /*
628 ** EISA bus defines
629 */
630 #define DE4X5_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */
631 #define DE4X5_EISA_TOTAL_SIZE 0x100 /* I/O address extent */
632
633 #define EISA_ALLOWED_IRQ_LIST {5, 9, 10, 11}
634
635 #define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
636 #define DE4X5_NAME_LENGTH 8
637
638 static c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
639
640 /*
641 ** Ethernet PROM defines for DC21040
642 */
643 #define PROBE_LENGTH 32
644 #define ETH_PROM_SIG 0xAA5500FFUL
645
646 /*
647 ** PCI Bus defines
648 */
649 #define PCI_MAX_BUS_NUM 8
650 #define DE4X5_PCI_TOTAL_SIZE 0x80 /* I/O address extent */
651 #define DE4X5_CLASS_CODE 0x00020000 /* Network controller, Ethernet */
652
653 /*
654 ** Memory Alignment. Each descriptor is 4 longwords long. To force a
655 ** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
656 ** DESC_ALIGN. ALIGN aligns the start address of the private memory area
657 ** and hence the RX descriptor ring's first entry.
658 */
659 #define DE4X5_ALIGN4 ((u_long)4 - 1) /* 1 longword align */
660 #define DE4X5_ALIGN8 ((u_long)8 - 1) /* 2 longword align */
661 #define DE4X5_ALIGN16 ((u_long)16 - 1) /* 4 longword align */
662 #define DE4X5_ALIGN32 ((u_long)32 - 1) /* 8 longword align */
663 #define DE4X5_ALIGN64 ((u_long)64 - 1) /* 16 longword align */
664 #define DE4X5_ALIGN128 ((u_long)128 - 1) /* 32 longword align */
665
666 #define DE4X5_ALIGN DE4X5_ALIGN32 /* Keep the DC21040 happy... */
667 #define DE4X5_CACHE_ALIGN CAL_16LONG
668 #define DESC_SKIP_LEN DSL_0 /* Must agree with DESC_ALIGN */
669 /*#define DESC_ALIGN u32 dummy[4]; / * Must agree with DESC_SKIP_LEN */
670 #define DESC_ALIGN
671
672 #ifndef DEC_ONLY /* See README.de4x5 for using this */
673 static int dec_only;
674 #else
675 static int dec_only = 1;
676 #endif
677
678 /*
679 ** DE4X5 IRQ ENABLE/DISABLE
680 */
681 #define ENABLE_IRQs { \
682 imr |= lp->irq_en;\
683 outl(imr, DE4X5_IMR); /* Enable the IRQs */\
684 }
685
686 #define DISABLE_IRQs {\
687 imr = inl(DE4X5_IMR);\
688 imr &= ~lp->irq_en;\
689 outl(imr, DE4X5_IMR); /* Disable the IRQs */\
690 }
691
692 #define UNMASK_IRQs {\
693 imr |= lp->irq_mask;\
694 outl(imr, DE4X5_IMR); /* Unmask the IRQs */\
695 }
696
697 #define MASK_IRQs {\
698 imr = inl(DE4X5_IMR);\
699 imr &= ~lp->irq_mask;\
700 outl(imr, DE4X5_IMR); /* Mask the IRQs */\
701 }
702
703 /*
704 ** DE4X5 START/STOP
705 */
706 #define START_DE4X5 {\
707 omr = inl(DE4X5_OMR);\
708 omr |= OMR_ST | OMR_SR;\
709 outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\
710 }
711
712 #define STOP_DE4X5 {\
713 omr = inl(DE4X5_OMR);\
714 omr &= ~(OMR_ST|OMR_SR);\
715 outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
716 }
717
718 /*
719 ** DE4X5 SIA RESET
720 */
721 #define RESET_SIA outl(0, DE4X5_SICR); /* Reset SIA connectivity regs */
722
723 /*
724 ** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS)
725 */
726 #define DE4X5_AUTOSENSE_MS 250
727
728 /*
729 ** SROM Structure
730 */
731 struct de4x5_srom {
732 char sub_vendor_id[2];
733 char sub_system_id[2];
734 char reserved[12];
735 char id_block_crc;
736 char reserved2;
737 char version;
738 char num_controllers;
739 char ieee_addr[6];
740 char info[100];
741 short chksum;
742 };
743 #define SUB_VENDOR_ID 0x500a
744
745 /*
746 ** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous
747 ** and have sizes of both a power of 2 and a multiple of 4.
748 ** A size of 256 bytes for each buffer could be chosen because over 90% of
749 ** all packets in our network are <256 bytes long and 64 longword alignment
750 ** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX
751 ** descriptors are needed for machines with an ALPHA CPU.
752 */
753 #define NUM_RX_DESC 8 /* Number of RX descriptors */
754 #define NUM_TX_DESC 32 /* Number of TX descriptors */
755 #define RX_BUFF_SZ 1536 /* Power of 2 for kmalloc and */
756 /* Multiple of 4 for DC21040 */
757 /* Allows 512 byte alignment */
758 struct de4x5_desc {
759 volatile __le32 status;
760 __le32 des1;
761 __le32 buf;
762 __le32 next;
763 DESC_ALIGN
764 };
765
766 /*
767 ** The DE4X5 private structure
768 */
769 #define DE4X5_PKT_STAT_SZ 16
770 #define DE4X5_PKT_BIN_SZ 128 /* Should be >=100 unless you
771 increase DE4X5_PKT_STAT_SZ */
772
773 struct pkt_stats {
774 u_int bins[DE4X5_PKT_STAT_SZ]; /* Private stats counters */
775 u_int unicast;
776 u_int multicast;
777 u_int broadcast;
778 u_int excessive_collisions;
779 u_int tx_underruns;
780 u_int excessive_underruns;
781 u_int rx_runt_frames;
782 u_int rx_collision;
783 u_int rx_dribble;
784 u_int rx_overflow;
785 };
786
787 struct de4x5_private {
788 char adapter_name[80]; /* Adapter name */
789 u_long interrupt; /* Aligned ISR flag */
790 struct de4x5_desc *rx_ring; /* RX descriptor ring */
791 struct de4x5_desc *tx_ring; /* TX descriptor ring */
792 struct sk_buff *tx_skb[NUM_TX_DESC]; /* TX skb for freeing when sent */
793 struct sk_buff *rx_skb[NUM_RX_DESC]; /* RX skb's */
794 int rx_new, rx_old; /* RX descriptor ring pointers */
795 int tx_new, tx_old; /* TX descriptor ring pointers */
796 char setup_frame[SETUP_FRAME_LEN]; /* Holds MCA and PA info. */
797 char frame[64]; /* Min sized packet for loopback*/
798 spinlock_t lock; /* Adapter specific spinlock */
799 struct net_device_stats stats; /* Public stats */
800 struct pkt_stats pktStats; /* Private stats counters */
801 char rxRingSize;
802 char txRingSize;
803 int bus; /* EISA or PCI */
804 int bus_num; /* PCI Bus number */
805 int device; /* Device number on PCI bus */
806 int state; /* Adapter OPENED or CLOSED */
807 int chipset; /* DC21040, DC21041 or DC21140 */
808 s32 irq_mask; /* Interrupt Mask (Enable) bits */
809 s32 irq_en; /* Summary interrupt bits */
810 int media; /* Media (eg TP), mode (eg 100B)*/
811 int c_media; /* Remember the last media conn */
812 bool fdx; /* media full duplex flag */
813 int linkOK; /* Link is OK */
814 int autosense; /* Allow/disallow autosensing */
815 bool tx_enable; /* Enable descriptor polling */
816 int setup_f; /* Setup frame filtering type */
817 int local_state; /* State within a 'media' state */
818 struct mii_phy phy[DE4X5_MAX_PHY]; /* List of attached PHY devices */
819 struct sia_phy sia; /* SIA PHY Information */
820 int active; /* Index to active PHY device */
821 int mii_cnt; /* Number of attached PHY's */
822 int timeout; /* Scheduling counter */
823 struct timer_list timer; /* Timer info for kernel */
824 int tmp; /* Temporary global per card */
825 struct {
826 u_long lock; /* Lock the cache accesses */
827 s32 csr0; /* Saved Bus Mode Register */
828 s32 csr6; /* Saved Operating Mode Reg. */
829 s32 csr7; /* Saved IRQ Mask Register */
830 s32 gep; /* Saved General Purpose Reg. */
831 s32 gepc; /* Control info for GEP */
832 s32 csr13; /* Saved SIA Connectivity Reg. */
833 s32 csr14; /* Saved SIA TX/RX Register */
834 s32 csr15; /* Saved SIA General Register */
835 int save_cnt; /* Flag if state already saved */
836 struct sk_buff_head queue; /* Save the (re-ordered) skb's */
837 } cache;
838 struct de4x5_srom srom; /* A copy of the SROM */
839 int cfrv; /* Card CFRV copy */
840 int rx_ovf; /* Check for 'RX overflow' tag */
841 bool useSROM; /* For non-DEC card use SROM */
842 bool useMII; /* Infoblock using the MII */
843 int asBitValid; /* Autosense bits in GEP? */
844 int asPolarity; /* 0 => asserted high */
845 int asBit; /* Autosense bit number in GEP */
846 int defMedium; /* SROM default medium */
847 int tcount; /* Last infoblock number */
848 int infoblock_init; /* Initialised this infoblock? */
849 int infoleaf_offset; /* SROM infoleaf for controller */
850 s32 infoblock_csr6; /* csr6 value in SROM infoblock */
851 int infoblock_media; /* infoblock media */
852 int (*infoleaf_fn)(struct net_device *); /* Pointer to infoleaf function */
853 u_char *rst; /* Pointer to Type 5 reset info */
854 u_char ibn; /* Infoblock number */
855 struct parameters params; /* Command line/ #defined params */
856 struct device *gendev; /* Generic device */
857 dma_addr_t dma_rings; /* DMA handle for rings */
858 int dma_size; /* Size of the DMA area */
859 char *rx_bufs; /* rx bufs on alpha, sparc, ... */
860 };
861
862 /*
863 ** To get around certain poxy cards that don't provide an SROM
864 ** for the second and more DECchip, I have to key off the first
865 ** chip's address. I'll assume there's not a bad SROM iff:
866 **
867 ** o the chipset is the same
868 ** o the bus number is the same and > 0
869 ** o the sum of all the returned hw address bytes is 0 or 0x5fa
870 **
871 ** Also have to save the irq for those cards whose hardware designers
872 ** can't follow the PCI to PCI Bridge Architecture spec.
873 */
874 static struct {
875 int chipset;
876 int bus;
877 int irq;
878 u_char addr[ETH_ALEN];
879 } last = {0,};
880
881 /*
882 ** The transmit ring full condition is described by the tx_old and tx_new
883 ** pointers by:
884 ** tx_old = tx_new Empty ring
885 ** tx_old = tx_new+1 Full ring
886 ** tx_old+txRingSize = tx_new+1 Full ring (wrapped condition)
887 */
888 #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
889 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
890 lp->tx_old -lp->tx_new-1)
891
892 #define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
893
894 /*
895 ** Public Functions
896 */
897 static int de4x5_open(struct net_device *dev);
898 static int de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev);
899 static irqreturn_t de4x5_interrupt(int irq, void *dev_id);
900 static int de4x5_close(struct net_device *dev);
901 static struct net_device_stats *de4x5_get_stats(struct net_device *dev);
902 static void de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len);
903 static void set_multicast_list(struct net_device *dev);
904 static int de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
905
906 /*
907 ** Private functions
908 */
909 static int de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev);
910 static int de4x5_init(struct net_device *dev);
911 static int de4x5_sw_reset(struct net_device *dev);
912 static int de4x5_rx(struct net_device *dev);
913 static int de4x5_tx(struct net_device *dev);
914 static void de4x5_ast(struct net_device *dev);
915 static int de4x5_txur(struct net_device *dev);
916 static int de4x5_rx_ovfc(struct net_device *dev);
917
918 static int autoconf_media(struct net_device *dev);
919 static void create_packet(struct net_device *dev, char *frame, int len);
920 static void load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb);
921 static int dc21040_autoconf(struct net_device *dev);
922 static int dc21041_autoconf(struct net_device *dev);
923 static int dc21140m_autoconf(struct net_device *dev);
924 static int dc2114x_autoconf(struct net_device *dev);
925 static int srom_autoconf(struct net_device *dev);
926 static int de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state, int (*fn)(struct net_device *, int), int (*asfn)(struct net_device *));
927 static int dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct net_device *, int));
928 static int test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
929 static int test_for_100Mb(struct net_device *dev, int msec);
930 static int wait_for_link(struct net_device *dev);
931 static int test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec);
932 static int is_spd_100(struct net_device *dev);
933 static int is_100_up(struct net_device *dev);
934 static int is_10_up(struct net_device *dev);
935 static int is_anc_capable(struct net_device *dev);
936 static int ping_media(struct net_device *dev, int msec);
937 static struct sk_buff *de4x5_alloc_rx_buff(struct net_device *dev, int index, int len);
938 static void de4x5_free_rx_buffs(struct net_device *dev);
939 static void de4x5_free_tx_buffs(struct net_device *dev);
940 static void de4x5_save_skbs(struct net_device *dev);
941 static void de4x5_rst_desc_ring(struct net_device *dev);
942 static void de4x5_cache_state(struct net_device *dev, int flag);
943 static void de4x5_put_cache(struct net_device *dev, struct sk_buff *skb);
944 static void de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb);
945 static struct sk_buff *de4x5_get_cache(struct net_device *dev);
946 static void de4x5_setup_intr(struct net_device *dev);
947 static void de4x5_init_connection(struct net_device *dev);
948 static int de4x5_reset_phy(struct net_device *dev);
949 static void reset_init_sia(struct net_device *dev, s32 sicr, s32 strr, s32 sigr);
950 static int test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec);
951 static int test_tp(struct net_device *dev, s32 msec);
952 static int EISA_signature(char *name, struct device *device);
953 static int PCI_signature(char *name, struct de4x5_private *lp);
954 static void DevicePresent(struct net_device *dev, u_long iobase);
955 static void enet_addr_rst(u_long aprom_addr);
956 static int de4x5_bad_srom(struct de4x5_private *lp);
957 static short srom_rd(u_long address, u_char offset);
958 static void srom_latch(u_int command, u_long address);
959 static void srom_command(u_int command, u_long address);
960 static void srom_address(u_int command, u_long address, u_char offset);
961 static short srom_data(u_int command, u_long address);
962 /*static void srom_busy(u_int command, u_long address);*/
963 static void sendto_srom(u_int command, u_long addr);
964 static int getfrom_srom(u_long addr);
965 static int srom_map_media(struct net_device *dev);
966 static int srom_infoleaf_info(struct net_device *dev);
967 static void srom_init(struct net_device *dev);
968 static void srom_exec(struct net_device *dev, u_char *p);
969 static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
970 static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
971 static int mii_rdata(u_long ioaddr);
972 static void mii_wdata(int data, int len, u_long ioaddr);
973 static void mii_ta(u_long rw, u_long ioaddr);
974 static int mii_swap(int data, int len);
975 static void mii_address(u_char addr, u_long ioaddr);
976 static void sendto_mii(u32 command, int data, u_long ioaddr);
977 static int getfrom_mii(u32 command, u_long ioaddr);
978 static int mii_get_oui(u_char phyaddr, u_long ioaddr);
979 static int mii_get_phy(struct net_device *dev);
980 static void SetMulticastFilter(struct net_device *dev);
981 static int get_hw_addr(struct net_device *dev);
982 static void srom_repair(struct net_device *dev, int card);
983 static int test_bad_enet(struct net_device *dev, int status);
984 static int an_exception(struct de4x5_private *lp);
985 static char *build_setup_frame(struct net_device *dev, int mode);
986 static void disable_ast(struct net_device *dev);
987 static long de4x5_switch_mac_port(struct net_device *dev);
988 static int gep_rd(struct net_device *dev);
989 static void gep_wr(s32 data, struct net_device *dev);
990 static void yawn(struct net_device *dev, int state);
991 static void de4x5_parse_params(struct net_device *dev);
992 static void de4x5_dbg_open(struct net_device *dev);
993 static void de4x5_dbg_mii(struct net_device *dev, int k);
994 static void de4x5_dbg_media(struct net_device *dev);
995 static void de4x5_dbg_srom(struct de4x5_srom *p);
996 static void de4x5_dbg_rx(struct sk_buff *skb, int len);
997 static int de4x5_strncmp(char *a, char *b, int n);
998 static int dc21041_infoleaf(struct net_device *dev);
999 static int dc21140_infoleaf(struct net_device *dev);
1000 static int dc21142_infoleaf(struct net_device *dev);
1001 static int dc21143_infoleaf(struct net_device *dev);
1002 static int type0_infoblock(struct net_device *dev, u_char count, u_char *p);
1003 static int type1_infoblock(struct net_device *dev, u_char count, u_char *p);
1004 static int type2_infoblock(struct net_device *dev, u_char count, u_char *p);
1005 static int type3_infoblock(struct net_device *dev, u_char count, u_char *p);
1006 static int type4_infoblock(struct net_device *dev, u_char count, u_char *p);
1007 static int type5_infoblock(struct net_device *dev, u_char count, u_char *p);
1008 static int compact_infoblock(struct net_device *dev, u_char count, u_char *p);
1009
1010 /*
1011 ** Note now that module autoprobing is allowed under EISA and PCI. The
1012 ** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
1013 ** to "do the right thing".
1014 */
1015
1016 static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED */
1017
1018 module_param(io, int, 0);
1019 module_param(de4x5_debug, int, 0);
1020 module_param(dec_only, int, 0);
1021 module_param(args, charp, 0);
1022
1023 MODULE_PARM_DESC(io, "de4x5 I/O base address");
1024 MODULE_PARM_DESC(de4x5_debug, "de4x5 debug mask");
1025 MODULE_PARM_DESC(dec_only, "de4x5 probe only for Digital boards (0-1)");
1026 MODULE_PARM_DESC(args, "de4x5 full duplex and media type settings; see de4x5.c for details");
1027 MODULE_LICENSE("GPL");
1028
1029 /*
1030 ** List the SROM infoleaf functions and chipsets
1031 */
1032 struct InfoLeaf {
1033 int chipset;
1034 int (*fn)(struct net_device *);
1035 };
1036 static struct InfoLeaf infoleaf_array[] = {
1037 {DC21041, dc21041_infoleaf},
1038 {DC21140, dc21140_infoleaf},
1039 {DC21142, dc21142_infoleaf},
1040 {DC21143, dc21143_infoleaf}
1041 };
1042 #define INFOLEAF_SIZE ARRAY_SIZE(infoleaf_array)
1043
1044 /*
1045 ** List the SROM info block functions
1046 */
1047 static int (*dc_infoblock[])(struct net_device *dev, u_char, u_char *) = {
1048 type0_infoblock,
1049 type1_infoblock,
1050 type2_infoblock,
1051 type3_infoblock,
1052 type4_infoblock,
1053 type5_infoblock,
1054 compact_infoblock
1055 };
1056
1057 #define COMPACT (ARRAY_SIZE(dc_infoblock) - 1)
1058
1059 /*
1060 ** Miscellaneous defines...
1061 */
1062 #define RESET_DE4X5 {\
1063 int i;\
1064 i=inl(DE4X5_BMR);\
1065 mdelay(1);\
1066 outl(i | BMR_SWR, DE4X5_BMR);\
1067 mdelay(1);\
1068 outl(i, DE4X5_BMR);\
1069 mdelay(1);\
1070 for (i=0;i<5;i++) {inl(DE4X5_BMR); mdelay(1);}\
1071 mdelay(1);\
1072 }
1073
1074 #define PHY_HARD_RESET {\
1075 outl(GEP_HRST, DE4X5_GEP); /* Hard RESET the PHY dev. */\
1076 mdelay(1); /* Assert for 1ms */\
1077 outl(0x00, DE4X5_GEP);\
1078 mdelay(2); /* Wait for 2ms */\
1079 }
1080
1081 static const struct net_device_ops de4x5_netdev_ops = {
1082 .ndo_open = de4x5_open,
1083 .ndo_stop = de4x5_close,
1084 .ndo_start_xmit = de4x5_queue_pkt,
1085 .ndo_get_stats = de4x5_get_stats,
1086 .ndo_set_multicast_list = set_multicast_list,
1087 .ndo_do_ioctl = de4x5_ioctl,
1088 .ndo_change_mtu = eth_change_mtu,
1089 .ndo_set_mac_address= eth_mac_addr,
1090 .ndo_validate_addr = eth_validate_addr,
1091 };
1092
1093
1094 static int __devinit
1095 de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev)
1096 {
1097 char name[DE4X5_NAME_LENGTH + 1];
1098 struct de4x5_private *lp = netdev_priv(dev);
1099 struct pci_dev *pdev = NULL;
1100 int i, status=0;
1101
1102 gendev->driver_data = dev;
1103
1104 /* Ensure we're not sleeping */
1105 if (lp->bus == EISA) {
1106 outb(WAKEUP, PCI_CFPM);
1107 } else {
1108 pdev = to_pci_dev (gendev);
1109 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
1110 }
1111 mdelay(10);
1112
1113 RESET_DE4X5;
1114
1115 if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
1116 return -ENXIO; /* Hardware could not reset */
1117 }
1118
1119 /*
1120 ** Now find out what kind of DC21040/DC21041/DC21140 board we have.
1121 */
1122 lp->useSROM = false;
1123 if (lp->bus == PCI) {
1124 PCI_signature(name, lp);
1125 } else {
1126 EISA_signature(name, gendev);
1127 }
1128
1129 if (*name == '\0') { /* Not found a board signature */
1130 return -ENXIO;
1131 }
1132
1133 dev->base_addr = iobase;
1134 printk ("%s: %s at 0x%04lx", dev_name(gendev), name, iobase);
1135
1136 status = get_hw_addr(dev);
1137 printk(", h/w address %pM\n", dev->dev_addr);
1138
1139 if (status != 0) {
1140 printk(" which has an Ethernet PROM CRC error.\n");
1141 return -ENXIO;
1142 } else {
1143 skb_queue_head_init(&lp->cache.queue);
1144 lp->cache.gepc = GEP_INIT;
1145 lp->asBit = GEP_SLNK;
1146 lp->asPolarity = GEP_SLNK;
1147 lp->asBitValid = ~0;
1148 lp->timeout = -1;
1149 lp->gendev = gendev;
1150 spin_lock_init(&lp->lock);
1151 init_timer(&lp->timer);
1152 lp->timer.function = (void (*)(unsigned long))de4x5_ast;
1153 lp->timer.data = (unsigned long)dev;
1154 de4x5_parse_params(dev);
1155
1156 /*
1157 ** Choose correct autosensing in case someone messed up
1158 */
1159 lp->autosense = lp->params.autosense;
1160 if (lp->chipset != DC21140) {
1161 if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1162 lp->params.autosense = TP;
1163 }
1164 if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1165 lp->params.autosense = BNC;
1166 }
1167 }
1168 lp->fdx = lp->params.fdx;
1169 sprintf(lp->adapter_name,"%s (%s)", name, dev_name(gendev));
1170
1171 lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc);
1172 #if defined(__alpha__) || defined(__powerpc__) || defined(CONFIG_SPARC) || defined(DE4X5_DO_MEMCPY)
1173 lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + DE4X5_ALIGN;
1174 #endif
1175 lp->rx_ring = dma_alloc_coherent(gendev, lp->dma_size,
1176 &lp->dma_rings, GFP_ATOMIC);
1177 if (lp->rx_ring == NULL) {
1178 return -ENOMEM;
1179 }
1180
1181 lp->tx_ring = lp->rx_ring + NUM_RX_DESC;
1182
1183 /*
1184 ** Set up the RX descriptor ring (Intels)
1185 ** Allocate contiguous receive buffers, long word aligned (Alphas)
1186 */
1187 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY)
1188 for (i=0; i<NUM_RX_DESC; i++) {
1189 lp->rx_ring[i].status = 0;
1190 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1191 lp->rx_ring[i].buf = 0;
1192 lp->rx_ring[i].next = 0;
1193 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1194 }
1195
1196 #else
1197 {
1198 dma_addr_t dma_rx_bufs;
1199
1200 dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC)
1201 * sizeof(struct de4x5_desc);
1202 dma_rx_bufs = (dma_rx_bufs + DE4X5_ALIGN) & ~DE4X5_ALIGN;
1203 lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC
1204 + NUM_TX_DESC) + DE4X5_ALIGN) & ~DE4X5_ALIGN);
1205 for (i=0; i<NUM_RX_DESC; i++) {
1206 lp->rx_ring[i].status = 0;
1207 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1208 lp->rx_ring[i].buf =
1209 cpu_to_le32(dma_rx_bufs+i*RX_BUFF_SZ);
1210 lp->rx_ring[i].next = 0;
1211 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1212 }
1213
1214 }
1215 #endif
1216
1217 barrier();
1218
1219 lp->rxRingSize = NUM_RX_DESC;
1220 lp->txRingSize = NUM_TX_DESC;
1221
1222 /* Write the end of list marker to the descriptor lists */
1223 lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1224 lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1225
1226 /* Tell the adapter where the TX/RX rings are located. */
1227 outl(lp->dma_rings, DE4X5_RRBA);
1228 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1229 DE4X5_TRBA);
1230
1231 /* Initialise the IRQ mask and Enable/Disable */
1232 lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1233 lp->irq_en = IMR_NIM | IMR_AIM;
1234
1235 /* Create a loopback packet frame for later media probing */
1236 create_packet(dev, lp->frame, sizeof(lp->frame));
1237
1238 /* Check if the RX overflow bug needs testing for */
1239 i = lp->cfrv & 0x000000fe;
1240 if ((lp->chipset == DC21140) && (i == 0x20)) {
1241 lp->rx_ovf = 1;
1242 }
1243
1244 /* Initialise the SROM pointers if possible */
1245 if (lp->useSROM) {
1246 lp->state = INITIALISED;
1247 if (srom_infoleaf_info(dev)) {
1248 dma_free_coherent (gendev, lp->dma_size,
1249 lp->rx_ring, lp->dma_rings);
1250 return -ENXIO;
1251 }
1252 srom_init(dev);
1253 }
1254
1255 lp->state = CLOSED;
1256
1257 /*
1258 ** Check for an MII interface
1259 */
1260 if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1261 mii_get_phy(dev);
1262 }
1263
1264 printk(" and requires IRQ%d (provided by %s).\n", dev->irq,
1265 ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1266 }
1267
1268 if (de4x5_debug & DEBUG_VERSION) {
1269 printk(version);
1270 }
1271
1272 /* The DE4X5-specific entries in the device structure. */
1273 SET_NETDEV_DEV(dev, gendev);
1274 dev->netdev_ops = &de4x5_netdev_ops;
1275 dev->mem_start = 0;
1276
1277 /* Fill in the generic fields of the device structure. */
1278 if ((status = register_netdev (dev))) {
1279 dma_free_coherent (gendev, lp->dma_size,
1280 lp->rx_ring, lp->dma_rings);
1281 return status;
1282 }
1283
1284 /* Let the adapter sleep to save power */
1285 yawn(dev, SLEEP);
1286
1287 return status;
1288 }
1289
1290
1291 static int
1292 de4x5_open(struct net_device *dev)
1293 {
1294 struct de4x5_private *lp = netdev_priv(dev);
1295 u_long iobase = dev->base_addr;
1296 int i, status = 0;
1297 s32 omr;
1298
1299 /* Allocate the RX buffers */
1300 for (i=0; i<lp->rxRingSize; i++) {
1301 if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
1302 de4x5_free_rx_buffs(dev);
1303 return -EAGAIN;
1304 }
1305 }
1306
1307 /*
1308 ** Wake up the adapter
1309 */
1310 yawn(dev, WAKEUP);
1311
1312 /*
1313 ** Re-initialize the DE4X5...
1314 */
1315 status = de4x5_init(dev);
1316 spin_lock_init(&lp->lock);
1317 lp->state = OPEN;
1318 de4x5_dbg_open(dev);
1319
1320 if (request_irq(dev->irq, de4x5_interrupt, IRQF_SHARED,
1321 lp->adapter_name, dev)) {
1322 printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq);
1323 if (request_irq(dev->irq, de4x5_interrupt, IRQF_DISABLED | IRQF_SHARED,
1324 lp->adapter_name, dev)) {
1325 printk("\n Cannot get IRQ- reconfigure your hardware.\n");
1326 disable_ast(dev);
1327 de4x5_free_rx_buffs(dev);
1328 de4x5_free_tx_buffs(dev);
1329 yawn(dev, SLEEP);
1330 lp->state = CLOSED;
1331 return -EAGAIN;
1332 } else {
1333 printk("\n Succeeded, but you should reconfigure your hardware to avoid this.\n");
1334 printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1335 }
1336 }
1337
1338 lp->interrupt = UNMASK_INTERRUPTS;
1339 dev->trans_start = jiffies;
1340
1341 START_DE4X5;
1342
1343 de4x5_setup_intr(dev);
1344
1345 if (de4x5_debug & DEBUG_OPEN) {
1346 printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
1347 printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
1348 printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
1349 printk("\tomr: 0x%08x\n", inl(DE4X5_OMR));
1350 printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
1351 printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
1352 printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
1353 printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
1354 }
1355
1356 return status;
1357 }
1358
1359 /*
1360 ** Initialize the DE4X5 operating conditions. NB: a chip problem with the
1361 ** DC21140 requires using perfect filtering mode for that chip. Since I can't
1362 ** see why I'd want > 14 multicast addresses, I have changed all chips to use
1363 ** the perfect filtering mode. Keep the DMA burst length at 8: there seems
1364 ** to be data corruption problems if it is larger (UDP errors seen from a
1365 ** ttcp source).
1366 */
1367 static int
1368 de4x5_init(struct net_device *dev)
1369 {
1370 /* Lock out other processes whilst setting up the hardware */
1371 netif_stop_queue(dev);
1372
1373 de4x5_sw_reset(dev);
1374
1375 /* Autoconfigure the connected port */
1376 autoconf_media(dev);
1377
1378 return 0;
1379 }
1380
1381 static int
1382 de4x5_sw_reset(struct net_device *dev)
1383 {
1384 struct de4x5_private *lp = netdev_priv(dev);
1385 u_long iobase = dev->base_addr;
1386 int i, j, status = 0;
1387 s32 bmr, omr;
1388
1389 /* Select the MII or SRL port now and RESET the MAC */
1390 if (!lp->useSROM) {
1391 if (lp->phy[lp->active].id != 0) {
1392 lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1393 } else {
1394 lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1395 }
1396 de4x5_switch_mac_port(dev);
1397 }
1398
1399 /*
1400 ** Set the programmable burst length to 8 longwords for all the DC21140
1401 ** Fasternet chips and 4 longwords for all others: DMA errors result
1402 ** without these values. Cache align 16 long.
1403 */
1404 bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | DE4X5_CACHE_ALIGN;
1405 bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1406 outl(bmr, DE4X5_BMR);
1407
1408 omr = inl(DE4X5_OMR) & ~OMR_PR; /* Turn off promiscuous mode */
1409 if (lp->chipset == DC21140) {
1410 omr |= (OMR_SDP | OMR_SB);
1411 }
1412 lp->setup_f = PERFECT;
1413 outl(lp->dma_rings, DE4X5_RRBA);
1414 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1415 DE4X5_TRBA);
1416
1417 lp->rx_new = lp->rx_old = 0;
1418 lp->tx_new = lp->tx_old = 0;
1419
1420 for (i = 0; i < lp->rxRingSize; i++) {
1421 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1422 }
1423
1424 for (i = 0; i < lp->txRingSize; i++) {
1425 lp->tx_ring[i].status = cpu_to_le32(0);
1426 }
1427
1428 barrier();
1429
1430 /* Build the setup frame depending on filtering mode */
1431 SetMulticastFilter(dev);
1432
1433 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1);
1434 outl(omr|OMR_ST, DE4X5_OMR);
1435
1436 /* Poll for setup frame completion (adapter interrupts are disabled now) */
1437
1438 for (j=0, i=0;(i<500) && (j==0);i++) { /* Upto 500ms delay */
1439 mdelay(1);
1440 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1441 }
1442 outl(omr, DE4X5_OMR); /* Stop everything! */
1443
1444 if (j == 0) {
1445 printk("%s: Setup frame timed out, status %08x\n", dev->name,
1446 inl(DE4X5_STS));
1447 status = -EIO;
1448 }
1449
1450 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1451 lp->tx_old = lp->tx_new;
1452
1453 return status;
1454 }
1455
1456 /*
1457 ** Writes a socket buffer address to the next available transmit descriptor.
1458 */
1459 static int
1460 de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev)
1461 {
1462 struct de4x5_private *lp = netdev_priv(dev);
1463 u_long iobase = dev->base_addr;
1464 int status = 0;
1465 u_long flags = 0;
1466
1467 netif_stop_queue(dev);
1468 if (!lp->tx_enable) { /* Cannot send for now */
1469 return -1;
1470 }
1471
1472 /*
1473 ** Clean out the TX ring asynchronously to interrupts - sometimes the
1474 ** interrupts are lost by delayed descriptor status updates relative to
1475 ** the irq assertion, especially with a busy PCI bus.
1476 */
1477 spin_lock_irqsave(&lp->lock, flags);
1478 de4x5_tx(dev);
1479 spin_unlock_irqrestore(&lp->lock, flags);
1480
1481 /* Test if cache is already locked - requeue skb if so */
1482 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1483 return -1;
1484
1485 /* Transmit descriptor ring full or stale skb */
1486 if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) {
1487 if (lp->interrupt) {
1488 de4x5_putb_cache(dev, skb); /* Requeue the buffer */
1489 } else {
1490 de4x5_put_cache(dev, skb);
1491 }
1492 if (de4x5_debug & DEBUG_TX) {
1493 printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%d\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx_new] > 1) ? "YES" : "NO");
1494 }
1495 } else if (skb->len > 0) {
1496 /* If we already have stuff queued locally, use that first */
1497 if (!skb_queue_empty(&lp->cache.queue) && !lp->interrupt) {
1498 de4x5_put_cache(dev, skb);
1499 skb = de4x5_get_cache(dev);
1500 }
1501
1502 while (skb && !netif_queue_stopped(dev) &&
1503 (u_long) lp->tx_skb[lp->tx_new] <= 1) {
1504 spin_lock_irqsave(&lp->lock, flags);
1505 netif_stop_queue(dev);
1506 load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1507 lp->stats.tx_bytes += skb->len;
1508 outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */
1509
1510 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1511 dev->trans_start = jiffies;
1512
1513 if (TX_BUFFS_AVAIL) {
1514 netif_start_queue(dev); /* Another pkt may be queued */
1515 }
1516 skb = de4x5_get_cache(dev);
1517 spin_unlock_irqrestore(&lp->lock, flags);
1518 }
1519 if (skb) de4x5_putb_cache(dev, skb);
1520 }
1521
1522 lp->cache.lock = 0;
1523
1524 return status;
1525 }
1526
1527 /*
1528 ** The DE4X5 interrupt handler.
1529 **
1530 ** I/O Read/Writes through intermediate PCI bridges are never 'posted',
1531 ** so that the asserted interrupt always has some real data to work with -
1532 ** if these I/O accesses are ever changed to memory accesses, ensure the
1533 ** STS write is read immediately to complete the transaction if the adapter
1534 ** is not on bus 0. Lost interrupts can still occur when the PCI bus load
1535 ** is high and descriptor status bits cannot be set before the associated
1536 ** interrupt is asserted and this routine entered.
1537 */
1538 static irqreturn_t
1539 de4x5_interrupt(int irq, void *dev_id)
1540 {
1541 struct net_device *dev = dev_id;
1542 struct de4x5_private *lp;
1543 s32 imr, omr, sts, limit;
1544 u_long iobase;
1545 unsigned int handled = 0;
1546
1547 lp = netdev_priv(dev);
1548 spin_lock(&lp->lock);
1549 iobase = dev->base_addr;
1550
1551 DISABLE_IRQs; /* Ensure non re-entrancy */
1552
1553 if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1554 printk("%s: Re-entering the interrupt handler.\n", dev->name);
1555
1556 synchronize_irq(dev->irq);
1557
1558 for (limit=0; limit<8; limit++) {
1559 sts = inl(DE4X5_STS); /* Read IRQ status */
1560 outl(sts, DE4X5_STS); /* Reset the board interrupts */
1561
1562 if (!(sts & lp->irq_mask)) break;/* All done */
1563 handled = 1;
1564
1565 if (sts & (STS_RI | STS_RU)) /* Rx interrupt (packet[s] arrived) */
1566 de4x5_rx(dev);
1567
1568 if (sts & (STS_TI | STS_TU)) /* Tx interrupt (packet sent) */
1569 de4x5_tx(dev);
1570
1571 if (sts & STS_LNF) { /* TP Link has failed */
1572 lp->irq_mask &= ~IMR_LFM;
1573 }
1574
1575 if (sts & STS_UNF) { /* Transmit underrun */
1576 de4x5_txur(dev);
1577 }
1578
1579 if (sts & STS_SE) { /* Bus Error */
1580 STOP_DE4X5;
1581 printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1582 dev->name, sts);
1583 spin_unlock(&lp->lock);
1584 return IRQ_HANDLED;
1585 }
1586 }
1587
1588 /* Load the TX ring with any locally stored packets */
1589 if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1590 while (!skb_queue_empty(&lp->cache.queue) && !netif_queue_stopped(dev) && lp->tx_enable) {
1591 de4x5_queue_pkt(de4x5_get_cache(dev), dev);
1592 }
1593 lp->cache.lock = 0;
1594 }
1595
1596 lp->interrupt = UNMASK_INTERRUPTS;
1597 ENABLE_IRQs;
1598 spin_unlock(&lp->lock);
1599
1600 return IRQ_RETVAL(handled);
1601 }
1602
1603 static int
1604 de4x5_rx(struct net_device *dev)
1605 {
1606 struct de4x5_private *lp = netdev_priv(dev);
1607 u_long iobase = dev->base_addr;
1608 int entry;
1609 s32 status;
1610
1611 for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1612 entry=lp->rx_new) {
1613 status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
1614
1615 if (lp->rx_ovf) {
1616 if (inl(DE4X5_MFC) & MFC_FOCM) {
1617 de4x5_rx_ovfc(dev);
1618 break;
1619 }
1620 }
1621
1622 if (status & RD_FS) { /* Remember the start of frame */
1623 lp->rx_old = entry;
1624 }
1625
1626 if (status & RD_LS) { /* Valid frame status */
1627 if (lp->tx_enable) lp->linkOK++;
1628 if (status & RD_ES) { /* There was an error. */
1629 lp->stats.rx_errors++; /* Update the error stats. */
1630 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1631 if (status & RD_CE) lp->stats.rx_crc_errors++;
1632 if (status & RD_OF) lp->stats.rx_fifo_errors++;
1633 if (status & RD_TL) lp->stats.rx_length_errors++;
1634 if (status & RD_RF) lp->pktStats.rx_runt_frames++;
1635 if (status & RD_CS) lp->pktStats.rx_collision++;
1636 if (status & RD_DB) lp->pktStats.rx_dribble++;
1637 if (status & RD_OF) lp->pktStats.rx_overflow++;
1638 } else { /* A valid frame received */
1639 struct sk_buff *skb;
1640 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1641 >> 16) - 4;
1642
1643 if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
1644 printk("%s: Insufficient memory; nuking packet.\n",
1645 dev->name);
1646 lp->stats.rx_dropped++;
1647 } else {
1648 de4x5_dbg_rx(skb, pkt_len);
1649
1650 /* Push up the protocol stack */
1651 skb->protocol=eth_type_trans(skb,dev);
1652 de4x5_local_stats(dev, skb->data, pkt_len);
1653 netif_rx(skb);
1654
1655 /* Update stats */
1656 lp->stats.rx_packets++;
1657 lp->stats.rx_bytes += pkt_len;
1658 }
1659 }
1660
1661 /* Change buffer ownership for this frame, back to the adapter */
1662 for (;lp->rx_old!=entry;lp->rx_old=(++lp->rx_old)%lp->rxRingSize) {
1663 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1664 barrier();
1665 }
1666 lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1667 barrier();
1668 }
1669
1670 /*
1671 ** Update entry information
1672 */
1673 lp->rx_new = (++lp->rx_new) % lp->rxRingSize;
1674 }
1675
1676 return 0;
1677 }
1678
1679 static inline void
1680 de4x5_free_tx_buff(struct de4x5_private *lp, int entry)
1681 {
1682 dma_unmap_single(lp->gendev, le32_to_cpu(lp->tx_ring[entry].buf),
1683 le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1,
1684 DMA_TO_DEVICE);
1685 if ((u_long) lp->tx_skb[entry] > 1)
1686 dev_kfree_skb_irq(lp->tx_skb[entry]);
1687 lp->tx_skb[entry] = NULL;
1688 }
1689
1690 /*
1691 ** Buffer sent - check for TX buffer errors.
1692 */
1693 static int
1694 de4x5_tx(struct net_device *dev)
1695 {
1696 struct de4x5_private *lp = netdev_priv(dev);
1697 u_long iobase = dev->base_addr;
1698 int entry;
1699 s32 status;
1700
1701 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1702 status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1703 if (status < 0) { /* Buffer not sent yet */
1704 break;
1705 } else if (status != 0x7fffffff) { /* Not setup frame */
1706 if (status & TD_ES) { /* An error happened */
1707 lp->stats.tx_errors++;
1708 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1709 if (status & TD_LC) lp->stats.tx_window_errors++;
1710 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1711 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1712 if (status & TD_DE) lp->stats.tx_aborted_errors++;
1713
1714 if (TX_PKT_PENDING) {
1715 outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */
1716 }
1717 } else { /* Packet sent */
1718 lp->stats.tx_packets++;
1719 if (lp->tx_enable) lp->linkOK++;
1720 }
1721 /* Update the collision counter */
1722 lp->stats.collisions += ((status & TD_EC) ? 16 :
1723 ((status & TD_CC) >> 3));
1724
1725 /* Free the buffer. */
1726 if (lp->tx_skb[entry] != NULL)
1727 de4x5_free_tx_buff(lp, entry);
1728 }
1729
1730 /* Update all the pointers */
1731 lp->tx_old = (++lp->tx_old) % lp->txRingSize;
1732 }
1733
1734 /* Any resources available? */
1735 if (TX_BUFFS_AVAIL && netif_queue_stopped(dev)) {
1736 if (lp->interrupt)
1737 netif_wake_queue(dev);
1738 else
1739 netif_start_queue(dev);
1740 }
1741
1742 return 0;
1743 }
1744
1745 static void
1746 de4x5_ast(struct net_device *dev)
1747 {
1748 struct de4x5_private *lp = netdev_priv(dev);
1749 int next_tick = DE4X5_AUTOSENSE_MS;
1750 int dt;
1751
1752 if (lp->useSROM)
1753 next_tick = srom_autoconf(dev);
1754 else if (lp->chipset == DC21140)
1755 next_tick = dc21140m_autoconf(dev);
1756 else if (lp->chipset == DC21041)
1757 next_tick = dc21041_autoconf(dev);
1758 else if (lp->chipset == DC21040)
1759 next_tick = dc21040_autoconf(dev);
1760 lp->linkOK = 0;
1761
1762 dt = (next_tick * HZ) / 1000;
1763
1764 if (!dt)
1765 dt = 1;
1766
1767 mod_timer(&lp->timer, jiffies + dt);
1768 }
1769
1770 static int
1771 de4x5_txur(struct net_device *dev)
1772 {
1773 struct de4x5_private *lp = netdev_priv(dev);
1774 u_long iobase = dev->base_addr;
1775 int omr;
1776
1777 omr = inl(DE4X5_OMR);
1778 if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1779 omr &= ~(OMR_ST|OMR_SR);
1780 outl(omr, DE4X5_OMR);
1781 while (inl(DE4X5_STS) & STS_TS);
1782 if ((omr & OMR_TR) < OMR_TR) {
1783 omr += 0x4000;
1784 } else {
1785 omr |= OMR_SF;
1786 }
1787 outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
1788 }
1789
1790 return 0;
1791 }
1792
1793 static int
1794 de4x5_rx_ovfc(struct net_device *dev)
1795 {
1796 struct de4x5_private *lp = netdev_priv(dev);
1797 u_long iobase = dev->base_addr;
1798 int omr;
1799
1800 omr = inl(DE4X5_OMR);
1801 outl(omr & ~OMR_SR, DE4X5_OMR);
1802 while (inl(DE4X5_STS) & STS_RS);
1803
1804 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1805 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1806 lp->rx_new = (++lp->rx_new % lp->rxRingSize);
1807 }
1808
1809 outl(omr, DE4X5_OMR);
1810
1811 return 0;
1812 }
1813
1814 static int
1815 de4x5_close(struct net_device *dev)
1816 {
1817 struct de4x5_private *lp = netdev_priv(dev);
1818 u_long iobase = dev->base_addr;
1819 s32 imr, omr;
1820
1821 disable_ast(dev);
1822
1823 netif_stop_queue(dev);
1824
1825 if (de4x5_debug & DEBUG_CLOSE) {
1826 printk("%s: Shutting down ethercard, status was %8.8x.\n",
1827 dev->name, inl(DE4X5_STS));
1828 }
1829
1830 /*
1831 ** We stop the DE4X5 here... mask interrupts and stop TX & RX
1832 */
1833 DISABLE_IRQs;
1834 STOP_DE4X5;
1835
1836 /* Free the associated irq */
1837 free_irq(dev->irq, dev);
1838 lp->state = CLOSED;
1839
1840 /* Free any socket buffers */
1841 de4x5_free_rx_buffs(dev);
1842 de4x5_free_tx_buffs(dev);
1843
1844 /* Put the adapter to sleep to save power */
1845 yawn(dev, SLEEP);
1846
1847 return 0;
1848 }
1849
1850 static struct net_device_stats *
1851 de4x5_get_stats(struct net_device *dev)
1852 {
1853 struct de4x5_private *lp = netdev_priv(dev);
1854 u_long iobase = dev->base_addr;
1855
1856 lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1857
1858 return &lp->stats;
1859 }
1860
1861 static void
1862 de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len)
1863 {
1864 struct de4x5_private *lp = netdev_priv(dev);
1865 int i;
1866
1867 for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1868 if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1869 lp->pktStats.bins[i]++;
1870 i = DE4X5_PKT_STAT_SZ;
1871 }
1872 }
1873 if (buf[0] & 0x01) { /* Multicast/Broadcast */
1874 if ((*(s32 *)&buf[0] == -1) && (*(s16 *)&buf[4] == -1)) {
1875 lp->pktStats.broadcast++;
1876 } else {
1877 lp->pktStats.multicast++;
1878 }
1879 } else if ((*(s32 *)&buf[0] == *(s32 *)&dev->dev_addr[0]) &&
1880 (*(s16 *)&buf[4] == *(s16 *)&dev->dev_addr[4])) {
1881 lp->pktStats.unicast++;
1882 }
1883
1884 lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */
1885 if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1886 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1887 }
1888
1889 return;
1890 }
1891
1892 /*
1893 ** Removes the TD_IC flag from previous descriptor to improve TX performance.
1894 ** If the flag is changed on a descriptor that is being read by the hardware,
1895 ** I assume PCI transaction ordering will mean you are either successful or
1896 ** just miss asserting the change to the hardware. Anyway you're messing with
1897 ** a descriptor you don't own, but this shouldn't kill the chip provided
1898 ** the descriptor register is read only to the hardware.
1899 */
1900 static void
1901 load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb)
1902 {
1903 struct de4x5_private *lp = netdev_priv(dev);
1904 int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1);
1905 dma_addr_t buf_dma = dma_map_single(lp->gendev, buf, flags & TD_TBS1, DMA_TO_DEVICE);
1906
1907 lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma);
1908 lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1909 lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
1910 lp->tx_skb[lp->tx_new] = skb;
1911 lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC);
1912 barrier();
1913
1914 lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
1915 barrier();
1916 }
1917
1918 /*
1919 ** Set or clear the multicast filter for this adaptor.
1920 */
1921 static void
1922 set_multicast_list(struct net_device *dev)
1923 {
1924 struct de4x5_private *lp = netdev_priv(dev);
1925 u_long iobase = dev->base_addr;
1926
1927 /* First, double check that the adapter is open */
1928 if (lp->state == OPEN) {
1929 if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
1930 u32 omr;
1931 omr = inl(DE4X5_OMR);
1932 omr |= OMR_PR;
1933 outl(omr, DE4X5_OMR);
1934 } else {
1935 SetMulticastFilter(dev);
1936 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1937 SETUP_FRAME_LEN, (struct sk_buff *)1);
1938
1939 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1940 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
1941 dev->trans_start = jiffies;
1942 }
1943 }
1944 }
1945
1946 /*
1947 ** Calculate the hash code and update the logical address filter
1948 ** from a list of ethernet multicast addresses.
1949 ** Little endian crc one liner from Matt Thomas, DEC.
1950 */
1951 static void
1952 SetMulticastFilter(struct net_device *dev)
1953 {
1954 struct de4x5_private *lp = netdev_priv(dev);
1955 struct dev_mc_list *dmi=dev->mc_list;
1956 u_long iobase = dev->base_addr;
1957 int i, j, bit, byte;
1958 u16 hashcode;
1959 u32 omr, crc;
1960 char *pa;
1961 unsigned char *addrs;
1962
1963 omr = inl(DE4X5_OMR);
1964 omr &= ~(OMR_PR | OMR_PM);
1965 pa = build_setup_frame(dev, ALL); /* Build the basic frame */
1966
1967 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 14)) {
1968 omr |= OMR_PM; /* Pass all multicasts */
1969 } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */
1970 for (i=0;i<dev->mc_count;i++) { /* for each address in the list */
1971 addrs=dmi->dmi_addr;
1972 dmi=dmi->next;
1973 if ((*addrs & 0x01) == 1) { /* multicast address? */
1974 crc = ether_crc_le(ETH_ALEN, addrs);
1975 hashcode = crc & HASH_BITS; /* hashcode is 9 LSb of CRC */
1976
1977 byte = hashcode >> 3; /* bit[3-8] -> byte in filter */
1978 bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */
1979
1980 byte <<= 1; /* calc offset into setup frame */
1981 if (byte & 0x02) {
1982 byte -= 1;
1983 }
1984 lp->setup_frame[byte] |= bit;
1985 }
1986 }
1987 } else { /* Perfect filtering */
1988 for (j=0; j<dev->mc_count; j++) {
1989 addrs=dmi->dmi_addr;
1990 dmi=dmi->next;
1991 for (i=0; i<ETH_ALEN; i++) {
1992 *(pa + (i&1)) = *addrs++;
1993 if (i & 0x01) pa += 4;
1994 }
1995 }
1996 }
1997 outl(omr, DE4X5_OMR);
1998
1999 return;
2000 }
2001
2002 #ifdef CONFIG_EISA
2003
2004 static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
2005
2006 static int __init de4x5_eisa_probe (struct device *gendev)
2007 {
2008 struct eisa_device *edev;
2009 u_long iobase;
2010 u_char irq, regval;
2011 u_short vendor;
2012 u32 cfid;
2013 int status, device;
2014 struct net_device *dev;
2015 struct de4x5_private *lp;
2016
2017 edev = to_eisa_device (gendev);
2018 iobase = edev->base_addr;
2019
2020 if (!request_region (iobase, DE4X5_EISA_TOTAL_SIZE, "de4x5"))
2021 return -EBUSY;
2022
2023 if (!request_region (iobase + DE4X5_EISA_IO_PORTS,
2024 DE4X5_EISA_TOTAL_SIZE, "de4x5")) {
2025 status = -EBUSY;
2026 goto release_reg_1;
2027 }
2028
2029 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2030 status = -ENOMEM;
2031 goto release_reg_2;
2032 }
2033 lp = netdev_priv(dev);
2034
2035 cfid = (u32) inl(PCI_CFID);
2036 lp->cfrv = (u_short) inl(PCI_CFRV);
2037 device = (cfid >> 8) & 0x00ffff00;
2038 vendor = (u_short) cfid;
2039
2040 /* Read the EISA Configuration Registers */
2041 regval = inb(EISA_REG0) & (ER0_INTL | ER0_INTT);
2042 #ifdef CONFIG_ALPHA
2043 /* Looks like the Jensen firmware (rev 2.2) doesn't really
2044 * care about the EISA configuration, and thus doesn't
2045 * configure the PLX bridge properly. Oh well... Simply mimic
2046 * the EISA config file to sort it out. */
2047
2048 /* EISA REG1: Assert DecChip 21040 HW Reset */
2049 outb (ER1_IAM | 1, EISA_REG1);
2050 mdelay (1);
2051
2052 /* EISA REG1: Deassert DecChip 21040 HW Reset */
2053 outb (ER1_IAM, EISA_REG1);
2054 mdelay (1);
2055
2056 /* EISA REG3: R/W Burst Transfer Enable */
2057 outb (ER3_BWE | ER3_BRE, EISA_REG3);
2058
2059 /* 32_bit slave/master, Preempt Time=23 bclks, Unlatched Interrupt */
2060 outb (ER0_BSW | ER0_BMW | ER0_EPT | regval, EISA_REG0);
2061 #endif
2062 irq = de4x5_irq[(regval >> 1) & 0x03];
2063
2064 if (is_DC2114x) {
2065 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2066 }
2067 lp->chipset = device;
2068 lp->bus = EISA;
2069
2070 /* Write the PCI Configuration Registers */
2071 outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
2072 outl(0x00006000, PCI_CFLT);
2073 outl(iobase, PCI_CBIO);
2074
2075 DevicePresent(dev, EISA_APROM);
2076
2077 dev->irq = irq;
2078
2079 if (!(status = de4x5_hw_init (dev, iobase, gendev))) {
2080 return 0;
2081 }
2082
2083 free_netdev (dev);
2084 release_reg_2:
2085 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2086 release_reg_1:
2087 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2088
2089 return status;
2090 }
2091
2092 static int __devexit de4x5_eisa_remove (struct device *device)
2093 {
2094 struct net_device *dev;
2095 u_long iobase;
2096
2097 dev = device->driver_data;
2098 iobase = dev->base_addr;
2099
2100 unregister_netdev (dev);
2101 free_netdev (dev);
2102 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2103 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2104
2105 return 0;
2106 }
2107
2108 static struct eisa_device_id de4x5_eisa_ids[] = {
2109 { "DEC4250", 0 }, /* 0 is the board name index... */
2110 { "" }
2111 };
2112 MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2113
2114 static struct eisa_driver de4x5_eisa_driver = {
2115 .id_table = de4x5_eisa_ids,
2116 .driver = {
2117 .name = "de4x5",
2118 .probe = de4x5_eisa_probe,
2119 .remove = __devexit_p (de4x5_eisa_remove),
2120 }
2121 };
2122 MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2123 #endif
2124
2125 #ifdef CONFIG_PCI
2126
2127 /*
2128 ** This function searches the current bus (which is >0) for a DECchip with an
2129 ** SROM, so that in multiport cards that have one SROM shared between multiple
2130 ** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2131 ** For single port cards this is a time waster...
2132 */
2133 static void __devinit
2134 srom_search(struct net_device *dev, struct pci_dev *pdev)
2135 {
2136 u_char pb;
2137 u_short vendor, status;
2138 u_int irq = 0, device;
2139 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2140 int i, j;
2141 struct de4x5_private *lp = netdev_priv(dev);
2142 struct list_head *walk;
2143
2144 list_for_each(walk, &pdev->bus_list) {
2145 struct pci_dev *this_dev = pci_dev_b(walk);
2146
2147 /* Skip the pci_bus list entry */
2148 if (list_entry(walk, struct pci_bus, devices) == pdev->bus) continue;
2149
2150 vendor = this_dev->vendor;
2151 device = this_dev->device << 8;
2152 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2153
2154 /* Get the chip configuration revision register */
2155 pb = this_dev->bus->number;
2156
2157 /* Set the device number information */
2158 lp->device = PCI_SLOT(this_dev->devfn);
2159 lp->bus_num = pb;
2160
2161 /* Set the chipset information */
2162 if (is_DC2114x) {
2163 device = ((this_dev->revision & CFRV_RN) < DC2114x_BRK
2164 ? DC21142 : DC21143);
2165 }
2166 lp->chipset = device;
2167
2168 /* Get the board I/O address (64 bits on sparc64) */
2169 iobase = pci_resource_start(this_dev, 0);
2170
2171 /* Fetch the IRQ to be used */
2172 irq = this_dev->irq;
2173 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2174
2175 /* Check if I/O accesses are enabled */
2176 pci_read_config_word(this_dev, PCI_COMMAND, &status);
2177 if (!(status & PCI_COMMAND_IO)) continue;
2178
2179 /* Search for a valid SROM attached to this DECchip */
2180 DevicePresent(dev, DE4X5_APROM);
2181 for (j=0, i=0; i<ETH_ALEN; i++) {
2182 j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2183 }
2184 if (j != 0 && j != 6 * 0xff) {
2185 last.chipset = device;
2186 last.bus = pb;
2187 last.irq = irq;
2188 for (i=0; i<ETH_ALEN; i++) {
2189 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2190 }
2191 return;
2192 }
2193 }
2194
2195 return;
2196 }
2197
2198 /*
2199 ** PCI bus I/O device probe
2200 ** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not
2201 ** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be
2202 ** enabled by the user first in the set up utility. Hence we just check for
2203 ** enabled features and silently ignore the card if they're not.
2204 **
2205 ** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering
2206 ** bit. Here, check for I/O accesses and then set BM. If you put the card in
2207 ** a non BM slot, you're on your own (and complain to the PC vendor that your
2208 ** PC doesn't conform to the PCI standard)!
2209 **
2210 ** This function is only compatible with the *latest* 2.1.x kernels. For 2.0.x
2211 ** kernels use the V0.535[n] drivers.
2212 */
2213
2214 static int __devinit de4x5_pci_probe (struct pci_dev *pdev,
2215 const struct pci_device_id *ent)
2216 {
2217 u_char pb, pbus = 0, dev_num, dnum = 0, timer;
2218 u_short vendor, status;
2219 u_int irq = 0, device;
2220 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2221 int error;
2222 struct net_device *dev;
2223 struct de4x5_private *lp;
2224
2225 dev_num = PCI_SLOT(pdev->devfn);
2226 pb = pdev->bus->number;
2227
2228 if (io) { /* probe a single PCI device */
2229 pbus = (u_short)(io >> 8);
2230 dnum = (u_short)(io & 0xff);
2231 if ((pbus != pb) || (dnum != dev_num))
2232 return -ENODEV;
2233 }
2234
2235 vendor = pdev->vendor;
2236 device = pdev->device << 8;
2237 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x))
2238 return -ENODEV;
2239
2240 /* Ok, the device seems to be for us. */
2241 if ((error = pci_enable_device (pdev)))
2242 return error;
2243
2244 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2245 error = -ENOMEM;
2246 goto disable_dev;
2247 }
2248
2249 lp = netdev_priv(dev);
2250 lp->bus = PCI;
2251 lp->bus_num = 0;
2252
2253 /* Search for an SROM on this bus */
2254 if (lp->bus_num != pb) {
2255 lp->bus_num = pb;
2256 srom_search(dev, pdev);
2257 }
2258
2259 /* Get the chip configuration revision register */
2260 lp->cfrv = pdev->revision;
2261
2262 /* Set the device number information */
2263 lp->device = dev_num;
2264 lp->bus_num = pb;
2265
2266 /* Set the chipset information */
2267 if (is_DC2114x) {
2268 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2269 }
2270 lp->chipset = device;
2271
2272 /* Get the board I/O address (64 bits on sparc64) */
2273 iobase = pci_resource_start(pdev, 0);
2274
2275 /* Fetch the IRQ to be used */
2276 irq = pdev->irq;
2277 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) {
2278 error = -ENODEV;
2279 goto free_dev;
2280 }
2281
2282 /* Check if I/O accesses and Bus Mastering are enabled */
2283 pci_read_config_word(pdev, PCI_COMMAND, &status);
2284 #ifdef __powerpc__
2285 if (!(status & PCI_COMMAND_IO)) {
2286 status |= PCI_COMMAND_IO;
2287 pci_write_config_word(pdev, PCI_COMMAND, status);
2288 pci_read_config_word(pdev, PCI_COMMAND, &status);
2289 }
2290 #endif /* __powerpc__ */
2291 if (!(status & PCI_COMMAND_IO)) {
2292 error = -ENODEV;
2293 goto free_dev;
2294 }
2295
2296 if (!(status & PCI_COMMAND_MASTER)) {
2297 status |= PCI_COMMAND_MASTER;
2298 pci_write_config_word(pdev, PCI_COMMAND, status);
2299 pci_read_config_word(pdev, PCI_COMMAND, &status);
2300 }
2301 if (!(status & PCI_COMMAND_MASTER)) {
2302 error = -ENODEV;
2303 goto free_dev;
2304 }
2305
2306 /* Check the latency timer for values >= 0x60 */
2307 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &timer);
2308 if (timer < 0x60) {
2309 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x60);
2310 }
2311
2312 DevicePresent(dev, DE4X5_APROM);
2313
2314 if (!request_region (iobase, DE4X5_PCI_TOTAL_SIZE, "de4x5")) {
2315 error = -EBUSY;
2316 goto free_dev;
2317 }
2318
2319 dev->irq = irq;
2320
2321 if ((error = de4x5_hw_init(dev, iobase, &pdev->dev))) {
2322 goto release;
2323 }
2324
2325 return 0;
2326
2327 release:
2328 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2329 free_dev:
2330 free_netdev (dev);
2331 disable_dev:
2332 pci_disable_device (pdev);
2333 return error;
2334 }
2335
2336 static void __devexit de4x5_pci_remove (struct pci_dev *pdev)
2337 {
2338 struct net_device *dev;
2339 u_long iobase;
2340
2341 dev = pdev->dev.driver_data;
2342 iobase = dev->base_addr;
2343
2344 unregister_netdev (dev);
2345 free_netdev (dev);
2346 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2347 pci_disable_device (pdev);
2348 }
2349
2350 static struct pci_device_id de4x5_pci_tbl[] = {
2351 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP,
2352 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
2353 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_PLUS,
2354 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
2355 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
2356 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
2357 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142,
2358 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
2359 { },
2360 };
2361
2362 static struct pci_driver de4x5_pci_driver = {
2363 .name = "de4x5",
2364 .id_table = de4x5_pci_tbl,
2365 .probe = de4x5_pci_probe,
2366 .remove = __devexit_p (de4x5_pci_remove),
2367 };
2368
2369 #endif
2370
2371 /*
2372 ** Auto configure the media here rather than setting the port at compile
2373 ** time. This routine is called by de4x5_init() and when a loss of media is
2374 ** detected (excessive collisions, loss of carrier, no carrier or link fail
2375 ** [TP] or no recent receive activity) to check whether the user has been
2376 ** sneaky and changed the port on us.
2377 */
2378 static int
2379 autoconf_media(struct net_device *dev)
2380 {
2381 struct de4x5_private *lp = netdev_priv(dev);
2382 u_long iobase = dev->base_addr;
2383
2384 disable_ast(dev);
2385
2386 lp->c_media = AUTO; /* Bogus last media */
2387 inl(DE4X5_MFC); /* Zero the lost frames counter */
2388 lp->media = INIT;
2389 lp->tcount = 0;
2390
2391 de4x5_ast(dev);
2392
2393 return lp->media;
2394 }
2395
2396 /*
2397 ** Autoconfigure the media when using the DC21040. AUI cannot be distinguished
2398 ** from BNC as the port has a jumper to set thick or thin wire. When set for
2399 ** BNC, the BNC port will indicate activity if it's not terminated correctly.
2400 ** The only way to test for that is to place a loopback packet onto the
2401 ** network and watch for errors. Since we're messing with the interrupt mask
2402 ** register, disable the board interrupts and do not allow any more packets to
2403 ** be queued to the hardware. Re-enable everything only when the media is
2404 ** found.
2405 ** I may have to "age out" locally queued packets so that the higher layer
2406 ** timeouts don't effectively duplicate packets on the network.
2407 */
2408 static int
2409 dc21040_autoconf(struct net_device *dev)
2410 {
2411 struct de4x5_private *lp = netdev_priv(dev);
2412 u_long iobase = dev->base_addr;
2413 int next_tick = DE4X5_AUTOSENSE_MS;
2414 s32 imr;
2415
2416 switch (lp->media) {
2417 case INIT:
2418 DISABLE_IRQs;
2419 lp->tx_enable = false;
2420 lp->timeout = -1;
2421 de4x5_save_skbs(dev);
2422 if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2423 lp->media = TP;
2424 } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2425 lp->media = BNC_AUI;
2426 } else if (lp->autosense == EXT_SIA) {
2427 lp->media = EXT_SIA;
2428 } else {
2429 lp->media = NC;
2430 }
2431 lp->local_state = 0;
2432 next_tick = dc21040_autoconf(dev);
2433 break;
2434
2435 case TP:
2436 next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
2437 TP_SUSPECT, test_tp);
2438 break;
2439
2440 case TP_SUSPECT:
2441 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
2442 break;
2443
2444 case BNC:
2445 case AUI:
2446 case BNC_AUI:
2447 next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
2448 BNC_AUI_SUSPECT, ping_media);
2449 break;
2450
2451 case BNC_AUI_SUSPECT:
2452 next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
2453 break;
2454
2455 case EXT_SIA:
2456 next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
2457 NC, EXT_SIA_SUSPECT, ping_media);
2458 break;
2459
2460 case EXT_SIA_SUSPECT:
2461 next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
2462 break;
2463
2464 case NC:
2465 /* default to TP for all */
2466 reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
2467 if (lp->media != lp->c_media) {
2468 de4x5_dbg_media(dev);
2469 lp->c_media = lp->media;
2470 }
2471 lp->media = INIT;
2472 lp->tx_enable = false;
2473 break;
2474 }
2475
2476 return next_tick;
2477 }
2478
2479 static int
2480 dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout,
2481 int next_state, int suspect_state,
2482 int (*fn)(struct net_device *, int))
2483 {
2484 struct de4x5_private *lp = netdev_priv(dev);
2485 int next_tick = DE4X5_AUTOSENSE_MS;
2486 int linkBad;
2487
2488 switch (lp->local_state) {
2489 case 0:
2490 reset_init_sia(dev, csr13, csr14, csr15);
2491 lp->local_state++;
2492 next_tick = 500;
2493 break;
2494
2495 case 1:
2496 if (!lp->tx_enable) {
2497 linkBad = fn(dev, timeout);
2498 if (linkBad < 0) {
2499 next_tick = linkBad & ~TIMER_CB;
2500 } else {
2501 if (linkBad && (lp->autosense == AUTO)) {
2502 lp->local_state = 0;
2503 lp->media = next_state;
2504 } else {
2505 de4x5_init_connection(dev);
2506 }
2507 }
2508 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2509 lp->media = suspect_state;
2510 next_tick = 3000;
2511 }
2512 break;
2513 }
2514
2515 return next_tick;
2516 }
2517
2518 static int
2519 de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state,
2520 int (*fn)(struct net_device *, int),
2521 int (*asfn)(struct net_device *))
2522 {
2523 struct de4x5_private *lp = netdev_priv(dev);
2524 int next_tick = DE4X5_AUTOSENSE_MS;
2525 int linkBad;
2526
2527 switch (lp->local_state) {
2528 case 1:
2529 if (lp->linkOK) {
2530 lp->media = prev_state;
2531 } else {
2532 lp->local_state++;
2533 next_tick = asfn(dev);
2534 }
2535 break;
2536
2537 case 2:
2538 linkBad = fn(dev, timeout);
2539 if (linkBad < 0) {
2540 next_tick = linkBad & ~TIMER_CB;
2541 } else if (!linkBad) {
2542 lp->local_state--;
2543 lp->media = prev_state;
2544 } else {
2545 lp->media = INIT;
2546 lp->tcount++;
2547 }
2548 }
2549
2550 return next_tick;
2551 }
2552
2553 /*
2554 ** Autoconfigure the media when using the DC21041. AUI needs to be tested
2555 ** before BNC, because the BNC port will indicate activity if it's not
2556 ** terminated correctly. The only way to test for that is to place a loopback
2557 ** packet onto the network and watch for errors. Since we're messing with
2558 ** the interrupt mask register, disable the board interrupts and do not allow
2559 ** any more packets to be queued to the hardware. Re-enable everything only
2560 ** when the media is found.
2561 */
2562 static int
2563 dc21041_autoconf(struct net_device *dev)
2564 {
2565 struct de4x5_private *lp = netdev_priv(dev);
2566 u_long iobase = dev->base_addr;
2567 s32 sts, irqs, irq_mask, imr, omr;
2568 int next_tick = DE4X5_AUTOSENSE_MS;
2569
2570 switch (lp->media) {
2571 case INIT:
2572 DISABLE_IRQs;
2573 lp->tx_enable = false;
2574 lp->timeout = -1;
2575 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2576 if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2577 lp->media = TP; /* On chip auto negotiation is broken */
2578 } else if (lp->autosense == TP) {
2579 lp->media = TP;
2580 } else if (lp->autosense == BNC) {
2581 lp->media = BNC;
2582 } else if (lp->autosense == AUI) {
2583 lp->media = AUI;
2584 } else {
2585 lp->media = NC;
2586 }
2587 lp->local_state = 0;
2588 next_tick = dc21041_autoconf(dev);
2589 break;
2590
2591 case TP_NW:
2592 if (lp->timeout < 0) {
2593 omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */
2594 outl(omr | OMR_FDX, DE4X5_OMR);
2595 }
2596 irqs = STS_LNF | STS_LNP;
2597 irq_mask = IMR_LFM | IMR_LPM;
2598 sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
2599 if (sts < 0) {
2600 next_tick = sts & ~TIMER_CB;
2601 } else {
2602 if (sts & STS_LNP) {
2603 lp->media = ANS;
2604 } else {
2605 lp->media = AUI;
2606 }
2607 next_tick = dc21041_autoconf(dev);
2608 }
2609 break;
2610
2611 case ANS:
2612 if (!lp->tx_enable) {
2613 irqs = STS_LNP;
2614 irq_mask = IMR_LPM;
2615 sts = test_ans(dev, irqs, irq_mask, 3000);
2616 if (sts < 0) {
2617 next_tick = sts & ~TIMER_CB;
2618 } else {
2619 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2620 lp->media = TP;
2621 next_tick = dc21041_autoconf(dev);
2622 } else {
2623 lp->local_state = 1;
2624 de4x5_init_connection(dev);
2625 }
2626 }
2627 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2628 lp->media = ANS_SUSPECT;
2629 next_tick = 3000;
2630 }
2631 break;
2632
2633 case ANS_SUSPECT:
2634 next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
2635 break;
2636
2637 case TP:
2638 if (!lp->tx_enable) {
2639 if (lp->timeout < 0) {
2640 omr = inl(DE4X5_OMR); /* Set up half duplex for TP */
2641 outl(omr & ~OMR_FDX, DE4X5_OMR);
2642 }
2643 irqs = STS_LNF | STS_LNP;
2644 irq_mask = IMR_LFM | IMR_LPM;
2645 sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
2646 if (sts < 0) {
2647 next_tick = sts & ~TIMER_CB;
2648 } else {
2649 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2650 if (inl(DE4X5_SISR) & SISR_NRA) {
2651 lp->media = AUI; /* Non selected port activity */
2652 } else {
2653 lp->media = BNC;
2654 }
2655 next_tick = dc21041_autoconf(dev);
2656 } else {
2657 lp->local_state = 1;
2658 de4x5_init_connection(dev);
2659 }
2660 }
2661 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2662 lp->media = TP_SUSPECT;
2663 next_tick = 3000;
2664 }
2665 break;
2666
2667 case TP_SUSPECT:
2668 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
2669 break;
2670
2671 case AUI:
2672 if (!lp->tx_enable) {
2673 if (lp->timeout < 0) {
2674 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
2675 outl(omr & ~OMR_FDX, DE4X5_OMR);
2676 }
2677 irqs = 0;
2678 irq_mask = 0;
2679 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000);
2680 if (sts < 0) {
2681 next_tick = sts & ~TIMER_CB;
2682 } else {
2683 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2684 lp->media = BNC;
2685 next_tick = dc21041_autoconf(dev);
2686 } else {
2687 lp->local_state = 1;
2688 de4x5_init_connection(dev);
2689 }
2690 }
2691 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2692 lp->media = AUI_SUSPECT;
2693 next_tick = 3000;
2694 }
2695 break;
2696
2697 case AUI_SUSPECT:
2698 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
2699 break;
2700
2701 case BNC:
2702 switch (lp->local_state) {
2703 case 0:
2704 if (lp->timeout < 0) {
2705 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
2706 outl(omr & ~OMR_FDX, DE4X5_OMR);
2707 }
2708 irqs = 0;
2709 irq_mask = 0;
2710 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000);
2711 if (sts < 0) {
2712 next_tick = sts & ~TIMER_CB;
2713 } else {
2714 lp->local_state++; /* Ensure media connected */
2715 next_tick = dc21041_autoconf(dev);
2716 }
2717 break;
2718
2719 case 1:
2720 if (!lp->tx_enable) {
2721 if ((sts = ping_media(dev, 3000)) < 0) {
2722 next_tick = sts & ~TIMER_CB;
2723 } else {
2724 if (sts) {
2725 lp->local_state = 0;
2726 lp->media = NC;
2727 } else {
2728 de4x5_init_connection(dev);
2729 }
2730 }
2731 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2732 lp->media = BNC_SUSPECT;
2733 next_tick = 3000;
2734 }
2735 break;
2736 }
2737 break;
2738
2739 case BNC_SUSPECT:
2740 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
2741 break;
2742
2743 case NC:
2744 omr = inl(DE4X5_OMR); /* Set up full duplex for the autonegotiate */
2745 outl(omr | OMR_FDX, DE4X5_OMR);
2746 reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
2747 if (lp->media != lp->c_media) {
2748 de4x5_dbg_media(dev);
2749 lp->c_media = lp->media;
2750 }
2751 lp->media = INIT;
2752 lp->tx_enable = false;
2753 break;
2754 }
2755
2756 return next_tick;
2757 }
2758
2759 /*
2760 ** Some autonegotiation chips are broken in that they do not return the
2761 ** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement
2762 ** register, except at the first power up negotiation.
2763 */
2764 static int
2765 dc21140m_autoconf(struct net_device *dev)
2766 {
2767 struct de4x5_private *lp = netdev_priv(dev);
2768 int ana, anlpa, cap, cr, slnk, sr;
2769 int next_tick = DE4X5_AUTOSENSE_MS;
2770 u_long imr, omr, iobase = dev->base_addr;
2771
2772 switch(lp->media) {
2773 case INIT:
2774 if (lp->timeout < 0) {
2775 DISABLE_IRQs;
2776 lp->tx_enable = false;
2777 lp->linkOK = 0;
2778 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2779 }
2780 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2781 next_tick &= ~TIMER_CB;
2782 } else {
2783 if (lp->useSROM) {
2784 if (srom_map_media(dev) < 0) {
2785 lp->tcount++;
2786 return next_tick;
2787 }
2788 srom_exec(dev, lp->phy[lp->active].gep);
2789 if (lp->infoblock_media == ANS) {
2790 ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2791 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2792 }
2793 } else {
2794 lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */
2795 SET_10Mb;
2796 if (lp->autosense == _100Mb) {
2797 lp->media = _100Mb;
2798 } else if (lp->autosense == _10Mb) {
2799 lp->media = _10Mb;
2800 } else if ((lp->autosense == AUTO) &&
2801 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2802 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2803 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2804 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2805 lp->media = ANS;
2806 } else if (lp->autosense == AUTO) {
2807 lp->media = SPD_DET;
2808 } else if (is_spd_100(dev) && is_100_up(dev)) {
2809 lp->media = _100Mb;
2810 } else {
2811 lp->media = NC;
2812 }
2813 }
2814 lp->local_state = 0;
2815 next_tick = dc21140m_autoconf(dev);
2816 }
2817 break;
2818
2819 case ANS:
2820 switch (lp->local_state) {
2821 case 0:
2822 if (lp->timeout < 0) {
2823 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2824 }
2825 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, false, 500);
2826 if (cr < 0) {
2827 next_tick = cr & ~TIMER_CB;
2828 } else {
2829 if (cr) {
2830 lp->local_state = 0;
2831 lp->media = SPD_DET;
2832 } else {
2833 lp->local_state++;
2834 }
2835 next_tick = dc21140m_autoconf(dev);
2836 }
2837 break;
2838
2839 case 1:
2840 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, true, 2000)) < 0) {
2841 next_tick = sr & ~TIMER_CB;
2842 } else {
2843 lp->media = SPD_DET;
2844 lp->local_state = 0;
2845 if (sr) { /* Success! */
2846 lp->tmp = MII_SR_ASSC;
2847 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2848 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2849 if (!(anlpa & MII_ANLPA_RF) &&
2850 (cap = anlpa & MII_ANLPA_TAF & ana)) {
2851 if (cap & MII_ANA_100M) {
2852 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
2853 lp->media = _100Mb;
2854 } else if (cap & MII_ANA_10M) {
2855 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
2856
2857 lp->media = _10Mb;
2858 }
2859 }
2860 } /* Auto Negotiation failed to finish */
2861 next_tick = dc21140m_autoconf(dev);
2862 } /* Auto Negotiation failed to start */
2863 break;
2864 }
2865 break;
2866
2867 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
2868 if (lp->timeout < 0) {
2869 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2870 (~gep_rd(dev) & GEP_LNP));
2871 SET_100Mb_PDET;
2872 }
2873 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
2874 next_tick = slnk & ~TIMER_CB;
2875 } else {
2876 if (is_spd_100(dev) && is_100_up(dev)) {
2877 lp->media = _100Mb;
2878 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2879 lp->media = _10Mb;
2880 } else {
2881 lp->media = NC;
2882 }
2883 next_tick = dc21140m_autoconf(dev);
2884 }
2885 break;
2886
2887 case _100Mb: /* Set 100Mb/s */
2888 next_tick = 3000;
2889 if (!lp->tx_enable) {
2890 SET_100Mb;
2891 de4x5_init_connection(dev);
2892 } else {
2893 if (!lp->linkOK && (lp->autosense == AUTO)) {
2894 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2895 lp->media = INIT;
2896 lp->tcount++;
2897 next_tick = DE4X5_AUTOSENSE_MS;
2898 }
2899 }
2900 }
2901 break;
2902
2903 case BNC:
2904 case AUI:
2905 case _10Mb: /* Set 10Mb/s */
2906 next_tick = 3000;
2907 if (!lp->tx_enable) {
2908 SET_10Mb;
2909 de4x5_init_connection(dev);
2910 } else {
2911 if (!lp->linkOK && (lp->autosense == AUTO)) {
2912 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2913 lp->media = INIT;
2914 lp->tcount++;
2915 next_tick = DE4X5_AUTOSENSE_MS;
2916 }
2917 }
2918 }
2919 break;
2920
2921 case NC:
2922 if (lp->media != lp->c_media) {
2923 de4x5_dbg_media(dev);
2924 lp->c_media = lp->media;
2925 }
2926 lp->media = INIT;
2927 lp->tx_enable = false;
2928 break;
2929 }
2930
2931 return next_tick;
2932 }
2933
2934 /*
2935 ** This routine may be merged into dc21140m_autoconf() sometime as I'm
2936 ** changing how I figure out the media - but trying to keep it backwards
2937 ** compatible with the de500-xa and de500-aa.
2938 ** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock
2939 ** functions and set during de4x5_mac_port() and/or de4x5_reset_phy().
2940 ** This routine just has to figure out whether 10Mb/s or 100Mb/s is
2941 ** active.
2942 ** When autonegotiation is working, the ANS part searches the SROM for
2943 ** the highest common speed (TP) link that both can run and if that can
2944 ** be full duplex. That infoblock is executed and then the link speed set.
2945 **
2946 ** Only _10Mb and _100Mb are tested here.
2947 */
2948 static int
2949 dc2114x_autoconf(struct net_device *dev)
2950 {
2951 struct de4x5_private *lp = netdev_priv(dev);
2952 u_long iobase = dev->base_addr;
2953 s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts;
2954 int next_tick = DE4X5_AUTOSENSE_MS;
2955
2956 switch (lp->media) {
2957 case INIT:
2958 if (lp->timeout < 0) {
2959 DISABLE_IRQs;
2960 lp->tx_enable = false;
2961 lp->linkOK = 0;
2962 lp->timeout = -1;
2963 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2964 if (lp->params.autosense & ~AUTO) {
2965 srom_map_media(dev); /* Fixed media requested */
2966 if (lp->media != lp->params.autosense) {
2967 lp->tcount++;
2968 lp->media = INIT;
2969 return next_tick;
2970 }
2971 lp->media = INIT;
2972 }
2973 }
2974 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2975 next_tick &= ~TIMER_CB;
2976 } else {
2977 if (lp->autosense == _100Mb) {
2978 lp->media = _100Mb;
2979 } else if (lp->autosense == _10Mb) {
2980 lp->media = _10Mb;
2981 } else if (lp->autosense == TP) {
2982 lp->media = TP;
2983 } else if (lp->autosense == BNC) {
2984 lp->media = BNC;
2985 } else if (lp->autosense == AUI) {
2986 lp->media = AUI;
2987 } else {
2988 lp->media = SPD_DET;
2989 if ((lp->infoblock_media == ANS) &&
2990 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2991 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2992 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2993 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2994 lp->media = ANS;
2995 }
2996 }
2997 lp->local_state = 0;
2998 next_tick = dc2114x_autoconf(dev);
2999 }
3000 break;
3001
3002 case ANS:
3003 switch (lp->local_state) {
3004 case 0:
3005 if (lp->timeout < 0) {
3006 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3007 }
3008 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, false, 500);
3009 if (cr < 0) {
3010 next_tick = cr & ~TIMER_CB;
3011 } else {
3012 if (cr) {
3013 lp->local_state = 0;
3014 lp->media = SPD_DET;
3015 } else {
3016 lp->local_state++;
3017 }
3018 next_tick = dc2114x_autoconf(dev);
3019 }
3020 break;
3021
3022 case 1:
3023 sr = test_mii_reg(dev, MII_SR, MII_SR_ASSC, true, 2000);
3024 if (sr < 0) {
3025 next_tick = sr & ~TIMER_CB;
3026 } else {
3027 lp->media = SPD_DET;
3028 lp->local_state = 0;
3029 if (sr) { /* Success! */
3030 lp->tmp = MII_SR_ASSC;
3031 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3032 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3033 if (!(anlpa & MII_ANLPA_RF) &&
3034 (cap = anlpa & MII_ANLPA_TAF & ana)) {
3035 if (cap & MII_ANA_100M) {
3036 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
3037 lp->media = _100Mb;
3038 } else if (cap & MII_ANA_10M) {
3039 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
3040 lp->media = _10Mb;
3041 }
3042 }
3043 } /* Auto Negotiation failed to finish */
3044 next_tick = dc2114x_autoconf(dev);
3045 } /* Auto Negotiation failed to start */
3046 break;
3047 }
3048 break;
3049
3050 case AUI:
3051 if (!lp->tx_enable) {
3052 if (lp->timeout < 0) {
3053 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
3054 outl(omr & ~OMR_FDX, DE4X5_OMR);
3055 }
3056 irqs = 0;
3057 irq_mask = 0;
3058 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3059 if (sts < 0) {
3060 next_tick = sts & ~TIMER_CB;
3061 } else {
3062 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3063 lp->media = BNC;
3064 next_tick = dc2114x_autoconf(dev);
3065 } else {
3066 lp->local_state = 1;
3067 de4x5_init_connection(dev);
3068 }
3069 }
3070 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3071 lp->media = AUI_SUSPECT;
3072 next_tick = 3000;
3073 }
3074 break;
3075
3076 case AUI_SUSPECT:
3077 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf);
3078 break;
3079
3080 case BNC:
3081 switch (lp->local_state) {
3082 case 0:
3083 if (lp->timeout < 0) {
3084 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
3085 outl(omr & ~OMR_FDX, DE4X5_OMR);
3086 }
3087 irqs = 0;
3088 irq_mask = 0;
3089 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3090 if (sts < 0) {
3091 next_tick = sts & ~TIMER_CB;
3092 } else {
3093 lp->local_state++; /* Ensure media connected */
3094 next_tick = dc2114x_autoconf(dev);
3095 }
3096 break;
3097
3098 case 1:
3099 if (!lp->tx_enable) {
3100 if ((sts = ping_media(dev, 3000)) < 0) {
3101 next_tick = sts & ~TIMER_CB;
3102 } else {
3103 if (sts) {
3104 lp->local_state = 0;
3105 lp->tcount++;
3106 lp->media = INIT;
3107 } else {
3108 de4x5_init_connection(dev);
3109 }
3110 }
3111 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3112 lp->media = BNC_SUSPECT;
3113 next_tick = 3000;
3114 }
3115 break;
3116 }
3117 break;
3118
3119 case BNC_SUSPECT:
3120 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf);
3121 break;
3122
3123 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
3124 if (srom_map_media(dev) < 0) {
3125 lp->tcount++;
3126 lp->media = INIT;
3127 return next_tick;
3128 }
3129 if (lp->media == _100Mb) {
3130 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3131 lp->media = SPD_DET;
3132 return (slnk & ~TIMER_CB);
3133 }
3134 } else {
3135 if (wait_for_link(dev) < 0) {
3136 lp->media = SPD_DET;
3137 return PDET_LINK_WAIT;
3138 }
3139 }
3140 if (lp->media == ANS) { /* Do MII parallel detection */
3141 if (is_spd_100(dev)) {
3142 lp->media = _100Mb;
3143 } else {
3144 lp->media = _10Mb;
3145 }
3146 next_tick = dc2114x_autoconf(dev);
3147 } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3148 (((lp->media == _10Mb) || (lp->media == TP) ||
3149 (lp->media == BNC) || (lp->media == AUI)) &&
3150 is_10_up(dev))) {
3151 next_tick = dc2114x_autoconf(dev);
3152 } else {
3153 lp->tcount++;
3154 lp->media = INIT;
3155 }
3156 break;
3157
3158 case _10Mb:
3159 next_tick = 3000;
3160 if (!lp->tx_enable) {
3161 SET_10Mb;
3162 de4x5_init_connection(dev);
3163 } else {
3164 if (!lp->linkOK && (lp->autosense == AUTO)) {
3165 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3166 lp->media = INIT;
3167 lp->tcount++;
3168 next_tick = DE4X5_AUTOSENSE_MS;
3169 }
3170 }
3171 }
3172 break;
3173
3174 case _100Mb:
3175 next_tick = 3000;
3176 if (!lp->tx_enable) {
3177 SET_100Mb;
3178 de4x5_init_connection(dev);
3179 } else {
3180 if (!lp->linkOK && (lp->autosense == AUTO)) {
3181 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3182 lp->media = INIT;
3183 lp->tcount++;
3184 next_tick = DE4X5_AUTOSENSE_MS;
3185 }
3186 }
3187 }
3188 break;
3189
3190 default:
3191 lp->tcount++;
3192 printk("Huh?: media:%02x\n", lp->media);
3193 lp->media = INIT;
3194 break;
3195 }
3196
3197 return next_tick;
3198 }
3199
3200 static int
3201 srom_autoconf(struct net_device *dev)
3202 {
3203 struct de4x5_private *lp = netdev_priv(dev);
3204
3205 return lp->infoleaf_fn(dev);
3206 }
3207
3208 /*
3209 ** This mapping keeps the original media codes and FDX flag unchanged.
3210 ** While it isn't strictly necessary, it helps me for the moment...
3211 ** The early return avoids a media state / SROM media space clash.
3212 */
3213 static int
3214 srom_map_media(struct net_device *dev)
3215 {
3216 struct de4x5_private *lp = netdev_priv(dev);
3217
3218 lp->fdx = false;
3219 if (lp->infoblock_media == lp->media)
3220 return 0;
3221
3222 switch(lp->infoblock_media) {
3223 case SROM_10BASETF:
3224 if (!lp->params.fdx) return -1;
3225 lp->fdx = true;
3226 case SROM_10BASET:
3227 if (lp->params.fdx && !lp->fdx) return -1;
3228 if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3229 lp->media = _10Mb;
3230 } else {
3231 lp->media = TP;
3232 }
3233 break;
3234
3235 case SROM_10BASE2:
3236 lp->media = BNC;
3237 break;
3238
3239 case SROM_10BASE5:
3240 lp->media = AUI;
3241 break;
3242
3243 case SROM_100BASETF:
3244 if (!lp->params.fdx) return -1;
3245 lp->fdx = true;
3246 case SROM_100BASET:
3247 if (lp->params.fdx && !lp->fdx) return -1;
3248 lp->media = _100Mb;
3249 break;
3250
3251 case SROM_100BASET4:
3252 lp->media = _100Mb;
3253 break;
3254
3255 case SROM_100BASEFF:
3256 if (!lp->params.fdx) return -1;
3257 lp->fdx = true;
3258 case SROM_100BASEF:
3259 if (lp->params.fdx && !lp->fdx) return -1;
3260 lp->media = _100Mb;
3261 break;
3262
3263 case ANS:
3264 lp->media = ANS;
3265 lp->fdx = lp->params.fdx;
3266 break;
3267
3268 default:
3269 printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
3270 lp->infoblock_media);
3271 return -1;
3272 break;
3273 }
3274
3275 return 0;
3276 }
3277
3278 static void
3279 de4x5_init_connection(struct net_device *dev)
3280 {
3281 struct de4x5_private *lp = netdev_priv(dev);
3282 u_long iobase = dev->base_addr;
3283 u_long flags = 0;
3284
3285 if (lp->media != lp->c_media) {
3286 de4x5_dbg_media(dev);
3287 lp->c_media = lp->media; /* Stop scrolling media messages */
3288 }
3289
3290 spin_lock_irqsave(&lp->lock, flags);
3291 de4x5_rst_desc_ring(dev);
3292 de4x5_setup_intr(dev);
3293 lp->tx_enable = true;
3294 spin_unlock_irqrestore(&lp->lock, flags);
3295 outl(POLL_DEMAND, DE4X5_TPD);
3296
3297 netif_wake_queue(dev);
3298
3299 return;
3300 }
3301
3302 /*
3303 ** General PHY reset function. Some MII devices don't reset correctly
3304 ** since their MII address pins can float at voltages that are dependent
3305 ** on the signal pin use. Do a double reset to ensure a reset.
3306 */
3307 static int
3308 de4x5_reset_phy(struct net_device *dev)
3309 {
3310 struct de4x5_private *lp = netdev_priv(dev);
3311 u_long iobase = dev->base_addr;
3312 int next_tick = 0;
3313
3314 if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3315 if (lp->timeout < 0) {
3316 if (lp->useSROM) {
3317 if (lp->phy[lp->active].rst) {
3318 srom_exec(dev, lp->phy[lp->active].rst);
3319 srom_exec(dev, lp->phy[lp->active].rst);
3320 } else if (lp->rst) { /* Type 5 infoblock reset */
3321 srom_exec(dev, lp->rst);
3322 srom_exec(dev, lp->rst);
3323 }
3324 } else {
3325 PHY_HARD_RESET;
3326 }
3327 if (lp->useMII) {
3328 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3329 }
3330 }
3331 if (lp->useMII) {
3332 next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, false, 500);
3333 }
3334 } else if (lp->chipset == DC21140) {
3335 PHY_HARD_RESET;
3336 }
3337
3338 return next_tick;
3339 }
3340
3341 static int
3342 test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
3343 {
3344 struct de4x5_private *lp = netdev_priv(dev);
3345 u_long iobase = dev->base_addr;
3346 s32 sts, csr12;
3347
3348 if (lp->timeout < 0) {
3349 lp->timeout = msec/100;
3350 if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */
3351 reset_init_sia(dev, csr13, csr14, csr15);
3352 }
3353
3354 /* set up the interrupt mask */
3355 outl(irq_mask, DE4X5_IMR);
3356
3357 /* clear all pending interrupts */
3358 sts = inl(DE4X5_STS);
3359 outl(sts, DE4X5_STS);
3360
3361 /* clear csr12 NRA and SRA bits */
3362 if ((lp->chipset == DC21041) || lp->useSROM) {
3363 csr12 = inl(DE4X5_SISR);
3364 outl(csr12, DE4X5_SISR);
3365 }
3366 }
3367
3368 sts = inl(DE4X5_STS) & ~TIMER_CB;
3369
3370 if (!(sts & irqs) && --lp->timeout) {
3371 sts = 100 | TIMER_CB;
3372 } else {
3373 lp->timeout = -1;
3374 }
3375
3376 return sts;
3377 }
3378
3379 static int
3380 test_tp(struct net_device *dev, s32 msec)
3381 {
3382 struct de4x5_private *lp = netdev_priv(dev);
3383 u_long iobase = dev->base_addr;
3384 int sisr;
3385
3386 if (lp->timeout < 0) {
3387 lp->timeout = msec/100;
3388 }
3389
3390 sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
3391
3392 if (sisr && --lp->timeout) {
3393 sisr = 100 | TIMER_CB;
3394 } else {
3395 lp->timeout = -1;
3396 }
3397
3398 return sisr;
3399 }
3400
3401 /*
3402 ** Samples the 100Mb Link State Signal. The sample interval is important
3403 ** because too fast a rate can give erroneous results and confuse the
3404 ** speed sense algorithm.
3405 */
3406 #define SAMPLE_INTERVAL 500 /* ms */
3407 #define SAMPLE_DELAY 2000 /* ms */
3408 static int
3409 test_for_100Mb(struct net_device *dev, int msec)
3410 {
3411 struct de4x5_private *lp = netdev_priv(dev);
3412 int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3413
3414 if (lp->timeout < 0) {
3415 if ((msec/SAMPLE_INTERVAL) <= 0) return 0;
3416 if (msec > SAMPLE_DELAY) {
3417 lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3418 gep = SAMPLE_DELAY | TIMER_CB;
3419 return gep;
3420 } else {
3421 lp->timeout = msec/SAMPLE_INTERVAL;
3422 }
3423 }
3424
3425 if (lp->phy[lp->active].id || lp->useSROM) {
3426 gep = is_100_up(dev) | is_spd_100(dev);
3427 } else {
3428 gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP));
3429 }
3430 if (!(gep & ret) && --lp->timeout) {
3431 gep = SAMPLE_INTERVAL | TIMER_CB;
3432 } else {
3433 lp->timeout = -1;
3434 }
3435
3436 return gep;
3437 }
3438
3439 static int
3440 wait_for_link(struct net_device *dev)
3441 {
3442 struct de4x5_private *lp = netdev_priv(dev);
3443
3444 if (lp->timeout < 0) {
3445 lp->timeout = 1;
3446 }
3447
3448 if (lp->timeout--) {
3449 return TIMER_CB;
3450 } else {
3451 lp->timeout = -1;
3452 }
3453
3454 return 0;
3455 }
3456
3457 /*
3458 **
3459 **
3460 */
3461 static int
3462 test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec)
3463 {
3464 struct de4x5_private *lp = netdev_priv(dev);
3465 int test;
3466 u_long iobase = dev->base_addr;
3467
3468 if (lp->timeout < 0) {
3469 lp->timeout = msec/100;
3470 }
3471
3472 reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3473 test = (reg ^ (pol ? ~0 : 0)) & mask;
3474
3475 if (test && --lp->timeout) {
3476 reg = 100 | TIMER_CB;
3477 } else {
3478 lp->timeout = -1;
3479 }
3480
3481 return reg;
3482 }
3483
3484 static int
3485 is_spd_100(struct net_device *dev)
3486 {
3487 struct de4x5_private *lp = netdev_priv(dev);
3488 u_long iobase = dev->base_addr;
3489 int spd;
3490
3491 if (lp->useMII) {
3492 spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3493 spd = ~(spd ^ lp->phy[lp->active].spd.value);
3494 spd &= lp->phy[lp->active].spd.mask;
3495 } else if (!lp->useSROM) { /* de500-xa */
3496 spd = ((~gep_rd(dev)) & GEP_SLNK);
3497 } else {
3498 if ((lp->ibn == 2) || !lp->asBitValid)
3499 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3500
3501 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3502 (lp->linkOK & ~lp->asBitValid);
3503 }
3504
3505 return spd;
3506 }
3507
3508 static int
3509 is_100_up(struct net_device *dev)
3510 {
3511 struct de4x5_private *lp = netdev_priv(dev);
3512 u_long iobase = dev->base_addr;
3513
3514 if (lp->useMII) {
3515 /* Double read for sticky bits & temporary drops */
3516 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3517 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3518 } else if (!lp->useSROM) { /* de500-xa */
3519 return ((~gep_rd(dev)) & GEP_SLNK);
3520 } else {
3521 if ((lp->ibn == 2) || !lp->asBitValid)
3522 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3523
3524 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3525 (lp->linkOK & ~lp->asBitValid));
3526 }
3527 }
3528
3529 static int
3530 is_10_up(struct net_device *dev)
3531 {
3532 struct de4x5_private *lp = netdev_priv(dev);
3533 u_long iobase = dev->base_addr;
3534
3535 if (lp->useMII) {
3536 /* Double read for sticky bits & temporary drops */
3537 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3538 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3539 } else if (!lp->useSROM) { /* de500-xa */
3540 return ((~gep_rd(dev)) & GEP_LNP);
3541 } else {
3542 if ((lp->ibn == 2) || !lp->asBitValid)
3543 return (((lp->chipset & ~0x00ff) == DC2114x) ?
3544 (~inl(DE4X5_SISR)&SISR_LS10):
3545 0);
3546
3547 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3548 (lp->linkOK & ~lp->asBitValid));
3549 }
3550 }
3551
3552 static int
3553 is_anc_capable(struct net_device *dev)
3554 {
3555 struct de4x5_private *lp = netdev_priv(dev);
3556 u_long iobase = dev->base_addr;
3557
3558 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3559 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII));
3560 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3561 return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3562 } else {
3563 return 0;
3564 }
3565 }
3566
3567 /*
3568 ** Send a packet onto the media and watch for send errors that indicate the
3569 ** media is bad or unconnected.
3570 */
3571 static int
3572 ping_media(struct net_device *dev, int msec)
3573 {
3574 struct de4x5_private *lp = netdev_priv(dev);
3575 u_long iobase = dev->base_addr;
3576 int sisr;
3577
3578 if (lp->timeout < 0) {
3579 lp->timeout = msec/100;
3580
3581 lp->tmp = lp->tx_new; /* Remember the ring position */
3582 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1);
3583 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
3584 outl(POLL_DEMAND, DE4X5_TPD);
3585 }
3586
3587 sisr = inl(DE4X5_SISR);
3588
3589 if ((!(sisr & SISR_NCR)) &&
3590 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3591 (--lp->timeout)) {
3592 sisr = 100 | TIMER_CB;
3593 } else {
3594 if ((!(sisr & SISR_NCR)) &&
3595 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3596 lp->timeout) {
3597 sisr = 0;
3598 } else {
3599 sisr = 1;
3600 }
3601 lp->timeout = -1;
3602 }
3603
3604 return sisr;
3605 }
3606
3607 /*
3608 ** This function does 2 things: on Intels it kmalloc's another buffer to
3609 ** replace the one about to be passed up. On Alpha's it kmallocs a buffer
3610 ** into which the packet is copied.
3611 */
3612 static struct sk_buff *
3613 de4x5_alloc_rx_buff(struct net_device *dev, int index, int len)
3614 {
3615 struct de4x5_private *lp = netdev_priv(dev);
3616 struct sk_buff *p;
3617
3618 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY)
3619 struct sk_buff *ret;
3620 u_long i=0, tmp;
3621
3622 p = dev_alloc_skb(IEEE802_3_SZ + DE4X5_ALIGN + 2);
3623 if (!p) return NULL;
3624
3625 tmp = virt_to_bus(p->data);
3626 i = ((tmp + DE4X5_ALIGN) & ~DE4X5_ALIGN) - tmp;
3627 skb_reserve(p, i);
3628 lp->rx_ring[index].buf = cpu_to_le32(tmp + i);
3629
3630 ret = lp->rx_skb[index];
3631 lp->rx_skb[index] = p;
3632
3633 if ((u_long) ret > 1) {
3634 skb_put(ret, len);
3635 }
3636
3637 return ret;
3638
3639 #else
3640 if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */
3641
3642 p = dev_alloc_skb(len + 2);
3643 if (!p) return NULL;
3644
3645 skb_reserve(p, 2); /* Align */
3646 if (index < lp->rx_old) { /* Wrapped buffer */
3647 short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3648 memcpy(skb_put(p,tlen),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,tlen);
3649 memcpy(skb_put(p,len-tlen),lp->rx_bufs,len-tlen);
3650 } else { /* Linear buffer */
3651 memcpy(skb_put(p,len),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,len);
3652 }
3653
3654 return p;
3655 #endif
3656 }
3657
3658 static void
3659 de4x5_free_rx_buffs(struct net_device *dev)
3660 {
3661 struct de4x5_private *lp = netdev_priv(dev);
3662 int i;
3663
3664 for (i=0; i<lp->rxRingSize; i++) {
3665 if ((u_long) lp->rx_skb[i] > 1) {
3666 dev_kfree_skb(lp->rx_skb[i]);
3667 }
3668 lp->rx_ring[i].status = 0;
3669 lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */
3670 }
3671
3672 return;
3673 }
3674
3675 static void
3676 de4x5_free_tx_buffs(struct net_device *dev)
3677 {
3678 struct de4x5_private *lp = netdev_priv(dev);
3679 int i;
3680
3681 for (i=0; i<lp->txRingSize; i++) {
3682 if (lp->tx_skb[i])
3683 de4x5_free_tx_buff(lp, i);
3684 lp->tx_ring[i].status = 0;
3685 }
3686
3687 /* Unload the locally queued packets */
3688 __skb_queue_purge(&lp->cache.queue);
3689 }
3690
3691 /*
3692 ** When a user pulls a connection, the DECchip can end up in a
3693 ** 'running - waiting for end of transmission' state. This means that we
3694 ** have to perform a chip soft reset to ensure that we can synchronize
3695 ** the hardware and software and make any media probes using a loopback
3696 ** packet meaningful.
3697 */
3698 static void
3699 de4x5_save_skbs(struct net_device *dev)
3700 {
3701 struct de4x5_private *lp = netdev_priv(dev);
3702 u_long iobase = dev->base_addr;
3703 s32 omr;
3704
3705 if (!lp->cache.save_cnt) {
3706 STOP_DE4X5;
3707 de4x5_tx(dev); /* Flush any sent skb's */
3708 de4x5_free_tx_buffs(dev);
3709 de4x5_cache_state(dev, DE4X5_SAVE_STATE);
3710 de4x5_sw_reset(dev);
3711 de4x5_cache_state(dev, DE4X5_RESTORE_STATE);
3712 lp->cache.save_cnt++;
3713 START_DE4X5;
3714 }
3715
3716 return;
3717 }
3718
3719 static void
3720 de4x5_rst_desc_ring(struct net_device *dev)
3721 {
3722 struct de4x5_private *lp = netdev_priv(dev);
3723 u_long iobase = dev->base_addr;
3724 int i;
3725 s32 omr;
3726
3727 if (lp->cache.save_cnt) {
3728 STOP_DE4X5;
3729 outl(lp->dma_rings, DE4X5_RRBA);
3730 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
3731 DE4X5_TRBA);
3732
3733 lp->rx_new = lp->rx_old = 0;
3734 lp->tx_new = lp->tx_old = 0;
3735
3736 for (i = 0; i < lp->rxRingSize; i++) {
3737 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3738 }
3739
3740 for (i = 0; i < lp->txRingSize; i++) {
3741 lp->tx_ring[i].status = cpu_to_le32(0);
3742 }
3743
3744 barrier();
3745 lp->cache.save_cnt--;
3746 START_DE4X5;
3747 }
3748
3749 return;
3750 }
3751
3752 static void
3753 de4x5_cache_state(struct net_device *dev, int flag)
3754 {
3755 struct de4x5_private *lp = netdev_priv(dev);
3756 u_long iobase = dev->base_addr;
3757
3758 switch(flag) {
3759 case DE4X5_SAVE_STATE:
3760 lp->cache.csr0 = inl(DE4X5_BMR);
3761 lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3762 lp->cache.csr7 = inl(DE4X5_IMR);
3763 break;
3764
3765 case DE4X5_RESTORE_STATE:
3766 outl(lp->cache.csr0, DE4X5_BMR);
3767 outl(lp->cache.csr6, DE4X5_OMR);
3768 outl(lp->cache.csr7, DE4X5_IMR);
3769 if (lp->chipset == DC21140) {
3770 gep_wr(lp->cache.gepc, dev);
3771 gep_wr(lp->cache.gep, dev);
3772 } else {
3773 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
3774 lp->cache.csr15);
3775 }
3776 break;
3777 }
3778
3779 return;
3780 }
3781
3782 static void
3783 de4x5_put_cache(struct net_device *dev, struct sk_buff *skb)
3784 {
3785 struct de4x5_private *lp = netdev_priv(dev);
3786
3787 __skb_queue_tail(&lp->cache.queue, skb);
3788 }
3789
3790 static void
3791 de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb)
3792 {
3793 struct de4x5_private *lp = netdev_priv(dev);
3794
3795 __skb_queue_head(&lp->cache.queue, skb);
3796 }
3797
3798 static struct sk_buff *
3799 de4x5_get_cache(struct net_device *dev)
3800 {
3801 struct de4x5_private *lp = netdev_priv(dev);
3802
3803 return __skb_dequeue(&lp->cache.queue);
3804 }
3805
3806 /*
3807 ** Check the Auto Negotiation State. Return OK when a link pass interrupt
3808 ** is received and the auto-negotiation status is NWAY OK.
3809 */
3810 static int
3811 test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec)
3812 {
3813 struct de4x5_private *lp = netdev_priv(dev);
3814 u_long iobase = dev->base_addr;
3815 s32 sts, ans;
3816
3817 if (lp->timeout < 0) {
3818 lp->timeout = msec/100;
3819 outl(irq_mask, DE4X5_IMR);
3820
3821 /* clear all pending interrupts */
3822 sts = inl(DE4X5_STS);
3823 outl(sts, DE4X5_STS);
3824 }
3825
3826 ans = inl(DE4X5_SISR) & SISR_ANS;
3827 sts = inl(DE4X5_STS) & ~TIMER_CB;
3828
3829 if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3830 sts = 100 | TIMER_CB;
3831 } else {
3832 lp->timeout = -1;
3833 }
3834
3835 return sts;
3836 }
3837
3838 static void
3839 de4x5_setup_intr(struct net_device *dev)
3840 {
3841 struct de4x5_private *lp = netdev_priv(dev);
3842 u_long iobase = dev->base_addr;
3843 s32 imr, sts;
3844
3845 if (inl(DE4X5_OMR) & OMR_SR) { /* Only unmask if TX/RX is enabled */
3846 imr = 0;
3847 UNMASK_IRQs;
3848 sts = inl(DE4X5_STS); /* Reset any pending (stale) interrupts */
3849 outl(sts, DE4X5_STS);
3850 ENABLE_IRQs;
3851 }
3852
3853 return;
3854 }
3855
3856 /*
3857 **
3858 */
3859 static void
3860 reset_init_sia(struct net_device *dev, s32 csr13, s32 csr14, s32 csr15)
3861 {
3862 struct de4x5_private *lp = netdev_priv(dev);
3863 u_long iobase = dev->base_addr;
3864
3865 RESET_SIA;
3866 if (lp->useSROM) {
3867 if (lp->ibn == 3) {
3868 srom_exec(dev, lp->phy[lp->active].rst);
3869 srom_exec(dev, lp->phy[lp->active].gep);
3870 outl(1, DE4X5_SICR);
3871 return;
3872 } else {
3873 csr15 = lp->cache.csr15;
3874 csr14 = lp->cache.csr14;
3875 csr13 = lp->cache.csr13;
3876 outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3877 outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3878 }
3879 } else {
3880 outl(csr15, DE4X5_SIGR);
3881 }
3882 outl(csr14, DE4X5_STRR);
3883 outl(csr13, DE4X5_SICR);
3884
3885 mdelay(10);
3886
3887 return;
3888 }
3889
3890 /*
3891 ** Create a loopback ethernet packet
3892 */
3893 static void
3894 create_packet(struct net_device *dev, char *frame, int len)
3895 {
3896 int i;
3897 char *buf = frame;
3898
3899 for (i=0; i<ETH_ALEN; i++) { /* Use this source address */
3900 *buf++ = dev->dev_addr[i];
3901 }
3902 for (i=0; i<ETH_ALEN; i++) { /* Use this destination address */
3903 *buf++ = dev->dev_addr[i];
3904 }
3905
3906 *buf++ = 0; /* Packet length (2 bytes) */
3907 *buf++ = 1;
3908
3909 return;
3910 }
3911
3912 /*
3913 ** Look for a particular board name in the EISA configuration space
3914 */
3915 static int
3916 EISA_signature(char *name, struct device *device)
3917 {
3918 int i, status = 0, siglen = ARRAY_SIZE(de4x5_signatures);
3919 struct eisa_device *edev;
3920
3921 *name = '\0';
3922 edev = to_eisa_device (device);
3923 i = edev->id.driver_data;
3924
3925 if (i >= 0 && i < siglen) {
3926 strcpy (name, de4x5_signatures[i]);
3927 status = 1;
3928 }
3929
3930 return status; /* return the device name string */
3931 }
3932
3933 /*
3934 ** Look for a particular board name in the PCI configuration space
3935 */
3936 static int
3937 PCI_signature(char *name, struct de4x5_private *lp)
3938 {
3939 int i, status = 0, siglen = ARRAY_SIZE(de4x5_signatures);
3940
3941 if (lp->chipset == DC21040) {
3942 strcpy(name, "DE434/5");
3943 return status;
3944 } else { /* Search for a DEC name in the SROM */
3945 int tmp = *((char *)&lp->srom + 19) * 3;
3946 strncpy(name, (char *)&lp->srom + 26 + tmp, 8);
3947 }
3948 name[8] = '\0';
3949 for (i=0; i<siglen; i++) {
3950 if (strstr(name,de4x5_signatures[i])!=NULL) break;
3951 }
3952 if (i == siglen) {
3953 if (dec_only) {
3954 *name = '\0';
3955 } else { /* Use chip name to avoid confusion */
3956 strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
3957 ((lp->chipset == DC21041) ? "DC21041" :
3958 ((lp->chipset == DC21140) ? "DC21140" :
3959 ((lp->chipset == DC21142) ? "DC21142" :
3960 ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
3961 )))))));
3962 }
3963 if (lp->chipset != DC21041) {
3964 lp->useSROM = true; /* card is not recognisably DEC */
3965 }
3966 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3967 lp->useSROM = true;
3968 }
3969
3970 return status;
3971 }
3972
3973 /*
3974 ** Set up the Ethernet PROM counter to the start of the Ethernet address on
3975 ** the DC21040, else read the SROM for the other chips.
3976 ** The SROM may not be present in a multi-MAC card, so first read the
3977 ** MAC address and check for a bad address. If there is a bad one then exit
3978 ** immediately with the prior srom contents intact (the h/w address will
3979 ** be fixed up later).
3980 */
3981 static void
3982 DevicePresent(struct net_device *dev, u_long aprom_addr)
3983 {
3984 int i, j=0;
3985 struct de4x5_private *lp = netdev_priv(dev);
3986
3987 if (lp->chipset == DC21040) {
3988 if (lp->bus == EISA) {
3989 enet_addr_rst(aprom_addr); /* Reset Ethernet Address ROM Pointer */
3990 } else {
3991 outl(0, aprom_addr); /* Reset Ethernet Address ROM Pointer */
3992 }
3993 } else { /* Read new srom */
3994 u_short tmp;
3995 __le16 *p = (__le16 *)((char *)&lp->srom + SROM_HWADD);
3996 for (i=0; i<(ETH_ALEN>>1); i++) {
3997 tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
3998 j += tmp; /* for check for 0:0:0:0:0:0 or ff:ff:ff:ff:ff:ff */
3999 *p = cpu_to_le16(tmp);
4000 }
4001 if (j == 0 || j == 3 * 0xffff) {
4002 /* could get 0 only from all-0 and 3 * 0xffff only from all-1 */
4003 return;
4004 }
4005
4006 p = (__le16 *)&lp->srom;
4007 for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
4008 tmp = srom_rd(aprom_addr, i);
4009 *p++ = cpu_to_le16(tmp);
4010 }
4011 de4x5_dbg_srom((struct de4x5_srom *)&lp->srom);
4012 }
4013
4014 return;
4015 }
4016
4017 /*
4018 ** Since the write on the Enet PROM register doesn't seem to reset the PROM
4019 ** pointer correctly (at least on my DE425 EISA card), this routine should do
4020 ** it...from depca.c.
4021 */
4022 static void
4023 enet_addr_rst(u_long aprom_addr)
4024 {
4025 union {
4026 struct {
4027 u32 a;
4028 u32 b;
4029 } llsig;
4030 char Sig[sizeof(u32) << 1];
4031 } dev;
4032 short sigLength=0;
4033 s8 data;
4034 int i, j;
4035
4036 dev.llsig.a = ETH_PROM_SIG;
4037 dev.llsig.b = ETH_PROM_SIG;
4038 sigLength = sizeof(u32) << 1;
4039
4040 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
4041 data = inb(aprom_addr);
4042 if (dev.Sig[j] == data) { /* track signature */
4043 j++;
4044 } else { /* lost signature; begin search again */
4045 if (data == dev.Sig[0]) { /* rare case.... */
4046 j=1;
4047 } else {
4048 j=0;
4049 }
4050 }
4051 }
4052
4053 return;
4054 }
4055
4056 /*
4057 ** For the bad status case and no SROM, then add one to the previous
4058 ** address. However, need to add one backwards in case we have 0xff
4059 ** as one or more of the bytes. Only the last 3 bytes should be checked
4060 ** as the first three are invariant - assigned to an organisation.
4061 */
4062 static int
4063 get_hw_addr(struct net_device *dev)
4064 {
4065 u_long iobase = dev->base_addr;
4066 int broken, i, k, tmp, status = 0;
4067 u_short j,chksum;
4068 struct de4x5_private *lp = netdev_priv(dev);
4069
4070 broken = de4x5_bad_srom(lp);
4071
4072 for (i=0,k=0,j=0;j<3;j++) {
4073 k <<= 1;
4074 if (k > 0xffff) k-=0xffff;
4075
4076 if (lp->bus == PCI) {
4077 if (lp->chipset == DC21040) {
4078 while ((tmp = inl(DE4X5_APROM)) < 0);
4079 k += (u_char) tmp;
4080 dev->dev_addr[i++] = (u_char) tmp;
4081 while ((tmp = inl(DE4X5_APROM)) < 0);
4082 k += (u_short) (tmp << 8);
4083 dev->dev_addr[i++] = (u_char) tmp;
4084 } else if (!broken) {
4085 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4086 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4087 } else if ((broken == SMC) || (broken == ACCTON)) {
4088 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4089 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4090 }
4091 } else {
4092 k += (u_char) (tmp = inb(EISA_APROM));
4093 dev->dev_addr[i++] = (u_char) tmp;
4094 k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4095 dev->dev_addr[i++] = (u_char) tmp;
4096 }
4097
4098 if (k > 0xffff) k-=0xffff;
4099 }
4100 if (k == 0xffff) k=0;
4101
4102 if (lp->bus == PCI) {
4103 if (lp->chipset == DC21040) {
4104 while ((tmp = inl(DE4X5_APROM)) < 0);
4105 chksum = (u_char) tmp;
4106 while ((tmp = inl(DE4X5_APROM)) < 0);
4107 chksum |= (u_short) (tmp << 8);
4108 if ((k != chksum) && (dec_only)) status = -1;
4109 }
4110 } else {
4111 chksum = (u_char) inb(EISA_APROM);
4112 chksum |= (u_short) (inb(EISA_APROM) << 8);
4113 if ((k != chksum) && (dec_only)) status = -1;
4114 }
4115
4116 /* If possible, try to fix a broken card - SMC only so far */
4117 srom_repair(dev, broken);
4118
4119 #ifdef CONFIG_PPC_PMAC
4120 /*
4121 ** If the address starts with 00 a0, we have to bit-reverse
4122 ** each byte of the address.
4123 */
4124 if ( machine_is(powermac) &&
4125 (dev->dev_addr[0] == 0) &&
4126 (dev->dev_addr[1] == 0xa0) )
4127 {
4128 for (i = 0; i < ETH_ALEN; ++i)
4129 {
4130 int x = dev->dev_addr[i];
4131 x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4);
4132 x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2);
4133 dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
4134 }
4135 }
4136 #endif /* CONFIG_PPC_PMAC */
4137
4138 /* Test for a bad enet address */
4139 status = test_bad_enet(dev, status);
4140
4141 return status;
4142 }
4143
4144 /*
4145 ** Test for enet addresses in the first 32 bytes. The built-in strncmp
4146 ** didn't seem to work here...?
4147 */
4148 static int
4149 de4x5_bad_srom(struct de4x5_private *lp)
4150 {
4151 int i, status = 0;
4152
4153 for (i = 0; i < ARRAY_SIZE(enet_det); i++) {
4154 if (!de4x5_strncmp((char *)&lp->srom, (char *)&enet_det[i], 3) &&
4155 !de4x5_strncmp((char *)&lp->srom+0x10, (char *)&enet_det[i], 3)) {
4156 if (i == 0) {
4157 status = SMC;
4158 } else if (i == 1) {
4159 status = ACCTON;
4160 }
4161 break;
4162 }
4163 }
4164
4165 return status;
4166 }
4167
4168 static int
4169 de4x5_strncmp(char *a, char *b, int n)
4170 {
4171 int ret=0;
4172
4173 for (;n && !ret; n--) {
4174 ret = *a++ - *b++;
4175 }
4176
4177 return ret;
4178 }
4179
4180 static void
4181 srom_repair(struct net_device *dev, int card)
4182 {
4183 struct de4x5_private *lp = netdev_priv(dev);
4184
4185 switch(card) {
4186 case SMC:
4187 memset((char *)&lp->srom, 0, sizeof(struct de4x5_srom));
4188 memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4189 memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4190 lp->useSROM = true;
4191 break;
4192 }
4193
4194 return;
4195 }
4196
4197 /*
4198 ** Assume that the irq's do not follow the PCI spec - this is seems
4199 ** to be true so far (2 for 2).
4200 */
4201 static int
4202 test_bad_enet(struct net_device *dev, int status)
4203 {
4204 struct de4x5_private *lp = netdev_priv(dev);
4205 int i, tmp;
4206
4207 for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4208 if ((tmp == 0) || (tmp == 0x5fa)) {
4209 if ((lp->chipset == last.chipset) &&
4210 (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4211 for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
4212 for (i=ETH_ALEN-1; i>2; --i) {
4213 dev->dev_addr[i] += 1;
4214 if (dev->dev_addr[i] != 0) break;
4215 }
4216 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4217 if (!an_exception(lp)) {
4218 dev->irq = last.irq;
4219 }
4220
4221 status = 0;
4222 }
4223 } else if (!status) {
4224 last.chipset = lp->chipset;
4225 last.bus = lp->bus_num;
4226 last.irq = dev->irq;
4227 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4228 }
4229
4230 return status;
4231 }
4232
4233 /*
4234 ** List of board exceptions with correctly wired IRQs
4235 */
4236 static int
4237 an_exception(struct de4x5_private *lp)
4238 {
4239 if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
4240 (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4241 return -1;
4242 }
4243
4244 return 0;
4245 }
4246
4247 /*
4248 ** SROM Read
4249 */
4250 static short
4251 srom_rd(u_long addr, u_char offset)
4252 {
4253 sendto_srom(SROM_RD | SROM_SR, addr);
4254
4255 srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
4256 srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
4257 srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
4258
4259 return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
4260 }
4261
4262 static void
4263 srom_latch(u_int command, u_long addr)
4264 {
4265 sendto_srom(command, addr);
4266 sendto_srom(command | DT_CLK, addr);
4267 sendto_srom(command, addr);
4268
4269 return;
4270 }
4271
4272 static void
4273 srom_command(u_int command, u_long addr)
4274 {
4275 srom_latch(command, addr);
4276 srom_latch(command, addr);
4277 srom_latch((command & 0x0000ff00) | DT_CS, addr);
4278
4279 return;
4280 }
4281
4282 static void
4283 srom_address(u_int command, u_long addr, u_char offset)
4284 {
4285 int i, a;
4286
4287 a = offset << 2;
4288 for (i=0; i<6; i++, a <<= 1) {
4289 srom_latch(command | ((a & 0x80) ? DT_IN : 0), addr);
4290 }
4291 udelay(1);
4292
4293 i = (getfrom_srom(addr) >> 3) & 0x01;
4294
4295 return;
4296 }
4297
4298 static short
4299 srom_data(u_int command, u_long addr)
4300 {
4301 int i;
4302 short word = 0;
4303 s32 tmp;
4304
4305 for (i=0; i<16; i++) {
4306 sendto_srom(command | DT_CLK, addr);
4307 tmp = getfrom_srom(addr);
4308 sendto_srom(command, addr);
4309
4310 word = (word << 1) | ((tmp >> 3) & 0x01);
4311 }
4312
4313 sendto_srom(command & 0x0000ff00, addr);
4314
4315 return word;
4316 }
4317
4318 /*
4319 static void
4320 srom_busy(u_int command, u_long addr)
4321 {
4322 sendto_srom((command & 0x0000ff00) | DT_CS, addr);
4323
4324 while (!((getfrom_srom(addr) >> 3) & 0x01)) {
4325 mdelay(1);
4326 }
4327
4328 sendto_srom(command & 0x0000ff00, addr);
4329
4330 return;
4331 }
4332 */
4333
4334 static void
4335 sendto_srom(u_int command, u_long addr)
4336 {
4337 outl(command, addr);
4338 udelay(1);
4339
4340 return;
4341 }
4342
4343 static int
4344 getfrom_srom(u_long addr)
4345 {
4346 s32 tmp;
4347
4348 tmp = inl(addr);
4349 udelay(1);
4350
4351 return tmp;
4352 }
4353
4354 static int
4355 srom_infoleaf_info(struct net_device *dev)
4356 {
4357 struct de4x5_private *lp = netdev_priv(dev);
4358 int i, count;
4359 u_char *p;
4360
4361 /* Find the infoleaf decoder function that matches this chipset */
4362 for (i=0; i<INFOLEAF_SIZE; i++) {
4363 if (lp->chipset == infoleaf_array[i].chipset) break;
4364 }
4365 if (i == INFOLEAF_SIZE) {
4366 lp->useSROM = false;
4367 printk("%s: Cannot find correct chipset for SROM decoding!\n",
4368 dev->name);
4369 return -ENXIO;
4370 }
4371
4372 lp->infoleaf_fn = infoleaf_array[i].fn;
4373
4374 /* Find the information offset that this function should use */
4375 count = *((u_char *)&lp->srom + 19);
4376 p = (u_char *)&lp->srom + 26;
4377
4378 if (count > 1) {
4379 for (i=count; i; --i, p+=3) {
4380 if (lp->device == *p) break;
4381 }
4382 if (i == 0) {
4383 lp->useSROM = false;
4384 printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
4385 dev->name, lp->device);
4386 return -ENXIO;
4387 }
4388 }
4389
4390 lp->infoleaf_offset = get_unaligned_le16(p + 1);
4391
4392 return 0;
4393 }
4394
4395 /*
4396 ** This routine loads any type 1 or 3 MII info into the mii device
4397 ** struct and executes any type 5 code to reset PHY devices for this
4398 ** controller.
4399 ** The info for the MII devices will be valid since the index used
4400 ** will follow the discovery process from MII address 1-31 then 0.
4401 */
4402 static void
4403 srom_init(struct net_device *dev)
4404 {
4405 struct de4x5_private *lp = netdev_priv(dev);
4406 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4407 u_char count;
4408
4409 p+=2;
4410 if (lp->chipset == DC21140) {
4411 lp->cache.gepc = (*p++ | GEP_CTRL);
4412 gep_wr(lp->cache.gepc, dev);
4413 }
4414
4415 /* Block count */
4416 count = *p++;
4417
4418 /* Jump the infoblocks to find types */
4419 for (;count; --count) {
4420 if (*p < 128) {
4421 p += COMPACT_LEN;
4422 } else if (*(p+1) == 5) {
4423 type5_infoblock(dev, 1, p);
4424 p += ((*p & BLOCK_LEN) + 1);
4425 } else if (*(p+1) == 4) {
4426 p += ((*p & BLOCK_LEN) + 1);
4427 } else if (*(p+1) == 3) {
4428 type3_infoblock(dev, 1, p);
4429 p += ((*p & BLOCK_LEN) + 1);
4430 } else if (*(p+1) == 2) {
4431 p += ((*p & BLOCK_LEN) + 1);
4432 } else if (*(p+1) == 1) {
4433 type1_infoblock(dev, 1, p);
4434 p += ((*p & BLOCK_LEN) + 1);
4435 } else {
4436 p += ((*p & BLOCK_LEN) + 1);
4437 }
4438 }
4439
4440 return;
4441 }
4442
4443 /*
4444 ** A generic routine that writes GEP control, data and reset information
4445 ** to the GEP register (21140) or csr15 GEP portion (2114[23]).
4446 */
4447 static void
4448 srom_exec(struct net_device *dev, u_char *p)
4449 {
4450 struct de4x5_private *lp = netdev_priv(dev);
4451 u_long iobase = dev->base_addr;
4452 u_char count = (p ? *p++ : 0);
4453 u_short *w = (u_short *)p;
4454
4455 if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4456
4457 if (lp->chipset != DC21140) RESET_SIA;
4458
4459 while (count--) {
4460 gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
4461 *p++ : get_unaligned_le16(w++)), dev);
4462 mdelay(2); /* 2ms per action */
4463 }
4464
4465 if (lp->chipset != DC21140) {
4466 outl(lp->cache.csr14, DE4X5_STRR);
4467 outl(lp->cache.csr13, DE4X5_SICR);
4468 }
4469
4470 return;
4471 }
4472
4473 /*
4474 ** Basically this function is a NOP since it will never be called,
4475 ** unless I implement the DC21041 SROM functions. There's no need
4476 ** since the existing code will be satisfactory for all boards.
4477 */
4478 static int
4479 dc21041_infoleaf(struct net_device *dev)
4480 {
4481 return DE4X5_AUTOSENSE_MS;
4482 }
4483
4484 static int
4485 dc21140_infoleaf(struct net_device *dev)
4486 {
4487 struct de4x5_private *lp = netdev_priv(dev);
4488 u_char count = 0;
4489 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4490 int next_tick = DE4X5_AUTOSENSE_MS;
4491
4492 /* Read the connection type */
4493 p+=2;
4494
4495 /* GEP control */
4496 lp->cache.gepc = (*p++ | GEP_CTRL);
4497
4498 /* Block count */
4499 count = *p++;
4500
4501 /* Recursively figure out the info blocks */
4502 if (*p < 128) {
4503 next_tick = dc_infoblock[COMPACT](dev, count, p);
4504 } else {
4505 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4506 }
4507
4508 if (lp->tcount == count) {
4509 lp->media = NC;
4510 if (lp->media != lp->c_media) {
4511 de4x5_dbg_media(dev);
4512 lp->c_media = lp->media;
4513 }
4514 lp->media = INIT;
4515 lp->tcount = 0;
4516 lp->tx_enable = false;
4517 }
4518
4519 return next_tick & ~TIMER_CB;
4520 }
4521
4522 static int
4523 dc21142_infoleaf(struct net_device *dev)
4524 {
4525 struct de4x5_private *lp = netdev_priv(dev);
4526 u_char count = 0;
4527 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4528 int next_tick = DE4X5_AUTOSENSE_MS;
4529
4530 /* Read the connection type */
4531 p+=2;
4532
4533 /* Block count */
4534 count = *p++;
4535
4536 /* Recursively figure out the info blocks */
4537 if (*p < 128) {
4538 next_tick = dc_infoblock[COMPACT](dev, count, p);
4539 } else {
4540 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4541 }
4542
4543 if (lp->tcount == count) {
4544 lp->media = NC;
4545 if (lp->media != lp->c_media) {
4546 de4x5_dbg_media(dev);
4547 lp->c_media = lp->media;
4548 }
4549 lp->media = INIT;
4550 lp->tcount = 0;
4551 lp->tx_enable = false;
4552 }
4553
4554 return next_tick & ~TIMER_CB;
4555 }
4556
4557 static int
4558 dc21143_infoleaf(struct net_device *dev)
4559 {
4560 struct de4x5_private *lp = netdev_priv(dev);
4561 u_char count = 0;
4562 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4563 int next_tick = DE4X5_AUTOSENSE_MS;
4564
4565 /* Read the connection type */
4566 p+=2;
4567
4568 /* Block count */
4569 count = *p++;
4570
4571 /* Recursively figure out the info blocks */
4572 if (*p < 128) {
4573 next_tick = dc_infoblock[COMPACT](dev, count, p);
4574 } else {
4575 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4576 }
4577 if (lp->tcount == count) {
4578 lp->media = NC;
4579 if (lp->media != lp->c_media) {
4580 de4x5_dbg_media(dev);
4581 lp->c_media = lp->media;
4582 }
4583 lp->media = INIT;
4584 lp->tcount = 0;
4585 lp->tx_enable = false;
4586 }
4587
4588 return next_tick & ~TIMER_CB;
4589 }
4590
4591 /*
4592 ** The compact infoblock is only designed for DC21140[A] chips, so
4593 ** we'll reuse the dc21140m_autoconf function. Non MII media only.
4594 */
4595 static int
4596 compact_infoblock(struct net_device *dev, u_char count, u_char *p)
4597 {
4598 struct de4x5_private *lp = netdev_priv(dev);
4599 u_char flags, csr6;
4600
4601 /* Recursively figure out the info blocks */
4602 if (--count > lp->tcount) {
4603 if (*(p+COMPACT_LEN) < 128) {
4604 return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
4605 } else {
4606 return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
4607 }
4608 }
4609
4610 if ((lp->media == INIT) && (lp->timeout < 0)) {
4611 lp->ibn = COMPACT;
4612 lp->active = 0;
4613 gep_wr(lp->cache.gepc, dev);
4614 lp->infoblock_media = (*p++) & COMPACT_MC;
4615 lp->cache.gep = *p++;
4616 csr6 = *p++;
4617 flags = *p++;
4618
4619 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4620 lp->defMedium = (flags & 0x40) ? -1 : 0;
4621 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4622 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4623 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4624 lp->useMII = false;
4625
4626 de4x5_switch_mac_port(dev);
4627 }
4628
4629 return dc21140m_autoconf(dev);
4630 }
4631
4632 /*
4633 ** This block describes non MII media for the DC21140[A] only.
4634 */
4635 static int
4636 type0_infoblock(struct net_device *dev, u_char count, u_char *p)
4637 {
4638 struct de4x5_private *lp = netdev_priv(dev);
4639 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4640
4641 /* Recursively figure out the info blocks */
4642 if (--count > lp->tcount) {
4643 if (*(p+len) < 128) {
4644 return dc_infoblock[COMPACT](dev, count, p+len);
4645 } else {
4646 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4647 }
4648 }
4649
4650 if ((lp->media == INIT) && (lp->timeout < 0)) {
4651 lp->ibn = 0;
4652 lp->active = 0;
4653 gep_wr(lp->cache.gepc, dev);
4654 p+=2;
4655 lp->infoblock_media = (*p++) & BLOCK0_MC;
4656 lp->cache.gep = *p++;
4657 csr6 = *p++;
4658 flags = *p++;
4659
4660 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4661 lp->defMedium = (flags & 0x40) ? -1 : 0;
4662 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4663 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4664 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4665 lp->useMII = false;
4666
4667 de4x5_switch_mac_port(dev);
4668 }
4669
4670 return dc21140m_autoconf(dev);
4671 }
4672
4673 /* These functions are under construction! */
4674
4675 static int
4676 type1_infoblock(struct net_device *dev, u_char count, u_char *p)
4677 {
4678 struct de4x5_private *lp = netdev_priv(dev);
4679 u_char len = (*p & BLOCK_LEN)+1;
4680
4681 /* Recursively figure out the info blocks */
4682 if (--count > lp->tcount) {
4683 if (*(p+len) < 128) {
4684 return dc_infoblock[COMPACT](dev, count, p+len);
4685 } else {
4686 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4687 }
4688 }
4689
4690 p += 2;
4691 if (lp->state == INITIALISED) {
4692 lp->ibn = 1;
4693 lp->active = *p++;
4694 lp->phy[lp->active].gep = (*p ? p : NULL); p += (*p + 1);
4695 lp->phy[lp->active].rst = (*p ? p : NULL); p += (*p + 1);
4696 lp->phy[lp->active].mc = get_unaligned_le16(p); p += 2;
4697 lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2;
4698 lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2;
4699 lp->phy[lp->active].ttm = get_unaligned_le16(p);
4700 return 0;
4701 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4702 lp->ibn = 1;
4703 lp->active = *p;
4704 lp->infoblock_csr6 = OMR_MII_100;
4705 lp->useMII = true;
4706 lp->infoblock_media = ANS;
4707
4708 de4x5_switch_mac_port(dev);
4709 }
4710
4711 return dc21140m_autoconf(dev);
4712 }
4713
4714 static int
4715 type2_infoblock(struct net_device *dev, u_char count, u_char *p)
4716 {
4717 struct de4x5_private *lp = netdev_priv(dev);
4718 u_char len = (*p & BLOCK_LEN)+1;
4719
4720 /* Recursively figure out the info blocks */
4721 if (--count > lp->tcount) {
4722 if (*(p+len) < 128) {
4723 return dc_infoblock[COMPACT](dev, count, p+len);
4724 } else {
4725 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4726 }
4727 }
4728
4729 if ((lp->media == INIT) && (lp->timeout < 0)) {
4730 lp->ibn = 2;
4731 lp->active = 0;
4732 p += 2;
4733 lp->infoblock_media = (*p) & MEDIA_CODE;
4734
4735 if ((*p++) & EXT_FIELD) {
4736 lp->cache.csr13 = get_unaligned_le16(p); p += 2;
4737 lp->cache.csr14 = get_unaligned_le16(p); p += 2;
4738 lp->cache.csr15 = get_unaligned_le16(p); p += 2;
4739 } else {
4740 lp->cache.csr13 = CSR13;
4741 lp->cache.csr14 = CSR14;
4742 lp->cache.csr15 = CSR15;
4743 }
4744 lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4745 lp->cache.gep = ((s32)(get_unaligned_le16(p)) << 16);
4746 lp->infoblock_csr6 = OMR_SIA;
4747 lp->useMII = false;
4748
4749 de4x5_switch_mac_port(dev);
4750 }
4751
4752 return dc2114x_autoconf(dev);
4753 }
4754
4755 static int
4756 type3_infoblock(struct net_device *dev, u_char count, u_char *p)
4757 {
4758 struct de4x5_private *lp = netdev_priv(dev);
4759 u_char len = (*p & BLOCK_LEN)+1;
4760
4761 /* Recursively figure out the info blocks */
4762 if (--count > lp->tcount) {
4763 if (*(p+len) < 128) {
4764 return dc_infoblock[COMPACT](dev, count, p+len);
4765 } else {
4766 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4767 }
4768 }
4769
4770 p += 2;
4771 if (lp->state == INITIALISED) {
4772 lp->ibn = 3;
4773 lp->active = *p++;
4774 if (MOTO_SROM_BUG) lp->active = 0;
4775 lp->phy[lp->active].gep = (*p ? p : NULL); p += (2 * (*p) + 1);
4776 lp->phy[lp->active].rst = (*p ? p : NULL); p += (2 * (*p) + 1);
4777 lp->phy[lp->active].mc = get_unaligned_le16(p); p += 2;
4778 lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2;
4779 lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2;
4780 lp->phy[lp->active].ttm = get_unaligned_le16(p); p += 2;
4781 lp->phy[lp->active].mci = *p;
4782 return 0;
4783 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4784 lp->ibn = 3;
4785 lp->active = *p;
4786 if (MOTO_SROM_BUG) lp->active = 0;
4787 lp->infoblock_csr6 = OMR_MII_100;
4788 lp->useMII = true;
4789 lp->infoblock_media = ANS;
4790
4791 de4x5_switch_mac_port(dev);
4792 }
4793
4794 return dc2114x_autoconf(dev);
4795 }
4796
4797 static int
4798 type4_infoblock(struct net_device *dev, u_char count, u_char *p)
4799 {
4800 struct de4x5_private *lp = netdev_priv(dev);
4801 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4802
4803 /* Recursively figure out the info blocks */
4804 if (--count > lp->tcount) {
4805 if (*(p+len) < 128) {
4806 return dc_infoblock[COMPACT](dev, count, p+len);
4807 } else {
4808 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4809 }
4810 }
4811
4812 if ((lp->media == INIT) && (lp->timeout < 0)) {
4813 lp->ibn = 4;
4814 lp->active = 0;
4815 p+=2;
4816 lp->infoblock_media = (*p++) & MEDIA_CODE;
4817 lp->cache.csr13 = CSR13; /* Hard coded defaults */
4818 lp->cache.csr14 = CSR14;
4819 lp->cache.csr15 = CSR15;
4820 lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4821 lp->cache.gep = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4822 csr6 = *p++;
4823 flags = *p++;
4824
4825 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4826 lp->defMedium = (flags & 0x40) ? -1 : 0;
4827 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4828 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4829 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4830 lp->useMII = false;
4831
4832 de4x5_switch_mac_port(dev);
4833 }
4834
4835 return dc2114x_autoconf(dev);
4836 }
4837
4838 /*
4839 ** This block type provides information for resetting external devices
4840 ** (chips) through the General Purpose Register.
4841 */
4842 static int
4843 type5_infoblock(struct net_device *dev, u_char count, u_char *p)
4844 {
4845 struct de4x5_private *lp = netdev_priv(dev);
4846 u_char len = (*p & BLOCK_LEN)+1;
4847
4848 /* Recursively figure out the info blocks */
4849 if (--count > lp->tcount) {
4850 if (*(p+len) < 128) {
4851 return dc_infoblock[COMPACT](dev, count, p+len);
4852 } else {
4853 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4854 }
4855 }
4856
4857 /* Must be initializing to run this code */
4858 if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4859 p+=2;
4860 lp->rst = p;
4861 srom_exec(dev, lp->rst);
4862 }
4863
4864 return DE4X5_AUTOSENSE_MS;
4865 }
4866
4867 /*
4868 ** MII Read/Write
4869 */
4870
4871 static int
4872 mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)
4873 {
4874 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4875 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4876 mii_wdata(MII_STRD, 4, ioaddr); /* SFD and Read operation */
4877 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4878 mii_address(phyreg, ioaddr); /* PHY Register to read */
4879 mii_ta(MII_STRD, ioaddr); /* Turn around time - 2 MDC */
4880
4881 return mii_rdata(ioaddr); /* Read data */
4882 }
4883
4884 static void
4885 mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)
4886 {
4887 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4888 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4889 mii_wdata(MII_STWR, 4, ioaddr); /* SFD and Write operation */
4890 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4891 mii_address(phyreg, ioaddr); /* PHY Register to write */
4892 mii_ta(MII_STWR, ioaddr); /* Turn around time - 2 MDC */
4893 data = mii_swap(data, 16); /* Swap data bit ordering */
4894 mii_wdata(data, 16, ioaddr); /* Write data */
4895
4896 return;
4897 }
4898
4899 static int
4900 mii_rdata(u_long ioaddr)
4901 {
4902 int i;
4903 s32 tmp = 0;
4904
4905 for (i=0; i<16; i++) {
4906 tmp <<= 1;
4907 tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4908 }
4909
4910 return tmp;
4911 }
4912
4913 static void
4914 mii_wdata(int data, int len, u_long ioaddr)
4915 {
4916 int i;
4917
4918 for (i=0; i<len; i++) {
4919 sendto_mii(MII_MWR | MII_WR, data, ioaddr);
4920 data >>= 1;
4921 }
4922
4923 return;
4924 }
4925
4926 static void
4927 mii_address(u_char addr, u_long ioaddr)
4928 {
4929 int i;
4930
4931 addr = mii_swap(addr, 5);
4932 for (i=0; i<5; i++) {
4933 sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
4934 addr >>= 1;
4935 }
4936
4937 return;
4938 }
4939
4940 static void
4941 mii_ta(u_long rw, u_long ioaddr)
4942 {
4943 if (rw == MII_STWR) {
4944 sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
4945 sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
4946 } else {
4947 getfrom_mii(MII_MRD | MII_RD, ioaddr); /* Tri-state MDIO */
4948 }
4949
4950 return;
4951 }
4952
4953 static int
4954 mii_swap(int data, int len)
4955 {
4956 int i, tmp = 0;
4957
4958 for (i=0; i<len; i++) {
4959 tmp <<= 1;
4960 tmp |= (data & 1);
4961 data >>= 1;
4962 }
4963
4964 return tmp;
4965 }
4966
4967 static void
4968 sendto_mii(u32 command, int data, u_long ioaddr)
4969 {
4970 u32 j;
4971
4972 j = (data & 1) << 17;
4973 outl(command | j, ioaddr);
4974 udelay(1);
4975 outl(command | MII_MDC | j, ioaddr);
4976 udelay(1);
4977
4978 return;
4979 }
4980
4981 static int
4982 getfrom_mii(u32 command, u_long ioaddr)
4983 {
4984 outl(command, ioaddr);
4985 udelay(1);
4986 outl(command | MII_MDC, ioaddr);
4987 udelay(1);
4988
4989 return ((inl(ioaddr) >> 19) & 1);
4990 }
4991
4992 /*
4993 ** Here's 3 ways to calculate the OUI from the ID registers.
4994 */
4995 static int
4996 mii_get_oui(u_char phyaddr, u_long ioaddr)
4997 {
4998 /*
4999 union {
5000 u_short reg;
5001 u_char breg[2];
5002 } a;
5003 int i, r2, r3, ret=0;*/
5004 int r2, r3;
5005
5006 /* Read r2 and r3 */
5007 r2 = mii_rd(MII_ID0, phyaddr, ioaddr);
5008 r3 = mii_rd(MII_ID1, phyaddr, ioaddr);
5009 /* SEEQ and Cypress way * /
5010 / * Shuffle r2 and r3 * /
5011 a.reg=0;
5012 r3 = ((r3>>10)|(r2<<6))&0x0ff;
5013 r2 = ((r2>>2)&0x3fff);
5014
5015 / * Bit reverse r3 * /
5016 for (i=0;i<8;i++) {
5017 ret<<=1;
5018 ret |= (r3&1);
5019 r3>>=1;
5020 }
5021
5022 / * Bit reverse r2 * /
5023 for (i=0;i<16;i++) {
5024 a.reg<<=1;
5025 a.reg |= (r2&1);
5026 r2>>=1;
5027 }
5028
5029 / * Swap r2 bytes * /
5030 i=a.breg[0];
5031 a.breg[0]=a.breg[1];
5032 a.breg[1]=i;
5033
5034 return ((a.reg<<8)|ret); */ /* SEEQ and Cypress way */
5035 /* return ((r2<<6)|(u_int)(r3>>10)); */ /* NATIONAL and BROADCOM way */
5036 return r2; /* (I did it) My way */
5037 }
5038
5039 /*
5040 ** The SROM spec forces us to search addresses [1-31 0]. Bummer.
5041 */
5042 static int
5043 mii_get_phy(struct net_device *dev)
5044 {
5045 struct de4x5_private *lp = netdev_priv(dev);
5046 u_long iobase = dev->base_addr;
5047 int i, j, k, n, limit=ARRAY_SIZE(phy_info);
5048 int id;
5049
5050 lp->active = 0;
5051 lp->useMII = true;
5052
5053 /* Search the MII address space for possible PHY devices */
5054 for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(i+1)%DE4X5_MAX_MII) {
5055 lp->phy[lp->active].addr = i;
5056 if (i==0) n++; /* Count cycles */
5057 while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */
5058 id = mii_get_oui(i, DE4X5_MII);
5059 if ((id == 0) || (id == 65535)) continue; /* Valid ID? */
5060 for (j=0; j<limit; j++) { /* Search PHY table */
5061 if (id != phy_info[j].id) continue; /* ID match? */
5062 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5063 if (k < DE4X5_MAX_PHY) {
5064 memcpy((char *)&lp->phy[k],
5065 (char *)&phy_info[j], sizeof(struct phy_table));
5066 lp->phy[k].addr = i;
5067 lp->mii_cnt++;
5068 lp->active++;
5069 } else {
5070 goto purgatory; /* Stop the search */
5071 }
5072 break;
5073 }
5074 if ((j == limit) && (i < DE4X5_MAX_MII)) {
5075 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5076 lp->phy[k].addr = i;
5077 lp->phy[k].id = id;
5078 lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */
5079 lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */
5080 lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */
5081 lp->mii_cnt++;
5082 lp->active++;
5083 printk("%s: Using generic MII device control. If the board doesn't operate, \nplease mail the following dump to the author:\n", dev->name);
5084 j = de4x5_debug;
5085 de4x5_debug |= DEBUG_MII;
5086 de4x5_dbg_mii(dev, k);
5087 de4x5_debug = j;
5088 printk("\n");
5089 }
5090 }
5091 purgatory:
5092 lp->active = 0;
5093 if (lp->phy[0].id) { /* Reset the PHY devices */
5094 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++) { /*For each PHY*/
5095 mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5096 while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
5097
5098 de4x5_dbg_mii(dev, k);
5099 }
5100 }
5101 if (!lp->mii_cnt) lp->useMII = false;
5102
5103 return lp->mii_cnt;
5104 }
5105
5106 static char *
5107 build_setup_frame(struct net_device *dev, int mode)
5108 {
5109 struct de4x5_private *lp = netdev_priv(dev);
5110 int i;
5111 char *pa = lp->setup_frame;
5112
5113 /* Initialise the setup frame */
5114 if (mode == ALL) {
5115 memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5116 }
5117
5118 if (lp->setup_f == HASH_PERF) {
5119 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5120 *(pa + i) = dev->dev_addr[i]; /* Host address */
5121 if (i & 0x01) pa += 2;
5122 }
5123 *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
5124 } else {
5125 for (i=0; i<ETH_ALEN; i++) { /* Host address */
5126 *(pa + (i&1)) = dev->dev_addr[i];
5127 if (i & 0x01) pa += 4;
5128 }
5129 for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */
5130 *(pa + (i&1)) = (char) 0xff;
5131 if (i & 0x01) pa += 4;
5132 }
5133 }
5134
5135 return pa; /* Points to the next entry */
5136 }
5137
5138 static void
5139 disable_ast(struct net_device *dev)
5140 {
5141 struct de4x5_private *lp = netdev_priv(dev);
5142 del_timer_sync(&lp->timer);
5143 }
5144
5145 static long
5146 de4x5_switch_mac_port(struct net_device *dev)
5147 {
5148 struct de4x5_private *lp = netdev_priv(dev);
5149 u_long iobase = dev->base_addr;
5150 s32 omr;
5151
5152 STOP_DE4X5;
5153
5154 /* Assert the OMR_PS bit in CSR6 */
5155 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
5156 OMR_FDX));
5157 omr |= lp->infoblock_csr6;
5158 if (omr & OMR_PS) omr |= OMR_HBD;
5159 outl(omr, DE4X5_OMR);
5160
5161 /* Soft Reset */
5162 RESET_DE4X5;
5163
5164 /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */
5165 if (lp->chipset == DC21140) {
5166 gep_wr(lp->cache.gepc, dev);
5167 gep_wr(lp->cache.gep, dev);
5168 } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5169 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5170 }
5171
5172 /* Restore CSR6 */
5173 outl(omr, DE4X5_OMR);
5174
5175 /* Reset CSR8 */
5176 inl(DE4X5_MFC);
5177
5178 return omr;
5179 }
5180
5181 static void
5182 gep_wr(s32 data, struct net_device *dev)
5183 {
5184 struct de4x5_private *lp = netdev_priv(dev);
5185 u_long iobase = dev->base_addr;
5186
5187 if (lp->chipset == DC21140) {
5188 outl(data, DE4X5_GEP);
5189 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5190 outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5191 }
5192
5193 return;
5194 }
5195
5196 static int
5197 gep_rd(struct net_device *dev)
5198 {
5199 struct de4x5_private *lp = netdev_priv(dev);
5200 u_long iobase = dev->base_addr;
5201
5202 if (lp->chipset == DC21140) {
5203 return inl(DE4X5_GEP);
5204 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5205 return (inl(DE4X5_SIGR) & 0x000fffff);
5206 }
5207
5208 return 0;
5209 }
5210
5211 static void
5212 yawn(struct net_device *dev, int state)
5213 {
5214 struct de4x5_private *lp = netdev_priv(dev);
5215 u_long iobase = dev->base_addr;
5216
5217 if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5218
5219 if(lp->bus == EISA) {
5220 switch(state) {
5221 case WAKEUP:
5222 outb(WAKEUP, PCI_CFPM);
5223 mdelay(10);
5224 break;
5225
5226 case SNOOZE:
5227 outb(SNOOZE, PCI_CFPM);
5228 break;
5229
5230 case SLEEP:
5231 outl(0, DE4X5_SICR);
5232 outb(SLEEP, PCI_CFPM);
5233 break;
5234 }
5235 } else {
5236 struct pci_dev *pdev = to_pci_dev (lp->gendev);
5237 switch(state) {
5238 case WAKEUP:
5239 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
5240 mdelay(10);
5241 break;
5242
5243 case SNOOZE:
5244 pci_write_config_byte(pdev, PCI_CFDA_PSM, SNOOZE);
5245 break;
5246
5247 case SLEEP:
5248 outl(0, DE4X5_SICR);
5249 pci_write_config_byte(pdev, PCI_CFDA_PSM, SLEEP);
5250 break;
5251 }
5252 }
5253
5254 return;
5255 }
5256
5257 static void
5258 de4x5_parse_params(struct net_device *dev)
5259 {
5260 struct de4x5_private *lp = netdev_priv(dev);
5261 char *p, *q, t;
5262
5263 lp->params.fdx = 0;
5264 lp->params.autosense = AUTO;
5265
5266 if (args == NULL) return;
5267
5268 if ((p = strstr(args, dev->name))) {
5269 if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p);
5270 t = *q;
5271 *q = '\0';
5272
5273 if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = 1;
5274
5275 if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) {
5276 if (strstr(p, "TP")) {
5277 lp->params.autosense = TP;
5278 } else if (strstr(p, "TP_NW")) {
5279 lp->params.autosense = TP_NW;
5280 } else if (strstr(p, "BNC")) {
5281 lp->params.autosense = BNC;
5282 } else if (strstr(p, "AUI")) {
5283 lp->params.autosense = AUI;
5284 } else if (strstr(p, "BNC_AUI")) {
5285 lp->params.autosense = BNC;
5286 } else if (strstr(p, "10Mb")) {
5287 lp->params.autosense = _10Mb;
5288 } else if (strstr(p, "100Mb")) {
5289 lp->params.autosense = _100Mb;
5290 } else if (strstr(p, "AUTO")) {
5291 lp->params.autosense = AUTO;
5292 }
5293 }
5294 *q = t;
5295 }
5296
5297 return;
5298 }
5299
5300 static void
5301 de4x5_dbg_open(struct net_device *dev)
5302 {
5303 struct de4x5_private *lp = netdev_priv(dev);
5304 int i;
5305
5306 if (de4x5_debug & DEBUG_OPEN) {
5307 printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
5308 printk("\tphysical address: ");
5309 for (i=0;i<6;i++) {
5310 printk("%2.2x:",(short)dev->dev_addr[i]);
5311 }
5312 printk("\n");
5313 printk("Descriptor head addresses:\n");
5314 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5315 printk("Descriptor addresses:\nRX: ");
5316 for (i=0;i<lp->rxRingSize-1;i++){
5317 if (i < 3) {
5318 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status);
5319 }
5320 }
5321 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5322 printk("TX: ");
5323 for (i=0;i<lp->txRingSize-1;i++){
5324 if (i < 3) {
5325 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status);
5326 }
5327 }
5328 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5329 printk("Descriptor buffers:\nRX: ");
5330 for (i=0;i<lp->rxRingSize-1;i++){
5331 if (i < 3) {
5332 printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf));
5333 }
5334 }
5335 printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5336 printk("TX: ");
5337 for (i=0;i<lp->txRingSize-1;i++){
5338 if (i < 3) {
5339 printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf));
5340 }
5341 }
5342 printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
5343 printk("Ring size: \nRX: %d\nTX: %d\n",
5344 (short)lp->rxRingSize,
5345 (short)lp->txRingSize);
5346 }
5347
5348 return;
5349 }
5350
5351 static void
5352 de4x5_dbg_mii(struct net_device *dev, int k)
5353 {
5354 struct de4x5_private *lp = netdev_priv(dev);
5355 u_long iobase = dev->base_addr;
5356
5357 if (de4x5_debug & DEBUG_MII) {
5358 printk("\nMII device address: %d\n", lp->phy[k].addr);
5359 printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5360 printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5361 printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5362 printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5363 if (lp->phy[k].id != BROADCOM_T4) {
5364 printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5365 printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5366 }
5367 printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5368 if (lp->phy[k].id != BROADCOM_T4) {
5369 printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5370 printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5371 } else {
5372 printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5373 }
5374 }
5375
5376 return;
5377 }
5378
5379 static void
5380 de4x5_dbg_media(struct net_device *dev)
5381 {
5382 struct de4x5_private *lp = netdev_priv(dev);
5383
5384 if (lp->media != lp->c_media) {
5385 if (de4x5_debug & DEBUG_MEDIA) {
5386 printk("%s: media is %s%s\n", dev->name,
5387 (lp->media == NC ? "unconnected, link down or incompatible connection" :
5388 (lp->media == TP ? "TP" :
5389 (lp->media == ANS ? "TP/Nway" :
5390 (lp->media == BNC ? "BNC" :
5391 (lp->media == AUI ? "AUI" :
5392 (lp->media == BNC_AUI ? "BNC/AUI" :
5393 (lp->media == EXT_SIA ? "EXT SIA" :
5394 (lp->media == _100Mb ? "100Mb/s" :
5395 (lp->media == _10Mb ? "10Mb/s" :
5396 "???"
5397 ))))))))), (lp->fdx?" full duplex.":"."));
5398 }
5399 lp->c_media = lp->media;
5400 }
5401
5402 return;
5403 }
5404
5405 static void
5406 de4x5_dbg_srom(struct de4x5_srom *p)
5407 {
5408 int i;
5409
5410 if (de4x5_debug & DEBUG_SROM) {
5411 printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
5412 printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id));
5413 printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc));
5414 printk("SROM version: %02x\n", (u_char)(p->version));
5415 printk("# controllers: %02x\n", (u_char)(p->num_controllers));
5416
5417 printk("Hardware Address: %pM\n", p->ieee_addr);
5418 printk("CRC checksum: %04x\n", (u_short)(p->chksum));
5419 for (i=0; i<64; i++) {
5420 printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i));
5421 }
5422 }
5423
5424 return;
5425 }
5426
5427 static void
5428 de4x5_dbg_rx(struct sk_buff *skb, int len)
5429 {
5430 int i, j;
5431
5432 if (de4x5_debug & DEBUG_RX) {
5433 printk("R: %pM <- %pM len/SAP:%02x%02x [%d]\n",
5434 skb->data, &skb->data[6],
5435 (u_char)skb->data[12],
5436 (u_char)skb->data[13],
5437 len);
5438 for (j=0; len>0;j+=16, len-=16) {
5439 printk(" %03x: ",j);
5440 for (i=0; i<16 && i<len; i++) {
5441 printk("%02x ",(u_char)skb->data[i+j]);
5442 }
5443 printk("\n");
5444 }
5445 }
5446
5447 return;
5448 }
5449
5450 /*
5451 ** Perform IOCTL call functions here. Some are privileged operations and the
5452 ** effective uid is checked in those cases. In the normal course of events
5453 ** this function is only used for my testing.
5454 */
5455 static int
5456 de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5457 {
5458 struct de4x5_private *lp = netdev_priv(dev);
5459 struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_ifru;
5460 u_long iobase = dev->base_addr;
5461 int i, j, status = 0;
5462 s32 omr;
5463 union {
5464 u8 addr[144];
5465 u16 sval[72];
5466 u32 lval[36];
5467 } tmp;
5468 u_long flags = 0;
5469
5470 switch(ioc->cmd) {
5471 case DE4X5_GET_HWADDR: /* Get the hardware address */
5472 ioc->len = ETH_ALEN;
5473 for (i=0; i<ETH_ALEN; i++) {
5474 tmp.addr[i] = dev->dev_addr[i];
5475 }
5476 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5477 break;
5478
5479 case DE4X5_SET_HWADDR: /* Set the hardware address */
5480 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5481 if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT;
5482 if (netif_queue_stopped(dev))
5483 return -EBUSY;
5484 netif_stop_queue(dev);
5485 for (i=0; i<ETH_ALEN; i++) {
5486 dev->dev_addr[i] = tmp.addr[i];
5487 }
5488 build_setup_frame(dev, PHYS_ADDR_ONLY);
5489 /* Set up the descriptor and give ownership to the card */
5490 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5491 SETUP_FRAME_LEN, (struct sk_buff *)1);
5492 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
5493 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
5494 netif_wake_queue(dev); /* Unlock the TX ring */
5495 break;
5496
5497 case DE4X5_SAY_BOO: /* Say "Boo!" to the kernel log file */
5498 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5499 printk("%s: Boo!\n", dev->name);
5500 break;
5501
5502 case DE4X5_MCA_EN: /* Enable pass all multicast addressing */
5503 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5504 omr = inl(DE4X5_OMR);
5505 omr |= OMR_PM;
5506 outl(omr, DE4X5_OMR);
5507 break;
5508
5509 case DE4X5_GET_STATS: /* Get the driver statistics */
5510 {
5511 struct pkt_stats statbuf;
5512 ioc->len = sizeof(statbuf);
5513 spin_lock_irqsave(&lp->lock, flags);
5514 memcpy(&statbuf, &lp->pktStats, ioc->len);
5515 spin_unlock_irqrestore(&lp->lock, flags);
5516 if (copy_to_user(ioc->data, &statbuf, ioc->len))
5517 return -EFAULT;
5518 break;
5519 }
5520 case DE4X5_CLR_STATS: /* Zero out the driver statistics */
5521 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5522 spin_lock_irqsave(&lp->lock, flags);
5523 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5524 spin_unlock_irqrestore(&lp->lock, flags);
5525 break;
5526
5527 case DE4X5_GET_OMR: /* Get the OMR Register contents */
5528 tmp.addr[0] = inl(DE4X5_OMR);
5529 if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT;
5530 break;
5531
5532 case DE4X5_SET_OMR: /* Set the OMR Register contents */
5533 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5534 if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT;
5535 outl(tmp.addr[0], DE4X5_OMR);
5536 break;
5537
5538 case DE4X5_GET_REG: /* Get the DE4X5 Registers */
5539 j = 0;
5540 tmp.lval[0] = inl(DE4X5_STS); j+=4;
5541 tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5542 tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5543 tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5544 tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5545 tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5546 tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5547 tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5548 ioc->len = j;
5549 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5550 break;
5551
5552 #define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */
5553 /*
5554 case DE4X5_DUMP:
5555 j = 0;
5556 tmp.addr[j++] = dev->irq;
5557 for (i=0; i<ETH_ALEN; i++) {
5558 tmp.addr[j++] = dev->dev_addr[i];
5559 }
5560 tmp.addr[j++] = lp->rxRingSize;
5561 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5562 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
5563
5564 for (i=0;i<lp->rxRingSize-1;i++){
5565 if (i < 3) {
5566 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5567 }
5568 }
5569 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5570 for (i=0;i<lp->txRingSize-1;i++){
5571 if (i < 3) {
5572 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5573 }
5574 }
5575 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5576
5577 for (i=0;i<lp->rxRingSize-1;i++){
5578 if (i < 3) {
5579 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5580 }
5581 }
5582 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5583 for (i=0;i<lp->txRingSize-1;i++){
5584 if (i < 3) {
5585 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5586 }
5587 }
5588 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5589
5590 for (i=0;i<lp->rxRingSize;i++){
5591 tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5592 }
5593 for (i=0;i<lp->txRingSize;i++){
5594 tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5595 }
5596
5597 tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
5598 tmp.lval[j>>2] = inl(DE4X5_TPD); j+=4;
5599 tmp.lval[j>>2] = inl(DE4X5_RPD); j+=4;
5600 tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4;
5601 tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4;
5602 tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
5603 tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
5604 tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
5605 tmp.lval[j>>2] = lp->chipset; j+=4;
5606 if (lp->chipset == DC21140) {
5607 tmp.lval[j>>2] = gep_rd(dev); j+=4;
5608 } else {
5609 tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
5610 tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
5611 tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
5612 tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
5613 }
5614 tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
5615 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
5616 tmp.lval[j>>2] = lp->active; j+=4;
5617 tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5618 tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5619 tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5620 tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5621 if (lp->phy[lp->active].id != BROADCOM_T4) {
5622 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5623 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5624 }
5625 tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5626 if (lp->phy[lp->active].id != BROADCOM_T4) {
5627 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5628 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5629 } else {
5630 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5631 }
5632 }
5633
5634 tmp.addr[j++] = lp->txRingSize;
5635 tmp.addr[j++] = netif_queue_stopped(dev);
5636
5637 ioc->len = j;
5638 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5639 break;
5640
5641 */
5642 default:
5643 return -EOPNOTSUPP;
5644 }
5645
5646 return status;
5647 }
5648
5649 static int __init de4x5_module_init (void)
5650 {
5651 int err = 0;
5652
5653 #ifdef CONFIG_PCI
5654 err = pci_register_driver(&de4x5_pci_driver);
5655 #endif
5656 #ifdef CONFIG_EISA
5657 err |= eisa_driver_register (&de4x5_eisa_driver);
5658 #endif
5659
5660 return err;
5661 }
5662
5663 static void __exit de4x5_module_exit (void)
5664 {
5665 #ifdef CONFIG_PCI
5666 pci_unregister_driver (&de4x5_pci_driver);
5667 #endif
5668 #ifdef CONFIG_EISA
5669 eisa_driver_unregister (&de4x5_eisa_driver);
5670 #endif
5671 }
5672
5673 module_init (de4x5_module_init);
5674 module_exit (de4x5_module_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree