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drm/radeon/kms: handle DP bridges
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / radeon / radeon_encoders.c
blob43c001b28ecc788dc3b19dba7fd202d323e54975
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
29 #include "radeon.h"
30 #include "atom.h"
31
32 extern int atom_debug;
33
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
37
38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
39 {
40 struct drm_device *dev = encoder->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
43 struct drm_encoder *clone_encoder;
44 uint32_t index_mask = 0;
45 int count;
46
47 /* DIG routing gets problematic */
48 if (rdev->family >= CHIP_R600)
49 return index_mask;
50 /* LVDS/TV are too wacky */
51 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
52 return index_mask;
53 /* DVO requires 2x ppll clocks depending on tmds chip */
54 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
55 return index_mask;
56
57 count = -1;
58 list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
59 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
60 count++;
61
62 if (clone_encoder == encoder)
63 continue;
64 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
65 continue;
66 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
67 continue;
68 else
69 index_mask |= (1 << count);
70 }
71 return index_mask;
72 }
73
74 void radeon_setup_encoder_clones(struct drm_device *dev)
75 {
76 struct drm_encoder *encoder;
77
78 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
79 encoder->possible_clones = radeon_encoder_clones(encoder);
80 }
81 }
82
83 uint32_t
84 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
85 {
86 struct radeon_device *rdev = dev->dev_private;
87 uint32_t ret = 0;
88
89 switch (supported_device) {
90 case ATOM_DEVICE_CRT1_SUPPORT:
91 case ATOM_DEVICE_TV1_SUPPORT:
92 case ATOM_DEVICE_TV2_SUPPORT:
93 case ATOM_DEVICE_CRT2_SUPPORT:
94 case ATOM_DEVICE_CV_SUPPORT:
95 switch (dac) {
96 case 1: /* dac a */
97 if ((rdev->family == CHIP_RS300) ||
98 (rdev->family == CHIP_RS400) ||
99 (rdev->family == CHIP_RS480))
100 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
101 else if (ASIC_IS_AVIVO(rdev))
102 ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
103 else
104 ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
105 break;
106 case 2: /* dac b */
107 if (ASIC_IS_AVIVO(rdev))
108 ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
109 else {
110 /*if (rdev->family == CHIP_R200)
111 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
112 else*/
113 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
114 }
115 break;
116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev))
118 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
119 else
120 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
121 break;
122 }
123 break;
124 case ATOM_DEVICE_LCD1_SUPPORT:
125 if (ASIC_IS_AVIVO(rdev))
126 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
127 else
128 ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
129 break;
130 case ATOM_DEVICE_DFP1_SUPPORT:
131 if ((rdev->family == CHIP_RS300) ||
132 (rdev->family == CHIP_RS400) ||
133 (rdev->family == CHIP_RS480))
134 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
135 else if (ASIC_IS_AVIVO(rdev))
136 ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
137 else
138 ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
139 break;
140 case ATOM_DEVICE_LCD2_SUPPORT:
141 case ATOM_DEVICE_DFP2_SUPPORT:
142 if ((rdev->family == CHIP_RS600) ||
143 (rdev->family == CHIP_RS690) ||
144 (rdev->family == CHIP_RS740))
145 ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
146 else if (ASIC_IS_AVIVO(rdev))
147 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
148 else
149 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
150 break;
151 case ATOM_DEVICE_DFP3_SUPPORT:
152 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
153 break;
154 }
155
156 return ret;
157 }
158
159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
160 {
161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162 switch (radeon_encoder->encoder_id) {
163 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
167 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
169 case ENCODER_OBJECT_ID_INTERNAL_DDI:
170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
174 return true;
175 default:
176 return false;
177 }
178 }
179
180 void
181 radeon_link_encoder_connector(struct drm_device *dev)
182 {
183 struct drm_connector *connector;
184 struct radeon_connector *radeon_connector;
185 struct drm_encoder *encoder;
186 struct radeon_encoder *radeon_encoder;
187
188 /* walk the list and link encoders to connectors */
189 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
190 radeon_connector = to_radeon_connector(connector);
191 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
192 radeon_encoder = to_radeon_encoder(encoder);
193 if (radeon_encoder->devices & radeon_connector->devices)
194 drm_mode_connector_attach_encoder(connector, encoder);
195 }
196 }
197 }
198
199 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
200 {
201 struct drm_device *dev = encoder->dev;
202 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
203 struct drm_connector *connector;
204
205 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
206 if (connector->encoder == encoder) {
207 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
208 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
209 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
210 radeon_encoder->active_device, radeon_encoder->devices,
211 radeon_connector->devices, encoder->encoder_type);
212 }
213 }
214 }
215
216 struct drm_connector *
217 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
218 {
219 struct drm_device *dev = encoder->dev;
220 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
221 struct drm_connector *connector;
222 struct radeon_connector *radeon_connector;
223
224 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
225 radeon_connector = to_radeon_connector(connector);
226 if (radeon_encoder->active_device & radeon_connector->devices)
227 return connector;
228 }
229 return NULL;
230 }
231
232 struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder)
233 {
234 struct drm_device *dev = encoder->dev;
235 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
236 struct drm_encoder *other_encoder;
237 struct radeon_encoder *other_radeon_encoder;
238
239 if (radeon_encoder->is_ext_encoder)
240 return NULL;
241
242 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
243 if (other_encoder == encoder)
244 continue;
245 other_radeon_encoder = to_radeon_encoder(other_encoder);
246 if (other_radeon_encoder->is_ext_encoder &&
247 (radeon_encoder->devices & other_radeon_encoder->devices))
248 return other_encoder;
249 }
250 return NULL;
251 }
252
253 bool radeon_encoder_is_dp_bridge(struct drm_encoder *encoder)
254 {
255 struct drm_encoder *other_encoder = radeon_atom_get_external_encoder(encoder);
256
257 if (other_encoder) {
258 struct radeon_encoder *radeon_encoder = to_radeon_encoder(other_encoder);
259
260 switch (radeon_encoder->encoder_id) {
261 case ENCODER_OBJECT_ID_TRAVIS:
262 case ENCODER_OBJECT_ID_NUTMEG:
263 return true;
264 default:
265 return false;
266 }
267 }
268
269 return false;
270 }
271
272 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
273 struct drm_display_mode *adjusted_mode)
274 {
275 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
276 struct drm_device *dev = encoder->dev;
277 struct radeon_device *rdev = dev->dev_private;
278 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
279 unsigned hblank = native_mode->htotal - native_mode->hdisplay;
280 unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
281 unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
282 unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
283 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
284 unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
285
286 adjusted_mode->clock = native_mode->clock;
287 adjusted_mode->flags = native_mode->flags;
288
289 if (ASIC_IS_AVIVO(rdev)) {
290 adjusted_mode->hdisplay = native_mode->hdisplay;
291 adjusted_mode->vdisplay = native_mode->vdisplay;
292 }
293
294 adjusted_mode->htotal = native_mode->hdisplay + hblank;
295 adjusted_mode->hsync_start = native_mode->hdisplay + hover;
296 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
297
298 adjusted_mode->vtotal = native_mode->vdisplay + vblank;
299 adjusted_mode->vsync_start = native_mode->vdisplay + vover;
300 adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
301
302 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
303
304 if (ASIC_IS_AVIVO(rdev)) {
305 adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
306 adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
307 }
308
309 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
310 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
311 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
312
313 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
314 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
315 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
316
317 }
318
319 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
320 struct drm_display_mode *mode,
321 struct drm_display_mode *adjusted_mode)
322 {
323 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
324 struct drm_device *dev = encoder->dev;
325 struct radeon_device *rdev = dev->dev_private;
326
327 /* set the active encoder to connector routing */
328 radeon_encoder_set_active_device(encoder);
329 drm_mode_set_crtcinfo(adjusted_mode, 0);
330
331 /* hw bug */
332 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
333 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
334 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
335
336 /* get the native mode for LVDS */
337 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
338 radeon_panel_mode_fixup(encoder, adjusted_mode);
339
340 /* get the native mode for TV */
341 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
342 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
343 if (tv_dac) {
344 if (tv_dac->tv_std == TV_STD_NTSC ||
345 tv_dac->tv_std == TV_STD_NTSC_J ||
346 tv_dac->tv_std == TV_STD_PAL_M)
347 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
348 else
349 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
350 }
351 }
352
353 if (ASIC_IS_DCE3(rdev) &&
354 (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
355 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
356 radeon_dp_set_link_config(connector, mode);
357 }
358
359 return true;
360 }
361
362 static void
363 atombios_dac_setup(struct drm_encoder *encoder, int action)
364 {
365 struct drm_device *dev = encoder->dev;
366 struct radeon_device *rdev = dev->dev_private;
367 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
368 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
369 int index = 0;
370 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
371
372 memset(&args, 0, sizeof(args));
373
374 switch (radeon_encoder->encoder_id) {
375 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
376 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
377 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
378 break;
379 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
380 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
381 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
382 break;
383 }
384
385 args.ucAction = action;
386
387 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
388 args.ucDacStandard = ATOM_DAC1_PS2;
389 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
390 args.ucDacStandard = ATOM_DAC1_CV;
391 else {
392 switch (dac_info->tv_std) {
393 case TV_STD_PAL:
394 case TV_STD_PAL_M:
395 case TV_STD_SCART_PAL:
396 case TV_STD_SECAM:
397 case TV_STD_PAL_CN:
398 args.ucDacStandard = ATOM_DAC1_PAL;
399 break;
400 case TV_STD_NTSC:
401 case TV_STD_NTSC_J:
402 case TV_STD_PAL_60:
403 default:
404 args.ucDacStandard = ATOM_DAC1_NTSC;
405 break;
406 }
407 }
408 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
409
410 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
411
412 }
413
414 static void
415 atombios_tv_setup(struct drm_encoder *encoder, int action)
416 {
417 struct drm_device *dev = encoder->dev;
418 struct radeon_device *rdev = dev->dev_private;
419 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
420 TV_ENCODER_CONTROL_PS_ALLOCATION args;
421 int index = 0;
422 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
423
424 memset(&args, 0, sizeof(args));
425
426 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
427
428 args.sTVEncoder.ucAction = action;
429
430 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
431 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
432 else {
433 switch (dac_info->tv_std) {
434 case TV_STD_NTSC:
435 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
436 break;
437 case TV_STD_PAL:
438 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
439 break;
440 case TV_STD_PAL_M:
441 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
442 break;
443 case TV_STD_PAL_60:
444 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
445 break;
446 case TV_STD_NTSC_J:
447 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
448 break;
449 case TV_STD_SCART_PAL:
450 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
451 break;
452 case TV_STD_SECAM:
453 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
454 break;
455 case TV_STD_PAL_CN:
456 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
457 break;
458 default:
459 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
460 break;
461 }
462 }
463
464 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
465
466 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
467
468 }
469
470 union dvo_encoder_control {
471 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
472 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
473 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
474 };
475
476 void
477 atombios_dvo_setup(struct drm_encoder *encoder, int action)
478 {
479 struct drm_device *dev = encoder->dev;
480 struct radeon_device *rdev = dev->dev_private;
481 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
482 union dvo_encoder_control args;
483 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
484
485 memset(&args, 0, sizeof(args));
486
487 if (ASIC_IS_DCE3(rdev)) {
488 /* DCE3+ */
489 args.dvo_v3.ucAction = action;
490 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
491 args.dvo_v3.ucDVOConfig = 0; /* XXX */
492 } else if (ASIC_IS_DCE2(rdev)) {
493 /* DCE2 (pre-DCE3 R6xx, RS600/690/740 */
494 args.dvo.sDVOEncoder.ucAction = action;
495 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
496 /* DFP1, CRT1, TV1 depending on the type of port */
497 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
498
499 if (radeon_encoder->pixel_clock > 165000)
500 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
501 } else {
502 /* R4xx, R5xx */
503 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
504
505 if (radeon_encoder->pixel_clock > 165000)
506 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
507
508 /*if (pScrn->rgbBits == 8)*/
509 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
510 }
511
512 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
513 }
514
515 union lvds_encoder_control {
516 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
517 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
518 };
519
520 void
521 atombios_digital_setup(struct drm_encoder *encoder, int action)
522 {
523 struct drm_device *dev = encoder->dev;
524 struct radeon_device *rdev = dev->dev_private;
525 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
526 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
527 union lvds_encoder_control args;
528 int index = 0;
529 int hdmi_detected = 0;
530 uint8_t frev, crev;
531
532 if (!dig)
533 return;
534
535 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
536 hdmi_detected = 1;
537
538 memset(&args, 0, sizeof(args));
539
540 switch (radeon_encoder->encoder_id) {
541 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
542 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
543 break;
544 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
545 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
546 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
547 break;
548 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
549 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
550 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
551 else
552 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
553 break;
554 }
555
556 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
557 return;
558
559 switch (frev) {
560 case 1:
561 case 2:
562 switch (crev) {
563 case 1:
564 args.v1.ucMisc = 0;
565 args.v1.ucAction = action;
566 if (hdmi_detected)
567 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
568 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
569 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
570 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
571 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
572 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
573 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
574 } else {
575 if (dig->linkb)
576 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
577 if (radeon_encoder->pixel_clock > 165000)
578 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
579 /*if (pScrn->rgbBits == 8) */
580 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
581 }
582 break;
583 case 2:
584 case 3:
585 args.v2.ucMisc = 0;
586 args.v2.ucAction = action;
587 if (crev == 3) {
588 if (dig->coherent_mode)
589 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
590 }
591 if (hdmi_detected)
592 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
593 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
594 args.v2.ucTruncate = 0;
595 args.v2.ucSpatial = 0;
596 args.v2.ucTemporal = 0;
597 args.v2.ucFRC = 0;
598 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
599 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
600 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
601 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
602 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
603 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
604 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
605 }
606 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
607 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
608 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
609 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
610 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
611 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
612 }
613 } else {
614 if (dig->linkb)
615 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
616 if (radeon_encoder->pixel_clock > 165000)
617 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
618 }
619 break;
620 default:
621 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
622 break;
623 }
624 break;
625 default:
626 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
627 break;
628 }
629
630 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
631 }
632
633 int
634 atombios_get_encoder_mode(struct drm_encoder *encoder)
635 {
636 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
637 struct drm_device *dev = encoder->dev;
638 struct radeon_device *rdev = dev->dev_private;
639 struct drm_connector *connector;
640 struct radeon_connector *radeon_connector;
641 struct radeon_connector_atom_dig *dig_connector;
642
643 /* dp bridges are always DP */
644 if (radeon_encoder_is_dp_bridge(encoder))
645 return ATOM_ENCODER_MODE_DP;
646
647 connector = radeon_get_connector_for_encoder(encoder);
648 if (!connector) {
649 switch (radeon_encoder->encoder_id) {
650 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
651 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
652 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
653 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
654 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
655 return ATOM_ENCODER_MODE_DVI;
656 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
657 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
658 default:
659 return ATOM_ENCODER_MODE_CRT;
660 }
661 }
662 radeon_connector = to_radeon_connector(connector);
663
664 switch (connector->connector_type) {
665 case DRM_MODE_CONNECTOR_DVII:
666 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
667 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
668 /* fix me */
669 if (ASIC_IS_DCE4(rdev))
670 return ATOM_ENCODER_MODE_DVI;
671 else
672 return ATOM_ENCODER_MODE_HDMI;
673 } else if (radeon_connector->use_digital)
674 return ATOM_ENCODER_MODE_DVI;
675 else
676 return ATOM_ENCODER_MODE_CRT;
677 break;
678 case DRM_MODE_CONNECTOR_DVID:
679 case DRM_MODE_CONNECTOR_HDMIA:
680 default:
681 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
682 /* fix me */
683 if (ASIC_IS_DCE4(rdev))
684 return ATOM_ENCODER_MODE_DVI;
685 else
686 return ATOM_ENCODER_MODE_HDMI;
687 } else
688 return ATOM_ENCODER_MODE_DVI;
689 break;
690 case DRM_MODE_CONNECTOR_LVDS:
691 return ATOM_ENCODER_MODE_LVDS;
692 break;
693 case DRM_MODE_CONNECTOR_DisplayPort:
694 dig_connector = radeon_connector->con_priv;
695 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
696 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
697 return ATOM_ENCODER_MODE_DP;
698 else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
699 /* fix me */
700 if (ASIC_IS_DCE4(rdev))
701 return ATOM_ENCODER_MODE_DVI;
702 else
703 return ATOM_ENCODER_MODE_HDMI;
704 } else
705 return ATOM_ENCODER_MODE_DVI;
706 break;
707 case DRM_MODE_CONNECTOR_eDP:
708 return ATOM_ENCODER_MODE_DP;
709 case DRM_MODE_CONNECTOR_DVIA:
710 case DRM_MODE_CONNECTOR_VGA:
711 return ATOM_ENCODER_MODE_CRT;
712 break;
713 case DRM_MODE_CONNECTOR_Composite:
714 case DRM_MODE_CONNECTOR_SVIDEO:
715 case DRM_MODE_CONNECTOR_9PinDIN:
716 /* fix me */
717 return ATOM_ENCODER_MODE_TV;
718 /*return ATOM_ENCODER_MODE_CV;*/
719 break;
720 }
721 }
722
723 /*
724 * DIG Encoder/Transmitter Setup
725 *
726 * DCE 3.0/3.1
727 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
728 * Supports up to 3 digital outputs
729 * - 2 DIG encoder blocks.
730 * DIG1 can drive UNIPHY link A or link B
731 * DIG2 can drive UNIPHY link B or LVTMA
732 *
733 * DCE 3.2
734 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
735 * Supports up to 5 digital outputs
736 * - 2 DIG encoder blocks.
737 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
738 *
739 * DCE 4.0/5.0
740 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
741 * Supports up to 6 digital outputs
742 * - 6 DIG encoder blocks.
743 * - DIG to PHY mapping is hardcoded
744 * DIG1 drives UNIPHY0 link A, A+B
745 * DIG2 drives UNIPHY0 link B
746 * DIG3 drives UNIPHY1 link A, A+B
747 * DIG4 drives UNIPHY1 link B
748 * DIG5 drives UNIPHY2 link A, A+B
749 * DIG6 drives UNIPHY2 link B
750 *
751 * DCE 4.1
752 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
753 * Supports up to 6 digital outputs
754 * - 2 DIG encoder blocks.
755 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
756 *
757 * Routing
758 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
759 * Examples:
760 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
761 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
762 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
763 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
764 */
765
766 union dig_encoder_control {
767 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
768 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
769 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
770 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
771 };
772
773 void
774 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
775 {
776 struct drm_device *dev = encoder->dev;
777 struct radeon_device *rdev = dev->dev_private;
778 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
779 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
780 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
781 union dig_encoder_control args;
782 int index = 0;
783 uint8_t frev, crev;
784 int dp_clock = 0;
785 int dp_lane_count = 0;
786 int hpd_id = RADEON_HPD_NONE;
787 int bpc = 8;
788
789 if (connector) {
790 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
791 struct radeon_connector_atom_dig *dig_connector =
792 radeon_connector->con_priv;
793
794 dp_clock = dig_connector->dp_clock;
795 dp_lane_count = dig_connector->dp_lane_count;
796 hpd_id = radeon_connector->hpd.hpd;
797 bpc = connector->display_info.bpc;
798 }
799
800 /* no dig encoder assigned */
801 if (dig->dig_encoder == -1)
802 return;
803
804 memset(&args, 0, sizeof(args));
805
806 if (ASIC_IS_DCE4(rdev))
807 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
808 else {
809 if (dig->dig_encoder)
810 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
811 else
812 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
813 }
814
815 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
816 return;
817
818 args.v1.ucAction = action;
819 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
820 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
821
822 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
823 (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST))
824 args.v1.ucLaneNum = dp_lane_count;
825 else if (radeon_encoder->pixel_clock > 165000)
826 args.v1.ucLaneNum = 8;
827 else
828 args.v1.ucLaneNum = 4;
829
830 if (ASIC_IS_DCE5(rdev)) {
831 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
832 (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) {
833 if (dp_clock == 270000)
834 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
835 else if (dp_clock == 540000)
836 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
837 }
838 args.v4.acConfig.ucDigSel = dig->dig_encoder;
839 switch (bpc) {
840 case 0:
841 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
842 break;
843 case 6:
844 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
845 break;
846 case 8:
847 default:
848 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
849 break;
850 case 10:
851 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
852 break;
853 case 12:
854 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
855 break;
856 case 16:
857 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
858 break;
859 }
860 if (hpd_id == RADEON_HPD_NONE)
861 args.v4.ucHPD_ID = 0;
862 else
863 args.v4.ucHPD_ID = hpd_id + 1;
864 } else if (ASIC_IS_DCE4(rdev)) {
865 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
866 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
867 args.v3.acConfig.ucDigSel = dig->dig_encoder;
868 switch (bpc) {
869 case 0:
870 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
871 break;
872 case 6:
873 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
874 break;
875 case 8:
876 default:
877 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
878 break;
879 case 10:
880 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
881 break;
882 case 12:
883 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
884 break;
885 case 16:
886 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
887 break;
888 }
889 } else {
890 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
891 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
892 switch (radeon_encoder->encoder_id) {
893 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
894 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
895 break;
896 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
897 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
898 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
899 break;
900 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
901 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
902 break;
903 }
904 if (dig->linkb)
905 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
906 else
907 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
908 }
909
910 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
911
912 }
913
914 union dig_transmitter_control {
915 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
916 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
917 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
918 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
919 };
920
921 void
922 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
923 {
924 struct drm_device *dev = encoder->dev;
925 struct radeon_device *rdev = dev->dev_private;
926 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
927 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
928 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
929 union dig_transmitter_control args;
930 int index = 0;
931 uint8_t frev, crev;
932 bool is_dp = false;
933 int pll_id = 0;
934 int dp_clock = 0;
935 int dp_lane_count = 0;
936 int connector_object_id = 0;
937 int igp_lane_info = 0;
938
939 if (connector) {
940 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
941 struct radeon_connector_atom_dig *dig_connector =
942 radeon_connector->con_priv;
943
944 dp_clock = dig_connector->dp_clock;
945 dp_lane_count = dig_connector->dp_lane_count;
946 connector_object_id =
947 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
948 igp_lane_info = dig_connector->igp_lane_info;
949 }
950
951 /* no dig encoder assigned */
952 if (dig->dig_encoder == -1)
953 return;
954
955 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
956 is_dp = true;
957
958 memset(&args, 0, sizeof(args));
959
960 switch (radeon_encoder->encoder_id) {
961 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
962 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
963 break;
964 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
965 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
966 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
967 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
968 break;
969 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
970 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
971 break;
972 }
973
974 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
975 return;
976
977 args.v1.ucAction = action;
978 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
979 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
980 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
981 args.v1.asMode.ucLaneSel = lane_num;
982 args.v1.asMode.ucLaneSet = lane_set;
983 } else {
984 if (is_dp)
985 args.v1.usPixelClock =
986 cpu_to_le16(dp_clock / 10);
987 else if (radeon_encoder->pixel_clock > 165000)
988 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
989 else
990 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
991 }
992 if (ASIC_IS_DCE4(rdev)) {
993 if (is_dp)
994 args.v3.ucLaneNum = dp_lane_count;
995 else if (radeon_encoder->pixel_clock > 165000)
996 args.v3.ucLaneNum = 8;
997 else
998 args.v3.ucLaneNum = 4;
999
1000 if (dig->linkb)
1001 args.v3.acConfig.ucLinkSel = 1;
1002 if (dig->dig_encoder & 1)
1003 args.v3.acConfig.ucEncoderSel = 1;
1004
1005 /* Select the PLL for the PHY
1006 * DP PHY should be clocked from external src if there is
1007 * one.
1008 */
1009 if (encoder->crtc) {
1010 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1011 pll_id = radeon_crtc->pll_id;
1012 }
1013
1014 if (ASIC_IS_DCE5(rdev)) {
1015 /* On DCE5 DCPLL usually generates the DP ref clock */
1016 if (is_dp) {
1017 if (rdev->clock.dp_extclk)
1018 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1019 else
1020 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1021 } else
1022 args.v4.acConfig.ucRefClkSource = pll_id;
1023 } else {
1024 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1025 if (is_dp && rdev->clock.dp_extclk)
1026 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1027 else
1028 args.v3.acConfig.ucRefClkSource = pll_id;
1029 }
1030
1031 switch (radeon_encoder->encoder_id) {
1032 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1033 args.v3.acConfig.ucTransmitterSel = 0;
1034 break;
1035 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1036 args.v3.acConfig.ucTransmitterSel = 1;
1037 break;
1038 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1039 args.v3.acConfig.ucTransmitterSel = 2;
1040 break;
1041 }
1042
1043 if (is_dp)
1044 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1045 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1046 if (dig->coherent_mode)
1047 args.v3.acConfig.fCoherentMode = 1;
1048 if (radeon_encoder->pixel_clock > 165000)
1049 args.v3.acConfig.fDualLinkConnector = 1;
1050 }
1051 } else if (ASIC_IS_DCE32(rdev)) {
1052 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
1053 if (dig->linkb)
1054 args.v2.acConfig.ucLinkSel = 1;
1055
1056 switch (radeon_encoder->encoder_id) {
1057 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1058 args.v2.acConfig.ucTransmitterSel = 0;
1059 break;
1060 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1061 args.v2.acConfig.ucTransmitterSel = 1;
1062 break;
1063 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1064 args.v2.acConfig.ucTransmitterSel = 2;
1065 break;
1066 }
1067
1068 if (is_dp)
1069 args.v2.acConfig.fCoherentMode = 1;
1070 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1071 if (dig->coherent_mode)
1072 args.v2.acConfig.fCoherentMode = 1;
1073 if (radeon_encoder->pixel_clock > 165000)
1074 args.v2.acConfig.fDualLinkConnector = 1;
1075 }
1076 } else {
1077 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1078
1079 if (dig->dig_encoder)
1080 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1081 else
1082 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1083
1084 if ((rdev->flags & RADEON_IS_IGP) &&
1085 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1086 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
1087 if (igp_lane_info & 0x1)
1088 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1089 else if (igp_lane_info & 0x2)
1090 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1091 else if (igp_lane_info & 0x4)
1092 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1093 else if (igp_lane_info & 0x8)
1094 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1095 } else {
1096 if (igp_lane_info & 0x3)
1097 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1098 else if (igp_lane_info & 0xc)
1099 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1100 }
1101 }
1102
1103 if (dig->linkb)
1104 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1105 else
1106 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1107
1108 if (is_dp)
1109 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1110 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1111 if (dig->coherent_mode)
1112 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1113 if (radeon_encoder->pixel_clock > 165000)
1114 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1115 }
1116 }
1117
1118 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1119 }
1120
1121 bool
1122 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1123 {
1124 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1125 struct drm_device *dev = radeon_connector->base.dev;
1126 struct radeon_device *rdev = dev->dev_private;
1127 union dig_transmitter_control args;
1128 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1129 uint8_t frev, crev;
1130
1131 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1132 goto done;
1133
1134 if (!ASIC_IS_DCE4(rdev))
1135 goto done;
1136
1137 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1138 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1139 goto done;
1140
1141 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1142 goto done;
1143
1144 memset(&args, 0, sizeof(args));
1145
1146 args.v1.ucAction = action;
1147
1148 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1149
1150 /* wait for the panel to power up */
1151 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1152 int i;
1153
1154 for (i = 0; i < 300; i++) {
1155 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1156 return true;
1157 mdelay(1);
1158 }
1159 return false;
1160 }
1161 done:
1162 return true;
1163 }
1164
1165 union external_encoder_control {
1166 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1167 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1168 };
1169
1170 static void
1171 atombios_external_encoder_setup(struct drm_encoder *encoder,
1172 struct drm_encoder *ext_encoder,
1173 int action)
1174 {
1175 struct drm_device *dev = encoder->dev;
1176 struct radeon_device *rdev = dev->dev_private;
1177 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1178 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1179 union external_encoder_control args;
1180 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1181 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1182 u8 frev, crev;
1183 int dp_clock = 0;
1184 int dp_lane_count = 0;
1185 int connector_object_id = 0;
1186 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1187 int bpc = 8;
1188
1189 if (connector) {
1190 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1191 struct radeon_connector_atom_dig *dig_connector =
1192 radeon_connector->con_priv;
1193
1194 dp_clock = dig_connector->dp_clock;
1195 dp_lane_count = dig_connector->dp_lane_count;
1196 connector_object_id =
1197 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1198 bpc = connector->display_info.bpc;
1199 }
1200
1201 memset(&args, 0, sizeof(args));
1202
1203 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1204 return;
1205
1206 switch (frev) {
1207 case 1:
1208 /* no params on frev 1 */
1209 break;
1210 case 2:
1211 switch (crev) {
1212 case 1:
1213 case 2:
1214 args.v1.sDigEncoder.ucAction = action;
1215 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1216 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1217
1218 if (args.v1.sDigEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1219 if (dp_clock == 270000)
1220 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1221 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1222 } else if (radeon_encoder->pixel_clock > 165000)
1223 args.v1.sDigEncoder.ucLaneNum = 8;
1224 else
1225 args.v1.sDigEncoder.ucLaneNum = 4;
1226 break;
1227 case 3:
1228 args.v3.sExtEncoder.ucAction = action;
1229 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1230 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1231 else
1232 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1233 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1234
1235 if (args.v3.sExtEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1236 if (dp_clock == 270000)
1237 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1238 else if (dp_clock == 540000)
1239 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1240 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1241 } else if (radeon_encoder->pixel_clock > 165000)
1242 args.v3.sExtEncoder.ucLaneNum = 8;
1243 else
1244 args.v3.sExtEncoder.ucLaneNum = 4;
1245 switch (ext_enum) {
1246 case GRAPH_OBJECT_ENUM_ID1:
1247 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1248 break;
1249 case GRAPH_OBJECT_ENUM_ID2:
1250 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1251 break;
1252 case GRAPH_OBJECT_ENUM_ID3:
1253 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1254 break;
1255 }
1256 switch (bpc) {
1257 case 0:
1258 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1259 break;
1260 case 6:
1261 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1262 break;
1263 case 8:
1264 default:
1265 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1266 break;
1267 case 10:
1268 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1269 break;
1270 case 12:
1271 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1272 break;
1273 case 16:
1274 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1275 break;
1276 }
1277 break;
1278 default:
1279 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1280 return;
1281 }
1282 break;
1283 default:
1284 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1285 return;
1286 }
1287 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1288 }
1289
1290 static void
1291 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1292 {
1293 struct drm_device *dev = encoder->dev;
1294 struct radeon_device *rdev = dev->dev_private;
1295 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1296 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1297 ENABLE_YUV_PS_ALLOCATION args;
1298 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1299 uint32_t temp, reg;
1300
1301 memset(&args, 0, sizeof(args));
1302
1303 if (rdev->family >= CHIP_R600)
1304 reg = R600_BIOS_3_SCRATCH;
1305 else
1306 reg = RADEON_BIOS_3_SCRATCH;
1307
1308 /* XXX: fix up scratch reg handling */
1309 temp = RREG32(reg);
1310 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1311 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1312 (radeon_crtc->crtc_id << 18)));
1313 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1314 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1315 else
1316 WREG32(reg, 0);
1317
1318 if (enable)
1319 args.ucEnable = ATOM_ENABLE;
1320 args.ucCRTC = radeon_crtc->crtc_id;
1321
1322 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1323
1324 WREG32(reg, temp);
1325 }
1326
1327 static void
1328 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1329 {
1330 struct drm_device *dev = encoder->dev;
1331 struct radeon_device *rdev = dev->dev_private;
1332 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1333 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1334 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1335 int index = 0;
1336 bool is_dig = false;
1337 bool is_dce5_dac = false;
1338 bool is_dce5_dvo = false;
1339
1340 memset(&args, 0, sizeof(args));
1341
1342 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1343 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1344 radeon_encoder->active_device);
1345 switch (radeon_encoder->encoder_id) {
1346 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1347 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1348 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1349 break;
1350 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1351 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1352 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1353 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1354 is_dig = true;
1355 break;
1356 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1357 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1358 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1359 break;
1360 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1361 if (ASIC_IS_DCE5(rdev))
1362 is_dce5_dvo = true;
1363 else if (ASIC_IS_DCE3(rdev))
1364 is_dig = true;
1365 else
1366 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1367 break;
1368 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1369 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1370 break;
1371 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1372 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1373 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1374 else
1375 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1376 break;
1377 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1378 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1379 if (ASIC_IS_DCE5(rdev))
1380 is_dce5_dac = true;
1381 else {
1382 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1383 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1384 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1385 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1386 else
1387 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1388 }
1389 break;
1390 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1391 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1392 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1393 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1394 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1395 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1396 else
1397 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1398 break;
1399 }
1400
1401 if (is_dig) {
1402 switch (mode) {
1403 case DRM_MODE_DPMS_ON:
1404 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1405 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1406 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1407
1408 if (connector &&
1409 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1410 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1411 struct radeon_connector_atom_dig *radeon_dig_connector =
1412 radeon_connector->con_priv;
1413 atombios_set_edp_panel_power(connector,
1414 ATOM_TRANSMITTER_ACTION_POWER_ON);
1415 radeon_dig_connector->edp_on = true;
1416 }
1417 dp_link_train(encoder, connector);
1418 if (ASIC_IS_DCE4(rdev))
1419 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
1420 }
1421 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1422 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1423 break;
1424 case DRM_MODE_DPMS_STANDBY:
1425 case DRM_MODE_DPMS_SUSPEND:
1426 case DRM_MODE_DPMS_OFF:
1427 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1428 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1429 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1430
1431 if (ASIC_IS_DCE4(rdev))
1432 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
1433 if (connector &&
1434 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1435 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1436 struct radeon_connector_atom_dig *radeon_dig_connector =
1437 radeon_connector->con_priv;
1438 atombios_set_edp_panel_power(connector,
1439 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1440 radeon_dig_connector->edp_on = false;
1441 }
1442 }
1443 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1444 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1445 break;
1446 }
1447 } else if (is_dce5_dac) {
1448 switch (mode) {
1449 case DRM_MODE_DPMS_ON:
1450 atombios_dac_setup(encoder, ATOM_ENABLE);
1451 break;
1452 case DRM_MODE_DPMS_STANDBY:
1453 case DRM_MODE_DPMS_SUSPEND:
1454 case DRM_MODE_DPMS_OFF:
1455 atombios_dac_setup(encoder, ATOM_DISABLE);
1456 break;
1457 }
1458 } else if (is_dce5_dvo) {
1459 switch (mode) {
1460 case DRM_MODE_DPMS_ON:
1461 atombios_dvo_setup(encoder, ATOM_ENABLE);
1462 break;
1463 case DRM_MODE_DPMS_STANDBY:
1464 case DRM_MODE_DPMS_SUSPEND:
1465 case DRM_MODE_DPMS_OFF:
1466 atombios_dvo_setup(encoder, ATOM_DISABLE);
1467 break;
1468 }
1469 } else {
1470 switch (mode) {
1471 case DRM_MODE_DPMS_ON:
1472 args.ucAction = ATOM_ENABLE;
1473 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1474 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1475 args.ucAction = ATOM_LCD_BLON;
1476 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1477 }
1478 break;
1479 case DRM_MODE_DPMS_STANDBY:
1480 case DRM_MODE_DPMS_SUSPEND:
1481 case DRM_MODE_DPMS_OFF:
1482 args.ucAction = ATOM_DISABLE;
1483 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1484 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1485 args.ucAction = ATOM_LCD_BLOFF;
1486 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1487 }
1488 break;
1489 }
1490 }
1491
1492 if (ext_encoder) {
1493 int action;
1494
1495 switch (mode) {
1496 case DRM_MODE_DPMS_ON:
1497 default:
1498 if (ASIC_IS_DCE41(rdev))
1499 action = EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT;
1500 else
1501 action = ATOM_ENABLE;
1502 break;
1503 case DRM_MODE_DPMS_STANDBY:
1504 case DRM_MODE_DPMS_SUSPEND:
1505 case DRM_MODE_DPMS_OFF:
1506 if (ASIC_IS_DCE41(rdev))
1507 action = EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT;
1508 else
1509 action = ATOM_DISABLE;
1510 break;
1511 }
1512 atombios_external_encoder_setup(encoder, ext_encoder, action);
1513 }
1514
1515 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1516
1517 }
1518
1519 union crtc_source_param {
1520 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1521 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1522 };
1523
1524 static void
1525 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1526 {
1527 struct drm_device *dev = encoder->dev;
1528 struct radeon_device *rdev = dev->dev_private;
1529 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1530 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1531 union crtc_source_param args;
1532 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1533 uint8_t frev, crev;
1534 struct radeon_encoder_atom_dig *dig;
1535
1536 memset(&args, 0, sizeof(args));
1537
1538 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1539 return;
1540
1541 switch (frev) {
1542 case 1:
1543 switch (crev) {
1544 case 1:
1545 default:
1546 if (ASIC_IS_AVIVO(rdev))
1547 args.v1.ucCRTC = radeon_crtc->crtc_id;
1548 else {
1549 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1550 args.v1.ucCRTC = radeon_crtc->crtc_id;
1551 } else {
1552 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1553 }
1554 }
1555 switch (radeon_encoder->encoder_id) {
1556 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1557 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1558 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1559 break;
1560 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1561 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1562 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1563 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1564 else
1565 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1566 break;
1567 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1568 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1569 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1570 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1571 break;
1572 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1573 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1574 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1575 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1576 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1577 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1578 else
1579 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1580 break;
1581 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1582 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1583 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1584 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1585 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1586 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1587 else
1588 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1589 break;
1590 }
1591 break;
1592 case 2:
1593 args.v2.ucCRTC = radeon_crtc->crtc_id;
1594 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1595 switch (radeon_encoder->encoder_id) {
1596 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1597 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1598 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1599 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1600 dig = radeon_encoder->enc_priv;
1601 switch (dig->dig_encoder) {
1602 case 0:
1603 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1604 break;
1605 case 1:
1606 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1607 break;
1608 case 2:
1609 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1610 break;
1611 case 3:
1612 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1613 break;
1614 case 4:
1615 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1616 break;
1617 case 5:
1618 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1619 break;
1620 }
1621 break;
1622 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1623 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1624 break;
1625 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1626 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1627 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1628 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1629 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1630 else
1631 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1632 break;
1633 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1634 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1635 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1636 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1637 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1638 else
1639 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1640 break;
1641 }
1642 break;
1643 }
1644 break;
1645 default:
1646 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1647 return;
1648 }
1649
1650 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1651
1652 /* update scratch regs with new routing */
1653 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1654 }
1655
1656 static void
1657 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1658 struct drm_display_mode *mode)
1659 {
1660 struct drm_device *dev = encoder->dev;
1661 struct radeon_device *rdev = dev->dev_private;
1662 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1663 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1664
1665 /* Funky macbooks */
1666 if ((dev->pdev->device == 0x71C5) &&
1667 (dev->pdev->subsystem_vendor == 0x106b) &&
1668 (dev->pdev->subsystem_device == 0x0080)) {
1669 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1670 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1671
1672 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1673 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1674
1675 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1676 }
1677 }
1678
1679 /* set scaler clears this on some chips */
1680 if (ASIC_IS_AVIVO(rdev) &&
1681 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1682 if (ASIC_IS_DCE4(rdev)) {
1683 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1684 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1685 EVERGREEN_INTERLEAVE_EN);
1686 else
1687 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1688 } else {
1689 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1690 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1691 AVIVO_D1MODE_INTERLEAVE_EN);
1692 else
1693 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1694 }
1695 }
1696 }
1697
1698 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1699 {
1700 struct drm_device *dev = encoder->dev;
1701 struct radeon_device *rdev = dev->dev_private;
1702 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1703 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1704 struct drm_encoder *test_encoder;
1705 struct radeon_encoder_atom_dig *dig;
1706 uint32_t dig_enc_in_use = 0;
1707
1708 /* DCE4/5 */
1709 if (ASIC_IS_DCE4(rdev)) {
1710 dig = radeon_encoder->enc_priv;
1711 if (ASIC_IS_DCE41(rdev))
1712 return radeon_crtc->crtc_id;
1713 else {
1714 switch (radeon_encoder->encoder_id) {
1715 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1716 if (dig->linkb)
1717 return 1;
1718 else
1719 return 0;
1720 break;
1721 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1722 if (dig->linkb)
1723 return 3;
1724 else
1725 return 2;
1726 break;
1727 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1728 if (dig->linkb)
1729 return 5;
1730 else
1731 return 4;
1732 break;
1733 }
1734 }
1735 }
1736
1737 /* on DCE32 and encoder can driver any block so just crtc id */
1738 if (ASIC_IS_DCE32(rdev)) {
1739 return radeon_crtc->crtc_id;
1740 }
1741
1742 /* on DCE3 - LVTMA can only be driven by DIGB */
1743 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1744 struct radeon_encoder *radeon_test_encoder;
1745
1746 if (encoder == test_encoder)
1747 continue;
1748
1749 if (!radeon_encoder_is_digital(test_encoder))
1750 continue;
1751
1752 radeon_test_encoder = to_radeon_encoder(test_encoder);
1753 dig = radeon_test_encoder->enc_priv;
1754
1755 if (dig->dig_encoder >= 0)
1756 dig_enc_in_use |= (1 << dig->dig_encoder);
1757 }
1758
1759 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1760 if (dig_enc_in_use & 0x2)
1761 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1762 return 1;
1763 }
1764 if (!(dig_enc_in_use & 1))
1765 return 0;
1766 return 1;
1767 }
1768
1769 static void
1770 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1771 struct drm_display_mode *mode,
1772 struct drm_display_mode *adjusted_mode)
1773 {
1774 struct drm_device *dev = encoder->dev;
1775 struct radeon_device *rdev = dev->dev_private;
1776 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1777 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1778
1779 radeon_encoder->pixel_clock = adjusted_mode->clock;
1780
1781 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1782 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1783 atombios_yuv_setup(encoder, true);
1784 else
1785 atombios_yuv_setup(encoder, false);
1786 }
1787
1788 switch (radeon_encoder->encoder_id) {
1789 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1790 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1791 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1792 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1793 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1794 break;
1795 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1796 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1797 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1798 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1799 if (ASIC_IS_DCE4(rdev)) {
1800 /* disable the transmitter */
1801 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1802 /* setup and enable the encoder */
1803 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
1804
1805 /* init and enable the transmitter */
1806 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1807 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1808 } else {
1809 /* disable the encoder and transmitter */
1810 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1811 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1812
1813 /* setup and enable the encoder and transmitter */
1814 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1815 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1816 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1817 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1818 }
1819 break;
1820 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1821 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1822 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1823 atombios_dvo_setup(encoder, ATOM_ENABLE);
1824 break;
1825 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1826 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1827 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1828 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1829 atombios_dac_setup(encoder, ATOM_ENABLE);
1830 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1831 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1832 atombios_tv_setup(encoder, ATOM_ENABLE);
1833 else
1834 atombios_tv_setup(encoder, ATOM_DISABLE);
1835 }
1836 break;
1837 }
1838
1839 if (ext_encoder) {
1840 if (ASIC_IS_DCE41(rdev)) {
1841 atombios_external_encoder_setup(encoder, ext_encoder,
1842 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1843 atombios_external_encoder_setup(encoder, ext_encoder,
1844 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1845 } else
1846 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1847 }
1848
1849 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1850
1851 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1852 r600_hdmi_enable(encoder);
1853 r600_hdmi_setmode(encoder, adjusted_mode);
1854 }
1855 }
1856
1857 static bool
1858 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1859 {
1860 struct drm_device *dev = encoder->dev;
1861 struct radeon_device *rdev = dev->dev_private;
1862 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1863 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1864
1865 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1866 ATOM_DEVICE_CV_SUPPORT |
1867 ATOM_DEVICE_CRT_SUPPORT)) {
1868 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1869 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1870 uint8_t frev, crev;
1871
1872 memset(&args, 0, sizeof(args));
1873
1874 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1875 return false;
1876
1877 args.sDacload.ucMisc = 0;
1878
1879 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1880 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1881 args.sDacload.ucDacType = ATOM_DAC_A;
1882 else
1883 args.sDacload.ucDacType = ATOM_DAC_B;
1884
1885 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1886 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1887 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1888 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1889 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1890 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1891 if (crev >= 3)
1892 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1893 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1894 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1895 if (crev >= 3)
1896 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1897 }
1898
1899 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1900
1901 return true;
1902 } else
1903 return false;
1904 }
1905
1906 static enum drm_connector_status
1907 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1908 {
1909 struct drm_device *dev = encoder->dev;
1910 struct radeon_device *rdev = dev->dev_private;
1911 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1912 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1913 uint32_t bios_0_scratch;
1914
1915 if (!atombios_dac_load_detect(encoder, connector)) {
1916 DRM_DEBUG_KMS("detect returned false \n");
1917 return connector_status_unknown;
1918 }
1919
1920 if (rdev->family >= CHIP_R600)
1921 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1922 else
1923 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1924
1925 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1926 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1927 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1928 return connector_status_connected;
1929 }
1930 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1931 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1932 return connector_status_connected;
1933 }
1934 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1935 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1936 return connector_status_connected;
1937 }
1938 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1939 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1940 return connector_status_connected; /* CTV */
1941 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1942 return connector_status_connected; /* STV */
1943 }
1944 return connector_status_disconnected;
1945 }
1946
1947 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1948 {
1949 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1950 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1951
1952 if ((radeon_encoder->active_device &
1953 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
1954 radeon_encoder_is_dp_bridge(encoder)) {
1955 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1956 if (dig)
1957 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1958 }
1959
1960 radeon_atom_output_lock(encoder, true);
1961 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1962
1963 if (connector) {
1964 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1965
1966 /* select the clock/data port if it uses a router */
1967 if (radeon_connector->router.cd_valid)
1968 radeon_router_select_cd_port(radeon_connector);
1969
1970 /* turn eDP panel on for mode set */
1971 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1972 atombios_set_edp_panel_power(connector,
1973 ATOM_TRANSMITTER_ACTION_POWER_ON);
1974 }
1975
1976 /* this is needed for the pll/ss setup to work correctly in some cases */
1977 atombios_set_encoder_crtc_source(encoder);
1978 }
1979
1980 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1981 {
1982 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1983 radeon_atom_output_lock(encoder, false);
1984 }
1985
1986 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1987 {
1988 struct drm_device *dev = encoder->dev;
1989 struct radeon_device *rdev = dev->dev_private;
1990 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1991 struct radeon_encoder_atom_dig *dig;
1992
1993 /* check for pre-DCE3 cards with shared encoders;
1994 * can't really use the links individually, so don't disable
1995 * the encoder if it's in use by another connector
1996 */
1997 if (!ASIC_IS_DCE3(rdev)) {
1998 struct drm_encoder *other_encoder;
1999 struct radeon_encoder *other_radeon_encoder;
2000
2001 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2002 other_radeon_encoder = to_radeon_encoder(other_encoder);
2003 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2004 drm_helper_encoder_in_use(other_encoder))
2005 goto disable_done;
2006 }
2007 }
2008
2009 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2010
2011 switch (radeon_encoder->encoder_id) {
2012 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2013 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2014 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2015 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2016 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2017 break;
2018 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2019 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2020 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2021 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2022 if (ASIC_IS_DCE4(rdev))
2023 /* disable the transmitter */
2024 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2025 else {
2026 /* disable the encoder and transmitter */
2027 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2028 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
2029 }
2030 break;
2031 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2032 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2033 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2034 atombios_dvo_setup(encoder, ATOM_DISABLE);
2035 break;
2036 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2037 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2038 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2039 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2040 atombios_dac_setup(encoder, ATOM_DISABLE);
2041 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2042 atombios_tv_setup(encoder, ATOM_DISABLE);
2043 break;
2044 }
2045
2046 disable_done:
2047 if (radeon_encoder_is_digital(encoder)) {
2048 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2049 r600_hdmi_disable(encoder);
2050 dig = radeon_encoder->enc_priv;
2051 dig->dig_encoder = -1;
2052 }
2053 radeon_encoder->active_device = 0;
2054 }
2055
2056 /* these are handled by the primary encoders */
2057 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2058 {
2059
2060 }
2061
2062 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2063 {
2064
2065 }
2066
2067 static void
2068 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2069 struct drm_display_mode *mode,
2070 struct drm_display_mode *adjusted_mode)
2071 {
2072
2073 }
2074
2075 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2076 {
2077
2078 }
2079
2080 static void
2081 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2082 {
2083
2084 }
2085
2086 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2087 struct drm_display_mode *mode,
2088 struct drm_display_mode *adjusted_mode)
2089 {
2090 return true;
2091 }
2092
2093 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2094 .dpms = radeon_atom_ext_dpms,
2095 .mode_fixup = radeon_atom_ext_mode_fixup,
2096 .prepare = radeon_atom_ext_prepare,
2097 .mode_set = radeon_atom_ext_mode_set,
2098 .commit = radeon_atom_ext_commit,
2099 .disable = radeon_atom_ext_disable,
2100 /* no detect for TMDS/LVDS yet */
2101 };
2102
2103 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2104 .dpms = radeon_atom_encoder_dpms,
2105 .mode_fixup = radeon_atom_mode_fixup,
2106 .prepare = radeon_atom_encoder_prepare,
2107 .mode_set = radeon_atom_encoder_mode_set,
2108 .commit = radeon_atom_encoder_commit,
2109 .disable = radeon_atom_encoder_disable,
2110 /* no detect for TMDS/LVDS yet */
2111 };
2112
2113 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2114 .dpms = radeon_atom_encoder_dpms,
2115 .mode_fixup = radeon_atom_mode_fixup,
2116 .prepare = radeon_atom_encoder_prepare,
2117 .mode_set = radeon_atom_encoder_mode_set,
2118 .commit = radeon_atom_encoder_commit,
2119 .detect = radeon_atom_dac_detect,
2120 };
2121
2122 void radeon_enc_destroy(struct drm_encoder *encoder)
2123 {
2124 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2125 kfree(radeon_encoder->enc_priv);
2126 drm_encoder_cleanup(encoder);
2127 kfree(radeon_encoder);
2128 }
2129
2130 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2131 .destroy = radeon_enc_destroy,
2132 };
2133
2134 struct radeon_encoder_atom_dac *
2135 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2136 {
2137 struct drm_device *dev = radeon_encoder->base.dev;
2138 struct radeon_device *rdev = dev->dev_private;
2139 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2140
2141 if (!dac)
2142 return NULL;
2143
2144 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2145 return dac;
2146 }
2147
2148 struct radeon_encoder_atom_dig *
2149 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2150 {
2151 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2152 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2153
2154 if (!dig)
2155 return NULL;
2156
2157 /* coherent mode by default */
2158 dig->coherent_mode = true;
2159 dig->dig_encoder = -1;
2160
2161 if (encoder_enum == 2)
2162 dig->linkb = true;
2163 else
2164 dig->linkb = false;
2165
2166 return dig;
2167 }
2168
2169 void
2170 radeon_add_atom_encoder(struct drm_device *dev,
2171 uint32_t encoder_enum,
2172 uint32_t supported_device,
2173 u16 caps)
2174 {
2175 struct radeon_device *rdev = dev->dev_private;
2176 struct drm_encoder *encoder;
2177 struct radeon_encoder *radeon_encoder;
2178
2179 /* see if we already added it */
2180 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2181 radeon_encoder = to_radeon_encoder(encoder);
2182 if (radeon_encoder->encoder_enum == encoder_enum) {
2183 radeon_encoder->devices |= supported_device;
2184 return;
2185 }
2186
2187 }
2188
2189 /* add a new one */
2190 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2191 if (!radeon_encoder)
2192 return;
2193
2194 encoder = &radeon_encoder->base;
2195 switch (rdev->num_crtc) {
2196 case 1:
2197 encoder->possible_crtcs = 0x1;
2198 break;
2199 case 2:
2200 default:
2201 encoder->possible_crtcs = 0x3;
2202 break;
2203 case 6:
2204 encoder->possible_crtcs = 0x3f;
2205 break;
2206 }
2207
2208 radeon_encoder->enc_priv = NULL;
2209
2210 radeon_encoder->encoder_enum = encoder_enum;
2211 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2212 radeon_encoder->devices = supported_device;
2213 radeon_encoder->rmx_type = RMX_OFF;
2214 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2215 radeon_encoder->is_ext_encoder = false;
2216 radeon_encoder->caps = caps;
2217
2218 switch (radeon_encoder->encoder_id) {
2219 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2220 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2221 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2222 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2223 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2224 radeon_encoder->rmx_type = RMX_FULL;
2225 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2226 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2227 } else {
2228 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2229 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2230 }
2231 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2232 break;
2233 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2234 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2235 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2236 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2237 break;
2238 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2239 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2240 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2241 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2242 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2243 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2244 break;
2245 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2246 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2247 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2248 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2249 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2250 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2251 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2252 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2253 radeon_encoder->rmx_type = RMX_FULL;
2254 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2255 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2256 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2257 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2258 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2259 } else {
2260 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2261 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2262 }
2263 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2264 break;
2265 case ENCODER_OBJECT_ID_SI170B:
2266 case ENCODER_OBJECT_ID_CH7303:
2267 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2268 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2269 case ENCODER_OBJECT_ID_TITFP513:
2270 case ENCODER_OBJECT_ID_VT1623:
2271 case ENCODER_OBJECT_ID_HDMI_SI1930:
2272 case ENCODER_OBJECT_ID_TRAVIS:
2273 case ENCODER_OBJECT_ID_NUTMEG:
2274 /* these are handled by the primary encoders */
2275 radeon_encoder->is_ext_encoder = true;
2276 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2277 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2278 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2279 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2280 else
2281 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2282 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2283 break;
2284 }
2285 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree