drivers/staging/gma500/mrst_crtc.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, write to the Free Software Foundation, Inc.,
  15  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  16  */
  17
  18 #include <linux/i2c.h>
  19 #include <linux/pm_runtime.h>
  20
  21 #include <drm/drmP.h>
  22 #include "psb_fb.h"
  23 #include "psb_drv.h"
  24 #include "psb_intel_drv.h"
  25 #include "psb_intel_reg.h"
  26 #include "psb_intel_display.h"
  27 #include "psb_powermgmt.h"
  28
  29 struct psb_intel_range_t {
  30         int min, max;
  31 };
  32
  33 struct mrst_limit_t {
  34         struct psb_intel_range_t dot, m, p1;
  35 };
  36
  37 struct mrst_clock_t {
  38         /* derived values */
  39         int dot;
  40         int m;
  41         int p1;
  42 };
  43
  44 #define MRST_LIMIT_LVDS_100L        0
  45 #define MRST_LIMIT_LVDS_83          1
  46 #define MRST_LIMIT_LVDS_100         2
  47
  48 #define MRST_DOT_MIN              19750
  49 #define MRST_DOT_MAX              120000
  50 #define MRST_M_MIN_100L             20
  51 #define MRST_M_MIN_100              10
  52 #define MRST_M_MIN_83               12
  53 #define MRST_M_MAX_100L             34
  54 #define MRST_M_MAX_100              17
  55 #define MRST_M_MAX_83               20
  56 #define MRST_P1_MIN                 2
  57 #define MRST_P1_MAX_0               7
  58 #define MRST_P1_MAX_1               8
  59
  60 static const struct mrst_limit_t mrst_limits[] = {
  61         {                       /* MRST_LIMIT_LVDS_100L */
  62          .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
  63          .m = {.min = MRST_M_MIN_100L, .max = MRST_M_MAX_100L},
  64          .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1},
  65          },
  66         {                       /* MRST_LIMIT_LVDS_83L */
  67          .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
  68          .m = {.min = MRST_M_MIN_83, .max = MRST_M_MAX_83},
  69          .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_0},
  70          },
  71         {                       /* MRST_LIMIT_LVDS_100 */
  72          .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
  73          .m = {.min = MRST_M_MIN_100, .max = MRST_M_MAX_100},
  74          .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1},
  75          },
  76 };
  77
  78 #define MRST_M_MIN          10
  79 static const u32 mrst_m_converts[] = {
  80         0x2B, 0x15, 0x2A, 0x35, 0x1A, 0x0D, 0x26, 0x33, 0x19, 0x2C,
  81         0x36, 0x3B, 0x1D, 0x2E, 0x37, 0x1B, 0x2D, 0x16, 0x0B, 0x25,
  82         0x12, 0x09, 0x24, 0x32, 0x39, 0x1c,
  83 };
  84
  85 static const struct mrst_limit_t *mrst_limit(struct drm_crtc *crtc)
  86 {
  87         const struct mrst_limit_t *limit = NULL;
  88         struct drm_device *dev = crtc->dev;
  89         DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
  90
  91         if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
  92             || psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_MIPI)) {
  93                 switch (dev_priv->core_freq) {
  94                 case 100:
  95                         limit = &mrst_limits[MRST_LIMIT_LVDS_100L];
  96                         break;
  97                 case 166:
  98                         limit = &mrst_limits[MRST_LIMIT_LVDS_83];
  99                         break;
 100                 case 200:
 101                         limit = &mrst_limits[MRST_LIMIT_LVDS_100];
 102                         break;
 103                 }
 104         } else {
 105                 limit = NULL;
 106                 PSB_DEBUG_ENTRY("mrst_limit Wrong display type.\n");
 107         }
 108
 109         return limit;
 110 }
 111
 112 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
 113 static void mrst_clock(int refclk, struct mrst_clock_t *clock)
 114 {
 115         clock->dot = (refclk * clock->m) / (14 * clock->p1);
 116 }
 117
 118 void mrstPrintPll(char *prefix, struct mrst_clock_t *clock)
 119 {
 120         PSB_DEBUG_ENTRY("%s: dotclock = %d,  m = %d, p1 = %d.\n",
 121              prefix, clock->dot, clock->m, clock->p1);
 122 }
 123
 124 /**
 125  * Returns a set of divisors for the desired target clock with the given refclk,
 126  * or FALSE.  Divisor values are the actual divisors for
 127  */
 128 static bool
 129 mrstFindBestPLL(struct drm_crtc *crtc, int target, int refclk,
 130                 struct mrst_clock_t *best_clock)
 131 {
 132         struct mrst_clock_t clock;
 133         const struct mrst_limit_t *limit = mrst_limit(crtc);
 134         int err = target;
 135
 136         memset(best_clock, 0, sizeof(*best_clock));
 137
 138         for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) {
 139                 for (clock.p1 = limit->p1.min; clock.p1 <= limit->p1.max;
 140                      clock.p1++) {
 141                         int this_err;
 142
 143                         mrst_clock(refclk, &clock);
 144
 145                         this_err = abs(clock.dot - target);
 146                         if (this_err < err) {
 147                                 *best_clock = clock;
 148                                 err = this_err;
 149                         }
 150                 }
 151         }
 152         DRM_DEBUG("mrstFindBestPLL err = %d.\n", err);
 153
 154         return err != target;
 155 }
 156
 157 /**
 158  * Sets the power management mode of the pipe and plane.
 159  *
 160  * This code should probably grow support for turning the cursor off and back
 161  * on appropriately at the same time as we're turning the pipe off/on.
 162  */
 163 static void mrst_crtc_dpms(struct drm_crtc *crtc, int mode)
 164 {
 165         struct drm_device *dev = crtc->dev;
 166         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 167         int pipe = psb_intel_crtc->pipe;
 168         int dpll_reg = (pipe == 0) ? MRST_DPLL_A : DPLL_B;
 169         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
 170         int dspbase_reg = (pipe == 0) ? MRST_DSPABASE : DSPBBASE;
 171         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
 172         u32 temp;
 173         bool enabled;
 174
 175         PSB_DEBUG_ENTRY("mode = %d, pipe = %d\n", mode, pipe);
 176
 177         if (!gma_power_begin(dev, true))
 178                 return;
 179
 180         /* XXX: When our outputs are all unaware of DPMS modes other than off
 181          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
 182          */
 183         switch (mode) {
 184         case DRM_MODE_DPMS_ON:
 185         case DRM_MODE_DPMS_STANDBY:
 186         case DRM_MODE_DPMS_SUSPEND:
 187                 /* Enable the DPLL */
 188                 temp = REG_READ(dpll_reg);
 189                 if ((temp & DPLL_VCO_ENABLE) == 0) {
 190                         REG_WRITE(dpll_reg, temp);
 191                         REG_READ(dpll_reg);
 192                         /* Wait for the clocks to stabilize. */
 193                         udelay(150);
 194                         REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
 195                         REG_READ(dpll_reg);
 196                         /* Wait for the clocks to stabilize. */
 197                         udelay(150);
 198                         REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
 199                         REG_READ(dpll_reg);
 200                         /* Wait for the clocks to stabilize. */
 201                         udelay(150);
 202                 }
 203                 /* Enable the pipe */
 204                 temp = REG_READ(pipeconf_reg);
 205                 if ((temp & PIPEACONF_ENABLE) == 0)
 206                         REG_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
 207                 /* Enable the plane */
 208                 temp = REG_READ(dspcntr_reg);
 209                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
 210                         REG_WRITE(dspcntr_reg,
 211                                   temp | DISPLAY_PLANE_ENABLE);
 212                         /* Flush the plane changes */
 213                         REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
 214                 }
 215
 216                 psb_intel_crtc_load_lut(crtc);
 217
 218                 /* Give the overlay scaler a chance to enable
 219                    if it's on this pipe */
 220                 /* psb_intel_crtc_dpms_video(crtc, true); TODO */
 221                 break;
 222         case DRM_MODE_DPMS_OFF:
 223                 /* Give the overlay scaler a chance to disable
 224                  * if it's on this pipe */
 225                 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
 226
 227                 /* Disable the VGA plane that we never use */
 228                 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
 229                 /* Disable display plane */
 230                 temp = REG_READ(dspcntr_reg);
 231                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
 232                         REG_WRITE(dspcntr_reg,
 233                                   temp & ~DISPLAY_PLANE_ENABLE);
 234                         /* Flush the plane changes */
 235                         REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
 236                         REG_READ(dspbase_reg);
 237                 }
 238
 239                 /* Next, disable display pipes */
 240                 temp = REG_READ(pipeconf_reg);
 241                 if ((temp & PIPEACONF_ENABLE) != 0) {
 242                         REG_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
 243                         REG_READ(pipeconf_reg);
 244                 }
 245                 /* Wait for for the pipe disable to take effect. */
 246                 psb_intel_wait_for_vblank(dev);
 247
 248                 temp = REG_READ(dpll_reg);
 249                 if ((temp & DPLL_VCO_ENABLE) != 0) {
 250                         REG_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
 251                         REG_READ(dpll_reg);
 252                 }
 253
 254                 /* Wait for the clocks to turn off. */
 255                 udelay(150);
 256                 break;
 257         }
 258
 259         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
 260
 261         /*Set FIFO Watermarks*/
 262         REG_WRITE(DSPARB, 0x3FFF);
 263         REG_WRITE(DSPFW1, 0x3F88080A);
 264         REG_WRITE(DSPFW2, 0x0b060808);
 265         REG_WRITE(DSPFW3, 0x0);
 266         REG_WRITE(DSPFW4, 0x08030404);
 267         REG_WRITE(DSPFW5, 0x04040404);
 268         REG_WRITE(DSPFW6, 0x78);
 269         REG_WRITE(0x70400, REG_READ(0x70400) | 0x4000);
 270         /* Must write Bit 14 of the Chicken Bit Register */
 271
 272         gma_power_end(dev);
 273 }
 274
 275 /**
 276  * Return the pipe currently connected to the panel fitter,
 277  * or -1 if the panel fitter is not present or not in use
 278  */
 279 static int mrst_panel_fitter_pipe(struct drm_device *dev)
 280 {
 281         u32 pfit_control;
 282
 283         pfit_control = REG_READ(PFIT_CONTROL);
 284
 285         /* See if the panel fitter is in use */
 286         if ((pfit_control & PFIT_ENABLE) == 0)
 287                 return -1;
 288         return (pfit_control >> 29) & 3;
 289 }
 290
 291 static int mrst_crtc_mode_set(struct drm_crtc *crtc,
 292                               struct drm_display_mode *mode,
 293                               struct drm_display_mode *adjusted_mode,
 294                               int x, int y,
 295                               struct drm_framebuffer *old_fb)
 296 {
 297         struct drm_device *dev = crtc->dev;
 298         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 299         DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
 300         int pipe = psb_intel_crtc->pipe;
 301         int fp_reg = (pipe == 0) ? MRST_FPA0 : FPB0;
 302         int dpll_reg = (pipe == 0) ? MRST_DPLL_A : DPLL_B;
 303         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
 304         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
 305         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
 306         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
 307         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
 308         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
 309         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
 310         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
 311         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
 312         int refclk = 0;
 313         struct mrst_clock_t clock;
 314         u32 dpll = 0, fp = 0, dspcntr, pipeconf;
 315         bool ok, is_sdvo = false;
 316         bool is_crt = false, is_lvds = false, is_tv = false;
 317         bool is_mipi = false;
 318         struct drm_mode_config *mode_config = &dev->mode_config;
 319         struct psb_intel_output *psb_intel_output = NULL;
 320         uint64_t scalingType = DRM_MODE_SCALE_FULLSCREEN;
 321         struct drm_encoder *encoder;
 322
 323         PSB_DEBUG_ENTRY("pipe = 0x%x\n", pipe);
 324
 325         if (!gma_power_begin(dev, true))
 326                 return 0;
 327
 328         memcpy(&psb_intel_crtc->saved_mode,
 329                 mode,
 330                 sizeof(struct drm_display_mode));
 331         memcpy(&psb_intel_crtc->saved_adjusted_mode,
 332                 adjusted_mode,
 333                 sizeof(struct drm_display_mode));
 334
 335         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 336
 337                 if (encoder->crtc != crtc)
 338                         continue;
 339
 340                 psb_intel_output = enc_to_psb_intel_output(encoder);
 341                 switch (psb_intel_output->type) {
 342                 case INTEL_OUTPUT_LVDS:
 343                         is_lvds = true;
 344                         break;
 345                 case INTEL_OUTPUT_SDVO:
 346                         is_sdvo = true;
 347                         break;
 348                 case INTEL_OUTPUT_TVOUT:
 349                         is_tv = true;
 350                         break;
 351                 case INTEL_OUTPUT_ANALOG:
 352                         is_crt = true;
 353                         break;
 354                 case INTEL_OUTPUT_MIPI:
 355                         is_mipi = true;
 356                         break;
 357                 }
 358         }
 359
 360         /* Disable the VGA plane that we never use */
 361         REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
 362
 363         /* Disable the panel fitter if it was on our pipe */
 364         if (mrst_panel_fitter_pipe(dev) == pipe)
 365                 REG_WRITE(PFIT_CONTROL, 0);
 366
 367         REG_WRITE(pipesrc_reg,
 368                   ((mode->crtc_hdisplay - 1) << 16) |
 369                   (mode->crtc_vdisplay - 1));
 370
 371         if (psb_intel_output)
 372                 drm_connector_property_get_value(&psb_intel_output->base,
 373                         dev->mode_config.scaling_mode_property, &scalingType);
 374
 375         if (scalingType == DRM_MODE_SCALE_NO_SCALE) {
 376                 /* Moorestown doesn't have register support for centering so
 377                  * we need to mess with the h/vblank and h/vsync start and
 378                  * ends to get centering */
 379                 int offsetX = 0, offsetY = 0;
 380
 381                 offsetX = (adjusted_mode->crtc_hdisplay -
 382                            mode->crtc_hdisplay) / 2;
 383                 offsetY = (adjusted_mode->crtc_vdisplay -
 384                            mode->crtc_vdisplay) / 2;
 385
 386                 REG_WRITE(htot_reg, (mode->crtc_hdisplay - 1) |
 387                         ((adjusted_mode->crtc_htotal - 1) << 16));
 388                 REG_WRITE(vtot_reg, (mode->crtc_vdisplay - 1) |
 389                         ((adjusted_mode->crtc_vtotal - 1) << 16));
 390                 REG_WRITE(hblank_reg,
 391                         (adjusted_mode->crtc_hblank_start - offsetX - 1) |
 392                         ((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16));
 393                 REG_WRITE(hsync_reg,
 394                         (adjusted_mode->crtc_hsync_start - offsetX - 1) |
 395                         ((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16));
 396                 REG_WRITE(vblank_reg,
 397                         (adjusted_mode->crtc_vblank_start - offsetY - 1) |
 398                         ((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16));
 399                 REG_WRITE(vsync_reg,
 400                         (adjusted_mode->crtc_vsync_start - offsetY - 1) |
 401                         ((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16));
 402         } else {
 403                 REG_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
 404                         ((adjusted_mode->crtc_htotal - 1) << 16));
 405                 REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
 406                         ((adjusted_mode->crtc_vtotal - 1) << 16));
 407                 REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
 408                         ((adjusted_mode->crtc_hblank_end - 1) << 16));
 409                 REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
 410                         ((adjusted_mode->crtc_hsync_end - 1) << 16));
 411                 REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
 412                         ((adjusted_mode->crtc_vblank_end - 1) << 16));
 413                 REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
 414                         ((adjusted_mode->crtc_vsync_end - 1) << 16));
 415         }
 416
 417         /* Flush the plane changes */
 418         {
 419                 struct drm_crtc_helper_funcs *crtc_funcs =
 420                     crtc->helper_private;
 421                 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
 422         }
 423
 424         /* setup pipeconf */
 425         pipeconf = REG_READ(pipeconf_reg);
 426
 427         /* Set up the display plane register */
 428         dspcntr = REG_READ(dspcntr_reg);
 429         dspcntr |= DISPPLANE_GAMMA_ENABLE;
 430
 431         if (pipe == 0)
 432                 dspcntr |= DISPPLANE_SEL_PIPE_A;
 433         else
 434                 dspcntr |= DISPPLANE_SEL_PIPE_B;
 435
 436         dev_priv->dspcntr = dspcntr |= DISPLAY_PLANE_ENABLE;
 437         dev_priv->pipeconf = pipeconf |= PIPEACONF_ENABLE;
 438
 439         if (is_mipi)
 440                 goto mrst_crtc_mode_set_exit;
 441
 442         refclk = dev_priv->core_freq * 1000;
 443
 444         dpll = 0;               /*BIT16 = 0 for 100MHz reference */
 445
 446         ok = mrstFindBestPLL(crtc, adjusted_mode->clock, refclk, &clock);
 447
 448         if (!ok) {
 449                 PSB_DEBUG_ENTRY(
 450                         "mrstFindBestPLL fail in mrst_crtc_mode_set.\n");
 451         } else {
 452                 PSB_DEBUG_ENTRY("mrst_crtc_mode_set pixel clock = %d,"
 453                          "m = %x, p1 = %x.\n", clock.dot, clock.m,
 454                          clock.p1);
 455         }
 456
 457         fp = mrst_m_converts[(clock.m - MRST_M_MIN)] << 8;
 458
 459         dpll |= DPLL_VGA_MODE_DIS;
 460
 461
 462         dpll |= DPLL_VCO_ENABLE;
 463
 464         if (is_lvds)
 465                 dpll |= DPLLA_MODE_LVDS;
 466         else
 467                 dpll |= DPLLB_MODE_DAC_SERIAL;
 468
 469         if (is_sdvo) {
 470                 int sdvo_pixel_multiply =
 471                     adjusted_mode->clock / mode->clock;
 472
 473                 dpll |= DPLL_DVO_HIGH_SPEED;
 474                 dpll |=
 475                     (sdvo_pixel_multiply -
 476                      1) << SDVO_MULTIPLIER_SHIFT_HIRES;
 477         }
 478
 479
 480         /* compute bitmask from p1 value */
 481         dpll |= (1 << (clock.p1 - 2)) << 17;
 482
 483         dpll |= DPLL_VCO_ENABLE;
 484
 485         mrstPrintPll("chosen", &clock);
 486
 487         if (dpll & DPLL_VCO_ENABLE) {
 488                 REG_WRITE(fp_reg, fp);
 489                 REG_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
 490                 REG_READ(dpll_reg);
 491                 /* Check the DPLLA lock bit PIPEACONF[29] */
 492                 udelay(150);
 493         }
 494
 495         REG_WRITE(fp_reg, fp);
 496         REG_WRITE(dpll_reg, dpll);
 497         REG_READ(dpll_reg);
 498         /* Wait for the clocks to stabilize. */
 499         udelay(150);
 500
 501         /* write it again -- the BIOS does, after all */
 502         REG_WRITE(dpll_reg, dpll);
 503         REG_READ(dpll_reg);
 504         /* Wait for the clocks to stabilize. */
 505         udelay(150);
 506
 507         REG_WRITE(pipeconf_reg, pipeconf);
 508         REG_READ(pipeconf_reg);
 509         psb_intel_wait_for_vblank(dev);
 510
 511         REG_WRITE(dspcntr_reg, dspcntr);
 512         psb_intel_wait_for_vblank(dev);
 513
 514 mrst_crtc_mode_set_exit:
 515         gma_power_end(dev);
 516         return 0;
 517 }
 518
 519 static bool mrst_crtc_mode_fixup(struct drm_crtc *crtc,
 520                                   struct drm_display_mode *mode,
 521                                   struct drm_display_mode *adjusted_mode)
 522 {
 523         return true;
 524 }
 525
 526 int mrst_pipe_set_base(struct drm_crtc *crtc,
 527                             int x, int y, struct drm_framebuffer *old_fb)
 528 {
 529         struct drm_device *dev = crtc->dev;
 530         /* struct drm_i915_master_private *master_priv; */
 531         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 532         struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
 533         int pipe = psb_intel_crtc->pipe;
 534         unsigned long start, offset;
 535         /* FIXME: check if we need this surely MRST is pipe 0 only */
 536         int dspbase = (pipe == 0 ? DSPALINOFF : DSPBBASE);
 537         int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
 538         int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
 539         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
 540         u32 dspcntr;
 541         int ret = 0;
 542
 543         PSB_DEBUG_ENTRY("\n");
 544
 545         /* no fb bound */
 546         if (!crtc->fb) {
 547                 DRM_DEBUG("No FB bound\n");
 548                 return 0;
 549         }
 550
 551         if (!gma_power_begin(dev, true))
 552                 return 0;
 553
 554         start = psbfb->gtt->offset;
 555         offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
 556
 557         REG_WRITE(dspstride, crtc->fb->pitch);
 558
 559         dspcntr = REG_READ(dspcntr_reg);
 560         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
 561
 562         switch (crtc->fb->bits_per_pixel) {
 563         case 8:
 564                 dspcntr |= DISPPLANE_8BPP;
 565                 break;
 566         case 16:
 567                 if (crtc->fb->depth == 15)
 568                         dspcntr |= DISPPLANE_15_16BPP;
 569                 else
 570                         dspcntr |= DISPPLANE_16BPP;
 571                 break;
 572         case 24:
 573         case 32:
 574                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
 575                 break;
 576         default:
 577                 DRM_ERROR("Unknown color depth\n");
 578                 ret = -EINVAL;
 579                 goto pipe_set_base_exit;
 580         }
 581         REG_WRITE(dspcntr_reg, dspcntr);
 582
 583         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", start, offset, x, y);
 584         if (0 /* FIXMEAC - check what PSB needs */) {
 585                 REG_WRITE(dspbase, offset);
 586                 REG_READ(dspbase);
 587                 REG_WRITE(dspsurf, start);
 588                 REG_READ(dspsurf);
 589         } else {
 590                 REG_WRITE(dspbase, start + offset);
 591                 REG_READ(dspbase);
 592         }
 593
 594 pipe_set_base_exit:
 595         gma_power_end(dev);
 596         return ret;
 597 }
 598
 599 static void mrst_crtc_prepare(struct drm_crtc *crtc)
 600 {
 601         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 602         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
 603 }
 604
 605 static void mrst_crtc_commit(struct drm_crtc *crtc)
 606 {
 607         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 608         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
 609 }
 610
 611 const struct drm_crtc_helper_funcs mrst_helper_funcs = {
 612         .dpms = mrst_crtc_dpms,
 613         .mode_fixup = mrst_crtc_mode_fixup,
 614         .mode_set = mrst_crtc_mode_set,
 615         .mode_set_base = mrst_pipe_set_base,
 616         .prepare = mrst_crtc_prepare,
 617         .commit = mrst_crtc_commit,
 618 };
 619