2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
54 #include <net/ieee80211_radiotap.h>
56 #include <asm/unaligned.h>
62 static int ath5k_calinterval
= 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63 static int modparam_nohwcrypt
;
64 module_param_named(nohwcrypt
, modparam_nohwcrypt
, bool, S_IRUGO
);
65 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
67 static int modparam_all_channels
;
68 module_param_named(all_channels
, modparam_all_channels
, bool, S_IRUGO
);
69 MODULE_PARM_DESC(all_channels
, "Expose all channels the device can use.");
77 MODULE_AUTHOR("Jiri Slaby");
78 MODULE_AUTHOR("Nick Kossifidis");
79 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
80 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
81 MODULE_LICENSE("Dual BSD/GPL");
82 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
86 static const struct pci_device_id ath5k_pci_id_table
[] = {
87 { PCI_VDEVICE(ATHEROS
, 0x0207), .driver_data
= AR5K_AR5210
}, /* 5210 early */
88 { PCI_VDEVICE(ATHEROS
, 0x0007), .driver_data
= AR5K_AR5210
}, /* 5210 */
89 { PCI_VDEVICE(ATHEROS
, 0x0011), .driver_data
= AR5K_AR5211
}, /* 5311 - this is on AHB bus !*/
90 { PCI_VDEVICE(ATHEROS
, 0x0012), .driver_data
= AR5K_AR5211
}, /* 5211 */
91 { PCI_VDEVICE(ATHEROS
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 5212 */
92 { PCI_VDEVICE(3COM_2
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 3com 5212 */
93 { PCI_VDEVICE(3COM
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 3com 3CRDAG675 5212 */
94 { PCI_VDEVICE(ATHEROS
, 0x1014), .driver_data
= AR5K_AR5212
}, /* IBM minipci 5212 */
95 { PCI_VDEVICE(ATHEROS
, 0x0014), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS
, 0x0015), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS
, 0x0016), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS
, 0x0017), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS
, 0x0018), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS
, 0x0019), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS
, 0x001a), .driver_data
= AR5K_AR5212
}, /* 2413 Griffin-lite */
102 { PCI_VDEVICE(ATHEROS
, 0x001b), .driver_data
= AR5K_AR5212
}, /* 5413 Eagle */
103 { PCI_VDEVICE(ATHEROS
, 0x001c), .driver_data
= AR5K_AR5212
}, /* PCI-E cards */
104 { PCI_VDEVICE(ATHEROS
, 0x001d), .driver_data
= AR5K_AR5212
}, /* 2417 Nala */
107 MODULE_DEVICE_TABLE(pci
, ath5k_pci_id_table
);
110 static const struct ath5k_srev_name srev_names
[] = {
111 { "5210", AR5K_VERSION_MAC
, AR5K_SREV_AR5210
},
112 { "5311", AR5K_VERSION_MAC
, AR5K_SREV_AR5311
},
113 { "5311A", AR5K_VERSION_MAC
, AR5K_SREV_AR5311A
},
114 { "5311B", AR5K_VERSION_MAC
, AR5K_SREV_AR5311B
},
115 { "5211", AR5K_VERSION_MAC
, AR5K_SREV_AR5211
},
116 { "5212", AR5K_VERSION_MAC
, AR5K_SREV_AR5212
},
117 { "5213", AR5K_VERSION_MAC
, AR5K_SREV_AR5213
},
118 { "5213A", AR5K_VERSION_MAC
, AR5K_SREV_AR5213A
},
119 { "2413", AR5K_VERSION_MAC
, AR5K_SREV_AR2413
},
120 { "2414", AR5K_VERSION_MAC
, AR5K_SREV_AR2414
},
121 { "5424", AR5K_VERSION_MAC
, AR5K_SREV_AR5424
},
122 { "5413", AR5K_VERSION_MAC
, AR5K_SREV_AR5413
},
123 { "5414", AR5K_VERSION_MAC
, AR5K_SREV_AR5414
},
124 { "2415", AR5K_VERSION_MAC
, AR5K_SREV_AR2415
},
125 { "5416", AR5K_VERSION_MAC
, AR5K_SREV_AR5416
},
126 { "5418", AR5K_VERSION_MAC
, AR5K_SREV_AR5418
},
127 { "2425", AR5K_VERSION_MAC
, AR5K_SREV_AR2425
},
128 { "2417", AR5K_VERSION_MAC
, AR5K_SREV_AR2417
},
129 { "xxxxx", AR5K_VERSION_MAC
, AR5K_SREV_UNKNOWN
},
130 { "5110", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5110
},
131 { "5111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111
},
132 { "5111A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111A
},
133 { "2111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2111
},
134 { "5112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112
},
135 { "5112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112A
},
136 { "5112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112B
},
137 { "2112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112
},
138 { "2112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112A
},
139 { "2112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112B
},
140 { "2413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2413
},
141 { "5413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5413
},
142 { "2316", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2316
},
143 { "2317", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2317
},
144 { "5424", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5424
},
145 { "5133", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5133
},
146 { "xxxxx", AR5K_VERSION_RAD
, AR5K_SREV_UNKNOWN
},
149 static const struct ieee80211_rate ath5k_rates
[] = {
151 .hw_value
= ATH5K_RATE_CODE_1M
, },
153 .hw_value
= ATH5K_RATE_CODE_2M
,
154 .hw_value_short
= ATH5K_RATE_CODE_2M
| AR5K_SET_SHORT_PREAMBLE
,
155 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
157 .hw_value
= ATH5K_RATE_CODE_5_5M
,
158 .hw_value_short
= ATH5K_RATE_CODE_5_5M
| AR5K_SET_SHORT_PREAMBLE
,
159 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
161 .hw_value
= ATH5K_RATE_CODE_11M
,
162 .hw_value_short
= ATH5K_RATE_CODE_11M
| AR5K_SET_SHORT_PREAMBLE
,
163 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
165 .hw_value
= ATH5K_RATE_CODE_6M
,
168 .hw_value
= ATH5K_RATE_CODE_9M
,
171 .hw_value
= ATH5K_RATE_CODE_12M
,
174 .hw_value
= ATH5K_RATE_CODE_18M
,
177 .hw_value
= ATH5K_RATE_CODE_24M
,
180 .hw_value
= ATH5K_RATE_CODE_36M
,
183 .hw_value
= ATH5K_RATE_CODE_48M
,
186 .hw_value
= ATH5K_RATE_CODE_54M
,
192 * Prototypes - PCI stack related functions
194 static int __devinit
ath5k_pci_probe(struct pci_dev
*pdev
,
195 const struct pci_device_id
*id
);
196 static void __devexit
ath5k_pci_remove(struct pci_dev
*pdev
);
198 static int ath5k_pci_suspend(struct pci_dev
*pdev
,
200 static int ath5k_pci_resume(struct pci_dev
*pdev
);
202 #define ath5k_pci_suspend NULL
203 #define ath5k_pci_resume NULL
204 #endif /* CONFIG_PM */
206 static struct pci_driver ath5k_pci_driver
= {
207 .name
= KBUILD_MODNAME
,
208 .id_table
= ath5k_pci_id_table
,
209 .probe
= ath5k_pci_probe
,
210 .remove
= __devexit_p(ath5k_pci_remove
),
211 .suspend
= ath5k_pci_suspend
,
212 .resume
= ath5k_pci_resume
,
218 * Prototypes - MAC 802.11 stack related functions
220 static int ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
);
221 static int ath5k_reset(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
);
222 static int ath5k_reset_wake(struct ath5k_softc
*sc
);
223 static int ath5k_start(struct ieee80211_hw
*hw
);
224 static void ath5k_stop(struct ieee80211_hw
*hw
);
225 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
226 struct ieee80211_if_init_conf
*conf
);
227 static void ath5k_remove_interface(struct ieee80211_hw
*hw
,
228 struct ieee80211_if_init_conf
*conf
);
229 static int ath5k_config(struct ieee80211_hw
*hw
, u32 changed
);
230 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
231 unsigned int changed_flags
,
232 unsigned int *new_flags
,
233 int mc_count
, struct dev_mc_list
*mclist
);
234 static int ath5k_set_key(struct ieee80211_hw
*hw
,
235 enum set_key_cmd cmd
,
236 struct ieee80211_vif
*vif
, struct ieee80211_sta
*sta
,
237 struct ieee80211_key_conf
*key
);
238 static int ath5k_get_stats(struct ieee80211_hw
*hw
,
239 struct ieee80211_low_level_stats
*stats
);
240 static int ath5k_get_tx_stats(struct ieee80211_hw
*hw
,
241 struct ieee80211_tx_queue_stats
*stats
);
242 static u64
ath5k_get_tsf(struct ieee80211_hw
*hw
);
243 static void ath5k_set_tsf(struct ieee80211_hw
*hw
, u64 tsf
);
244 static void ath5k_reset_tsf(struct ieee80211_hw
*hw
);
245 static int ath5k_beacon_update(struct ieee80211_hw
*hw
,
246 struct ieee80211_vif
*vif
);
247 static void ath5k_bss_info_changed(struct ieee80211_hw
*hw
,
248 struct ieee80211_vif
*vif
,
249 struct ieee80211_bss_conf
*bss_conf
,
252 static const struct ieee80211_ops ath5k_hw_ops
= {
254 .start
= ath5k_start
,
256 .add_interface
= ath5k_add_interface
,
257 .remove_interface
= ath5k_remove_interface
,
258 .config
= ath5k_config
,
259 .configure_filter
= ath5k_configure_filter
,
260 .set_key
= ath5k_set_key
,
261 .get_stats
= ath5k_get_stats
,
263 .get_tx_stats
= ath5k_get_tx_stats
,
264 .get_tsf
= ath5k_get_tsf
,
265 .set_tsf
= ath5k_set_tsf
,
266 .reset_tsf
= ath5k_reset_tsf
,
267 .bss_info_changed
= ath5k_bss_info_changed
,
271 * Prototypes - Internal functions
274 static int ath5k_attach(struct pci_dev
*pdev
,
275 struct ieee80211_hw
*hw
);
276 static void ath5k_detach(struct pci_dev
*pdev
,
277 struct ieee80211_hw
*hw
);
278 /* Channel/mode setup */
279 static inline short ath5k_ieee2mhz(short chan
);
280 static unsigned int ath5k_copy_channels(struct ath5k_hw
*ah
,
281 struct ieee80211_channel
*channels
,
284 static int ath5k_setup_bands(struct ieee80211_hw
*hw
);
285 static int ath5k_chan_set(struct ath5k_softc
*sc
,
286 struct ieee80211_channel
*chan
);
287 static void ath5k_setcurmode(struct ath5k_softc
*sc
,
289 static void ath5k_mode_setup(struct ath5k_softc
*sc
);
291 /* Descriptor setup */
292 static int ath5k_desc_alloc(struct ath5k_softc
*sc
,
293 struct pci_dev
*pdev
);
294 static void ath5k_desc_free(struct ath5k_softc
*sc
,
295 struct pci_dev
*pdev
);
297 static int ath5k_rxbuf_setup(struct ath5k_softc
*sc
,
298 struct ath5k_buf
*bf
);
299 static int ath5k_txbuf_setup(struct ath5k_softc
*sc
,
300 struct ath5k_buf
*bf
);
301 static inline void ath5k_txbuf_free(struct ath5k_softc
*sc
,
302 struct ath5k_buf
*bf
)
307 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, bf
->skb
->len
,
309 dev_kfree_skb_any(bf
->skb
);
313 static inline void ath5k_rxbuf_free(struct ath5k_softc
*sc
,
314 struct ath5k_buf
*bf
)
319 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, sc
->rxbufsize
,
321 dev_kfree_skb_any(bf
->skb
);
327 static struct ath5k_txq
*ath5k_txq_setup(struct ath5k_softc
*sc
,
328 int qtype
, int subtype
);
329 static int ath5k_beaconq_setup(struct ath5k_hw
*ah
);
330 static int ath5k_beaconq_config(struct ath5k_softc
*sc
);
331 static void ath5k_txq_drainq(struct ath5k_softc
*sc
,
332 struct ath5k_txq
*txq
);
333 static void ath5k_txq_cleanup(struct ath5k_softc
*sc
);
334 static void ath5k_txq_release(struct ath5k_softc
*sc
);
336 static int ath5k_rx_start(struct ath5k_softc
*sc
);
337 static void ath5k_rx_stop(struct ath5k_softc
*sc
);
338 static unsigned int ath5k_rx_decrypted(struct ath5k_softc
*sc
,
339 struct ath5k_desc
*ds
,
341 struct ath5k_rx_status
*rs
);
342 static void ath5k_tasklet_rx(unsigned long data
);
344 static void ath5k_tx_processq(struct ath5k_softc
*sc
,
345 struct ath5k_txq
*txq
);
346 static void ath5k_tasklet_tx(unsigned long data
);
347 /* Beacon handling */
348 static int ath5k_beacon_setup(struct ath5k_softc
*sc
,
349 struct ath5k_buf
*bf
);
350 static void ath5k_beacon_send(struct ath5k_softc
*sc
);
351 static void ath5k_beacon_config(struct ath5k_softc
*sc
);
352 static void ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
);
353 static void ath5k_tasklet_beacon(unsigned long data
);
355 static inline u64
ath5k_extend_tsf(struct ath5k_hw
*ah
, u32 rstamp
)
357 u64 tsf
= ath5k_hw_get_tsf64(ah
);
359 if ((tsf
& 0x7fff) < rstamp
)
362 return (tsf
& ~0x7fff) | rstamp
;
365 /* Interrupt handling */
366 static int ath5k_init(struct ath5k_softc
*sc
);
367 static int ath5k_stop_locked(struct ath5k_softc
*sc
);
368 static int ath5k_stop_hw(struct ath5k_softc
*sc
);
369 static irqreturn_t
ath5k_intr(int irq
, void *dev_id
);
370 static void ath5k_tasklet_reset(unsigned long data
);
372 static void ath5k_calibrate(unsigned long data
);
375 * Module init/exit functions
384 ret
= pci_register_driver(&ath5k_pci_driver
);
386 printk(KERN_ERR
"ath5k_pci: can't register pci driver\n");
396 pci_unregister_driver(&ath5k_pci_driver
);
398 ath5k_debug_finish();
401 module_init(init_ath5k_pci
);
402 module_exit(exit_ath5k_pci
);
405 /********************\
406 * PCI Initialization *
407 \********************/
410 ath5k_chip_name(enum ath5k_srev_type type
, u_int16_t val
)
412 const char *name
= "xxxxx";
415 for (i
= 0; i
< ARRAY_SIZE(srev_names
); i
++) {
416 if (srev_names
[i
].sr_type
!= type
)
419 if ((val
& 0xf0) == srev_names
[i
].sr_val
)
420 name
= srev_names
[i
].sr_name
;
422 if ((val
& 0xff) == srev_names
[i
].sr_val
) {
423 name
= srev_names
[i
].sr_name
;
432 ath5k_pci_probe(struct pci_dev
*pdev
,
433 const struct pci_device_id
*id
)
436 struct ath5k_softc
*sc
;
437 struct ieee80211_hw
*hw
;
441 ret
= pci_enable_device(pdev
);
443 dev_err(&pdev
->dev
, "can't enable device\n");
447 /* XXX 32-bit addressing only */
448 ret
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
450 dev_err(&pdev
->dev
, "32-bit DMA not available\n");
455 * Cache line size is used to size and align various
456 * structures used to communicate with the hardware.
458 pci_read_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, &csz
);
461 * Linux 2.4.18 (at least) writes the cache line size
462 * register as a 16-bit wide register which is wrong.
463 * We must have this setup properly for rx buffer
464 * DMA to work so force a reasonable value here if it
467 csz
= L1_CACHE_BYTES
/ sizeof(u32
);
468 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, csz
);
471 * The default setting of latency timer yields poor results,
472 * set it to the value used by other systems. It may be worth
473 * tweaking this setting more.
475 pci_write_config_byte(pdev
, PCI_LATENCY_TIMER
, 0xa8);
477 /* Enable bus mastering */
478 pci_set_master(pdev
);
481 * Disable the RETRY_TIMEOUT register (0x41) to keep
482 * PCI Tx retries from interfering with C3 CPU state.
484 pci_write_config_byte(pdev
, 0x41, 0);
486 ret
= pci_request_region(pdev
, 0, "ath5k");
488 dev_err(&pdev
->dev
, "cannot reserve PCI memory region\n");
492 mem
= pci_iomap(pdev
, 0, 0);
494 dev_err(&pdev
->dev
, "cannot remap PCI memory region\n") ;
500 * Allocate hw (mac80211 main struct)
501 * and hw->priv (driver private data)
503 hw
= ieee80211_alloc_hw(sizeof(*sc
), &ath5k_hw_ops
);
505 dev_err(&pdev
->dev
, "cannot allocate ieee80211_hw\n");
510 dev_info(&pdev
->dev
, "registered as '%s'\n", wiphy_name(hw
->wiphy
));
512 /* Initialize driver private data */
513 SET_IEEE80211_DEV(hw
, &pdev
->dev
);
514 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
515 IEEE80211_HW_SIGNAL_DBM
|
516 IEEE80211_HW_NOISE_DBM
;
518 hw
->wiphy
->interface_modes
=
519 BIT(NL80211_IFTYPE_AP
) |
520 BIT(NL80211_IFTYPE_STATION
) |
521 BIT(NL80211_IFTYPE_ADHOC
) |
522 BIT(NL80211_IFTYPE_MESH_POINT
);
524 hw
->extra_tx_headroom
= 2;
525 hw
->channel_change_time
= 5000;
530 ath5k_debug_init_device(sc
);
533 * Mark the device as detached to avoid processing
534 * interrupts until setup is complete.
536 __set_bit(ATH_STAT_INVALID
, sc
->status
);
538 sc
->iobase
= mem
; /* So we can unmap it on detach */
539 sc
->cachelsz
= csz
* sizeof(u32
); /* convert to bytes */
540 sc
->opmode
= NL80211_IFTYPE_STATION
;
542 mutex_init(&sc
->lock
);
543 spin_lock_init(&sc
->rxbuflock
);
544 spin_lock_init(&sc
->txbuflock
);
545 spin_lock_init(&sc
->block
);
547 /* Set private data */
548 pci_set_drvdata(pdev
, hw
);
550 /* Setup interrupt handler */
551 ret
= request_irq(pdev
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", sc
);
553 ATH5K_ERR(sc
, "request_irq failed\n");
557 /* Initialize device */
558 sc
->ah
= ath5k_hw_attach(sc
, id
->driver_data
);
559 if (IS_ERR(sc
->ah
)) {
560 ret
= PTR_ERR(sc
->ah
);
564 /* set up multi-rate retry capabilities */
565 if (sc
->ah
->ah_version
== AR5K_AR5212
) {
567 hw
->max_rate_tries
= 11;
570 /* Finish private driver data initialization */
571 ret
= ath5k_attach(pdev
, hw
);
575 ATH5K_INFO(sc
, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
576 ath5k_chip_name(AR5K_VERSION_MAC
, sc
->ah
->ah_mac_srev
),
578 sc
->ah
->ah_phy_revision
);
580 if (!sc
->ah
->ah_single_chip
) {
581 /* Single chip radio (!RF5111) */
582 if (sc
->ah
->ah_radio_5ghz_revision
&&
583 !sc
->ah
->ah_radio_2ghz_revision
) {
584 /* No 5GHz support -> report 2GHz radio */
585 if (!test_bit(AR5K_MODE_11A
,
586 sc
->ah
->ah_capabilities
.cap_mode
)) {
587 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
588 ath5k_chip_name(AR5K_VERSION_RAD
,
589 sc
->ah
->ah_radio_5ghz_revision
),
590 sc
->ah
->ah_radio_5ghz_revision
);
591 /* No 2GHz support (5110 and some
592 * 5Ghz only cards) -> report 5Ghz radio */
593 } else if (!test_bit(AR5K_MODE_11B
,
594 sc
->ah
->ah_capabilities
.cap_mode
)) {
595 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
596 ath5k_chip_name(AR5K_VERSION_RAD
,
597 sc
->ah
->ah_radio_5ghz_revision
),
598 sc
->ah
->ah_radio_5ghz_revision
);
599 /* Multiband radio */
601 ATH5K_INFO(sc
, "RF%s multiband radio found"
603 ath5k_chip_name(AR5K_VERSION_RAD
,
604 sc
->ah
->ah_radio_5ghz_revision
),
605 sc
->ah
->ah_radio_5ghz_revision
);
608 /* Multi chip radio (RF5111 - RF2111) ->
609 * report both 2GHz/5GHz radios */
610 else if (sc
->ah
->ah_radio_5ghz_revision
&&
611 sc
->ah
->ah_radio_2ghz_revision
){
612 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
613 ath5k_chip_name(AR5K_VERSION_RAD
,
614 sc
->ah
->ah_radio_5ghz_revision
),
615 sc
->ah
->ah_radio_5ghz_revision
);
616 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
617 ath5k_chip_name(AR5K_VERSION_RAD
,
618 sc
->ah
->ah_radio_2ghz_revision
),
619 sc
->ah
->ah_radio_2ghz_revision
);
624 /* ready to process interrupts */
625 __clear_bit(ATH_STAT_INVALID
, sc
->status
);
629 ath5k_hw_detach(sc
->ah
);
631 free_irq(pdev
->irq
, sc
);
633 ieee80211_free_hw(hw
);
635 pci_iounmap(pdev
, mem
);
637 pci_release_region(pdev
, 0);
639 pci_disable_device(pdev
);
644 static void __devexit
645 ath5k_pci_remove(struct pci_dev
*pdev
)
647 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
648 struct ath5k_softc
*sc
= hw
->priv
;
650 ath5k_debug_finish_device(sc
);
651 ath5k_detach(pdev
, hw
);
652 ath5k_hw_detach(sc
->ah
);
653 free_irq(pdev
->irq
, sc
);
654 pci_iounmap(pdev
, sc
->iobase
);
655 pci_release_region(pdev
, 0);
656 pci_disable_device(pdev
);
657 ieee80211_free_hw(hw
);
662 ath5k_pci_suspend(struct pci_dev
*pdev
, pm_message_t state
)
664 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
665 struct ath5k_softc
*sc
= hw
->priv
;
669 free_irq(pdev
->irq
, sc
);
670 pci_save_state(pdev
);
671 pci_disable_device(pdev
);
672 pci_set_power_state(pdev
, PCI_D3hot
);
678 ath5k_pci_resume(struct pci_dev
*pdev
)
680 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
681 struct ath5k_softc
*sc
= hw
->priv
;
684 pci_restore_state(pdev
);
686 err
= pci_enable_device(pdev
);
691 * Suspend/Resume resets the PCI configuration space, so we have to
692 * re-disable the RETRY_TIMEOUT register (0x41) to keep
693 * PCI Tx retries from interfering with C3 CPU state
695 pci_write_config_byte(pdev
, 0x41, 0);
697 err
= request_irq(pdev
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", sc
);
699 ATH5K_ERR(sc
, "request_irq failed\n");
703 ath5k_led_enable(sc
);
707 pci_disable_device(pdev
);
710 #endif /* CONFIG_PM */
713 /***********************\
714 * Driver Initialization *
715 \***********************/
717 static int ath5k_reg_notifier(struct wiphy
*wiphy
, struct regulatory_request
*request
)
719 struct ieee80211_hw
*hw
= wiphy_to_ieee80211_hw(wiphy
);
720 struct ath5k_softc
*sc
= hw
->priv
;
721 struct ath_regulatory
*reg
= &sc
->ah
->ah_regulatory
;
723 return ath_reg_notifier_apply(wiphy
, request
, reg
);
727 ath5k_attach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
729 struct ath5k_softc
*sc
= hw
->priv
;
730 struct ath5k_hw
*ah
= sc
->ah
;
731 u8 mac
[ETH_ALEN
] = {};
734 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "devid 0x%x\n", pdev
->device
);
737 * Check if the MAC has multi-rate retry support.
738 * We do this by trying to setup a fake extended
739 * descriptor. MAC's that don't have support will
740 * return false w/o doing anything. MAC's that do
741 * support it will return true w/o doing anything.
743 ret
= ah
->ah_setup_mrr_tx_desc(ah
, NULL
, 0, 0, 0, 0, 0, 0);
747 __set_bit(ATH_STAT_MRRETRY
, sc
->status
);
750 * Collect the channel list. The 802.11 layer
751 * is resposible for filtering this list based
752 * on settings like the phy mode and regulatory
753 * domain restrictions.
755 ret
= ath5k_setup_bands(hw
);
757 ATH5K_ERR(sc
, "can't get channels\n");
761 /* NB: setup here so ath5k_rate_update is happy */
762 if (test_bit(AR5K_MODE_11A
, ah
->ah_modes
))
763 ath5k_setcurmode(sc
, AR5K_MODE_11A
);
765 ath5k_setcurmode(sc
, AR5K_MODE_11B
);
768 * Allocate tx+rx descriptors and populate the lists.
770 ret
= ath5k_desc_alloc(sc
, pdev
);
772 ATH5K_ERR(sc
, "can't allocate descriptors\n");
777 * Allocate hardware transmit queues: one queue for
778 * beacon frames and one data queue for each QoS
779 * priority. Note that hw functions handle reseting
780 * these queues at the needed time.
782 ret
= ath5k_beaconq_setup(ah
);
784 ATH5K_ERR(sc
, "can't setup a beacon xmit queue\n");
789 sc
->txq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BK
);
790 if (IS_ERR(sc
->txq
)) {
791 ATH5K_ERR(sc
, "can't setup xmit queue\n");
792 ret
= PTR_ERR(sc
->txq
);
796 tasklet_init(&sc
->rxtq
, ath5k_tasklet_rx
, (unsigned long)sc
);
797 tasklet_init(&sc
->txtq
, ath5k_tasklet_tx
, (unsigned long)sc
);
798 tasklet_init(&sc
->restq
, ath5k_tasklet_reset
, (unsigned long)sc
);
799 tasklet_init(&sc
->beacontq
, ath5k_tasklet_beacon
, (unsigned long)sc
);
800 setup_timer(&sc
->calib_tim
, ath5k_calibrate
, (unsigned long)sc
);
802 ret
= ath5k_eeprom_read_mac(ah
, mac
);
804 ATH5K_ERR(sc
, "unable to read address from EEPROM: 0x%04x\n",
809 SET_IEEE80211_PERM_ADDR(hw
, mac
);
810 /* All MAC address bits matter for ACKs */
811 memset(sc
->bssidmask
, 0xff, ETH_ALEN
);
812 ath5k_hw_set_bssid_mask(sc
->ah
, sc
->bssidmask
);
814 ah
->ah_regulatory
.current_rd
=
815 ah
->ah_capabilities
.cap_eeprom
.ee_regdomain
;
816 ret
= ath_regd_init(&ah
->ah_regulatory
, hw
->wiphy
, ath5k_reg_notifier
);
818 ATH5K_ERR(sc
, "can't initialize regulatory system\n");
822 ret
= ieee80211_register_hw(hw
);
824 ATH5K_ERR(sc
, "can't register ieee80211 hw\n");
828 if (!ath_is_world_regd(&sc
->ah
->ah_regulatory
))
829 regulatory_hint(hw
->wiphy
, sc
->ah
->ah_regulatory
.alpha2
);
835 ath5k_txq_release(sc
);
837 ath5k_hw_release_tx_queue(ah
, sc
->bhalq
);
839 ath5k_desc_free(sc
, pdev
);
845 ath5k_detach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
847 struct ath5k_softc
*sc
= hw
->priv
;
850 * NB: the order of these is important:
851 * o call the 802.11 layer before detaching ath5k_hw to
852 * insure callbacks into the driver to delete global
853 * key cache entries can be handled
854 * o reclaim the tx queue data structures after calling
855 * the 802.11 layer as we'll get called back to reclaim
856 * node state and potentially want to use them
857 * o to cleanup the tx queues the hal is called, so detach
859 * XXX: ??? detach ath5k_hw ???
860 * Other than that, it's straightforward...
862 ieee80211_unregister_hw(hw
);
863 ath5k_desc_free(sc
, pdev
);
864 ath5k_txq_release(sc
);
865 ath5k_hw_release_tx_queue(sc
->ah
, sc
->bhalq
);
866 ath5k_unregister_leds(sc
);
869 * NB: can't reclaim these until after ieee80211_ifdetach
870 * returns because we'll get called back to reclaim node
871 * state and potentially want to use them.
878 /********************\
879 * Channel/mode setup *
880 \********************/
883 * Convert IEEE channel number to MHz frequency.
886 ath5k_ieee2mhz(short chan
)
888 if (chan
<= 14 || chan
>= 27)
889 return ieee80211chan2mhz(chan
);
891 return 2212 + chan
* 20;
895 * Returns true for the channel numbers used without all_channels modparam.
897 static bool ath5k_is_standard_channel(short chan
)
899 return ((chan
<= 14) ||
901 ((chan
& 3) == 0 && chan
>= 36 && chan
<= 64) ||
903 ((chan
& 3) == 0 && chan
>= 100 && chan
<= 140) ||
905 ((chan
& 3) == 1 && chan
>= 149 && chan
<= 165));
909 ath5k_copy_channels(struct ath5k_hw
*ah
,
910 struct ieee80211_channel
*channels
,
914 unsigned int i
, count
, size
, chfreq
, freq
, ch
;
916 if (!test_bit(mode
, ah
->ah_modes
))
921 case AR5K_MODE_11A_TURBO
:
922 /* 1..220, but 2GHz frequencies are filtered by check_channel */
924 chfreq
= CHANNEL_5GHZ
;
928 case AR5K_MODE_11G_TURBO
:
930 chfreq
= CHANNEL_2GHZ
;
933 ATH5K_WARN(ah
->ah_sc
, "bad mode, not copying channels\n");
937 for (i
= 0, count
= 0; i
< size
&& max
> 0; i
++) {
939 freq
= ath5k_ieee2mhz(ch
);
941 /* Check if channel is supported by the chipset */
942 if (!ath5k_channel_ok(ah
, freq
, chfreq
))
945 if (!modparam_all_channels
&& !ath5k_is_standard_channel(ch
))
948 /* Write channel info and increment counter */
949 channels
[count
].center_freq
= freq
;
950 channels
[count
].band
= (chfreq
== CHANNEL_2GHZ
) ?
951 IEEE80211_BAND_2GHZ
: IEEE80211_BAND_5GHZ
;
955 channels
[count
].hw_value
= chfreq
| CHANNEL_OFDM
;
957 case AR5K_MODE_11A_TURBO
:
958 case AR5K_MODE_11G_TURBO
:
959 channels
[count
].hw_value
= chfreq
|
960 CHANNEL_OFDM
| CHANNEL_TURBO
;
963 channels
[count
].hw_value
= CHANNEL_B
;
974 ath5k_setup_rate_idx(struct ath5k_softc
*sc
, struct ieee80211_supported_band
*b
)
978 for (i
= 0; i
< AR5K_MAX_RATES
; i
++)
979 sc
->rate_idx
[b
->band
][i
] = -1;
981 for (i
= 0; i
< b
->n_bitrates
; i
++) {
982 sc
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value
] = i
;
983 if (b
->bitrates
[i
].hw_value_short
)
984 sc
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value_short
] = i
;
989 ath5k_setup_bands(struct ieee80211_hw
*hw
)
991 struct ath5k_softc
*sc
= hw
->priv
;
992 struct ath5k_hw
*ah
= sc
->ah
;
993 struct ieee80211_supported_band
*sband
;
994 int max_c
, count_c
= 0;
997 BUILD_BUG_ON(ARRAY_SIZE(sc
->sbands
) < IEEE80211_NUM_BANDS
);
998 max_c
= ARRAY_SIZE(sc
->channels
);
1001 sband
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
1002 sband
->band
= IEEE80211_BAND_2GHZ
;
1003 sband
->bitrates
= &sc
->rates
[IEEE80211_BAND_2GHZ
][0];
1005 if (test_bit(AR5K_MODE_11G
, sc
->ah
->ah_capabilities
.cap_mode
)) {
1007 memcpy(sband
->bitrates
, &ath5k_rates
[0],
1008 sizeof(struct ieee80211_rate
) * 12);
1009 sband
->n_bitrates
= 12;
1011 sband
->channels
= sc
->channels
;
1012 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
1013 AR5K_MODE_11G
, max_c
);
1015 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
1016 count_c
= sband
->n_channels
;
1018 } else if (test_bit(AR5K_MODE_11B
, sc
->ah
->ah_capabilities
.cap_mode
)) {
1020 memcpy(sband
->bitrates
, &ath5k_rates
[0],
1021 sizeof(struct ieee80211_rate
) * 4);
1022 sband
->n_bitrates
= 4;
1024 /* 5211 only supports B rates and uses 4bit rate codes
1025 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1028 if (ah
->ah_version
== AR5K_AR5211
) {
1029 for (i
= 0; i
< 4; i
++) {
1030 sband
->bitrates
[i
].hw_value
=
1031 sband
->bitrates
[i
].hw_value
& 0xF;
1032 sband
->bitrates
[i
].hw_value_short
=
1033 sband
->bitrates
[i
].hw_value_short
& 0xF;
1037 sband
->channels
= sc
->channels
;
1038 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
1039 AR5K_MODE_11B
, max_c
);
1041 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
1042 count_c
= sband
->n_channels
;
1045 ath5k_setup_rate_idx(sc
, sband
);
1047 /* 5GHz band, A mode */
1048 if (test_bit(AR5K_MODE_11A
, sc
->ah
->ah_capabilities
.cap_mode
)) {
1049 sband
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
1050 sband
->band
= IEEE80211_BAND_5GHZ
;
1051 sband
->bitrates
= &sc
->rates
[IEEE80211_BAND_5GHZ
][0];
1053 memcpy(sband
->bitrates
, &ath5k_rates
[4],
1054 sizeof(struct ieee80211_rate
) * 8);
1055 sband
->n_bitrates
= 8;
1057 sband
->channels
= &sc
->channels
[count_c
];
1058 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
1059 AR5K_MODE_11A
, max_c
);
1061 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = sband
;
1063 ath5k_setup_rate_idx(sc
, sband
);
1065 ath5k_debug_dump_bands(sc
);
1071 * Set/change channels. If the channel is really being changed,
1072 * it's done by reseting the chip. To accomplish this we must
1073 * first cleanup any pending DMA, then restart stuff after a la
1076 * Called with sc->lock.
1079 ath5k_chan_set(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
)
1081 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "(%u MHz) -> (%u MHz)\n",
1082 sc
->curchan
->center_freq
, chan
->center_freq
);
1084 if (chan
->center_freq
!= sc
->curchan
->center_freq
||
1085 chan
->hw_value
!= sc
->curchan
->hw_value
) {
1088 * To switch channels clear any pending DMA operations;
1089 * wait long enough for the RX fifo to drain, reset the
1090 * hardware at the new frequency, and then re-enable
1091 * the relevant bits of the h/w.
1093 return ath5k_reset(sc
, chan
);
1100 ath5k_setcurmode(struct ath5k_softc
*sc
, unsigned int mode
)
1104 if (mode
== AR5K_MODE_11A
) {
1105 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
1107 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
1112 ath5k_mode_setup(struct ath5k_softc
*sc
)
1114 struct ath5k_hw
*ah
= sc
->ah
;
1117 /* configure rx filter */
1118 rfilt
= sc
->filter_flags
;
1119 ath5k_hw_set_rx_filter(ah
, rfilt
);
1121 if (ath5k_hw_hasbssidmask(ah
))
1122 ath5k_hw_set_bssid_mask(ah
, sc
->bssidmask
);
1124 /* configure operational mode */
1125 ath5k_hw_set_opmode(ah
);
1127 ath5k_hw_set_mcast_filter(ah
, 0, 0);
1128 ATH5K_DBG(sc
, ATH5K_DEBUG_MODE
, "RX filter 0x%x\n", rfilt
);
1132 ath5k_hw_to_driver_rix(struct ath5k_softc
*sc
, int hw_rix
)
1136 /* return base rate on errors */
1137 if (WARN(hw_rix
< 0 || hw_rix
>= AR5K_MAX_RATES
,
1138 "hw_rix out of bounds: %x\n", hw_rix
))
1141 rix
= sc
->rate_idx
[sc
->curband
->band
][hw_rix
];
1142 if (WARN(rix
< 0, "invalid hw_rix: %x\n", hw_rix
))
1153 struct sk_buff
*ath5k_rx_skb_alloc(struct ath5k_softc
*sc
, dma_addr_t
*skb_addr
)
1155 struct sk_buff
*skb
;
1159 * Allocate buffer with headroom_needed space for the
1160 * fake physical layer header at the start.
1162 skb
= dev_alloc_skb(sc
->rxbufsize
+ sc
->cachelsz
- 1);
1165 ATH5K_ERR(sc
, "can't alloc skbuff of size %u\n",
1166 sc
->rxbufsize
+ sc
->cachelsz
- 1);
1170 * Cache-line-align. This is important (for the
1171 * 5210 at least) as not doing so causes bogus data
1174 off
= ((unsigned long)skb
->data
) % sc
->cachelsz
;
1176 skb_reserve(skb
, sc
->cachelsz
- off
);
1178 *skb_addr
= pci_map_single(sc
->pdev
,
1179 skb
->data
, sc
->rxbufsize
, PCI_DMA_FROMDEVICE
);
1180 if (unlikely(pci_dma_mapping_error(sc
->pdev
, *skb_addr
))) {
1181 ATH5K_ERR(sc
, "%s: DMA mapping failed\n", __func__
);
1189 ath5k_rxbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1191 struct ath5k_hw
*ah
= sc
->ah
;
1192 struct sk_buff
*skb
= bf
->skb
;
1193 struct ath5k_desc
*ds
;
1196 skb
= ath5k_rx_skb_alloc(sc
, &bf
->skbaddr
);
1203 * Setup descriptors. For receive we always terminate
1204 * the descriptor list with a self-linked entry so we'll
1205 * not get overrun under high load (as can happen with a
1206 * 5212 when ANI processing enables PHY error frames).
1208 * To insure the last descriptor is self-linked we create
1209 * each descriptor as self-linked and add it to the end. As
1210 * each additional descriptor is added the previous self-linked
1211 * entry is ``fixed'' naturally. This should be safe even
1212 * if DMA is happening. When processing RX interrupts we
1213 * never remove/process the last, self-linked, entry on the
1214 * descriptor list. This insures the hardware always has
1215 * someplace to write a new frame.
1218 ds
->ds_link
= bf
->daddr
; /* link to self */
1219 ds
->ds_data
= bf
->skbaddr
;
1220 ah
->ah_setup_rx_desc(ah
, ds
,
1221 skb_tailroom(skb
), /* buffer size */
1224 if (sc
->rxlink
!= NULL
)
1225 *sc
->rxlink
= bf
->daddr
;
1226 sc
->rxlink
= &ds
->ds_link
;
1231 ath5k_txbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1233 struct ath5k_hw
*ah
= sc
->ah
;
1234 struct ath5k_txq
*txq
= sc
->txq
;
1235 struct ath5k_desc
*ds
= bf
->desc
;
1236 struct sk_buff
*skb
= bf
->skb
;
1237 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1238 unsigned int pktlen
, flags
, keyidx
= AR5K_TXKEYIX_INVALID
;
1239 struct ieee80211_rate
*rate
;
1240 unsigned int mrr_rate
[3], mrr_tries
[3];
1247 flags
= AR5K_TXDESC_INTREQ
| AR5K_TXDESC_CLRDMASK
;
1249 /* XXX endianness */
1250 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
1253 rate
= ieee80211_get_tx_rate(sc
->hw
, info
);
1255 if (info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
1256 flags
|= AR5K_TXDESC_NOACK
;
1258 rc_flags
= info
->control
.rates
[0].flags
;
1259 hw_rate
= (rc_flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
) ?
1260 rate
->hw_value_short
: rate
->hw_value
;
1264 /* FIXME: If we are in g mode and rate is a CCK rate
1265 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1266 * from tx power (value is in dB units already) */
1267 if (info
->control
.hw_key
) {
1268 keyidx
= info
->control
.hw_key
->hw_key_idx
;
1269 pktlen
+= info
->control
.hw_key
->icv_len
;
1271 if (rc_flags
& IEEE80211_TX_RC_USE_RTS_CTS
) {
1272 flags
|= AR5K_TXDESC_RTSENA
;
1273 cts_rate
= ieee80211_get_rts_cts_rate(sc
->hw
, info
)->hw_value
;
1274 duration
= le16_to_cpu(ieee80211_rts_duration(sc
->hw
,
1275 sc
->vif
, pktlen
, info
));
1277 if (rc_flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
) {
1278 flags
|= AR5K_TXDESC_CTSENA
;
1279 cts_rate
= ieee80211_get_rts_cts_rate(sc
->hw
, info
)->hw_value
;
1280 duration
= le16_to_cpu(ieee80211_ctstoself_duration(sc
->hw
,
1281 sc
->vif
, pktlen
, info
));
1283 ret
= ah
->ah_setup_tx_desc(ah
, ds
, pktlen
,
1284 ieee80211_get_hdrlen_from_skb(skb
), AR5K_PKT_TYPE_NORMAL
,
1285 (sc
->power_level
* 2),
1287 info
->control
.rates
[0].count
, keyidx
, ah
->ah_tx_ant
, flags
,
1288 cts_rate
, duration
);
1292 memset(mrr_rate
, 0, sizeof(mrr_rate
));
1293 memset(mrr_tries
, 0, sizeof(mrr_tries
));
1294 for (i
= 0; i
< 3; i
++) {
1295 rate
= ieee80211_get_alt_retry_rate(sc
->hw
, info
, i
);
1299 mrr_rate
[i
] = rate
->hw_value
;
1300 mrr_tries
[i
] = info
->control
.rates
[i
+ 1].count
;
1303 ah
->ah_setup_mrr_tx_desc(ah
, ds
,
1304 mrr_rate
[0], mrr_tries
[0],
1305 mrr_rate
[1], mrr_tries
[1],
1306 mrr_rate
[2], mrr_tries
[2]);
1309 ds
->ds_data
= bf
->skbaddr
;
1311 spin_lock_bh(&txq
->lock
);
1312 list_add_tail(&bf
->list
, &txq
->q
);
1313 sc
->tx_stats
[txq
->qnum
].len
++;
1314 if (txq
->link
== NULL
) /* is this first packet? */
1315 ath5k_hw_set_txdp(ah
, txq
->qnum
, bf
->daddr
);
1316 else /* no, so only link it */
1317 *txq
->link
= bf
->daddr
;
1319 txq
->link
= &ds
->ds_link
;
1320 ath5k_hw_start_tx_dma(ah
, txq
->qnum
);
1322 spin_unlock_bh(&txq
->lock
);
1326 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
1330 /*******************\
1331 * Descriptors setup *
1332 \*******************/
1335 ath5k_desc_alloc(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
1337 struct ath5k_desc
*ds
;
1338 struct ath5k_buf
*bf
;
1343 /* allocate descriptors */
1344 sc
->desc_len
= sizeof(struct ath5k_desc
) *
1345 (ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
+ 1);
1346 sc
->desc
= pci_alloc_consistent(pdev
, sc
->desc_len
, &sc
->desc_daddr
);
1347 if (sc
->desc
== NULL
) {
1348 ATH5K_ERR(sc
, "can't allocate descriptors\n");
1353 da
= sc
->desc_daddr
;
1354 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "DMA map: %p (%zu) -> %llx\n",
1355 ds
, sc
->desc_len
, (unsigned long long)sc
->desc_daddr
);
1357 bf
= kcalloc(1 + ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
,
1358 sizeof(struct ath5k_buf
), GFP_KERNEL
);
1360 ATH5K_ERR(sc
, "can't allocate bufptr\n");
1366 INIT_LIST_HEAD(&sc
->rxbuf
);
1367 for (i
= 0; i
< ATH_RXBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
1370 list_add_tail(&bf
->list
, &sc
->rxbuf
);
1373 INIT_LIST_HEAD(&sc
->txbuf
);
1374 sc
->txbuf_len
= ATH_TXBUF
;
1375 for (i
= 0; i
< ATH_TXBUF
; i
++, bf
++, ds
++,
1376 da
+= sizeof(*ds
)) {
1379 list_add_tail(&bf
->list
, &sc
->txbuf
);
1389 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
1396 ath5k_desc_free(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
1398 struct ath5k_buf
*bf
;
1400 ath5k_txbuf_free(sc
, sc
->bbuf
);
1401 list_for_each_entry(bf
, &sc
->txbuf
, list
)
1402 ath5k_txbuf_free(sc
, bf
);
1403 list_for_each_entry(bf
, &sc
->rxbuf
, list
)
1404 ath5k_rxbuf_free(sc
, bf
);
1406 /* Free memory associated with all descriptors */
1407 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
1421 static struct ath5k_txq
*
1422 ath5k_txq_setup(struct ath5k_softc
*sc
,
1423 int qtype
, int subtype
)
1425 struct ath5k_hw
*ah
= sc
->ah
;
1426 struct ath5k_txq
*txq
;
1427 struct ath5k_txq_info qi
= {
1428 .tqi_subtype
= subtype
,
1429 .tqi_aifs
= AR5K_TXQ_USEDEFAULT
,
1430 .tqi_cw_min
= AR5K_TXQ_USEDEFAULT
,
1431 .tqi_cw_max
= AR5K_TXQ_USEDEFAULT
1436 * Enable interrupts only for EOL and DESC conditions.
1437 * We mark tx descriptors to receive a DESC interrupt
1438 * when a tx queue gets deep; otherwise waiting for the
1439 * EOL to reap descriptors. Note that this is done to
1440 * reduce interrupt load and this only defers reaping
1441 * descriptors, never transmitting frames. Aside from
1442 * reducing interrupts this also permits more concurrency.
1443 * The only potential downside is if the tx queue backs
1444 * up in which case the top half of the kernel may backup
1445 * due to a lack of tx descriptors.
1447 qi
.tqi_flags
= AR5K_TXQ_FLAG_TXEOLINT_ENABLE
|
1448 AR5K_TXQ_FLAG_TXDESCINT_ENABLE
;
1449 qnum
= ath5k_hw_setup_tx_queue(ah
, qtype
, &qi
);
1452 * NB: don't print a message, this happens
1453 * normally on parts with too few tx queues
1455 return ERR_PTR(qnum
);
1457 if (qnum
>= ARRAY_SIZE(sc
->txqs
)) {
1458 ATH5K_ERR(sc
, "hw qnum %u out of range, max %tu!\n",
1459 qnum
, ARRAY_SIZE(sc
->txqs
));
1460 ath5k_hw_release_tx_queue(ah
, qnum
);
1461 return ERR_PTR(-EINVAL
);
1463 txq
= &sc
->txqs
[qnum
];
1467 INIT_LIST_HEAD(&txq
->q
);
1468 spin_lock_init(&txq
->lock
);
1471 return &sc
->txqs
[qnum
];
1475 ath5k_beaconq_setup(struct ath5k_hw
*ah
)
1477 struct ath5k_txq_info qi
= {
1478 .tqi_aifs
= AR5K_TXQ_USEDEFAULT
,
1479 .tqi_cw_min
= AR5K_TXQ_USEDEFAULT
,
1480 .tqi_cw_max
= AR5K_TXQ_USEDEFAULT
,
1481 /* NB: for dynamic turbo, don't enable any other interrupts */
1482 .tqi_flags
= AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1485 return ath5k_hw_setup_tx_queue(ah
, AR5K_TX_QUEUE_BEACON
, &qi
);
1489 ath5k_beaconq_config(struct ath5k_softc
*sc
)
1491 struct ath5k_hw
*ah
= sc
->ah
;
1492 struct ath5k_txq_info qi
;
1495 ret
= ath5k_hw_get_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1498 if (sc
->opmode
== NL80211_IFTYPE_AP
||
1499 sc
->opmode
== NL80211_IFTYPE_MESH_POINT
) {
1501 * Always burst out beacon and CAB traffic
1502 * (aifs = cwmin = cwmax = 0)
1507 } else if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
1509 * Adhoc mode; backoff between 0 and (2 * cw_min).
1513 qi
.tqi_cw_max
= 2 * ah
->ah_cw_min
;
1516 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1517 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1518 qi
.tqi_aifs
, qi
.tqi_cw_min
, qi
.tqi_cw_max
);
1520 ret
= ath5k_hw_set_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1522 ATH5K_ERR(sc
, "%s: unable to update parameters for beacon "
1523 "hardware queue!\n", __func__
);
1527 return ath5k_hw_reset_tx_queue(ah
, sc
->bhalq
); /* push to h/w */;
1531 ath5k_txq_drainq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1533 struct ath5k_buf
*bf
, *bf0
;
1536 * NB: this assumes output has been stopped and
1537 * we do not need to block ath5k_tx_tasklet
1539 spin_lock_bh(&txq
->lock
);
1540 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1541 ath5k_debug_printtxbuf(sc
, bf
);
1543 ath5k_txbuf_free(sc
, bf
);
1545 spin_lock_bh(&sc
->txbuflock
);
1546 sc
->tx_stats
[txq
->qnum
].len
--;
1547 list_move_tail(&bf
->list
, &sc
->txbuf
);
1549 spin_unlock_bh(&sc
->txbuflock
);
1552 spin_unlock_bh(&txq
->lock
);
1556 * Drain the transmit queues and reclaim resources.
1559 ath5k_txq_cleanup(struct ath5k_softc
*sc
)
1561 struct ath5k_hw
*ah
= sc
->ah
;
1564 /* XXX return value */
1565 if (likely(!test_bit(ATH_STAT_INVALID
, sc
->status
))) {
1566 /* don't touch the hardware if marked invalid */
1567 ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
);
1568 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "beacon queue %x\n",
1569 ath5k_hw_get_txdp(ah
, sc
->bhalq
));
1570 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1571 if (sc
->txqs
[i
].setup
) {
1572 ath5k_hw_stop_tx_dma(ah
, sc
->txqs
[i
].qnum
);
1573 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "txq [%u] %x, "
1576 ath5k_hw_get_txdp(ah
,
1581 ieee80211_wake_queues(sc
->hw
); /* XXX move to callers */
1583 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1584 if (sc
->txqs
[i
].setup
)
1585 ath5k_txq_drainq(sc
, &sc
->txqs
[i
]);
1589 ath5k_txq_release(struct ath5k_softc
*sc
)
1591 struct ath5k_txq
*txq
= sc
->txqs
;
1594 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++, txq
++)
1596 ath5k_hw_release_tx_queue(sc
->ah
, txq
->qnum
);
1609 * Enable the receive h/w following a reset.
1612 ath5k_rx_start(struct ath5k_softc
*sc
)
1614 struct ath5k_hw
*ah
= sc
->ah
;
1615 struct ath5k_buf
*bf
;
1618 sc
->rxbufsize
= roundup(IEEE80211_MAX_LEN
, sc
->cachelsz
);
1620 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "cachelsz %u rxbufsize %u\n",
1621 sc
->cachelsz
, sc
->rxbufsize
);
1623 spin_lock_bh(&sc
->rxbuflock
);
1625 list_for_each_entry(bf
, &sc
->rxbuf
, list
) {
1626 ret
= ath5k_rxbuf_setup(sc
, bf
);
1628 spin_unlock_bh(&sc
->rxbuflock
);
1632 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1633 ath5k_hw_set_rxdp(ah
, bf
->daddr
);
1634 spin_unlock_bh(&sc
->rxbuflock
);
1636 ath5k_hw_start_rx_dma(ah
); /* enable recv descriptors */
1637 ath5k_mode_setup(sc
); /* set filters, etc. */
1638 ath5k_hw_start_rx_pcu(ah
); /* re-enable PCU/DMA engine */
1646 * Disable the receive h/w in preparation for a reset.
1649 ath5k_rx_stop(struct ath5k_softc
*sc
)
1651 struct ath5k_hw
*ah
= sc
->ah
;
1653 ath5k_hw_stop_rx_pcu(ah
); /* disable PCU */
1654 ath5k_hw_set_rx_filter(ah
, 0); /* clear recv filter */
1655 ath5k_hw_stop_rx_dma(ah
); /* disable DMA engine */
1657 ath5k_debug_printrxbuffs(sc
, ah
);
1659 sc
->rxlink
= NULL
; /* just in case */
1663 ath5k_rx_decrypted(struct ath5k_softc
*sc
, struct ath5k_desc
*ds
,
1664 struct sk_buff
*skb
, struct ath5k_rx_status
*rs
)
1666 struct ieee80211_hdr
*hdr
= (void *)skb
->data
;
1667 unsigned int keyix
, hlen
;
1669 if (!(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1670 rs
->rs_keyix
!= AR5K_RXKEYIX_INVALID
)
1671 return RX_FLAG_DECRYPTED
;
1673 /* Apparently when a default key is used to decrypt the packet
1674 the hw does not set the index used to decrypt. In such cases
1675 get the index from the packet. */
1676 hlen
= ieee80211_hdrlen(hdr
->frame_control
);
1677 if (ieee80211_has_protected(hdr
->frame_control
) &&
1678 !(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1679 skb
->len
>= hlen
+ 4) {
1680 keyix
= skb
->data
[hlen
+ 3] >> 6;
1682 if (test_bit(keyix
, sc
->keymap
))
1683 return RX_FLAG_DECRYPTED
;
1691 ath5k_check_ibss_tsf(struct ath5k_softc
*sc
, struct sk_buff
*skb
,
1692 struct ieee80211_rx_status
*rxs
)
1696 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1698 if (ieee80211_is_beacon(mgmt
->frame_control
) &&
1699 le16_to_cpu(mgmt
->u
.beacon
.capab_info
) & WLAN_CAPABILITY_IBSS
&&
1700 memcmp(mgmt
->bssid
, sc
->ah
->ah_bssid
, ETH_ALEN
) == 0) {
1702 * Received an IBSS beacon with the same BSSID. Hardware *must*
1703 * have updated the local TSF. We have to work around various
1704 * hardware bugs, though...
1706 tsf
= ath5k_hw_get_tsf64(sc
->ah
);
1707 bc_tstamp
= le64_to_cpu(mgmt
->u
.beacon
.timestamp
);
1708 hw_tu
= TSF_TO_TU(tsf
);
1710 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1711 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1712 (unsigned long long)bc_tstamp
,
1713 (unsigned long long)rxs
->mactime
,
1714 (unsigned long long)(rxs
->mactime
- bc_tstamp
),
1715 (unsigned long long)tsf
);
1718 * Sometimes the HW will give us a wrong tstamp in the rx
1719 * status, causing the timestamp extension to go wrong.
1720 * (This seems to happen especially with beacon frames bigger
1721 * than 78 byte (incl. FCS))
1722 * But we know that the receive timestamp must be later than the
1723 * timestamp of the beacon since HW must have synced to that.
1725 * NOTE: here we assume mactime to be after the frame was
1726 * received, not like mac80211 which defines it at the start.
1728 if (bc_tstamp
> rxs
->mactime
) {
1729 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1730 "fixing mactime from %llx to %llx\n",
1731 (unsigned long long)rxs
->mactime
,
1732 (unsigned long long)tsf
);
1737 * Local TSF might have moved higher than our beacon timers,
1738 * in that case we have to update them to continue sending
1739 * beacons. This also takes care of synchronizing beacon sending
1740 * times with other stations.
1742 if (hw_tu
>= sc
->nexttbtt
)
1743 ath5k_beacon_update_timers(sc
, bc_tstamp
);
1748 ath5k_tasklet_rx(unsigned long data
)
1750 struct ieee80211_rx_status rxs
= {};
1751 struct ath5k_rx_status rs
= {};
1752 struct sk_buff
*skb
, *next_skb
;
1753 dma_addr_t next_skb_addr
;
1754 struct ath5k_softc
*sc
= (void *)data
;
1755 struct ath5k_buf
*bf
;
1756 struct ath5k_desc
*ds
;
1761 spin_lock(&sc
->rxbuflock
);
1762 if (list_empty(&sc
->rxbuf
)) {
1763 ATH5K_WARN(sc
, "empty rx buf pool\n");
1769 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1770 BUG_ON(bf
->skb
== NULL
);
1774 /* bail if HW is still using self-linked descriptor */
1775 if (ath5k_hw_get_rxdp(sc
->ah
) == bf
->daddr
)
1778 ret
= sc
->ah
->ah_proc_rx_desc(sc
->ah
, ds
, &rs
);
1779 if (unlikely(ret
== -EINPROGRESS
))
1781 else if (unlikely(ret
)) {
1782 ATH5K_ERR(sc
, "error in processing rx descriptor\n");
1783 spin_unlock(&sc
->rxbuflock
);
1787 if (unlikely(rs
.rs_more
)) {
1788 ATH5K_WARN(sc
, "unsupported jumbo\n");
1792 if (unlikely(rs
.rs_status
)) {
1793 if (rs
.rs_status
& AR5K_RXERR_PHY
)
1795 if (rs
.rs_status
& AR5K_RXERR_DECRYPT
) {
1797 * Decrypt error. If the error occurred
1798 * because there was no hardware key, then
1799 * let the frame through so the upper layers
1800 * can process it. This is necessary for 5210
1801 * parts which have no way to setup a ``clear''
1804 * XXX do key cache faulting
1806 if (rs
.rs_keyix
== AR5K_RXKEYIX_INVALID
&&
1807 !(rs
.rs_status
& AR5K_RXERR_CRC
))
1810 if (rs
.rs_status
& AR5K_RXERR_MIC
) {
1811 rxs
.flag
|= RX_FLAG_MMIC_ERROR
;
1815 /* let crypto-error packets fall through in MNTR */
1817 ~(AR5K_RXERR_DECRYPT
|AR5K_RXERR_MIC
)) ||
1818 sc
->opmode
!= NL80211_IFTYPE_MONITOR
)
1822 next_skb
= ath5k_rx_skb_alloc(sc
, &next_skb_addr
);
1825 * If we can't replace bf->skb with a new skb under memory
1826 * pressure, just skip this packet
1831 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, sc
->rxbufsize
,
1832 PCI_DMA_FROMDEVICE
);
1833 skb_put(skb
, rs
.rs_datalen
);
1835 /* The MAC header is padded to have 32-bit boundary if the
1836 * packet payload is non-zero. The general calculation for
1837 * padsize would take into account odd header lengths:
1838 * padsize = (4 - hdrlen % 4) % 4; However, since only
1839 * even-length headers are used, padding can only be 0 or 2
1840 * bytes and we can optimize this a bit. In addition, we must
1841 * not try to remove padding from short control frames that do
1842 * not have payload. */
1843 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1844 padsize
= ath5k_pad_size(hdrlen
);
1846 memmove(skb
->data
+ padsize
, skb
->data
, hdrlen
);
1847 skb_pull(skb
, padsize
);
1851 * always extend the mac timestamp, since this information is
1852 * also needed for proper IBSS merging.
1854 * XXX: it might be too late to do it here, since rs_tstamp is
1855 * 15bit only. that means TSF extension has to be done within
1856 * 32768usec (about 32ms). it might be necessary to move this to
1857 * the interrupt handler, like it is done in madwifi.
1859 * Unfortunately we don't know when the hardware takes the rx
1860 * timestamp (beginning of phy frame, data frame, end of rx?).
1861 * The only thing we know is that it is hardware specific...
1862 * On AR5213 it seems the rx timestamp is at the end of the
1863 * frame, but i'm not sure.
1865 * NOTE: mac80211 defines mactime at the beginning of the first
1866 * data symbol. Since we don't have any time references it's
1867 * impossible to comply to that. This affects IBSS merge only
1868 * right now, so it's not too bad...
1870 rxs
.mactime
= ath5k_extend_tsf(sc
->ah
, rs
.rs_tstamp
);
1871 rxs
.flag
|= RX_FLAG_TSFT
;
1873 rxs
.freq
= sc
->curchan
->center_freq
;
1874 rxs
.band
= sc
->curband
->band
;
1876 rxs
.noise
= sc
->ah
->ah_noise_floor
;
1877 rxs
.signal
= rxs
.noise
+ rs
.rs_rssi
;
1879 /* An rssi of 35 indicates you should be able use
1880 * 54 Mbps reliably. A more elaborate scheme can be used
1881 * here but it requires a map of SNR/throughput for each
1882 * possible mode used */
1883 rxs
.qual
= rs
.rs_rssi
* 100 / 35;
1885 /* rssi can be more than 35 though, anything above that
1886 * should be considered at 100% */
1890 rxs
.antenna
= rs
.rs_antenna
;
1891 rxs
.rate_idx
= ath5k_hw_to_driver_rix(sc
, rs
.rs_rate
);
1892 rxs
.flag
|= ath5k_rx_decrypted(sc
, ds
, skb
, &rs
);
1894 if (rxs
.rate_idx
>= 0 && rs
.rs_rate
==
1895 sc
->curband
->bitrates
[rxs
.rate_idx
].hw_value_short
)
1896 rxs
.flag
|= RX_FLAG_SHORTPRE
;
1898 ath5k_debug_dump_skb(sc
, skb
, "RX ", 0);
1900 /* check beacons in IBSS mode */
1901 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
)
1902 ath5k_check_ibss_tsf(sc
, skb
, &rxs
);
1904 __ieee80211_rx(sc
->hw
, skb
, &rxs
);
1907 bf
->skbaddr
= next_skb_addr
;
1909 list_move_tail(&bf
->list
, &sc
->rxbuf
);
1910 } while (ath5k_rxbuf_setup(sc
, bf
) == 0);
1912 spin_unlock(&sc
->rxbuflock
);
1923 ath5k_tx_processq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1925 struct ath5k_tx_status ts
= {};
1926 struct ath5k_buf
*bf
, *bf0
;
1927 struct ath5k_desc
*ds
;
1928 struct sk_buff
*skb
;
1929 struct ieee80211_tx_info
*info
;
1932 spin_lock(&txq
->lock
);
1933 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1936 ret
= sc
->ah
->ah_proc_tx_desc(sc
->ah
, ds
, &ts
);
1937 if (unlikely(ret
== -EINPROGRESS
))
1939 else if (unlikely(ret
)) {
1940 ATH5K_ERR(sc
, "error %d while processing queue %u\n",
1946 info
= IEEE80211_SKB_CB(skb
);
1949 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
,
1952 ieee80211_tx_info_clear_status(info
);
1953 for (i
= 0; i
< 4; i
++) {
1954 struct ieee80211_tx_rate
*r
=
1955 &info
->status
.rates
[i
];
1957 if (ts
.ts_rate
[i
]) {
1958 r
->idx
= ath5k_hw_to_driver_rix(sc
, ts
.ts_rate
[i
]);
1959 r
->count
= ts
.ts_retry
[i
];
1966 /* count the successful attempt as well */
1967 info
->status
.rates
[ts
.ts_final_idx
].count
++;
1969 if (unlikely(ts
.ts_status
)) {
1970 sc
->ll_stats
.dot11ACKFailureCount
++;
1971 if (ts
.ts_status
& AR5K_TXERR_FILT
)
1972 info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
1974 info
->flags
|= IEEE80211_TX_STAT_ACK
;
1975 info
->status
.ack_signal
= ts
.ts_rssi
;
1978 ieee80211_tx_status(sc
->hw
, skb
);
1979 sc
->tx_stats
[txq
->qnum
].count
++;
1981 spin_lock(&sc
->txbuflock
);
1982 sc
->tx_stats
[txq
->qnum
].len
--;
1983 list_move_tail(&bf
->list
, &sc
->txbuf
);
1985 spin_unlock(&sc
->txbuflock
);
1987 if (likely(list_empty(&txq
->q
)))
1989 spin_unlock(&txq
->lock
);
1990 if (sc
->txbuf_len
> ATH_TXBUF
/ 5)
1991 ieee80211_wake_queues(sc
->hw
);
1995 ath5k_tasklet_tx(unsigned long data
)
1997 struct ath5k_softc
*sc
= (void *)data
;
1999 ath5k_tx_processq(sc
, sc
->txq
);
2008 * Setup the beacon frame for transmit.
2011 ath5k_beacon_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
2013 struct sk_buff
*skb
= bf
->skb
;
2014 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
2015 struct ath5k_hw
*ah
= sc
->ah
;
2016 struct ath5k_desc
*ds
;
2021 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
2023 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "skb %p [data %p len %u] "
2024 "skbaddr %llx\n", skb
, skb
->data
, skb
->len
,
2025 (unsigned long long)bf
->skbaddr
);
2026 if (pci_dma_mapping_error(sc
->pdev
, bf
->skbaddr
)) {
2027 ATH5K_ERR(sc
, "beacon DMA mapping failed\n");
2032 antenna
= ah
->ah_tx_ant
;
2034 flags
= AR5K_TXDESC_NOACK
;
2035 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
&& ath5k_hw_hasveol(ah
)) {
2036 ds
->ds_link
= bf
->daddr
; /* self-linked */
2037 flags
|= AR5K_TXDESC_VEOL
;
2042 * If we use multiple antennas on AP and use
2043 * the Sectored AP scenario, switch antenna every
2044 * 4 beacons to make sure everybody hears our AP.
2045 * When a client tries to associate, hw will keep
2046 * track of the tx antenna to be used for this client
2047 * automaticaly, based on ACKed packets.
2049 * Note: AP still listens and transmits RTS on the
2050 * default antenna which is supposed to be an omni.
2052 * Note2: On sectored scenarios it's possible to have
2053 * multiple antennas (1omni -the default- and 14 sectors)
2054 * so if we choose to actually support this mode we need
2055 * to allow user to set how many antennas we have and tweak
2056 * the code below to send beacons on all of them.
2058 if (ah
->ah_ant_mode
== AR5K_ANTMODE_SECTOR_AP
)
2059 antenna
= sc
->bsent
& 4 ? 2 : 1;
2062 /* FIXME: If we are in g mode and rate is a CCK rate
2063 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2064 * from tx power (value is in dB units already) */
2065 ds
->ds_data
= bf
->skbaddr
;
2066 ret
= ah
->ah_setup_tx_desc(ah
, ds
, skb
->len
,
2067 ieee80211_get_hdrlen_from_skb(skb
),
2068 AR5K_PKT_TYPE_BEACON
, (sc
->power_level
* 2),
2069 ieee80211_get_tx_rate(sc
->hw
, info
)->hw_value
,
2070 1, AR5K_TXKEYIX_INVALID
,
2071 antenna
, flags
, 0, 0);
2077 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
2081 static void ath5k_beacon_disable(struct ath5k_softc
*sc
)
2083 sc
->imask
&= ~(AR5K_INT_BMISS
| AR5K_INT_SWBA
);
2084 ath5k_hw_set_imr(sc
->ah
, sc
->imask
);
2085 ath5k_hw_stop_tx_dma(sc
->ah
, sc
->bhalq
);
2089 * Transmit a beacon frame at SWBA. Dynamic updates to the
2090 * frame contents are done as needed and the slot time is
2091 * also adjusted based on current state.
2093 * This is called from software irq context (beacontq or restq
2094 * tasklets) or user context from ath5k_beacon_config.
2097 ath5k_beacon_send(struct ath5k_softc
*sc
)
2099 struct ath5k_buf
*bf
= sc
->bbuf
;
2100 struct ath5k_hw
*ah
= sc
->ah
;
2102 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "in beacon_send\n");
2104 if (unlikely(bf
->skb
== NULL
|| sc
->opmode
== NL80211_IFTYPE_STATION
||
2105 sc
->opmode
== NL80211_IFTYPE_MONITOR
)) {
2106 ATH5K_WARN(sc
, "bf=%p bf_skb=%p\n", bf
, bf
? bf
->skb
: NULL
);
2110 * Check if the previous beacon has gone out. If
2111 * not don't don't try to post another, skip this
2112 * period and wait for the next. Missed beacons
2113 * indicate a problem and should not occur. If we
2114 * miss too many consecutive beacons reset the device.
2116 if (unlikely(ath5k_hw_num_tx_pending(ah
, sc
->bhalq
) != 0)) {
2118 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2119 "missed %u consecutive beacons\n", sc
->bmisscount
);
2120 if (sc
->bmisscount
> 10) { /* NB: 10 is a guess */
2121 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2122 "stuck beacon time (%u missed)\n",
2124 tasklet_schedule(&sc
->restq
);
2128 if (unlikely(sc
->bmisscount
!= 0)) {
2129 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2130 "resume beacon xmit after %u misses\n",
2136 * Stop any current dma and put the new frame on the queue.
2137 * This should never fail since we check above that no frames
2138 * are still pending on the queue.
2140 if (unlikely(ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
))) {
2141 ATH5K_WARN(sc
, "beacon queue %u didn't start/stop ?\n", sc
->bhalq
);
2142 /* NB: hw still stops DMA, so proceed */
2145 /* refresh the beacon for AP mode */
2146 if (sc
->opmode
== NL80211_IFTYPE_AP
)
2147 ath5k_beacon_update(sc
->hw
, sc
->vif
);
2149 ath5k_hw_set_txdp(ah
, sc
->bhalq
, bf
->daddr
);
2150 ath5k_hw_start_tx_dma(ah
, sc
->bhalq
);
2151 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "TXDP[%u] = %llx (%p)\n",
2152 sc
->bhalq
, (unsigned long long)bf
->daddr
, bf
->desc
);
2159 * ath5k_beacon_update_timers - update beacon timers
2161 * @sc: struct ath5k_softc pointer we are operating on
2162 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2163 * beacon timer update based on the current HW TSF.
2165 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2166 * of a received beacon or the current local hardware TSF and write it to the
2167 * beacon timer registers.
2169 * This is called in a variety of situations, e.g. when a beacon is received,
2170 * when a TSF update has been detected, but also when an new IBSS is created or
2171 * when we otherwise know we have to update the timers, but we keep it in this
2172 * function to have it all together in one place.
2175 ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
)
2177 struct ath5k_hw
*ah
= sc
->ah
;
2178 u32 nexttbtt
, intval
, hw_tu
, bc_tu
;
2181 intval
= sc
->bintval
& AR5K_BEACON_PERIOD
;
2182 if (WARN_ON(!intval
))
2185 /* beacon TSF converted to TU */
2186 bc_tu
= TSF_TO_TU(bc_tsf
);
2188 /* current TSF converted to TU */
2189 hw_tsf
= ath5k_hw_get_tsf64(ah
);
2190 hw_tu
= TSF_TO_TU(hw_tsf
);
2193 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2196 * no beacons received, called internally.
2197 * just need to refresh timers based on HW TSF.
2199 nexttbtt
= roundup(hw_tu
+ FUDGE
, intval
);
2200 } else if (bc_tsf
== 0) {
2202 * no beacon received, probably called by ath5k_reset_tsf().
2203 * reset TSF to start with 0.
2206 intval
|= AR5K_BEACON_RESET_TSF
;
2207 } else if (bc_tsf
> hw_tsf
) {
2209 * beacon received, SW merge happend but HW TSF not yet updated.
2210 * not possible to reconfigure timers yet, but next time we
2211 * receive a beacon with the same BSSID, the hardware will
2212 * automatically update the TSF and then we need to reconfigure
2215 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2216 "need to wait for HW TSF sync\n");
2220 * most important case for beacon synchronization between STA.
2222 * beacon received and HW TSF has been already updated by HW.
2223 * update next TBTT based on the TSF of the beacon, but make
2224 * sure it is ahead of our local TSF timer.
2226 nexttbtt
= bc_tu
+ roundup(hw_tu
+ FUDGE
- bc_tu
, intval
);
2230 sc
->nexttbtt
= nexttbtt
;
2232 intval
|= AR5K_BEACON_ENA
;
2233 ath5k_hw_init_beacon(ah
, nexttbtt
, intval
);
2236 * debugging output last in order to preserve the time critical aspect
2240 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2241 "reconfigured timers based on HW TSF\n");
2242 else if (bc_tsf
== 0)
2243 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2244 "reset HW TSF and timers\n");
2246 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2247 "updated timers based on beacon TSF\n");
2249 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2250 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2251 (unsigned long long) bc_tsf
,
2252 (unsigned long long) hw_tsf
, bc_tu
, hw_tu
, nexttbtt
);
2253 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "intval %u %s %s\n",
2254 intval
& AR5K_BEACON_PERIOD
,
2255 intval
& AR5K_BEACON_ENA
? "AR5K_BEACON_ENA" : "",
2256 intval
& AR5K_BEACON_RESET_TSF
? "AR5K_BEACON_RESET_TSF" : "");
2261 * ath5k_beacon_config - Configure the beacon queues and interrupts
2263 * @sc: struct ath5k_softc pointer we are operating on
2265 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2266 * interrupts to detect TSF updates only.
2269 ath5k_beacon_config(struct ath5k_softc
*sc
)
2271 struct ath5k_hw
*ah
= sc
->ah
;
2272 unsigned long flags
;
2274 ath5k_hw_set_imr(ah
, 0);
2276 sc
->imask
&= ~(AR5K_INT_BMISS
| AR5K_INT_SWBA
);
2278 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
||
2279 sc
->opmode
== NL80211_IFTYPE_MESH_POINT
||
2280 sc
->opmode
== NL80211_IFTYPE_AP
) {
2282 * In IBSS mode we use a self-linked tx descriptor and let the
2283 * hardware send the beacons automatically. We have to load it
2285 * We use the SWBA interrupt only to keep track of the beacon
2286 * timers in order to detect automatic TSF updates.
2288 ath5k_beaconq_config(sc
);
2290 sc
->imask
|= AR5K_INT_SWBA
;
2292 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
2293 if (ath5k_hw_hasveol(ah
)) {
2294 spin_lock_irqsave(&sc
->block
, flags
);
2295 ath5k_beacon_send(sc
);
2296 spin_unlock_irqrestore(&sc
->block
, flags
);
2299 ath5k_beacon_update_timers(sc
, -1);
2302 ath5k_hw_set_imr(ah
, sc
->imask
);
2305 static void ath5k_tasklet_beacon(unsigned long data
)
2307 struct ath5k_softc
*sc
= (struct ath5k_softc
*) data
;
2310 * Software beacon alert--time to send a beacon.
2312 * In IBSS mode we use this interrupt just to
2313 * keep track of the next TBTT (target beacon
2314 * transmission time) in order to detect wether
2315 * automatic TSF updates happened.
2317 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
2318 /* XXX: only if VEOL suppported */
2319 u64 tsf
= ath5k_hw_get_tsf64(sc
->ah
);
2320 sc
->nexttbtt
+= sc
->bintval
;
2321 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2322 "SWBA nexttbtt: %x hw_tu: %x "
2326 (unsigned long long) tsf
);
2328 spin_lock(&sc
->block
);
2329 ath5k_beacon_send(sc
);
2330 spin_unlock(&sc
->block
);
2335 /********************\
2336 * Interrupt handling *
2337 \********************/
2340 ath5k_init(struct ath5k_softc
*sc
)
2342 struct ath5k_hw
*ah
= sc
->ah
;
2345 mutex_lock(&sc
->lock
);
2347 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "mode %d\n", sc
->opmode
);
2350 * Stop anything previously setup. This is safe
2351 * no matter this is the first time through or not.
2353 ath5k_stop_locked(sc
);
2356 * The basic interface to setting the hardware in a good
2357 * state is ``reset''. On return the hardware is known to
2358 * be powered up and with interrupts disabled. This must
2359 * be followed by initialization of the appropriate bits
2360 * and then setup of the interrupt mask.
2362 sc
->curchan
= sc
->hw
->conf
.channel
;
2363 sc
->curband
= &sc
->sbands
[sc
->curchan
->band
];
2364 sc
->imask
= AR5K_INT_RXOK
| AR5K_INT_RXERR
| AR5K_INT_RXEOL
|
2365 AR5K_INT_RXORN
| AR5K_INT_TXDESC
| AR5K_INT_TXEOL
|
2366 AR5K_INT_FATAL
| AR5K_INT_GLOBAL
;
2367 ret
= ath5k_reset(sc
, NULL
);
2371 ath5k_rfkill_hw_start(ah
);
2374 * Reset the key cache since some parts do not reset the
2375 * contents on initial power up or resume from suspend.
2377 for (i
= 0; i
< AR5K_KEYTABLE_SIZE
; i
++)
2378 ath5k_hw_reset_key(ah
, i
);
2380 /* Set ack to be sent at low bit-rates */
2381 ath5k_hw_set_ack_bitrate_high(ah
, false);
2383 mod_timer(&sc
->calib_tim
, round_jiffies(jiffies
+
2384 msecs_to_jiffies(ath5k_calinterval
* 1000)));
2389 mutex_unlock(&sc
->lock
);
2394 ath5k_stop_locked(struct ath5k_softc
*sc
)
2396 struct ath5k_hw
*ah
= sc
->ah
;
2398 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "invalid %u\n",
2399 test_bit(ATH_STAT_INVALID
, sc
->status
));
2402 * Shutdown the hardware and driver:
2403 * stop output from above
2404 * disable interrupts
2406 * turn off the radio
2407 * clear transmit machinery
2408 * clear receive machinery
2409 * drain and release tx queues
2410 * reclaim beacon resources
2411 * power down hardware
2413 * Note that some of this work is not possible if the
2414 * hardware is gone (invalid).
2416 ieee80211_stop_queues(sc
->hw
);
2418 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2420 ath5k_hw_set_imr(ah
, 0);
2421 synchronize_irq(sc
->pdev
->irq
);
2423 ath5k_txq_cleanup(sc
);
2424 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2426 ath5k_hw_phy_disable(ah
);
2434 * Stop the device, grabbing the top-level lock to protect
2435 * against concurrent entry through ath5k_init (which can happen
2436 * if another thread does a system call and the thread doing the
2437 * stop is preempted).
2440 ath5k_stop_hw(struct ath5k_softc
*sc
)
2444 mutex_lock(&sc
->lock
);
2445 ret
= ath5k_stop_locked(sc
);
2446 if (ret
== 0 && !test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2448 * Set the chip in full sleep mode. Note that we are
2449 * careful to do this only when bringing the interface
2450 * completely to a stop. When the chip is in this state
2451 * it must be carefully woken up or references to
2452 * registers in the PCI clock domain may freeze the bus
2453 * (and system). This varies by chip and is mostly an
2454 * issue with newer parts that go to sleep more quickly.
2456 if (sc
->ah
->ah_mac_srev
>= 0x78) {
2459 * don't put newer MAC revisions > 7.8 to sleep because
2460 * of the above mentioned problems
2462 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "mac version > 7.8, "
2463 "not putting device to sleep\n");
2465 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2466 "putting device to full sleep\n");
2467 ath5k_hw_set_power(sc
->ah
, AR5K_PM_FULL_SLEEP
, true, 0);
2470 ath5k_txbuf_free(sc
, sc
->bbuf
);
2473 mutex_unlock(&sc
->lock
);
2475 del_timer_sync(&sc
->calib_tim
);
2476 tasklet_kill(&sc
->rxtq
);
2477 tasklet_kill(&sc
->txtq
);
2478 tasklet_kill(&sc
->restq
);
2479 tasklet_kill(&sc
->beacontq
);
2481 ath5k_rfkill_hw_stop(sc
->ah
);
2487 ath5k_intr(int irq
, void *dev_id
)
2489 struct ath5k_softc
*sc
= dev_id
;
2490 struct ath5k_hw
*ah
= sc
->ah
;
2491 enum ath5k_int status
;
2492 unsigned int counter
= 1000;
2494 if (unlikely(test_bit(ATH_STAT_INVALID
, sc
->status
) ||
2495 !ath5k_hw_is_intr_pending(ah
)))
2499 ath5k_hw_get_isr(ah
, &status
); /* NB: clears IRQ too */
2500 ATH5K_DBG(sc
, ATH5K_DEBUG_INTR
, "status 0x%x/0x%x\n",
2502 if (unlikely(status
& AR5K_INT_FATAL
)) {
2504 * Fatal errors are unrecoverable.
2505 * Typically these are caused by DMA errors.
2507 tasklet_schedule(&sc
->restq
);
2508 } else if (unlikely(status
& AR5K_INT_RXORN
)) {
2509 tasklet_schedule(&sc
->restq
);
2511 if (status
& AR5K_INT_SWBA
) {
2512 tasklet_hi_schedule(&sc
->beacontq
);
2514 if (status
& AR5K_INT_RXEOL
) {
2516 * NB: the hardware should re-read the link when
2517 * RXE bit is written, but it doesn't work at
2518 * least on older hardware revs.
2522 if (status
& AR5K_INT_TXURN
) {
2523 /* bump tx trigger level */
2524 ath5k_hw_update_tx_triglevel(ah
, true);
2526 if (status
& (AR5K_INT_RXOK
| AR5K_INT_RXERR
))
2527 tasklet_schedule(&sc
->rxtq
);
2528 if (status
& (AR5K_INT_TXOK
| AR5K_INT_TXDESC
2529 | AR5K_INT_TXERR
| AR5K_INT_TXEOL
))
2530 tasklet_schedule(&sc
->txtq
);
2531 if (status
& AR5K_INT_BMISS
) {
2534 if (status
& AR5K_INT_MIB
) {
2536 * These stats are also used for ANI i think
2537 * so how about updating them more often ?
2539 ath5k_hw_update_mib_counters(ah
, &sc
->ll_stats
);
2541 if (status
& AR5K_INT_GPIO
)
2542 tasklet_schedule(&sc
->rf_kill
.toggleq
);
2545 } while (ath5k_hw_is_intr_pending(ah
) && --counter
> 0);
2547 if (unlikely(!counter
))
2548 ATH5K_WARN(sc
, "too many interrupts, giving up for now\n");
2554 ath5k_tasklet_reset(unsigned long data
)
2556 struct ath5k_softc
*sc
= (void *)data
;
2558 ath5k_reset_wake(sc
);
2562 * Periodically recalibrate the PHY to account
2563 * for temperature/environment changes.
2566 ath5k_calibrate(unsigned long data
)
2568 struct ath5k_softc
*sc
= (void *)data
;
2569 struct ath5k_hw
*ah
= sc
->ah
;
2571 ATH5K_DBG(sc
, ATH5K_DEBUG_CALIBRATE
, "channel %u/%x\n",
2572 ieee80211_frequency_to_channel(sc
->curchan
->center_freq
),
2573 sc
->curchan
->hw_value
);
2575 if (ath5k_hw_gainf_calibrate(ah
) == AR5K_RFGAIN_NEED_CHANGE
) {
2577 * Rfgain is out of bounds, reset the chip
2578 * to load new gain values.
2580 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "calibration, resetting\n");
2581 ath5k_reset_wake(sc
);
2583 if (ath5k_hw_phy_calibrate(ah
, sc
->curchan
))
2584 ATH5K_ERR(sc
, "calibration of channel %u failed\n",
2585 ieee80211_frequency_to_channel(
2586 sc
->curchan
->center_freq
));
2588 mod_timer(&sc
->calib_tim
, round_jiffies(jiffies
+
2589 msecs_to_jiffies(ath5k_calinterval
* 1000)));
2593 /********************\
2594 * Mac80211 functions *
2595 \********************/
2598 ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
2600 struct ath5k_softc
*sc
= hw
->priv
;
2601 struct ath5k_buf
*bf
;
2602 unsigned long flags
;
2606 ath5k_debug_dump_skb(sc
, skb
, "TX ", 1);
2608 if (sc
->opmode
== NL80211_IFTYPE_MONITOR
)
2609 ATH5K_DBG(sc
, ATH5K_DEBUG_XMIT
, "tx in monitor (scan?)\n");
2612 * the hardware expects the header padded to 4 byte boundaries
2613 * if this is not the case we add the padding after the header
2615 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
2616 padsize
= ath5k_pad_size(hdrlen
);
2619 if (skb_headroom(skb
) < padsize
) {
2620 ATH5K_ERR(sc
, "tx hdrlen not %%4: %d not enough"
2621 " headroom to pad %d\n", hdrlen
, padsize
);
2624 skb_push(skb
, padsize
);
2625 memmove(skb
->data
, skb
->data
+padsize
, hdrlen
);
2628 spin_lock_irqsave(&sc
->txbuflock
, flags
);
2629 if (list_empty(&sc
->txbuf
)) {
2630 ATH5K_ERR(sc
, "no further txbuf available, dropping packet\n");
2631 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2632 ieee80211_stop_queue(hw
, skb_get_queue_mapping(skb
));
2635 bf
= list_first_entry(&sc
->txbuf
, struct ath5k_buf
, list
);
2636 list_del(&bf
->list
);
2638 if (list_empty(&sc
->txbuf
))
2639 ieee80211_stop_queues(hw
);
2640 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2644 if (ath5k_txbuf_setup(sc
, bf
)) {
2646 spin_lock_irqsave(&sc
->txbuflock
, flags
);
2647 list_add_tail(&bf
->list
, &sc
->txbuf
);
2649 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2652 return NETDEV_TX_OK
;
2655 dev_kfree_skb_any(skb
);
2656 return NETDEV_TX_OK
;
2660 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2661 * and change to the given channel.
2664 ath5k_reset(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
)
2666 struct ath5k_hw
*ah
= sc
->ah
;
2669 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "resetting\n");
2672 ath5k_hw_set_imr(ah
, 0);
2673 ath5k_txq_cleanup(sc
);
2677 sc
->curband
= &sc
->sbands
[chan
->band
];
2679 ret
= ath5k_hw_reset(ah
, sc
->opmode
, sc
->curchan
, true);
2681 ATH5K_ERR(sc
, "can't reset hardware (%d)\n", ret
);
2685 ret
= ath5k_rx_start(sc
);
2687 ATH5K_ERR(sc
, "can't start recv logic\n");
2692 * Change channels and update the h/w rate map if we're switching;
2693 * e.g. 11a to 11b/g.
2695 * We may be doing a reset in response to an ioctl that changes the
2696 * channel so update any state that might change as a result.
2700 /* ath5k_chan_change(sc, c); */
2702 ath5k_beacon_config(sc
);
2703 /* intrs are enabled by ath5k_beacon_config */
2711 ath5k_reset_wake(struct ath5k_softc
*sc
)
2715 ret
= ath5k_reset(sc
, sc
->curchan
);
2717 ieee80211_wake_queues(sc
->hw
);
2722 static int ath5k_start(struct ieee80211_hw
*hw
)
2724 return ath5k_init(hw
->priv
);
2727 static void ath5k_stop(struct ieee80211_hw
*hw
)
2729 ath5k_stop_hw(hw
->priv
);
2732 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
2733 struct ieee80211_if_init_conf
*conf
)
2735 struct ath5k_softc
*sc
= hw
->priv
;
2738 mutex_lock(&sc
->lock
);
2744 sc
->vif
= conf
->vif
;
2746 switch (conf
->type
) {
2747 case NL80211_IFTYPE_AP
:
2748 case NL80211_IFTYPE_STATION
:
2749 case NL80211_IFTYPE_ADHOC
:
2750 case NL80211_IFTYPE_MESH_POINT
:
2751 case NL80211_IFTYPE_MONITOR
:
2752 sc
->opmode
= conf
->type
;
2759 ath5k_hw_set_lladdr(sc
->ah
, conf
->mac_addr
);
2763 mutex_unlock(&sc
->lock
);
2768 ath5k_remove_interface(struct ieee80211_hw
*hw
,
2769 struct ieee80211_if_init_conf
*conf
)
2771 struct ath5k_softc
*sc
= hw
->priv
;
2772 u8 mac
[ETH_ALEN
] = {};
2774 mutex_lock(&sc
->lock
);
2775 if (sc
->vif
!= conf
->vif
)
2778 ath5k_hw_set_lladdr(sc
->ah
, mac
);
2779 ath5k_beacon_disable(sc
);
2782 mutex_unlock(&sc
->lock
);
2786 * TODO: Phy disable/diversity etc
2789 ath5k_config(struct ieee80211_hw
*hw
, u32 changed
)
2791 struct ath5k_softc
*sc
= hw
->priv
;
2792 struct ath5k_hw
*ah
= sc
->ah
;
2793 struct ieee80211_conf
*conf
= &hw
->conf
;
2796 mutex_lock(&sc
->lock
);
2798 ret
= ath5k_chan_set(sc
, conf
->channel
);
2802 if ((changed
& IEEE80211_CONF_CHANGE_POWER
) &&
2803 (sc
->power_level
!= conf
->power_level
)) {
2804 sc
->power_level
= conf
->power_level
;
2807 ath5k_hw_set_txpower_limit(ah
, (conf
->power_level
* 2));
2811 * 1) Move this on config_interface and handle each case
2812 * separately eg. when we have only one STA vif, use
2813 * AR5K_ANTMODE_SINGLE_AP
2815 * 2) Allow the user to change antenna mode eg. when only
2816 * one antenna is present
2818 * 3) Allow the user to set default/tx antenna when possible
2820 * 4) Default mode should handle 90% of the cases, together
2821 * with fixed a/b and single AP modes we should be able to
2822 * handle 99%. Sectored modes are extreme cases and i still
2823 * haven't found a usage for them. If we decide to support them,
2824 * then we must allow the user to set how many tx antennas we
2827 ath5k_hw_set_antenna_mode(ah
, AR5K_ANTMODE_DEFAULT
);
2830 mutex_unlock(&sc
->lock
);
2834 #define SUPPORTED_FIF_FLAGS \
2835 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2836 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2837 FIF_BCN_PRBRESP_PROMISC
2839 * o always accept unicast, broadcast, and multicast traffic
2840 * o multicast traffic for all BSSIDs will be enabled if mac80211
2842 * o maintain current state of phy ofdm or phy cck error reception.
2843 * If the hardware detects any of these type of errors then
2844 * ath5k_hw_get_rx_filter() will pass to us the respective
2845 * hardware filters to be able to receive these type of frames.
2846 * o probe request frames are accepted only when operating in
2847 * hostap, adhoc, or monitor modes
2848 * o enable promiscuous mode according to the interface state
2850 * - when operating in adhoc mode so the 802.11 layer creates
2851 * node table entries for peers,
2852 * - when operating in station mode for collecting rssi data when
2853 * the station is otherwise quiet, or
2856 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
2857 unsigned int changed_flags
,
2858 unsigned int *new_flags
,
2859 int mc_count
, struct dev_mc_list
*mclist
)
2861 struct ath5k_softc
*sc
= hw
->priv
;
2862 struct ath5k_hw
*ah
= sc
->ah
;
2863 u32 mfilt
[2], val
, rfilt
;
2870 /* Only deal with supported flags */
2871 changed_flags
&= SUPPORTED_FIF_FLAGS
;
2872 *new_flags
&= SUPPORTED_FIF_FLAGS
;
2874 /* If HW detects any phy or radar errors, leave those filters on.
2875 * Also, always enable Unicast, Broadcasts and Multicast
2876 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2877 rfilt
= (ath5k_hw_get_rx_filter(ah
) & (AR5K_RX_FILTER_PHYERR
)) |
2878 (AR5K_RX_FILTER_UCAST
| AR5K_RX_FILTER_BCAST
|
2879 AR5K_RX_FILTER_MCAST
);
2881 if (changed_flags
& (FIF_PROMISC_IN_BSS
| FIF_OTHER_BSS
)) {
2882 if (*new_flags
& FIF_PROMISC_IN_BSS
) {
2883 rfilt
|= AR5K_RX_FILTER_PROM
;
2884 __set_bit(ATH_STAT_PROMISC
, sc
->status
);
2886 __clear_bit(ATH_STAT_PROMISC
, sc
->status
);
2890 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2891 if (*new_flags
& FIF_ALLMULTI
) {
2895 for (i
= 0; i
< mc_count
; i
++) {
2898 /* calculate XOR of eight 6-bit values */
2899 val
= get_unaligned_le32(mclist
->dmi_addr
+ 0);
2900 pos
= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2901 val
= get_unaligned_le32(mclist
->dmi_addr
+ 3);
2902 pos
^= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2904 mfilt
[pos
/ 32] |= (1 << (pos
% 32));
2905 /* XXX: we might be able to just do this instead,
2906 * but not sure, needs testing, if we do use this we'd
2907 * neet to inform below to not reset the mcast */
2908 /* ath5k_hw_set_mcast_filterindex(ah,
2909 * mclist->dmi_addr[5]); */
2910 mclist
= mclist
->next
;
2914 /* This is the best we can do */
2915 if (*new_flags
& (FIF_FCSFAIL
| FIF_PLCPFAIL
))
2916 rfilt
|= AR5K_RX_FILTER_PHYERR
;
2918 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2919 * and probes for any BSSID, this needs testing */
2920 if (*new_flags
& FIF_BCN_PRBRESP_PROMISC
)
2921 rfilt
|= AR5K_RX_FILTER_BEACON
| AR5K_RX_FILTER_PROBEREQ
;
2923 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2924 * set we should only pass on control frames for this
2925 * station. This needs testing. I believe right now this
2926 * enables *all* control frames, which is OK.. but
2927 * but we should see if we can improve on granularity */
2928 if (*new_flags
& FIF_CONTROL
)
2929 rfilt
|= AR5K_RX_FILTER_CONTROL
;
2931 /* Additional settings per mode -- this is per ath5k */
2933 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2935 if (sc
->opmode
== NL80211_IFTYPE_MONITOR
)
2936 rfilt
|= AR5K_RX_FILTER_CONTROL
| AR5K_RX_FILTER_BEACON
|
2937 AR5K_RX_FILTER_PROBEREQ
| AR5K_RX_FILTER_PROM
;
2938 if (sc
->opmode
!= NL80211_IFTYPE_STATION
)
2939 rfilt
|= AR5K_RX_FILTER_PROBEREQ
;
2940 if (sc
->opmode
!= NL80211_IFTYPE_AP
&&
2941 sc
->opmode
!= NL80211_IFTYPE_MESH_POINT
&&
2942 test_bit(ATH_STAT_PROMISC
, sc
->status
))
2943 rfilt
|= AR5K_RX_FILTER_PROM
;
2944 if ((sc
->opmode
== NL80211_IFTYPE_STATION
&& sc
->assoc
) ||
2945 sc
->opmode
== NL80211_IFTYPE_ADHOC
||
2946 sc
->opmode
== NL80211_IFTYPE_AP
)
2947 rfilt
|= AR5K_RX_FILTER_BEACON
;
2948 if (sc
->opmode
== NL80211_IFTYPE_MESH_POINT
)
2949 rfilt
|= AR5K_RX_FILTER_CONTROL
| AR5K_RX_FILTER_BEACON
|
2950 AR5K_RX_FILTER_PROBEREQ
| AR5K_RX_FILTER_PROM
;
2953 ath5k_hw_set_rx_filter(ah
, rfilt
);
2955 /* Set multicast bits */
2956 ath5k_hw_set_mcast_filter(ah
, mfilt
[0], mfilt
[1]);
2957 /* Set the cached hw filter flags, this will alter actually
2959 sc
->filter_flags
= rfilt
;
2963 ath5k_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
2964 struct ieee80211_vif
*vif
, struct ieee80211_sta
*sta
,
2965 struct ieee80211_key_conf
*key
)
2967 struct ath5k_softc
*sc
= hw
->priv
;
2970 if (modparam_nohwcrypt
)
2984 mutex_lock(&sc
->lock
);
2988 ret
= ath5k_hw_set_key(sc
->ah
, key
->keyidx
, key
,
2989 sta
? sta
->addr
: NULL
);
2991 ATH5K_ERR(sc
, "can't set the key\n");
2994 __set_bit(key
->keyidx
, sc
->keymap
);
2995 key
->hw_key_idx
= key
->keyidx
;
2996 key
->flags
|= (IEEE80211_KEY_FLAG_GENERATE_IV
|
2997 IEEE80211_KEY_FLAG_GENERATE_MMIC
);
3000 ath5k_hw_reset_key(sc
->ah
, key
->keyidx
);
3001 __clear_bit(key
->keyidx
, sc
->keymap
);
3010 mutex_unlock(&sc
->lock
);
3015 ath5k_get_stats(struct ieee80211_hw
*hw
,
3016 struct ieee80211_low_level_stats
*stats
)
3018 struct ath5k_softc
*sc
= hw
->priv
;
3019 struct ath5k_hw
*ah
= sc
->ah
;
3022 ath5k_hw_update_mib_counters(ah
, &sc
->ll_stats
);
3024 memcpy(stats
, &sc
->ll_stats
, sizeof(sc
->ll_stats
));
3030 ath5k_get_tx_stats(struct ieee80211_hw
*hw
,
3031 struct ieee80211_tx_queue_stats
*stats
)
3033 struct ath5k_softc
*sc
= hw
->priv
;
3035 memcpy(stats
, &sc
->tx_stats
, sizeof(sc
->tx_stats
));
3041 ath5k_get_tsf(struct ieee80211_hw
*hw
)
3043 struct ath5k_softc
*sc
= hw
->priv
;
3045 return ath5k_hw_get_tsf64(sc
->ah
);
3049 ath5k_set_tsf(struct ieee80211_hw
*hw
, u64 tsf
)
3051 struct ath5k_softc
*sc
= hw
->priv
;
3053 ath5k_hw_set_tsf64(sc
->ah
, tsf
);
3057 ath5k_reset_tsf(struct ieee80211_hw
*hw
)
3059 struct ath5k_softc
*sc
= hw
->priv
;
3062 * in IBSS mode we need to update the beacon timers too.
3063 * this will also reset the TSF if we call it with 0
3065 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
)
3066 ath5k_beacon_update_timers(sc
, 0);
3068 ath5k_hw_reset_tsf(sc
->ah
);
3072 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3073 * this is called only once at config_bss time, for AP we do it every
3074 * SWBA interrupt so that the TIM will reflect buffered frames.
3076 * Called with the beacon lock.
3079 ath5k_beacon_update(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
)
3082 struct ath5k_softc
*sc
= hw
->priv
;
3083 struct sk_buff
*skb
;
3085 if (WARN_ON(!vif
)) {
3090 skb
= ieee80211_beacon_get(hw
, vif
);
3097 ath5k_debug_dump_skb(sc
, skb
, "BC ", 1);
3099 ath5k_txbuf_free(sc
, sc
->bbuf
);
3100 sc
->bbuf
->skb
= skb
;
3101 ret
= ath5k_beacon_setup(sc
, sc
->bbuf
);
3103 sc
->bbuf
->skb
= NULL
;
3109 * Update the beacon and reconfigure the beacon queues.
3112 ath5k_beacon_reconfig(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
)
3115 unsigned long flags
;
3116 struct ath5k_softc
*sc
= hw
->priv
;
3118 spin_lock_irqsave(&sc
->block
, flags
);
3119 ret
= ath5k_beacon_update(hw
, vif
);
3120 spin_unlock_irqrestore(&sc
->block
, flags
);
3122 ath5k_beacon_config(sc
);
3128 set_beacon_filter(struct ieee80211_hw
*hw
, bool enable
)
3130 struct ath5k_softc
*sc
= hw
->priv
;
3131 struct ath5k_hw
*ah
= sc
->ah
;
3133 rfilt
= ath5k_hw_get_rx_filter(ah
);
3135 rfilt
|= AR5K_RX_FILTER_BEACON
;
3137 rfilt
&= ~AR5K_RX_FILTER_BEACON
;
3138 ath5k_hw_set_rx_filter(ah
, rfilt
);
3139 sc
->filter_flags
= rfilt
;
3142 static void ath5k_bss_info_changed(struct ieee80211_hw
*hw
,
3143 struct ieee80211_vif
*vif
,
3144 struct ieee80211_bss_conf
*bss_conf
,
3147 struct ath5k_softc
*sc
= hw
->priv
;
3148 struct ath5k_hw
*ah
= sc
->ah
;
3150 mutex_lock(&sc
->lock
);
3151 if (WARN_ON(sc
->vif
!= vif
))
3154 if (changes
& BSS_CHANGED_BSSID
) {
3155 /* Cache for later use during resets */
3156 memcpy(ah
->ah_bssid
, bss_conf
->bssid
, ETH_ALEN
);
3157 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
3158 * a clean way of letting us retrieve this yet. */
3159 ath5k_hw_set_associd(ah
, ah
->ah_bssid
, 0);
3163 if (changes
& BSS_CHANGED_BEACON_INT
)
3164 sc
->bintval
= bss_conf
->beacon_int
;
3166 if (changes
& BSS_CHANGED_ASSOC
) {
3167 sc
->assoc
= bss_conf
->assoc
;
3168 if (sc
->opmode
== NL80211_IFTYPE_STATION
)
3169 set_beacon_filter(hw
, sc
->assoc
);
3172 if (changes
& BSS_CHANGED_BEACON
&&
3173 (vif
->type
== NL80211_IFTYPE_ADHOC
||
3174 vif
->type
== NL80211_IFTYPE_MESH_POINT
||
3175 vif
->type
== NL80211_IFTYPE_AP
)) {
3176 ath5k_beacon_reconfig(hw
, vif
);
3180 mutex_unlock(&sc
->lock
);