2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
33 #include "drm_crtc_helper.h"
34 #include "intel_drv.h"
37 #include "drm_dp_helper.h"
40 #define DP_LINK_STATUS_SIZE 6
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43 #define DP_LINK_CONFIGURATION_SIZE 9
45 #define IS_eDP(i) ((i)->base.type == INTEL_OUTPUT_EDP)
46 #define IS_PCH_eDP(i) ((i)->is_pch_edp)
49 struct intel_encoder base
;
52 uint8_t link_configuration
[DP_LINK_CONFIGURATION_SIZE
];
58 struct i2c_adapter adapter
;
59 struct i2c_algo_dp_aux_data algo
;
63 static struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
65 return container_of(enc_to_intel_encoder(encoder
), struct intel_dp
, base
);
68 static void intel_dp_link_train(struct intel_dp
*intel_dp
);
69 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
72 intel_edp_link_config (struct intel_encoder
*intel_encoder
,
73 int *lane_num
, int *link_bw
)
75 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
77 *lane_num
= intel_dp
->lane_count
;
78 if (intel_dp
->link_bw
== DP_LINK_BW_1_62
)
80 else if (intel_dp
->link_bw
== DP_LINK_BW_2_7
)
85 intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
87 int max_lane_count
= 4;
89 if (intel_dp
->dpcd
[0] >= 0x11) {
90 max_lane_count
= intel_dp
->dpcd
[2] & 0x1f;
91 switch (max_lane_count
) {
92 case 1: case 2: case 4:
98 return max_lane_count
;
102 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
104 int max_link_bw
= intel_dp
->dpcd
[1];
106 switch (max_link_bw
) {
107 case DP_LINK_BW_1_62
:
111 max_link_bw
= DP_LINK_BW_1_62
;
118 intel_dp_link_clock(uint8_t link_bw
)
120 if (link_bw
== DP_LINK_BW_2_7
)
126 /* I think this is a fiction */
128 intel_dp_link_required(struct drm_device
*dev
, struct intel_dp
*intel_dp
, int pixel_clock
)
130 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
132 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
))
133 return (pixel_clock
* dev_priv
->edp_bpp
) / 8;
135 return pixel_clock
* 3;
139 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
141 return (max_link_clock
* max_lanes
* 8) / 10;
145 intel_dp_mode_valid(struct drm_connector
*connector
,
146 struct drm_display_mode
*mode
)
148 struct drm_encoder
*encoder
= intel_attached_encoder(connector
);
149 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
150 struct drm_device
*dev
= connector
->dev
;
151 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
152 int max_link_clock
= intel_dp_link_clock(intel_dp_max_link_bw(intel_dp
));
153 int max_lanes
= intel_dp_max_lane_count(intel_dp
);
155 if ((IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
)) &&
156 dev_priv
->panel_fixed_mode
) {
157 if (mode
->hdisplay
> dev_priv
->panel_fixed_mode
->hdisplay
)
160 if (mode
->vdisplay
> dev_priv
->panel_fixed_mode
->vdisplay
)
164 /* only refuse the mode on non eDP since we have seen some wierd eDP panels
165 which are outside spec tolerances but somehow work by magic */
166 if (!IS_eDP(intel_dp
) &&
167 (intel_dp_link_required(connector
->dev
, intel_dp
, mode
->clock
)
168 > intel_dp_max_data_rate(max_link_clock
, max_lanes
)))
169 return MODE_CLOCK_HIGH
;
171 if (mode
->clock
< 10000)
172 return MODE_CLOCK_LOW
;
178 pack_aux(uint8_t *src
, int src_bytes
)
185 for (i
= 0; i
< src_bytes
; i
++)
186 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
191 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
196 for (i
= 0; i
< dst_bytes
; i
++)
197 dst
[i
] = src
>> ((3-i
) * 8);
200 /* hrawclock is 1/4 the FSB frequency */
202 intel_hrawclk(struct drm_device
*dev
)
204 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
207 clkcfg
= I915_READ(CLKCFG
);
208 switch (clkcfg
& CLKCFG_FSB_MASK
) {
217 case CLKCFG_FSB_1067
:
219 case CLKCFG_FSB_1333
:
221 /* these two are just a guess; one of them might be right */
222 case CLKCFG_FSB_1600
:
223 case CLKCFG_FSB_1600_ALT
:
231 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
232 uint8_t *send
, int send_bytes
,
233 uint8_t *recv
, int recv_size
)
235 uint32_t output_reg
= intel_dp
->output_reg
;
236 struct drm_device
*dev
= intel_dp
->base
.enc
.dev
;
237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
238 uint32_t ch_ctl
= output_reg
+ 0x10;
239 uint32_t ch_data
= ch_ctl
+ 4;
244 uint32_t aux_clock_divider
;
247 /* The clock divider is based off the hrawclk,
248 * and would like to run at 2MHz. So, take the
249 * hrawclk value and divide by 2 and use that
251 if (IS_eDP(intel_dp
)) {
253 aux_clock_divider
= 200; /* SNB eDP input clock at 400Mhz */
255 aux_clock_divider
= 225; /* eDP input clock at 450Mhz */
256 } else if (HAS_PCH_SPLIT(dev
))
257 aux_clock_divider
= 62; /* IRL input clock fixed at 125Mhz */
259 aux_clock_divider
= intel_hrawclk(dev
) / 2;
266 /* Must try at least 3 times according to DP spec */
267 for (try = 0; try < 5; try++) {
268 /* Load the send data into the aux channel data registers */
269 for (i
= 0; i
< send_bytes
; i
+= 4) {
270 uint32_t d
= pack_aux(send
+ i
, send_bytes
- i
);
272 I915_WRITE(ch_data
+ i
, d
);
275 ctl
= (DP_AUX_CH_CTL_SEND_BUSY
|
276 DP_AUX_CH_CTL_TIME_OUT_400us
|
277 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
278 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
279 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
) |
281 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
282 DP_AUX_CH_CTL_RECEIVE_ERROR
);
284 /* Send the command and wait for it to complete */
285 I915_WRITE(ch_ctl
, ctl
);
286 (void) I915_READ(ch_ctl
);
289 status
= I915_READ(ch_ctl
);
290 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
294 /* Clear done status and any errors */
295 I915_WRITE(ch_ctl
, (status
|
297 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
298 DP_AUX_CH_CTL_RECEIVE_ERROR
));
299 (void) I915_READ(ch_ctl
);
300 if ((status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) == 0)
304 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
305 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
309 /* Check for timeout or receive error.
310 * Timeouts occur when the sink is not connected
312 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
313 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
317 /* Timeouts occur when the device isn't connected, so they're
318 * "normal" -- don't fill the kernel log with these */
319 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
320 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
324 /* Unload any bytes sent back from the other side */
325 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
326 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
328 if (recv_bytes
> recv_size
)
329 recv_bytes
= recv_size
;
331 for (i
= 0; i
< recv_bytes
; i
+= 4) {
332 uint32_t d
= I915_READ(ch_data
+ i
);
334 unpack_aux(d
, recv
+ i
, recv_bytes
- i
);
340 /* Write data to the aux channel in native mode */
342 intel_dp_aux_native_write(struct intel_dp
*intel_dp
,
343 uint16_t address
, uint8_t *send
, int send_bytes
)
352 msg
[0] = AUX_NATIVE_WRITE
<< 4;
353 msg
[1] = address
>> 8;
354 msg
[2] = address
& 0xff;
355 msg
[3] = send_bytes
- 1;
356 memcpy(&msg
[4], send
, send_bytes
);
357 msg_bytes
= send_bytes
+ 4;
359 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
, &ack
, 1);
362 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
364 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
372 /* Write a single byte to the aux channel in native mode */
374 intel_dp_aux_native_write_1(struct intel_dp
*intel_dp
,
375 uint16_t address
, uint8_t byte
)
377 return intel_dp_aux_native_write(intel_dp
, address
, &byte
, 1);
380 /* read bytes from a native aux channel */
382 intel_dp_aux_native_read(struct intel_dp
*intel_dp
,
383 uint16_t address
, uint8_t *recv
, int recv_bytes
)
392 msg
[0] = AUX_NATIVE_READ
<< 4;
393 msg
[1] = address
>> 8;
394 msg
[2] = address
& 0xff;
395 msg
[3] = recv_bytes
- 1;
398 reply_bytes
= recv_bytes
+ 1;
401 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
,
408 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
) {
409 memcpy(recv
, reply
+ 1, ret
- 1);
412 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
420 intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
421 uint8_t write_byte
, uint8_t *read_byte
)
423 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
424 struct intel_dp
*intel_dp
= container_of(adapter
,
427 uint16_t address
= algo_data
->address
;
434 /* Set up the command byte */
435 if (mode
& MODE_I2C_READ
)
436 msg
[0] = AUX_I2C_READ
<< 4;
438 msg
[0] = AUX_I2C_WRITE
<< 4;
440 if (!(mode
& MODE_I2C_STOP
))
441 msg
[0] |= AUX_I2C_MOT
<< 4;
443 msg
[1] = address
>> 8;
465 ret
= intel_dp_aux_ch(intel_dp
,
469 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
472 switch (reply
[0] & AUX_I2C_REPLY_MASK
) {
473 case AUX_I2C_REPLY_ACK
:
474 if (mode
== MODE_I2C_READ
) {
475 *read_byte
= reply
[1];
477 return reply_bytes
- 1;
478 case AUX_I2C_REPLY_NACK
:
479 DRM_DEBUG_KMS("aux_ch nack\n");
481 case AUX_I2C_REPLY_DEFER
:
482 DRM_DEBUG_KMS("aux_ch defer\n");
486 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply
[0]);
493 intel_dp_i2c_init(struct intel_dp
*intel_dp
,
494 struct intel_connector
*intel_connector
, const char *name
)
496 DRM_DEBUG_KMS("i2c_init %s\n", name
);
497 intel_dp
->algo
.running
= false;
498 intel_dp
->algo
.address
= 0;
499 intel_dp
->algo
.aux_ch
= intel_dp_i2c_aux_ch
;
501 memset(&intel_dp
->adapter
, '\0', sizeof (intel_dp
->adapter
));
502 intel_dp
->adapter
.owner
= THIS_MODULE
;
503 intel_dp
->adapter
.class = I2C_CLASS_DDC
;
504 strncpy (intel_dp
->adapter
.name
, name
, sizeof(intel_dp
->adapter
.name
) - 1);
505 intel_dp
->adapter
.name
[sizeof(intel_dp
->adapter
.name
) - 1] = '\0';
506 intel_dp
->adapter
.algo_data
= &intel_dp
->algo
;
507 intel_dp
->adapter
.dev
.parent
= &intel_connector
->base
.kdev
;
509 return i2c_dp_aux_add_bus(&intel_dp
->adapter
);
513 intel_dp_mode_fixup(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
514 struct drm_display_mode
*adjusted_mode
)
516 struct drm_device
*dev
= encoder
->dev
;
517 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
518 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
519 int lane_count
, clock
;
520 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
521 int max_clock
= intel_dp_max_link_bw(intel_dp
) == DP_LINK_BW_2_7
? 1 : 0;
522 static int bws
[2] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
};
524 if ((IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
)) &&
525 dev_priv
->panel_fixed_mode
) {
526 struct drm_display_mode
*fixed_mode
= dev_priv
->panel_fixed_mode
;
528 adjusted_mode
->hdisplay
= fixed_mode
->hdisplay
;
529 adjusted_mode
->hsync_start
= fixed_mode
->hsync_start
;
530 adjusted_mode
->hsync_end
= fixed_mode
->hsync_end
;
531 adjusted_mode
->htotal
= fixed_mode
->htotal
;
533 adjusted_mode
->vdisplay
= fixed_mode
->vdisplay
;
534 adjusted_mode
->vsync_start
= fixed_mode
->vsync_start
;
535 adjusted_mode
->vsync_end
= fixed_mode
->vsync_end
;
536 adjusted_mode
->vtotal
= fixed_mode
->vtotal
;
538 adjusted_mode
->clock
= fixed_mode
->clock
;
539 drm_mode_set_crtcinfo(adjusted_mode
, CRTC_INTERLACE_HALVE_V
);
542 * the mode->clock is used to calculate the Data&Link M/N
543 * of the pipe. For the eDP the fixed clock should be used.
545 mode
->clock
= dev_priv
->panel_fixed_mode
->clock
;
548 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
549 for (clock
= 0; clock
<= max_clock
; clock
++) {
550 int link_avail
= intel_dp_max_data_rate(intel_dp_link_clock(bws
[clock
]), lane_count
);
552 if (intel_dp_link_required(encoder
->dev
, intel_dp
, mode
->clock
)
554 intel_dp
->link_bw
= bws
[clock
];
555 intel_dp
->lane_count
= lane_count
;
556 adjusted_mode
->clock
= intel_dp_link_clock(intel_dp
->link_bw
);
557 DRM_DEBUG_KMS("Display port link bw %02x lane "
558 "count %d clock %d\n",
559 intel_dp
->link_bw
, intel_dp
->lane_count
,
560 adjusted_mode
->clock
);
566 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
)) {
567 /* okay we failed just pick the highest */
568 intel_dp
->lane_count
= max_lane_count
;
569 intel_dp
->link_bw
= bws
[max_clock
];
570 adjusted_mode
->clock
= intel_dp_link_clock(intel_dp
->link_bw
);
571 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
572 "count %d clock %d\n",
573 intel_dp
->link_bw
, intel_dp
->lane_count
,
574 adjusted_mode
->clock
);
580 struct intel_dp_m_n
{
589 intel_reduce_ratio(uint32_t *num
, uint32_t *den
)
591 while (*num
> 0xffffff || *den
> 0xffffff) {
598 intel_dp_compute_m_n(int bpp
,
602 struct intel_dp_m_n
*m_n
)
605 m_n
->gmch_m
= (pixel_clock
* bpp
) >> 3;
606 m_n
->gmch_n
= link_clock
* nlanes
;
607 intel_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
608 m_n
->link_m
= pixel_clock
;
609 m_n
->link_n
= link_clock
;
610 intel_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
613 bool intel_pch_has_edp(struct drm_crtc
*crtc
)
615 struct drm_device
*dev
= crtc
->dev
;
616 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
617 struct drm_encoder
*encoder
;
619 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
620 struct intel_dp
*intel_dp
;
622 if (encoder
->crtc
!= crtc
)
625 intel_dp
= enc_to_intel_dp(encoder
);
626 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
)
627 return intel_dp
->is_pch_edp
;
633 intel_dp_set_m_n(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
634 struct drm_display_mode
*adjusted_mode
)
636 struct drm_device
*dev
= crtc
->dev
;
637 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
638 struct drm_encoder
*encoder
;
639 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
640 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
641 int lane_count
= 4, bpp
= 24;
642 struct intel_dp_m_n m_n
;
645 * Find the lane count in the intel_encoder private
647 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
648 struct intel_dp
*intel_dp
;
650 if (encoder
->crtc
!= crtc
)
653 intel_dp
= enc_to_intel_dp(encoder
);
654 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
655 lane_count
= intel_dp
->lane_count
;
656 if (IS_PCH_eDP(intel_dp
))
657 bpp
= dev_priv
->edp_bpp
;
663 * Compute the GMCH and Link ratios. The '3' here is
664 * the number of bytes_per_pixel post-LUT, which we always
665 * set up for 8-bits of R/G/B, or 3 bytes total.
667 intel_dp_compute_m_n(bpp
, lane_count
,
668 mode
->clock
, adjusted_mode
->clock
, &m_n
);
670 if (HAS_PCH_SPLIT(dev
)) {
671 if (intel_crtc
->pipe
== 0) {
672 I915_WRITE(TRANSA_DATA_M1
,
673 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
675 I915_WRITE(TRANSA_DATA_N1
, m_n
.gmch_n
);
676 I915_WRITE(TRANSA_DP_LINK_M1
, m_n
.link_m
);
677 I915_WRITE(TRANSA_DP_LINK_N1
, m_n
.link_n
);
679 I915_WRITE(TRANSB_DATA_M1
,
680 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
682 I915_WRITE(TRANSB_DATA_N1
, m_n
.gmch_n
);
683 I915_WRITE(TRANSB_DP_LINK_M1
, m_n
.link_m
);
684 I915_WRITE(TRANSB_DP_LINK_N1
, m_n
.link_n
);
687 if (intel_crtc
->pipe
== 0) {
688 I915_WRITE(PIPEA_GMCH_DATA_M
,
689 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
691 I915_WRITE(PIPEA_GMCH_DATA_N
,
693 I915_WRITE(PIPEA_DP_LINK_M
, m_n
.link_m
);
694 I915_WRITE(PIPEA_DP_LINK_N
, m_n
.link_n
);
696 I915_WRITE(PIPEB_GMCH_DATA_M
,
697 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
699 I915_WRITE(PIPEB_GMCH_DATA_N
,
701 I915_WRITE(PIPEB_DP_LINK_M
, m_n
.link_m
);
702 I915_WRITE(PIPEB_DP_LINK_N
, m_n
.link_n
);
708 intel_dp_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
709 struct drm_display_mode
*adjusted_mode
)
711 struct drm_device
*dev
= encoder
->dev
;
712 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
713 struct drm_crtc
*crtc
= intel_dp
->base
.enc
.crtc
;
714 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
716 intel_dp
->DP
= (DP_VOLTAGE_0_4
|
719 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
720 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
721 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
722 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
724 if (HAS_PCH_CPT(dev
) && !IS_eDP(intel_dp
))
725 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
727 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
729 switch (intel_dp
->lane_count
) {
731 intel_dp
->DP
|= DP_PORT_WIDTH_1
;
734 intel_dp
->DP
|= DP_PORT_WIDTH_2
;
737 intel_dp
->DP
|= DP_PORT_WIDTH_4
;
740 if (intel_dp
->has_audio
)
741 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
743 memset(intel_dp
->link_configuration
, 0, DP_LINK_CONFIGURATION_SIZE
);
744 intel_dp
->link_configuration
[0] = intel_dp
->link_bw
;
745 intel_dp
->link_configuration
[1] = intel_dp
->lane_count
;
748 * Check for DPCD version > 1.1 and enhanced framing support
750 if (intel_dp
->dpcd
[0] >= 0x11 && (intel_dp
->dpcd
[2] & DP_ENHANCED_FRAME_CAP
)) {
751 intel_dp
->link_configuration
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
752 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
755 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
756 if (intel_crtc
->pipe
== 1 && !HAS_PCH_CPT(dev
))
757 intel_dp
->DP
|= DP_PIPEB_SELECT
;
759 if (IS_eDP(intel_dp
)) {
760 /* don't miss out required setting for eDP */
761 intel_dp
->DP
|= DP_PLL_ENABLE
;
762 if (adjusted_mode
->clock
< 200000)
763 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
765 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
769 static void ironlake_edp_panel_on (struct drm_device
*dev
)
771 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
772 unsigned long timeout
= jiffies
+ msecs_to_jiffies(5000);
775 pp_status
= I915_READ(PCH_PP_STATUS
);
776 if (pp_status
& PP_ON
)
779 pp
= I915_READ(PCH_PP_CONTROL
);
780 pp
|= PANEL_UNLOCK_REGS
| POWER_TARGET_ON
;
781 I915_WRITE(PCH_PP_CONTROL
, pp
);
783 pp_status
= I915_READ(PCH_PP_STATUS
);
784 } while (((pp_status
& PP_ON
) == 0) && !time_after(jiffies
, timeout
));
786 if (time_after(jiffies
, timeout
))
787 DRM_DEBUG_KMS("panel on wait timed out: 0x%08x\n", pp_status
);
789 pp
&= ~(PANEL_UNLOCK_REGS
| EDP_FORCE_VDD
);
790 I915_WRITE(PCH_PP_CONTROL
, pp
);
793 static void ironlake_edp_panel_off (struct drm_device
*dev
)
795 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
796 unsigned long timeout
= jiffies
+ msecs_to_jiffies(5000);
799 pp
= I915_READ(PCH_PP_CONTROL
);
800 pp
&= ~POWER_TARGET_ON
;
801 I915_WRITE(PCH_PP_CONTROL
, pp
);
803 pp_status
= I915_READ(PCH_PP_STATUS
);
804 } while ((pp_status
& PP_ON
) && !time_after(jiffies
, timeout
));
806 if (time_after(jiffies
, timeout
))
807 DRM_DEBUG_KMS("panel off wait timed out\n");
809 /* Make sure VDD is enabled so DP AUX will work */
811 I915_WRITE(PCH_PP_CONTROL
, pp
);
814 static void ironlake_edp_backlight_on (struct drm_device
*dev
)
816 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
820 pp
= I915_READ(PCH_PP_CONTROL
);
821 pp
|= EDP_BLC_ENABLE
;
822 I915_WRITE(PCH_PP_CONTROL
, pp
);
825 static void ironlake_edp_backlight_off (struct drm_device
*dev
)
827 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
831 pp
= I915_READ(PCH_PP_CONTROL
);
832 pp
&= ~EDP_BLC_ENABLE
;
833 I915_WRITE(PCH_PP_CONTROL
, pp
);
837 intel_dp_dpms(struct drm_encoder
*encoder
, int mode
)
839 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
840 struct drm_device
*dev
= encoder
->dev
;
841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
842 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
844 if (mode
!= DRM_MODE_DPMS_ON
) {
845 if (dp_reg
& DP_PORT_EN
) {
846 intel_dp_link_down(intel_dp
);
847 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
)) {
848 ironlake_edp_backlight_off(dev
);
849 ironlake_edp_panel_off(dev
);
853 if (!(dp_reg
& DP_PORT_EN
)) {
854 intel_dp_link_train(intel_dp
);
855 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
)) {
856 ironlake_edp_panel_on(dev
);
857 ironlake_edp_backlight_on(dev
);
861 intel_dp
->dpms_mode
= mode
;
865 * Fetch AUX CH registers 0x202 - 0x207 which contain
866 * link status information
869 intel_dp_get_link_status(struct intel_dp
*intel_dp
,
870 uint8_t link_status
[DP_LINK_STATUS_SIZE
])
874 ret
= intel_dp_aux_native_read(intel_dp
,
876 link_status
, DP_LINK_STATUS_SIZE
);
877 if (ret
!= DP_LINK_STATUS_SIZE
)
883 intel_dp_link_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
886 return link_status
[r
- DP_LANE0_1_STATUS
];
890 intel_get_adjust_request_voltage(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
893 int i
= DP_ADJUST_REQUEST_LANE0_1
+ (lane
>> 1);
894 int s
= ((lane
& 1) ?
895 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT
:
896 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT
);
897 uint8_t l
= intel_dp_link_status(link_status
, i
);
899 return ((l
>> s
) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT
;
903 intel_get_adjust_request_pre_emphasis(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
906 int i
= DP_ADJUST_REQUEST_LANE0_1
+ (lane
>> 1);
907 int s
= ((lane
& 1) ?
908 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT
:
909 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT
);
910 uint8_t l
= intel_dp_link_status(link_status
, i
);
912 return ((l
>> s
) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT
;
917 static char *voltage_names
[] = {
918 "0.4V", "0.6V", "0.8V", "1.2V"
920 static char *pre_emph_names
[] = {
921 "0dB", "3.5dB", "6dB", "9.5dB"
923 static char *link_train_names
[] = {
924 "pattern 1", "pattern 2", "idle", "off"
929 * These are source-specific values; current Intel hardware supports
930 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
932 #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
935 intel_dp_pre_emphasis_max(uint8_t voltage_swing
)
937 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
938 case DP_TRAIN_VOLTAGE_SWING_400
:
939 return DP_TRAIN_PRE_EMPHASIS_6
;
940 case DP_TRAIN_VOLTAGE_SWING_600
:
941 return DP_TRAIN_PRE_EMPHASIS_6
;
942 case DP_TRAIN_VOLTAGE_SWING_800
:
943 return DP_TRAIN_PRE_EMPHASIS_3_5
;
944 case DP_TRAIN_VOLTAGE_SWING_1200
:
946 return DP_TRAIN_PRE_EMPHASIS_0
;
951 intel_get_adjust_train(struct intel_dp
*intel_dp
,
952 uint8_t link_status
[DP_LINK_STATUS_SIZE
],
954 uint8_t train_set
[4])
960 for (lane
= 0; lane
< lane_count
; lane
++) {
961 uint8_t this_v
= intel_get_adjust_request_voltage(link_status
, lane
);
962 uint8_t this_p
= intel_get_adjust_request_pre_emphasis(link_status
, lane
);
970 if (v
>= I830_DP_VOLTAGE_MAX
)
971 v
= I830_DP_VOLTAGE_MAX
| DP_TRAIN_MAX_SWING_REACHED
;
973 if (p
>= intel_dp_pre_emphasis_max(v
))
974 p
= intel_dp_pre_emphasis_max(v
) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
976 for (lane
= 0; lane
< 4; lane
++)
977 train_set
[lane
] = v
| p
;
981 intel_dp_signal_levels(uint8_t train_set
, int lane_count
)
983 uint32_t signal_levels
= 0;
985 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
986 case DP_TRAIN_VOLTAGE_SWING_400
:
988 signal_levels
|= DP_VOLTAGE_0_4
;
990 case DP_TRAIN_VOLTAGE_SWING_600
:
991 signal_levels
|= DP_VOLTAGE_0_6
;
993 case DP_TRAIN_VOLTAGE_SWING_800
:
994 signal_levels
|= DP_VOLTAGE_0_8
;
996 case DP_TRAIN_VOLTAGE_SWING_1200
:
997 signal_levels
|= DP_VOLTAGE_1_2
;
1000 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
1001 case DP_TRAIN_PRE_EMPHASIS_0
:
1003 signal_levels
|= DP_PRE_EMPHASIS_0
;
1005 case DP_TRAIN_PRE_EMPHASIS_3_5
:
1006 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
1008 case DP_TRAIN_PRE_EMPHASIS_6
:
1009 signal_levels
|= DP_PRE_EMPHASIS_6
;
1011 case DP_TRAIN_PRE_EMPHASIS_9_5
:
1012 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
1015 return signal_levels
;
1018 /* Gen6's DP voltage swing and pre-emphasis control */
1020 intel_gen6_edp_signal_levels(uint8_t train_set
)
1022 switch (train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|DP_TRAIN_PRE_EMPHASIS_MASK
)) {
1023 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1024 return EDP_LINK_TRAIN_400MV_0DB_SNB_B
;
1025 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1026 return EDP_LINK_TRAIN_400MV_6DB_SNB_B
;
1027 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1028 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B
;
1029 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1030 return EDP_LINK_TRAIN_800MV_0DB_SNB_B
;
1032 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
1033 return EDP_LINK_TRAIN_400MV_0DB_SNB_B
;
1038 intel_get_lane_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1041 int i
= DP_LANE0_1_STATUS
+ (lane
>> 1);
1042 int s
= (lane
& 1) * 4;
1043 uint8_t l
= intel_dp_link_status(link_status
, i
);
1045 return (l
>> s
) & 0xf;
1048 /* Check for clock recovery is done on all channels */
1050 intel_clock_recovery_ok(uint8_t link_status
[DP_LINK_STATUS_SIZE
], int lane_count
)
1053 uint8_t lane_status
;
1055 for (lane
= 0; lane
< lane_count
; lane
++) {
1056 lane_status
= intel_get_lane_status(link_status
, lane
);
1057 if ((lane_status
& DP_LANE_CR_DONE
) == 0)
1063 /* Check to see if channel eq is done on all channels */
1064 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1065 DP_LANE_CHANNEL_EQ_DONE|\
1066 DP_LANE_SYMBOL_LOCKED)
1068 intel_channel_eq_ok(uint8_t link_status
[DP_LINK_STATUS_SIZE
], int lane_count
)
1071 uint8_t lane_status
;
1074 lane_align
= intel_dp_link_status(link_status
,
1075 DP_LANE_ALIGN_STATUS_UPDATED
);
1076 if ((lane_align
& DP_INTERLANE_ALIGN_DONE
) == 0)
1078 for (lane
= 0; lane
< lane_count
; lane
++) {
1079 lane_status
= intel_get_lane_status(link_status
, lane
);
1080 if ((lane_status
& CHANNEL_EQ_BITS
) != CHANNEL_EQ_BITS
)
1087 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
1088 uint32_t dp_reg_value
,
1089 uint8_t dp_train_pat
,
1090 uint8_t train_set
[4],
1093 struct drm_device
*dev
= intel_dp
->base
.enc
.dev
;
1094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1097 I915_WRITE(intel_dp
->output_reg
, dp_reg_value
);
1098 POSTING_READ(intel_dp
->output_reg
);
1100 intel_wait_for_vblank(dev
);
1102 intel_dp_aux_native_write_1(intel_dp
,
1103 DP_TRAINING_PATTERN_SET
,
1106 ret
= intel_dp_aux_native_write(intel_dp
,
1107 DP_TRAINING_LANE0_SET
, train_set
, 4);
1115 intel_dp_link_train(struct intel_dp
*intel_dp
)
1117 struct drm_device
*dev
= intel_dp
->base
.enc
.dev
;
1118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1119 uint8_t train_set
[4];
1120 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1123 bool clock_recovery
= false;
1124 bool channel_eq
= false;
1128 uint32_t DP
= intel_dp
->DP
;
1130 /* Write the link configuration data */
1131 intel_dp_aux_native_write(intel_dp
, DP_LINK_BW_SET
,
1132 intel_dp
->link_configuration
,
1133 DP_LINK_CONFIGURATION_SIZE
);
1136 if (HAS_PCH_CPT(dev
) && !IS_eDP(intel_dp
))
1137 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
1139 DP
&= ~DP_LINK_TRAIN_MASK
;
1140 memset(train_set
, 0, 4);
1143 clock_recovery
= false;
1145 /* Use train_set[0] to set the voltage and pre emphasis values */
1146 uint32_t signal_levels
;
1147 if (IS_GEN6(dev
) && IS_eDP(intel_dp
)) {
1148 signal_levels
= intel_gen6_edp_signal_levels(train_set
[0]);
1149 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1151 signal_levels
= intel_dp_signal_levels(train_set
[0], intel_dp
->lane_count
);
1152 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1155 if (HAS_PCH_CPT(dev
) && !IS_eDP(intel_dp
))
1156 reg
= DP
| DP_LINK_TRAIN_PAT_1_CPT
;
1158 reg
= DP
| DP_LINK_TRAIN_PAT_1
;
1160 if (!intel_dp_set_link_train(intel_dp
, reg
,
1161 DP_TRAINING_PATTERN_1
, train_set
, first
))
1164 /* Set training pattern 1 */
1167 if (!intel_dp_get_link_status(intel_dp
, link_status
))
1170 if (intel_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1171 clock_recovery
= true;
1175 /* Check to see if we've tried the max voltage */
1176 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
1177 if ((train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
1179 if (i
== intel_dp
->lane_count
)
1182 /* Check to see if we've tried the same voltage 5 times */
1183 if ((train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
1189 voltage
= train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
1191 /* Compute new train_set as requested by target */
1192 intel_get_adjust_train(intel_dp
, link_status
, intel_dp
->lane_count
, train_set
);
1195 /* channel equalization */
1199 /* Use train_set[0] to set the voltage and pre emphasis values */
1200 uint32_t signal_levels
;
1202 if (IS_GEN6(dev
) && IS_eDP(intel_dp
)) {
1203 signal_levels
= intel_gen6_edp_signal_levels(train_set
[0]);
1204 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1206 signal_levels
= intel_dp_signal_levels(train_set
[0], intel_dp
->lane_count
);
1207 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1210 if (HAS_PCH_CPT(dev
) && !IS_eDP(intel_dp
))
1211 reg
= DP
| DP_LINK_TRAIN_PAT_2_CPT
;
1213 reg
= DP
| DP_LINK_TRAIN_PAT_2
;
1215 /* channel eq pattern */
1216 if (!intel_dp_set_link_train(intel_dp
, reg
,
1217 DP_TRAINING_PATTERN_2
, train_set
,
1222 if (!intel_dp_get_link_status(intel_dp
, link_status
))
1225 if (intel_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
1234 /* Compute new train_set as requested by target */
1235 intel_get_adjust_train(intel_dp
, link_status
, intel_dp
->lane_count
, train_set
);
1239 if (HAS_PCH_CPT(dev
) && !IS_eDP(intel_dp
))
1240 reg
= DP
| DP_LINK_TRAIN_OFF_CPT
;
1242 reg
= DP
| DP_LINK_TRAIN_OFF
;
1244 I915_WRITE(intel_dp
->output_reg
, reg
);
1245 POSTING_READ(intel_dp
->output_reg
);
1246 intel_dp_aux_native_write_1(intel_dp
,
1247 DP_TRAINING_PATTERN_SET
, DP_TRAINING_PATTERN_DISABLE
);
1251 intel_dp_link_down(struct intel_dp
*intel_dp
)
1253 struct drm_device
*dev
= intel_dp
->base
.enc
.dev
;
1254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1255 uint32_t DP
= intel_dp
->DP
;
1257 DRM_DEBUG_KMS("\n");
1259 if (IS_eDP(intel_dp
)) {
1260 DP
&= ~DP_PLL_ENABLE
;
1261 I915_WRITE(intel_dp
->output_reg
, DP
);
1262 POSTING_READ(intel_dp
->output_reg
);
1266 if (HAS_PCH_CPT(dev
) && !IS_eDP(intel_dp
)) {
1267 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
1268 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
1269 POSTING_READ(intel_dp
->output_reg
);
1271 DP
&= ~DP_LINK_TRAIN_MASK
;
1272 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
1273 POSTING_READ(intel_dp
->output_reg
);
1278 if (IS_eDP(intel_dp
))
1279 DP
|= DP_LINK_TRAIN_OFF
;
1280 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
1281 POSTING_READ(intel_dp
->output_reg
);
1285 * According to DP spec
1288 * 2. Configure link according to Receiver Capabilities
1289 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1290 * 4. Check link status on receipt of hot-plug interrupt
1294 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
1296 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1298 if (!intel_dp
->base
.enc
.crtc
)
1301 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
1302 intel_dp_link_down(intel_dp
);
1306 if (!intel_channel_eq_ok(link_status
, intel_dp
->lane_count
))
1307 intel_dp_link_train(intel_dp
);
1310 static enum drm_connector_status
1311 ironlake_dp_detect(struct drm_connector
*connector
)
1313 struct drm_encoder
*encoder
= intel_attached_encoder(connector
);
1314 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1315 enum drm_connector_status status
;
1317 status
= connector_status_disconnected
;
1318 if (intel_dp_aux_native_read(intel_dp
,
1319 0x000, intel_dp
->dpcd
,
1320 sizeof (intel_dp
->dpcd
)) == sizeof (intel_dp
->dpcd
))
1322 if (intel_dp
->dpcd
[0] != 0)
1323 status
= connector_status_connected
;
1325 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp
->dpcd
[0],
1326 intel_dp
->dpcd
[1], intel_dp
->dpcd
[2], intel_dp
->dpcd
[3]);
1331 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1333 * \return true if DP port is connected.
1334 * \return false if DP port is disconnected.
1336 static enum drm_connector_status
1337 intel_dp_detect(struct drm_connector
*connector
)
1339 struct drm_encoder
*encoder
= intel_attached_encoder(connector
);
1340 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1341 struct drm_device
*dev
= intel_dp
->base
.enc
.dev
;
1342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1344 enum drm_connector_status status
;
1346 intel_dp
->has_audio
= false;
1348 if (HAS_PCH_SPLIT(dev
))
1349 return ironlake_dp_detect(connector
);
1351 switch (intel_dp
->output_reg
) {
1353 bit
= DPB_HOTPLUG_INT_STATUS
;
1356 bit
= DPC_HOTPLUG_INT_STATUS
;
1359 bit
= DPD_HOTPLUG_INT_STATUS
;
1362 return connector_status_unknown
;
1365 temp
= I915_READ(PORT_HOTPLUG_STAT
);
1367 if ((temp
& bit
) == 0)
1368 return connector_status_disconnected
;
1370 status
= connector_status_disconnected
;
1371 if (intel_dp_aux_native_read(intel_dp
,
1372 0x000, intel_dp
->dpcd
,
1373 sizeof (intel_dp
->dpcd
)) == sizeof (intel_dp
->dpcd
))
1375 if (intel_dp
->dpcd
[0] != 0)
1376 status
= connector_status_connected
;
1381 static int intel_dp_get_modes(struct drm_connector
*connector
)
1383 struct drm_encoder
*encoder
= intel_attached_encoder(connector
);
1384 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1385 struct drm_device
*dev
= intel_dp
->base
.enc
.dev
;
1386 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1389 /* We should parse the EDID data and find out if it has an audio sink
1392 ret
= intel_ddc_get_modes(connector
, intel_dp
->base
.ddc_bus
);
1394 if ((IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
)) &&
1395 !dev_priv
->panel_fixed_mode
) {
1396 struct drm_display_mode
*newmode
;
1397 list_for_each_entry(newmode
, &connector
->probed_modes
,
1399 if (newmode
->type
& DRM_MODE_TYPE_PREFERRED
) {
1400 dev_priv
->panel_fixed_mode
=
1401 drm_mode_duplicate(dev
, newmode
);
1410 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1411 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
)) {
1412 if (dev_priv
->panel_fixed_mode
!= NULL
) {
1413 struct drm_display_mode
*mode
;
1414 mode
= drm_mode_duplicate(dev
, dev_priv
->panel_fixed_mode
);
1415 drm_mode_probed_add(connector
, mode
);
1423 intel_dp_destroy (struct drm_connector
*connector
)
1425 drm_sysfs_connector_remove(connector
);
1426 drm_connector_cleanup(connector
);
1430 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs
= {
1431 .dpms
= intel_dp_dpms
,
1432 .mode_fixup
= intel_dp_mode_fixup
,
1433 .prepare
= intel_encoder_prepare
,
1434 .mode_set
= intel_dp_mode_set
,
1435 .commit
= intel_encoder_commit
,
1438 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
1439 .dpms
= drm_helper_connector_dpms
,
1440 .detect
= intel_dp_detect
,
1441 .fill_modes
= drm_helper_probe_single_connector_modes
,
1442 .destroy
= intel_dp_destroy
,
1445 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
1446 .get_modes
= intel_dp_get_modes
,
1447 .mode_valid
= intel_dp_mode_valid
,
1448 .best_encoder
= intel_attached_encoder
,
1451 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
1452 .destroy
= intel_encoder_destroy
,
1456 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
1458 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
1460 if (intel_dp
->dpms_mode
== DRM_MODE_DPMS_ON
)
1461 intel_dp_check_link_status(intel_dp
);
1464 /* Return which DP Port should be selected for Transcoder DP control */
1466 intel_trans_dp_port_sel (struct drm_crtc
*crtc
)
1468 struct drm_device
*dev
= crtc
->dev
;
1469 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
1470 struct drm_encoder
*encoder
;
1472 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
1473 struct intel_dp
*intel_dp
;
1475 if (encoder
->crtc
!= crtc
)
1478 intel_dp
= enc_to_intel_dp(encoder
);
1479 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
)
1480 return intel_dp
->output_reg
;
1486 /* check the VBT to see whether the eDP is on DP-D port */
1487 bool intel_dpd_is_edp(struct drm_device
*dev
)
1489 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1490 struct child_device_config
*p_child
;
1493 if (!dev_priv
->child_dev_num
)
1496 for (i
= 0; i
< dev_priv
->child_dev_num
; i
++) {
1497 p_child
= dev_priv
->child_dev
+ i
;
1499 if (p_child
->dvo_port
== PORT_IDPD
&&
1500 p_child
->device_type
== DEVICE_TYPE_eDP
)
1507 intel_dp_init(struct drm_device
*dev
, int output_reg
)
1509 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1510 struct drm_connector
*connector
;
1511 struct intel_dp
*intel_dp
;
1512 struct intel_encoder
*intel_encoder
;
1513 struct intel_connector
*intel_connector
;
1514 const char *name
= NULL
;
1517 intel_dp
= kzalloc(sizeof(struct intel_dp
), GFP_KERNEL
);
1521 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
1522 if (!intel_connector
) {
1526 intel_encoder
= &intel_dp
->base
;
1528 if (HAS_PCH_SPLIT(dev
) && output_reg
== PCH_DP_D
)
1529 if (intel_dpd_is_edp(dev
))
1530 intel_dp
->is_pch_edp
= true;
1532 if (output_reg
== DP_A
|| IS_PCH_eDP(intel_dp
)) {
1533 type
= DRM_MODE_CONNECTOR_eDP
;
1534 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
1536 type
= DRM_MODE_CONNECTOR_DisplayPort
;
1537 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
1540 connector
= &intel_connector
->base
;
1541 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
1542 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
1544 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
1546 if (output_reg
== DP_B
|| output_reg
== PCH_DP_B
)
1547 intel_encoder
->clone_mask
= (1 << INTEL_DP_B_CLONE_BIT
);
1548 else if (output_reg
== DP_C
|| output_reg
== PCH_DP_C
)
1549 intel_encoder
->clone_mask
= (1 << INTEL_DP_C_CLONE_BIT
);
1550 else if (output_reg
== DP_D
|| output_reg
== PCH_DP_D
)
1551 intel_encoder
->clone_mask
= (1 << INTEL_DP_D_CLONE_BIT
);
1553 if (IS_eDP(intel_dp
))
1554 intel_encoder
->clone_mask
= (1 << INTEL_EDP_CLONE_BIT
);
1556 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
1557 connector
->interlace_allowed
= true;
1558 connector
->doublescan_allowed
= 0;
1560 intel_dp
->output_reg
= output_reg
;
1561 intel_dp
->has_audio
= false;
1562 intel_dp
->dpms_mode
= DRM_MODE_DPMS_ON
;
1564 drm_encoder_init(dev
, &intel_encoder
->enc
, &intel_dp_enc_funcs
,
1565 DRM_MODE_ENCODER_TMDS
);
1566 drm_encoder_helper_add(&intel_encoder
->enc
, &intel_dp_helper_funcs
);
1568 drm_mode_connector_attach_encoder(&intel_connector
->base
,
1569 &intel_encoder
->enc
);
1570 drm_sysfs_connector_add(connector
);
1572 /* Set up the DDC bus. */
1573 switch (output_reg
) {
1579 dev_priv
->hotplug_supported_mask
|=
1580 HDMIB_HOTPLUG_INT_STATUS
;
1585 dev_priv
->hotplug_supported_mask
|=
1586 HDMIC_HOTPLUG_INT_STATUS
;
1591 dev_priv
->hotplug_supported_mask
|=
1592 HDMID_HOTPLUG_INT_STATUS
;
1597 intel_dp_i2c_init(intel_dp
, intel_connector
, name
);
1599 intel_encoder
->ddc_bus
= &intel_dp
->adapter
;
1600 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
1602 if (output_reg
== DP_A
|| IS_PCH_eDP(intel_dp
)) {
1603 /* initialize panel mode from VBT if available for eDP */
1604 if (dev_priv
->lfp_lvds_vbt_mode
) {
1605 dev_priv
->panel_fixed_mode
=
1606 drm_mode_duplicate(dev
, dev_priv
->lfp_lvds_vbt_mode
);
1607 if (dev_priv
->panel_fixed_mode
) {
1608 dev_priv
->panel_fixed_mode
->type
|=
1609 DRM_MODE_TYPE_PREFERRED
;
1614 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1615 * 0xd. Failure to do so will result in spurious interrupts being
1616 * generated on the port when a cable is not attached.
1618 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
1619 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
1620 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);