2 * linux/drivers/ide/pci/cmd64x.c Version 1.50 May 10, 2007
4 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
5 * Due to massive hardware bugs, UltraDMA is only supported
6 * on the 646U2 and not on the 646U.
8 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
9 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
11 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
12 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
15 #include <linux/module.h>
16 #include <linux/types.h>
17 #include <linux/pci.h>
18 #include <linux/delay.h>
19 #include <linux/hdreg.h>
20 #include <linux/ide.h>
21 #include <linux/init.h>
25 #define DISPLAY_CMD64X_TIMINGS
30 #define cmdprintk(x...) printk(x)
32 #define cmdprintk(x...)
36 * CMD64x specific registers definition.
39 #define CFR_INTR_CH0 0x04
41 #define CNTRL_ENA_1ST 0x04
42 #define CNTRL_ENA_2ND 0x08
43 #define CNTRL_DIS_RA0 0x40
44 #define CNTRL_DIS_RA1 0x80
52 #define ARTTIM23_DIS_RA2 0x04
53 #define ARTTIM23_DIS_RA3 0x08
54 #define ARTTIM23_INTR_CH1 0x10
61 #define MRDMODE_INTR_CH0 0x04
62 #define MRDMODE_INTR_CH1 0x08
63 #define MRDMODE_BLK_CH0 0x10
64 #define MRDMODE_BLK_CH1 0x20
66 #define UDIDETCR0 0x73
71 #define UDIDETCR1 0x7B
74 #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
75 #include <linux/stat.h>
76 #include <linux/proc_fs.h>
78 static u8 cmd64x_proc
= 0;
80 #define CMD_MAX_DEVS 5
82 static struct pci_dev
*cmd_devs
[CMD_MAX_DEVS
];
83 static int n_cmd_devs
;
85 static char * print_cmd64x_get_info (char *buf
, struct pci_dev
*dev
, int index
)
88 u8 reg72
= 0, reg73
= 0; /* primary */
89 u8 reg7a
= 0, reg7b
= 0; /* secondary */
90 u8 reg50
= 1, reg51
= 1, reg57
= 0, reg71
= 0; /* extra */
92 p
+= sprintf(p
, "\nController: %d\n", index
);
93 p
+= sprintf(p
, "PCI-%x Chipset.\n", dev
->device
);
95 (void) pci_read_config_byte(dev
, CFR
, ®50
);
96 (void) pci_read_config_byte(dev
, CNTRL
, ®51
);
97 (void) pci_read_config_byte(dev
, ARTTIM23
, ®57
);
98 (void) pci_read_config_byte(dev
, MRDMODE
, ®71
);
99 (void) pci_read_config_byte(dev
, BMIDESR0
, ®72
);
100 (void) pci_read_config_byte(dev
, UDIDETCR0
, ®73
);
101 (void) pci_read_config_byte(dev
, BMIDESR1
, ®7a
);
102 (void) pci_read_config_byte(dev
, UDIDETCR1
, ®7b
);
104 /* PCI0643/6 originally didn't have the primary channel enable bit */
105 if ((dev
->device
== PCI_DEVICE_ID_CMD_643
) ||
106 (dev
->device
== PCI_DEVICE_ID_CMD_646
&& dev
->revision
< 3))
107 reg51
|= CNTRL_ENA_1ST
;
109 p
+= sprintf(p
, "---------------- Primary Channel "
110 "---------------- Secondary Channel ------------\n");
111 p
+= sprintf(p
, " %s %s\n",
112 (reg51
& CNTRL_ENA_1ST
) ? "enabled " : "disabled",
113 (reg51
& CNTRL_ENA_2ND
) ? "enabled " : "disabled");
114 p
+= sprintf(p
, "---------------- drive0 --------- drive1 "
115 "-------- drive0 --------- drive1 ------\n");
116 p
+= sprintf(p
, "DMA enabled: %s %s"
118 (reg72
& 0x20) ? "yes" : "no ", (reg72
& 0x40) ? "yes" : "no ",
119 (reg7a
& 0x20) ? "yes" : "no ", (reg7a
& 0x40) ? "yes" : "no ");
120 p
+= sprintf(p
, "UltraDMA mode: %s (%c) %s (%c)",
121 ( reg73
& 0x01) ? " on" : "off",
122 ((reg73
& 0x30) == 0x30) ? ((reg73
& 0x04) ? '3' : '0') :
123 ((reg73
& 0x30) == 0x20) ? ((reg73
& 0x04) ? '3' : '1') :
124 ((reg73
& 0x30) == 0x10) ? ((reg73
& 0x04) ? '4' : '2') :
125 ((reg73
& 0x30) == 0x00) ? ((reg73
& 0x04) ? '5' : '2') : '?',
126 ( reg73
& 0x02) ? " on" : "off",
127 ((reg73
& 0xC0) == 0xC0) ? ((reg73
& 0x08) ? '3' : '0') :
128 ((reg73
& 0xC0) == 0x80) ? ((reg73
& 0x08) ? '3' : '1') :
129 ((reg73
& 0xC0) == 0x40) ? ((reg73
& 0x08) ? '4' : '2') :
130 ((reg73
& 0xC0) == 0x00) ? ((reg73
& 0x08) ? '5' : '2') : '?');
131 p
+= sprintf(p
, " %s (%c) %s (%c)\n",
132 ( reg7b
& 0x01) ? " on" : "off",
133 ((reg7b
& 0x30) == 0x30) ? ((reg7b
& 0x04) ? '3' : '0') :
134 ((reg7b
& 0x30) == 0x20) ? ((reg7b
& 0x04) ? '3' : '1') :
135 ((reg7b
& 0x30) == 0x10) ? ((reg7b
& 0x04) ? '4' : '2') :
136 ((reg7b
& 0x30) == 0x00) ? ((reg7b
& 0x04) ? '5' : '2') : '?',
137 ( reg7b
& 0x02) ? " on" : "off",
138 ((reg7b
& 0xC0) == 0xC0) ? ((reg7b
& 0x08) ? '3' : '0') :
139 ((reg7b
& 0xC0) == 0x80) ? ((reg7b
& 0x08) ? '3' : '1') :
140 ((reg7b
& 0xC0) == 0x40) ? ((reg7b
& 0x08) ? '4' : '2') :
141 ((reg7b
& 0xC0) == 0x00) ? ((reg7b
& 0x08) ? '5' : '2') : '?');
142 p
+= sprintf(p
, "Interrupt: %s, %s %s, %s\n",
143 (reg71
& MRDMODE_BLK_CH0
) ? "blocked" : "enabled",
144 (reg50
& CFR_INTR_CH0
) ? "pending" : "clear ",
145 (reg71
& MRDMODE_BLK_CH1
) ? "blocked" : "enabled",
146 (reg57
& ARTTIM23_INTR_CH1
) ? "pending" : "clear ");
151 static int cmd64x_get_info (char *buffer
, char **addr
, off_t offset
, int count
)
156 for (i
= 0; i
< n_cmd_devs
; i
++) {
157 struct pci_dev
*dev
= cmd_devs
[i
];
158 p
= print_cmd64x_get_info(p
, dev
, i
);
160 return p
-buffer
; /* => must be less than 4k! */
163 #endif /* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */
165 static u8
quantize_timing(int timing
, int quant
)
167 return (timing
+ quant
- 1) / quant
;
171 * This routine calculates active/recovery counts and then writes them into
172 * the chipset registers.
174 static void program_cycle_times (ide_drive_t
*drive
, int cycle_time
, int active_time
)
176 struct pci_dev
*dev
= HWIF(drive
)->pci_dev
;
177 int clock_time
= 1000 / system_bus_clock();
178 u8 cycle_count
, active_count
, recovery_count
, drwtim
;
179 static const u8 recovery_values
[] =
180 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
181 static const u8 drwtim_regs
[4] = {DRWTIM0
, DRWTIM1
, DRWTIM2
, DRWTIM3
};
183 cmdprintk("program_cycle_times parameters: total=%d, active=%d\n",
184 cycle_time
, active_time
);
186 cycle_count
= quantize_timing( cycle_time
, clock_time
);
187 active_count
= quantize_timing(active_time
, clock_time
);
188 recovery_count
= cycle_count
- active_count
;
191 * In case we've got too long recovery phase, try to lengthen
194 if (recovery_count
> 16) {
195 active_count
+= recovery_count
- 16;
198 if (active_count
> 16) /* shouldn't actually happen... */
201 cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n",
202 cycle_count
, active_count
, recovery_count
);
205 * Convert values to internal chipset representation
207 recovery_count
= recovery_values
[recovery_count
];
208 active_count
&= 0x0f;
210 /* Program the active/recovery counts into the DRWTIM register */
211 drwtim
= (active_count
<< 4) | recovery_count
;
212 (void) pci_write_config_byte(dev
, drwtim_regs
[drive
->dn
], drwtim
);
213 cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim
, drwtim_regs
[drive
->dn
]);
217 * This routine writes into the chipset registers
218 * PIO setup/active/recovery timings.
220 static void cmd64x_tune_pio(ide_drive_t
*drive
, const u8 pio
)
222 ide_hwif_t
*hwif
= HWIF(drive
);
223 struct pci_dev
*dev
= hwif
->pci_dev
;
224 unsigned int cycle_time
;
225 u8 setup_count
, arttim
= 0;
227 static const u8 setup_values
[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
228 static const u8 arttim_regs
[4] = {ARTTIM0
, ARTTIM1
, ARTTIM23
, ARTTIM23
};
230 cycle_time
= ide_pio_cycle_time(drive
, pio
);
232 program_cycle_times(drive
, cycle_time
,
233 ide_pio_timings
[pio
].active_time
);
235 setup_count
= quantize_timing(ide_pio_timings
[pio
].setup_time
,
236 1000 / system_bus_clock());
239 * The primary channel has individual address setup timing registers
240 * for each drive and the hardware selects the slowest timing itself.
241 * The secondary channel has one common register and we have to select
242 * the slowest address setup timing ourselves.
245 ide_drive_t
*drives
= hwif
->drives
;
247 drive
->drive_data
= setup_count
;
248 setup_count
= max(drives
[0].drive_data
, drives
[1].drive_data
);
251 if (setup_count
> 5) /* shouldn't actually happen... */
253 cmdprintk("Final address setup count: %d\n", setup_count
);
256 * Program the address setup clocks into the ARTTIM registers.
257 * Avoid clearing the secondary channel's interrupt bit.
259 (void) pci_read_config_byte (dev
, arttim_regs
[drive
->dn
], &arttim
);
261 arttim
&= ~ARTTIM23_INTR_CH1
;
263 arttim
|= setup_values
[setup_count
];
264 (void) pci_write_config_byte(dev
, arttim_regs
[drive
->dn
], arttim
);
265 cmdprintk("Write 0x%02x to reg 0x%x\n", arttim
, arttim_regs
[drive
->dn
]);
269 * Attempts to set drive's PIO mode.
270 * Special cases are 8: prefetch off, 9: prefetch on (both never worked)
273 static void cmd64x_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
276 * Filter out the prefetch control values
277 * to prevent PIO5 from being programmed
279 if (pio
== 8 || pio
== 9)
282 cmd64x_tune_pio(drive
, pio
);
285 static void cmd64x_set_dma_mode(ide_drive_t
*drive
, const u8 speed
)
287 ide_hwif_t
*hwif
= HWIF(drive
);
288 struct pci_dev
*dev
= hwif
->pci_dev
;
289 u8 unit
= drive
->dn
& 0x01;
290 u8 regU
= 0, pciU
= hwif
->channel
? UDIDETCR1
: UDIDETCR0
;
292 if (speed
>= XFER_SW_DMA_0
) {
293 (void) pci_read_config_byte(dev
, pciU
, ®U
);
294 regU
&= ~(unit
? 0xCA : 0x35);
299 regU
|= unit
? 0x0A : 0x05;
302 regU
|= unit
? 0x4A : 0x15;
305 regU
|= unit
? 0x8A : 0x25;
308 regU
|= unit
? 0x42 : 0x11;
311 regU
|= unit
? 0x82 : 0x21;
314 regU
|= unit
? 0xC2 : 0x31;
317 program_cycle_times(drive
, 120, 70);
320 program_cycle_times(drive
, 150, 80);
323 program_cycle_times(drive
, 480, 215);
329 if (speed
>= XFER_SW_DMA_0
)
330 (void) pci_write_config_byte(dev
, pciU
, regU
);
333 static int cmd648_ide_dma_end (ide_drive_t
*drive
)
335 ide_hwif_t
*hwif
= HWIF(drive
);
336 int err
= __ide_dma_end(drive
);
337 u8 irq_mask
= hwif
->channel
? MRDMODE_INTR_CH1
:
339 u8 mrdmode
= inb(hwif
->dma_master
+ 0x01);
341 /* clear the interrupt bit */
342 outb(mrdmode
| irq_mask
, hwif
->dma_master
+ 0x01);
347 static int cmd64x_ide_dma_end (ide_drive_t
*drive
)
349 ide_hwif_t
*hwif
= HWIF(drive
);
350 struct pci_dev
*dev
= hwif
->pci_dev
;
351 int irq_reg
= hwif
->channel
? ARTTIM23
: CFR
;
352 u8 irq_mask
= hwif
->channel
? ARTTIM23_INTR_CH1
:
355 int err
= __ide_dma_end(drive
);
357 (void) pci_read_config_byte(dev
, irq_reg
, &irq_stat
);
358 /* clear the interrupt bit */
359 (void) pci_write_config_byte(dev
, irq_reg
, irq_stat
| irq_mask
);
364 static int cmd648_ide_dma_test_irq (ide_drive_t
*drive
)
366 ide_hwif_t
*hwif
= HWIF(drive
);
367 u8 irq_mask
= hwif
->channel
? MRDMODE_INTR_CH1
:
369 u8 dma_stat
= inb(hwif
->dma_status
);
370 u8 mrdmode
= inb(hwif
->dma_master
+ 0x01);
373 printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n",
374 drive
->name
, dma_stat
, mrdmode
, irq_mask
);
376 if (!(mrdmode
& irq_mask
))
379 /* return 1 if INTR asserted */
386 static int cmd64x_ide_dma_test_irq (ide_drive_t
*drive
)
388 ide_hwif_t
*hwif
= HWIF(drive
);
389 struct pci_dev
*dev
= hwif
->pci_dev
;
390 int irq_reg
= hwif
->channel
? ARTTIM23
: CFR
;
391 u8 irq_mask
= hwif
->channel
? ARTTIM23_INTR_CH1
:
393 u8 dma_stat
= inb(hwif
->dma_status
);
396 (void) pci_read_config_byte(dev
, irq_reg
, &irq_stat
);
399 printk("%s: dma_stat: 0x%02x irq_stat: 0x%02x irq_mask: 0x%02x\n",
400 drive
->name
, dma_stat
, irq_stat
, irq_mask
);
402 if (!(irq_stat
& irq_mask
))
405 /* return 1 if INTR asserted */
413 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
414 * event order for DMA transfers.
417 static int cmd646_1_ide_dma_end (ide_drive_t
*drive
)
419 ide_hwif_t
*hwif
= HWIF(drive
);
420 u8 dma_stat
= 0, dma_cmd
= 0;
422 drive
->waiting_for_dma
= 0;
424 dma_stat
= inb(hwif
->dma_status
);
425 /* read DMA command state */
426 dma_cmd
= inb(hwif
->dma_command
);
428 outb(dma_cmd
& ~1, hwif
->dma_command
);
429 /* clear the INTR & ERROR bits */
430 outb(dma_stat
| 6, hwif
->dma_status
);
431 /* and free any DMA resources */
432 ide_destroy_dmatable(drive
);
433 /* verify good DMA status */
434 return (dma_stat
& 7) != 4;
437 static unsigned int __devinit
init_chipset_cmd64x(struct pci_dev
*dev
, const char *name
)
441 if (dev
->device
== PCI_DEVICE_ID_CMD_646
) {
444 pci_read_config_byte(dev
, PCI_REVISION_ID
, &rev
);
449 printk("%s: UltraDMA capable\n", name
);
453 printk("%s: MultiWord DMA force limited\n", name
);
456 printk("%s: MultiWord DMA limited, "
457 "IRQ workaround enabled\n", name
);
462 /* Set a good latency timer and cache line size value. */
463 (void) pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 64);
464 /* FIXME: pci_set_master() to ensure a good latency timer value */
467 * Enable interrupts, select MEMORY READ LINE for reads.
469 * NOTE: although not mentioned in the PCI0646U specs,
470 * bits 0-1 are write only and won't be read back as
471 * set or not -- PCI0646U2 specs clarify this point.
473 (void) pci_read_config_byte (dev
, MRDMODE
, &mrdmode
);
475 (void) pci_write_config_byte(dev
, MRDMODE
, (mrdmode
| 0x02));
477 #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
479 cmd_devs
[n_cmd_devs
++] = dev
;
483 ide_pci_create_host_proc("cmd64x", cmd64x_get_info
);
485 #endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_IDE_PROC_FS */
490 static u8 __devinit
ata66_cmd64x(ide_hwif_t
*hwif
)
492 struct pci_dev
*dev
= hwif
->pci_dev
;
493 u8 bmidecsr
= 0, mask
= hwif
->channel
? 0x02 : 0x01;
495 switch (dev
->device
) {
496 case PCI_DEVICE_ID_CMD_648
:
497 case PCI_DEVICE_ID_CMD_649
:
498 pci_read_config_byte(dev
, BMIDECSR
, &bmidecsr
);
499 return (bmidecsr
& mask
) ? ATA_CBL_PATA80
: ATA_CBL_PATA40
;
501 return ATA_CBL_PATA40
;
505 static void __devinit
init_hwif_cmd64x(ide_hwif_t
*hwif
)
507 struct pci_dev
*dev
= hwif
->pci_dev
;
510 pci_read_config_byte(dev
, PCI_REVISION_ID
, &rev
);
512 hwif
->set_pio_mode
= &cmd64x_set_pio_mode
;
513 hwif
->set_dma_mode
= &cmd64x_set_dma_mode
;
515 hwif
->drives
[0].autotune
= hwif
->drives
[1].autotune
= 1;
521 hwif
->mwdma_mask
= 0x07;
522 hwif
->ultra_mask
= hwif
->cds
->udma_mask
;
525 * UltraDMA only supported on PCI646U and PCI646U2, which
526 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
527 * Actually, although the CMD tech support people won't
528 * tell me the details, the 0x03 revision cannot support
529 * UDMA correctly without hardware modifications, and even
530 * then it only works with Quantum disks due to some
531 * hold time assumptions in the 646U part which are fixed
534 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
536 if (dev
->device
== PCI_DEVICE_ID_CMD_646
&& rev
< 5)
537 hwif
->ultra_mask
= 0x00;
539 if (hwif
->cbl
!= ATA_CBL_PATA40_SHORT
)
540 hwif
->cbl
= ata66_cmd64x(hwif
);
542 switch (dev
->device
) {
543 case PCI_DEVICE_ID_CMD_648
:
544 case PCI_DEVICE_ID_CMD_649
:
546 hwif
->ide_dma_end
= &cmd648_ide_dma_end
;
547 hwif
->ide_dma_test_irq
= &cmd648_ide_dma_test_irq
;
549 case PCI_DEVICE_ID_CMD_646
:
550 hwif
->chipset
= ide_cmd646
;
552 hwif
->ide_dma_end
= &cmd646_1_ide_dma_end
;
554 } else if (rev
>= 0x03)
558 hwif
->ide_dma_end
= &cmd64x_ide_dma_end
;
559 hwif
->ide_dma_test_irq
= &cmd64x_ide_dma_test_irq
;
564 static int __devinit
init_setup_cmd64x(struct pci_dev
*dev
, ide_pci_device_t
*d
)
566 return ide_setup_pci_device(dev
, d
);
569 static int __devinit
init_setup_cmd646(struct pci_dev
*dev
, ide_pci_device_t
*d
)
572 * The original PCI0646 didn't have the primary channel enable bit,
573 * it appeared starting with PCI0646U (i.e. revision ID 3).
575 if (dev
->revision
< 3)
576 d
->enablebits
[0].reg
= 0;
578 return ide_setup_pci_device(dev
, d
);
581 static ide_pci_device_t cmd64x_chipsets
[] __devinitdata
= {
584 .init_setup
= init_setup_cmd64x
,
585 .init_chipset
= init_chipset_cmd64x
,
586 .init_hwif
= init_hwif_cmd64x
,
588 .enablebits
= {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
589 .bootable
= ON_BOARD
,
590 .host_flags
= IDE_HFLAG_ABUSE_PREFETCH
,
591 .pio_mask
= ATA_PIO5
,
592 .udma_mask
= 0x00, /* no udma */
595 .init_setup
= init_setup_cmd646
,
596 .init_chipset
= init_chipset_cmd64x
,
597 .init_hwif
= init_hwif_cmd64x
,
599 .enablebits
= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
600 .bootable
= ON_BOARD
,
601 .host_flags
= IDE_HFLAG_ABUSE_PREFETCH
,
602 .pio_mask
= ATA_PIO5
,
603 .udma_mask
= 0x07, /* udma0-2 */
606 .init_setup
= init_setup_cmd64x
,
607 .init_chipset
= init_chipset_cmd64x
,
608 .init_hwif
= init_hwif_cmd64x
,
610 .enablebits
= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
611 .bootable
= ON_BOARD
,
612 .host_flags
= IDE_HFLAG_ABUSE_PREFETCH
,
613 .pio_mask
= ATA_PIO5
,
614 .udma_mask
= 0x1f, /* udma0-4 */
617 .init_setup
= init_setup_cmd64x
,
618 .init_chipset
= init_chipset_cmd64x
,
619 .init_hwif
= init_hwif_cmd64x
,
621 .enablebits
= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
622 .bootable
= ON_BOARD
,
623 .host_flags
= IDE_HFLAG_ABUSE_PREFETCH
,
624 .pio_mask
= ATA_PIO5
,
625 .udma_mask
= 0x3f, /* udma0-5 */
630 * We may have to modify enablebits for PCI0646, so we'd better pass
631 * a local copy of the ide_pci_device_t structure down the call chain...
633 static int __devinit
cmd64x_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
635 ide_pci_device_t d
= cmd64x_chipsets
[id
->driver_data
];
637 return d
.init_setup(dev
, &d
);
640 static const struct pci_device_id cmd64x_pci_tbl
[] = {
641 { PCI_VDEVICE(CMD
, PCI_DEVICE_ID_CMD_643
), 0 },
642 { PCI_VDEVICE(CMD
, PCI_DEVICE_ID_CMD_646
), 1 },
643 { PCI_VDEVICE(CMD
, PCI_DEVICE_ID_CMD_648
), 2 },
644 { PCI_VDEVICE(CMD
, PCI_DEVICE_ID_CMD_649
), 3 },
647 MODULE_DEVICE_TABLE(pci
, cmd64x_pci_tbl
);
649 static struct pci_driver driver
= {
650 .name
= "CMD64x_IDE",
651 .id_table
= cmd64x_pci_tbl
,
652 .probe
= cmd64x_init_one
,
655 static int __init
cmd64x_ide_init(void)
657 return ide_pci_register_driver(&driver
);
660 module_init(cmd64x_ide_init
);
662 MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
663 MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
664 MODULE_LICENSE("GPL");