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omap: i2c: add a timeout to the busy waiting
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / rtl8187se / r8180_rtl8225z2.c
blob6edf5a46fa4055bdd7222ea7328ba0fd7c37dc46
1 /*
2 This is part of the rtl8180-sa2400 driver
3 released under the GPL (See file COPYING for details).
4 Copyright (c) 2005 Andrea Merello <andreamrl@tiscali.it>
5
6 This files contains programming code for the rtl8225
7 radio frontend.
8
9 *Many* thanks to Realtek Corp. for their great support!
10
11 */
12
13 #include "r8180_hw.h"
14 #include "r8180_rtl8225.h"
15 #include "r8180_93cx6.h"
16
17 #include "ieee80211/dot11d.h"
18
19
20 static void write_rtl8225(struct net_device *dev, u8 adr, u16 data)
21 {
22 int i;
23 u16 out, select;
24 u8 bit;
25 u32 bangdata = (data << 4) | (adr & 0xf);
26
27 out = read_nic_word(dev, RFPinsOutput) & 0xfff3;
28
29 write_nic_word(dev, RFPinsEnable,
30 (read_nic_word(dev, RFPinsEnable) | 0x7));
31
32 select = read_nic_word(dev, RFPinsSelect);
33
34 write_nic_word(dev, RFPinsSelect, select | 0x7 |
35 SW_CONTROL_GPIO);
36
37 force_pci_posting(dev);
38 udelay(10);
39
40 write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
41
42 force_pci_posting(dev);
43 udelay(2);
44
45 write_nic_word(dev, RFPinsOutput, out);
46
47 force_pci_posting(dev);
48 udelay(10);
49
50 for (i = 15; i >= 0; i--) {
51 bit = (bangdata & (1 << i)) >> i;
52
53 write_nic_word(dev, RFPinsOutput, bit | out);
54
55 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
56 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
57
58 i--;
59 bit = (bangdata & (1 << i)) >> i;
60
61 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
62 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
63
64 write_nic_word(dev, RFPinsOutput, bit | out);
65
66 }
67
68 write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
69
70 force_pci_posting(dev);
71 udelay(10);
72
73 write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
74
75 write_nic_word(dev, RFPinsSelect, select | SW_CONTROL_GPIO);
76
77 rtl8185_rf_pins_enable(dev);
78 }
79
80 static const u16 rtl8225bcd_rxgain[] = {
81 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
82 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
83 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
84 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
85 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
86 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
87 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
88 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
89 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
90 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
91 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3,
92 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb
93
94 };
95
96 static const u8 rtl8225_agc[] = {
97 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e,
98 0x9d, 0x9c, 0x9b, 0x9a, 0x99, 0x98, 0x97, 0x96,
99 0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 0x8f, 0x8e,
100 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86,
101 0x85, 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e,
102 0x3d, 0x3c, 0x3b, 0x3a, 0x39, 0x38, 0x37, 0x36,
103 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 0x2e,
104 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26,
105 0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e,
106 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18, 0x17, 0x16,
107 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e,
108 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06,
109 0x05, 0x04, 0x03, 0x02, 0x01, 0x01, 0x01, 0x01,
110 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
111 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
112 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
113 };
114
115 static const u8 rtl8225_gain[] = {
116 0x23, 0x88, 0x7c, 0xa5, /* -82dBm */
117 0x23, 0x88, 0x7c, 0xb5, /* -82dBm */
118 0x23, 0x88, 0x7c, 0xc5, /* -82dBm */
119 0x33, 0x80, 0x79, 0xc5, /* -78dBm */
120 0x43, 0x78, 0x76, 0xc5, /* -74dBm */
121 0x53, 0x60, 0x73, 0xc5, /* -70dBm */
122 0x63, 0x58, 0x70, 0xc5, /* -66dBm */
123 };
124
125 static const u8 rtl8225_tx_gain_cck_ofdm[] = {
126 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e
127 };
128
129 static const u8 rtl8225_tx_power_cck[] = {
130 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02,
131 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02,
132 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02,
133 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02,
134 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03,
135 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03
136 };
137
138 static const u8 rtl8225_tx_power_cck_ch14[] = {
139 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00,
140 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00,
141 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00,
142 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00,
143 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00,
144 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00
145 };
146
147 static const u8 rtl8225_tx_power_ofdm[] = {
148 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4
149 };
150
151 static const u32 rtl8225_chan[] = {
152 0,
153 0x0080, 0x0100, 0x0180, 0x0200, 0x0280, 0x0300, 0x0380,
154 0x0400, 0x0480, 0x0500, 0x0580, 0x0600, 0x0680, 0x074A,
155 };
156
157 static void rtl8225_SetTXPowerLevel(struct net_device *dev, short ch)
158 {
159 struct r8180_priv *priv = ieee80211_priv(dev);
160 int GainIdx;
161 int GainSetting;
162 int i;
163 u8 power;
164 const u8 *cck_power_table;
165 u8 max_cck_power_level;
166 u8 max_ofdm_power_level;
167 u8 min_ofdm_power_level;
168 u8 cck_power_level = 0xff & priv->chtxpwr[ch];
169 u8 ofdm_power_level = 0xff & priv->chtxpwr_ofdm[ch];
170
171 max_cck_power_level = 35;
172 max_ofdm_power_level = 35;
173 min_ofdm_power_level = 0;
174
175 if (cck_power_level > max_cck_power_level)
176 cck_power_level = max_cck_power_level;
177
178 GainIdx = cck_power_level % 6;
179 GainSetting = cck_power_level / 6;
180
181 if (ch == 14)
182 cck_power_table = rtl8225_tx_power_cck_ch14;
183 else
184 cck_power_table = rtl8225_tx_power_cck;
185
186 write_nic_byte(dev, TX_GAIN_CCK,
187 rtl8225_tx_gain_cck_ofdm[GainSetting] >> 1);
188
189 for (i = 0; i < 8; i++) {
190 power = cck_power_table[GainIdx * 8 + i];
191 write_phy_cck(dev, 0x44 + i, power);
192 }
193
194 /* FIXME Is this delay really needeed ? */
195 force_pci_posting(dev);
196 mdelay(1);
197
198 if (ofdm_power_level > (max_ofdm_power_level - min_ofdm_power_level))
199 ofdm_power_level = max_ofdm_power_level;
200 else
201 ofdm_power_level += min_ofdm_power_level;
202
203 if (ofdm_power_level > 35)
204 ofdm_power_level = 35;
205
206 GainIdx = ofdm_power_level % 6;
207 GainSetting = ofdm_power_level / 6;
208
209 rtl8185_set_anaparam2(dev, RTL8225_ANAPARAM2_ON);
210
211 write_phy_ofdm(dev, 2, 0x42);
212 write_phy_ofdm(dev, 6, 0x00);
213 write_phy_ofdm(dev, 8, 0x00);
214
215 write_nic_byte(dev, TX_GAIN_OFDM,
216 rtl8225_tx_gain_cck_ofdm[GainSetting] >> 1);
217
218 power = rtl8225_tx_power_ofdm[GainIdx];
219
220 write_phy_ofdm(dev, 5, power);
221 write_phy_ofdm(dev, 7, power);
222
223 force_pci_posting(dev);
224 mdelay(1);
225 }
226
227 static const u8 rtl8225z2_threshold[] = {
228 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd,
229 };
230
231 static const u8 rtl8225z2_gain_bg[] = {
232 0x23, 0x15, 0xa5, /* -82-1dBm */
233 0x23, 0x15, 0xb5, /* -82-2dBm */
234 0x23, 0x15, 0xc5, /* -82-3dBm */
235 0x33, 0x15, 0xc5, /* -78dBm */
236 0x43, 0x15, 0xc5, /* -74dBm */
237 0x53, 0x15, 0xc5, /* -70dBm */
238 0x63, 0x15, 0xc5, /* -66dBm */
239 };
240
241 static const u8 rtl8225z2_gain_a[] = {
242 0x13, 0x27, 0x5a, /* -82dBm */
243 0x23, 0x23, 0x58, /* -82dBm */
244 0x33, 0x1f, 0x56, /* -82dBm */
245 0x43, 0x1b, 0x54, /* -78dBm */
246 0x53, 0x17, 0x51, /* -74dBm */
247 0x63, 0x24, 0x4f, /* -70dBm */
248 0x73, 0x0f, 0x4c, /* -66dBm */
249 };
250
251 static const u16 rtl8225z2_rxgain[] = {
252 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
253 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
254 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
255 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
256 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
257 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
258 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
259 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
260 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
261 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
262 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
263 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
264
265 };
266
267 static const u8 ZEBRA2_CCK_OFDM_GAIN_SETTING[] = {
268 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
269 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b,
270 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11,
271 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
272 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d,
273 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23,
274 };
275
276 static const u8 rtl8225z2_tx_power_ofdm[] = {
277 0x42, 0x00, 0x40, 0x00, 0x40
278 };
279
280 static const u8 rtl8225z2_tx_power_cck_ch14[] = {
281 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00
282 };
283
284 static const u8 rtl8225z2_tx_power_cck[] = {
285 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04
286 };
287
288 void rtl8225z2_set_gain(struct net_device *dev, short gain)
289 {
290 const u8 *rtl8225_gain;
291 struct r8180_priv *priv = ieee80211_priv(dev);
292 u8 mode = priv->ieee80211->mode;
293
294 if (mode == IEEE_B || mode == IEEE_G)
295 rtl8225_gain = rtl8225z2_gain_bg;
296 else
297 rtl8225_gain = rtl8225z2_gain_a;
298
299 write_phy_ofdm(dev, 0x0b, rtl8225_gain[gain * 3]);
300 write_phy_ofdm(dev, 0x1b, rtl8225_gain[gain * 3 + 1]);
301 write_phy_ofdm(dev, 0x1d, rtl8225_gain[gain * 3 + 2]);
302 write_phy_ofdm(dev, 0x21, 0x37);
303 }
304
305 static u32 read_rtl8225(struct net_device *dev, u8 adr)
306 {
307 u32 data2Write = ((u32)(adr & 0x1f)) << 27;
308 u32 dataRead;
309 u32 mask;
310 u16 oval,oval2,oval3,tmp;
311 int i;
312 short bit, rw;
313 u8 wLength = 6;
314 u8 rLength = 12;
315 u8 low2high = 0;
316
317 oval = read_nic_word(dev, RFPinsOutput);
318 oval2 = read_nic_word(dev, RFPinsEnable);
319 oval3 = read_nic_word(dev, RFPinsSelect);
320
321 write_nic_word(dev, RFPinsEnable, (oval2|0xf));
322 write_nic_word(dev, RFPinsSelect, (oval3|0xf));
323
324 dataRead = 0;
325
326 oval &= ~0xf;
327
328 write_nic_word(dev, RFPinsOutput, oval | BB_HOST_BANG_EN ); udelay(4);
329
330 write_nic_word(dev, RFPinsOutput, oval ); udelay(5);
331
332 rw = 0;
333
334 mask = (low2high) ? 0x01 : (((u32)0x01)<<(32-1));
335
336 for (i = 0; i < wLength/2; i++) {
337 bit = ((data2Write&mask) != 0) ? 1 : 0;
338 write_nic_word(dev, RFPinsOutput, bit|oval | rw); udelay(1);
339
340 write_nic_word(dev, RFPinsOutput, bit|oval | BB_HOST_BANG_CLK | rw); udelay(2);
341 write_nic_word(dev, RFPinsOutput, bit|oval | BB_HOST_BANG_CLK | rw); udelay(2);
342
343 mask = (low2high) ? (mask<<1): (mask>>1);
344
345 if (i == 2) {
346 rw = BB_HOST_BANG_RW;
347 write_nic_word(dev, RFPinsOutput, bit|oval | BB_HOST_BANG_CLK | rw); udelay(2);
348 write_nic_word(dev, RFPinsOutput, bit|oval | rw); udelay(2);
349 break;
350 }
351
352 bit = ((data2Write&mask) != 0) ? 1: 0;
353
354 write_nic_word(dev, RFPinsOutput, oval|bit|rw| BB_HOST_BANG_CLK); udelay(2);
355 write_nic_word(dev, RFPinsOutput, oval|bit|rw| BB_HOST_BANG_CLK); udelay(2);
356
357 write_nic_word(dev, RFPinsOutput, oval| bit |rw); udelay(1);
358
359 mask = (low2high) ? (mask<<1) : (mask>>1);
360 }
361
362 write_nic_word(dev, RFPinsOutput, rw|oval); udelay(2);
363 mask = (low2high) ? 0x01 : (((u32)0x01) << (12-1));
364
365 /*
366 * We must set data pin to HW controled, otherwise RF can't driver it
367 * and value RF register won't be able to read back properly.
368 */
369 write_nic_word(dev, RFPinsEnable, (oval2 & (~0x01)));
370
371 for (i = 0; i < rLength; i++) {
372 write_nic_word(dev, RFPinsOutput, rw|oval); udelay(1);
373
374 write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK); udelay(2);
375 write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK); udelay(2);
376 write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK); udelay(2);
377 tmp = read_nic_word(dev, RFPinsInput);
378
379 dataRead |= (tmp & BB_HOST_BANG_CLK ? mask : 0);
380
381 write_nic_word(dev, RFPinsOutput, (rw|oval)); udelay(2);
382
383 mask = (low2high) ? (mask<<1) : (mask>>1);
384 }
385
386 write_nic_word(dev, RFPinsOutput, BB_HOST_BANG_EN|BB_HOST_BANG_RW|oval); udelay(2);
387
388 write_nic_word(dev, RFPinsEnable, oval2);
389 write_nic_word(dev, RFPinsSelect, oval3); /* Set To SW Switch */
390 write_nic_word(dev, RFPinsOutput, 0x3a0);
391
392 return dataRead;
393 }
394
395 short rtl8225_is_V_z2(struct net_device *dev)
396 {
397 short vz2 = 1;
398
399 if (read_rtl8225(dev, 8) != 0x588)
400 vz2 = 0;
401 else /* reg 9 pg 1 = 24 */
402 if (read_rtl8225(dev, 9) != 0x700)
403 vz2 = 0;
404
405 /* sw back to pg 0 */
406 write_rtl8225(dev, 0, 0xb7);
407
408 return vz2;
409 }
410
411 void rtl8225z2_rf_close(struct net_device *dev)
412 {
413 RF_WriteReg(dev, 0x4, 0x1f);
414
415 force_pci_posting(dev);
416 mdelay(1);
417
418 rtl8180_set_anaparam(dev, RTL8225z2_ANAPARAM_OFF);
419 rtl8185_set_anaparam2(dev, RTL8225z2_ANAPARAM2_OFF);
420 }
421
422 /*
423 * Map dBm into Tx power index according to current HW model, for example,
424 * RF and PA, and current wireless mode.
425 */
426 s8 DbmToTxPwrIdx(struct r8180_priv *priv, WIRELESS_MODE WirelessMode,
427 s32 PowerInDbm)
428 {
429 bool bUseDefault = true;
430 s8 TxPwrIdx = 0;
431
432 /*
433 * OFDM Power in dBm = Index * 0.5 + 0
434 * CCK Power in dBm = Index * 0.25 + 13
435 */
436 s32 tmp = 0;
437
438 if (WirelessMode == WIRELESS_MODE_G) {
439 bUseDefault = false;
440 tmp = (2 * PowerInDbm);
441
442 if (tmp < 0)
443 TxPwrIdx = 0;
444 else if (tmp > 40) /* 40 means 20 dBm. */
445 TxPwrIdx = 40;
446 else
447 TxPwrIdx = (s8)tmp;
448 } else if (WirelessMode == WIRELESS_MODE_B) {
449 bUseDefault = false;
450 tmp = (4 * PowerInDbm) - 52;
451
452 if (tmp < 0)
453 TxPwrIdx = 0;
454 else if (tmp > 28) /* 28 means 20 dBm. */
455 TxPwrIdx = 28;
456 else
457 TxPwrIdx = (s8)tmp;
458 }
459
460 /*
461 * TRUE if we want to use a default implementation.
462 * We shall set it to FALSE when we have exact translation formular
463 * for target IC. 070622, by rcnjko.
464 */
465 if (bUseDefault) {
466 if (PowerInDbm < 0)
467 TxPwrIdx = 0;
468 else if (PowerInDbm > 35)
469 TxPwrIdx = 35;
470 else
471 TxPwrIdx = (u8)PowerInDbm;
472 }
473
474 return TxPwrIdx;
475 }
476
477 void rtl8225z2_SetTXPowerLevel(struct net_device *dev, short ch)
478 {
479 struct r8180_priv *priv = ieee80211_priv(dev);
480 u8 max_cck_power_level;
481 u8 max_ofdm_power_level;
482 u8 min_ofdm_power_level;
483 char cck_power_level = (char)(0xff & priv->chtxpwr[ch]);
484 char ofdm_power_level = (char)(0xff & priv->chtxpwr_ofdm[ch]);
485
486 if (IS_DOT11D_ENABLE(priv->ieee80211) &&
487 IS_DOT11D_STATE_DONE(priv->ieee80211)) {
488 u8 MaxTxPwrInDbm = DOT11D_GetMaxTxPwrInDbm(priv->ieee80211, ch);
489 u8 CckMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_B, MaxTxPwrInDbm);
490 u8 OfdmMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_G, MaxTxPwrInDbm);
491
492 if (cck_power_level > CckMaxPwrIdx)
493 cck_power_level = CckMaxPwrIdx;
494 if (ofdm_power_level > OfdmMaxPwrIdx)
495 ofdm_power_level = OfdmMaxPwrIdx;
496 }
497
498 max_cck_power_level = 15;
499 max_ofdm_power_level = 25;
500 min_ofdm_power_level = 10;
501
502 if (cck_power_level > 35)
503 cck_power_level = 35;
504
505 write_nic_byte(dev, CCK_TXAGC,
506 (ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)cck_power_level]));
507 force_pci_posting(dev);
508 mdelay(1);
509
510 if (ofdm_power_level > 35)
511 ofdm_power_level = 35;
512
513 if (priv->up == 0) {
514 write_phy_ofdm(dev, 2, 0x42);
515 write_phy_ofdm(dev, 5, 0x00);
516 write_phy_ofdm(dev, 6, 0x40);
517 write_phy_ofdm(dev, 7, 0x00);
518 write_phy_ofdm(dev, 8, 0x40);
519 }
520
521 write_nic_byte(dev, OFDM_TXAGC,
522 ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)ofdm_power_level]);
523
524 if (ofdm_power_level <= 11) {
525 write_phy_ofdm(dev, 0x07, 0x5c);
526 write_phy_ofdm(dev, 0x09, 0x5c);
527 }
528
529 if (ofdm_power_level <= 17) {
530 write_phy_ofdm(dev, 0x07, 0x54);
531 write_phy_ofdm(dev, 0x09, 0x54);
532 } else {
533 write_phy_ofdm(dev, 0x07, 0x50);
534 write_phy_ofdm(dev, 0x09, 0x50);
535 }
536
537 force_pci_posting(dev);
538 mdelay(1);
539 }
540
541 void rtl8225z2_rf_set_chan(struct net_device *dev, short ch)
542 {
543 rtl8225z2_SetTXPowerLevel(dev, ch);
544
545 RF_WriteReg(dev, 0x7, rtl8225_chan[ch]);
546
547 if ((RF_ReadReg(dev, 0x7) & 0x0F80) != rtl8225_chan[ch])
548 RF_WriteReg(dev, 0x7, rtl8225_chan[ch]);
549
550 mdelay(1);
551
552 force_pci_posting(dev);
553 mdelay(10);
554 }
555
556 static void rtl8225_host_pci_init(struct net_device *dev)
557 {
558 write_nic_word(dev, RFPinsOutput, 0x480);
559
560 rtl8185_rf_pins_enable(dev);
561
562 write_nic_word(dev, RFPinsSelect, 0x88 | SW_CONTROL_GPIO);
563
564 write_nic_byte(dev, GP_ENABLE, 0);
565
566 force_pci_posting(dev);
567 mdelay(200);
568
569 /* bit 6 is for RF on/off detection */
570 write_nic_word(dev, GP_ENABLE, 0xff & (~(1 << 6)));
571 }
572
573 static void rtl8225_rf_set_chan(struct net_device *dev, short ch)
574 {
575 struct r8180_priv *priv = ieee80211_priv(dev);
576 short gset = (priv->ieee80211->state == IEEE80211_LINKED &&
577 ieee80211_is_54g(priv->ieee80211->current_network)) ||
578 priv->ieee80211->iw_mode == IW_MODE_MONITOR;
579
580 rtl8225_SetTXPowerLevel(dev, ch);
581
582 write_rtl8225(dev, 0x7, rtl8225_chan[ch]);
583
584 force_pci_posting(dev);
585 mdelay(10);
586
587 if (gset) {
588 write_nic_byte(dev, SIFS, 0x22);
589 write_nic_byte(dev, DIFS, 0x14);
590 } else {
591 write_nic_byte(dev, SIFS, 0x44);
592 write_nic_byte(dev, DIFS, 0x24);
593 }
594
595 if (priv->ieee80211->state == IEEE80211_LINKED &&
596 ieee80211_is_shortslot(priv->ieee80211->current_network))
597 write_nic_byte(dev, SLOT, 0x9);
598 else
599 write_nic_byte(dev, SLOT, 0x14);
600
601 if (gset) {
602 write_nic_byte(dev, EIFS, 81);
603 write_nic_byte(dev, CW_VAL, 0x73);
604 } else {
605 write_nic_byte(dev, EIFS, 81);
606 write_nic_byte(dev, CW_VAL, 0xa5);
607 }
608 }
609
610 void rtl8225z2_rf_init(struct net_device *dev)
611 {
612 struct r8180_priv *priv = ieee80211_priv(dev);
613 int i;
614 short channel = 1;
615 u16 brsr;
616 u32 data,addr;
617
618 priv->chan = channel;
619
620 rtl8225_host_pci_init(dev);
621
622 write_nic_dword(dev, RF_TIMING, 0x000a8008);
623
624 brsr = read_nic_word(dev, BRSR);
625
626 write_nic_word(dev, BRSR, 0xffff);
627
628 write_nic_dword(dev, RF_PARA, 0x100044);
629
630 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
631 write_nic_byte(dev, CONFIG3, 0x44);
632 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
633
634 rtl8185_rf_pins_enable(dev);
635
636 write_rtl8225(dev, 0x0, 0x2bf); mdelay(1);
637 write_rtl8225(dev, 0x1, 0xee0); mdelay(1);
638 write_rtl8225(dev, 0x2, 0x44d); mdelay(1);
639 write_rtl8225(dev, 0x3, 0x441); mdelay(1);
640 write_rtl8225(dev, 0x4, 0x8c3); mdelay(1);
641 write_rtl8225(dev, 0x5, 0xc72); mdelay(1);
642 write_rtl8225(dev, 0x6, 0xe6); mdelay(1);
643 write_rtl8225(dev, 0x7, rtl8225_chan[channel]); mdelay(1);
644 write_rtl8225(dev, 0x8, 0x3f); mdelay(1);
645 write_rtl8225(dev, 0x9, 0x335); mdelay(1);
646 write_rtl8225(dev, 0xa, 0x9d4); mdelay(1);
647 write_rtl8225(dev, 0xb, 0x7bb); mdelay(1);
648 write_rtl8225(dev, 0xc, 0x850); mdelay(1);
649 write_rtl8225(dev, 0xd, 0xcdf); mdelay(1);
650 write_rtl8225(dev, 0xe, 0x2b); mdelay(1);
651 write_rtl8225(dev, 0xf, 0x114);
652
653 mdelay(100);
654
655 write_rtl8225(dev, 0x0, 0x1b7);
656
657 for (i = 0; i < 95; i++) {
658 write_rtl8225(dev, 0x1, (u8)(i + 1));
659 write_rtl8225(dev, 0x2, rtl8225z2_rxgain[i]);
660 }
661
662 write_rtl8225(dev, 0x3, 0x80);
663 write_rtl8225(dev, 0x5, 0x4);
664
665 write_rtl8225(dev, 0x0, 0xb7);
666
667 write_rtl8225(dev, 0x2, 0xc4d);
668
669 /* FIXME!! rtl8187 we have to check if calibrarion
670 * is successful and eventually cal. again (repeat
671 * the two write on reg 2)
672 */
673 data = read_rtl8225(dev, 6);
674 if (!(data & 0x00000080)) {
675 write_rtl8225(dev, 0x02, 0x0c4d);
676 force_pci_posting(dev); mdelay(200);
677 write_rtl8225(dev, 0x02, 0x044d);
678 force_pci_posting(dev); mdelay(100);
679 data = read_rtl8225(dev, 6);
680 if (!(data & 0x00000080))
681 DMESGW("RF Calibration Failed!!!!\n");
682 }
683
684 mdelay(200);
685
686 write_rtl8225(dev, 0x0, 0x2bf);
687
688 for (i = 0; i < 128; i++) {
689 data = rtl8225_agc[i];
690
691 addr = i + 0x80; /* enable writing AGC table */
692 write_phy_ofdm(dev, 0xb, data);
693 mdelay(1);
694
695 write_phy_ofdm(dev, 0xa, addr);
696 mdelay(1);
697 }
698
699 force_pci_posting(dev);
700 mdelay(1);
701
702 write_phy_ofdm(dev, 0x00, 0x01); mdelay(1);
703 write_phy_ofdm(dev, 0x01, 0x02); mdelay(1);
704 write_phy_ofdm(dev, 0x02, 0x62); mdelay(1);
705 write_phy_ofdm(dev, 0x03, 0x00); mdelay(1);
706 write_phy_ofdm(dev, 0x04, 0x00); mdelay(1);
707 write_phy_ofdm(dev, 0x05, 0x00); mdelay(1);
708 write_phy_ofdm(dev, 0x06, 0x40); mdelay(1);
709 write_phy_ofdm(dev, 0x07, 0x00); mdelay(1);
710 write_phy_ofdm(dev, 0x08, 0x40); mdelay(1);
711 write_phy_ofdm(dev, 0x09, 0xfe); mdelay(1);
712 write_phy_ofdm(dev, 0x0a, 0x08); mdelay(1);
713 write_phy_ofdm(dev, 0x0b, 0x80); mdelay(1);
714 write_phy_ofdm(dev, 0x0c, 0x01); mdelay(1);
715 write_phy_ofdm(dev, 0x0d, 0x43);
716 write_phy_ofdm(dev, 0x0e, 0xd3); mdelay(1);
717 write_phy_ofdm(dev, 0x0f, 0x38); mdelay(1);
718 write_phy_ofdm(dev, 0x10, 0x84); mdelay(1);
719 write_phy_ofdm(dev, 0x11, 0x07); mdelay(1);
720 write_phy_ofdm(dev, 0x12, 0x20); mdelay(1);
721 write_phy_ofdm(dev, 0x13, 0x20); mdelay(1);
722 write_phy_ofdm(dev, 0x14, 0x00); mdelay(1);
723 write_phy_ofdm(dev, 0x15, 0x40); mdelay(1);
724 write_phy_ofdm(dev, 0x16, 0x00); mdelay(1);
725 write_phy_ofdm(dev, 0x17, 0x40); mdelay(1);
726 write_phy_ofdm(dev, 0x18, 0xef); mdelay(1);
727 write_phy_ofdm(dev, 0x19, 0x19); mdelay(1);
728 write_phy_ofdm(dev, 0x1a, 0x20); mdelay(1);
729 write_phy_ofdm(dev, 0x1b, 0x15); mdelay(1);
730 write_phy_ofdm(dev, 0x1c, 0x04); mdelay(1);
731 write_phy_ofdm(dev, 0x1d, 0xc5); mdelay(1);
732 write_phy_ofdm(dev, 0x1e, 0x95); mdelay(1);
733 write_phy_ofdm(dev, 0x1f, 0x75); mdelay(1);
734 write_phy_ofdm(dev, 0x20, 0x1f); mdelay(1);
735 write_phy_ofdm(dev, 0x21, 0x17); mdelay(1);
736 write_phy_ofdm(dev, 0x22, 0x16); mdelay(1);
737 write_phy_ofdm(dev, 0x23, 0x80); mdelay(1); /* FIXME maybe not needed */
738 write_phy_ofdm(dev, 0x24, 0x46); mdelay(1);
739 write_phy_ofdm(dev, 0x25, 0x00); mdelay(1);
740 write_phy_ofdm(dev, 0x26, 0x90); mdelay(1);
741 write_phy_ofdm(dev, 0x27, 0x88); mdelay(1);
742
743 rtl8225z2_set_gain(dev,4);
744
745 write_phy_cck(dev, 0x0, 0x98); mdelay(1);
746 write_phy_cck(dev, 0x3, 0x20); mdelay(1);
747 write_phy_cck(dev, 0x4, 0x7e); mdelay(1);
748 write_phy_cck(dev, 0x5, 0x12); mdelay(1);
749 write_phy_cck(dev, 0x6, 0xfc); mdelay(1);
750 write_phy_cck(dev, 0x7, 0x78); mdelay(1);
751 write_phy_cck(dev, 0x8, 0x2e); mdelay(1);
752 write_phy_cck(dev, 0x10, 0x93); mdelay(1);
753 write_phy_cck(dev, 0x11, 0x88); mdelay(1);
754 write_phy_cck(dev, 0x12, 0x47); mdelay(1);
755 write_phy_cck(dev, 0x13, 0xd0);
756 write_phy_cck(dev, 0x19, 0x00);
757 write_phy_cck(dev, 0x1a, 0xa0);
758 write_phy_cck(dev, 0x1b, 0x08);
759 write_phy_cck(dev, 0x40, 0x86); /* CCK Carrier Sense Threshold */
760 write_phy_cck(dev, 0x41, 0x8d); mdelay(1);
761 write_phy_cck(dev, 0x42, 0x15); mdelay(1);
762 write_phy_cck(dev, 0x43, 0x18); mdelay(1);
763 write_phy_cck(dev, 0x44, 0x36); mdelay(1);
764 write_phy_cck(dev, 0x45, 0x35); mdelay(1);
765 write_phy_cck(dev, 0x46, 0x2e); mdelay(1);
766 write_phy_cck(dev, 0x47, 0x25); mdelay(1);
767 write_phy_cck(dev, 0x48, 0x1c); mdelay(1);
768 write_phy_cck(dev, 0x49, 0x12); mdelay(1);
769 write_phy_cck(dev, 0x4a, 0x09); mdelay(1);
770 write_phy_cck(dev, 0x4b, 0x04); mdelay(1);
771 write_phy_cck(dev, 0x4c, 0x05); mdelay(1);
772
773 write_nic_byte(dev, 0x5b, 0x0d); mdelay(1);
774
775 rtl8225z2_SetTXPowerLevel(dev, channel);
776
777 /* RX antenna default to A */
778 write_phy_cck(dev, 0x11, 0x9b); mdelay(1); /* B: 0xDB */
779 write_phy_ofdm(dev, 0x26, 0x90); mdelay(1); /* B: 0x10 */
780
781 rtl8185_tx_antenna(dev, 0x03); /* B: 0x00 */
782
783 /* switch to high-speed 3-wire
784 * last digit. 2 for both cck and ofdm
785 */
786 write_nic_dword(dev, 0x94, 0x15c00002);
787 rtl8185_rf_pins_enable(dev);
788
789 rtl8225_rf_set_chan(dev, priv->chan);
790 }
791
792 void rtl8225z2_rf_set_mode(struct net_device *dev)
793 {
794 struct r8180_priv *priv = ieee80211_priv(dev);
795
796 if (priv->ieee80211->mode == IEEE_A) {
797 write_rtl8225(dev, 0x5, 0x1865);
798 write_nic_dword(dev, RF_PARA, 0x10084);
799 write_nic_dword(dev, RF_TIMING, 0xa8008);
800 write_phy_ofdm(dev, 0x0, 0x0);
801 write_phy_ofdm(dev, 0xa, 0x6);
802 write_phy_ofdm(dev, 0xb, 0x99);
803 write_phy_ofdm(dev, 0xf, 0x20);
804 write_phy_ofdm(dev, 0x11, 0x7);
805
806 rtl8225z2_set_gain(dev,4);
807
808 write_phy_ofdm(dev,0x15, 0x40);
809 write_phy_ofdm(dev,0x17, 0x40);
810
811 write_nic_dword(dev, 0x94,0x10000000);
812 } else {
813 write_rtl8225(dev, 0x5, 0x1864);
814 write_nic_dword(dev, RF_PARA, 0x10044);
815 write_nic_dword(dev, RF_TIMING, 0xa8008);
816 write_phy_ofdm(dev, 0x0, 0x1);
817 write_phy_ofdm(dev, 0xa, 0x6);
818 write_phy_ofdm(dev, 0xb, 0x99);
819 write_phy_ofdm(dev, 0xf, 0x20);
820 write_phy_ofdm(dev, 0x11, 0x7);
821
822 rtl8225z2_set_gain(dev,4);
823
824 write_phy_ofdm(dev,0x15, 0x40);
825 write_phy_ofdm(dev,0x17, 0x40);
826
827 write_nic_dword(dev, 0x94,0x04000002);
828 }
829 }
830
831 #define MAX_DOZE_WAITING_TIMES_85B 20
832 #define MAX_POLLING_24F_TIMES_87SE 10
833 #define LPS_MAX_SLEEP_WAITING_TIMES_87SE 5
834
835 bool SetZebraRFPowerState8185(struct net_device *dev,
836 RT_RF_POWER_STATE eRFPowerState)
837 {
838 struct r8180_priv *priv = ieee80211_priv(dev);
839 u8 btCR9346, btConfig3;
840 bool bActionAllowed = true, bTurnOffBB = true;
841 u8 u1bTmp;
842 int i;
843 bool bResult = true;
844 u8 QueueID;
845
846 if (priv->SetRFPowerStateInProgress == true)
847 return false;
848
849 priv->SetRFPowerStateInProgress = true;
850
851 btCR9346 = read_nic_byte(dev, CR9346);
852 write_nic_byte(dev, CR9346, (btCR9346 | 0xC0));
853
854 btConfig3 = read_nic_byte(dev, CONFIG3);
855 write_nic_byte(dev, CONFIG3, (btConfig3 | CONFIG3_PARM_En));
856
857 switch (eRFPowerState) {
858 case eRfOn:
859 write_nic_word(dev, 0x37C, 0x00EC);
860
861 /* turn on AFE */
862 write_nic_byte(dev, 0x54, 0x00);
863 write_nic_byte(dev, 0x62, 0x00);
864
865 /* turn on RF */
866 RF_WriteReg(dev, 0x0, 0x009f); udelay(500);
867 RF_WriteReg(dev, 0x4, 0x0972); udelay(500);
868
869 /* turn on RF again */
870 RF_WriteReg(dev, 0x0, 0x009f); udelay(500);
871 RF_WriteReg(dev, 0x4, 0x0972); udelay(500);
872
873 /* turn on BB */
874 write_phy_ofdm(dev, 0x10, 0x40);
875 write_phy_ofdm(dev, 0x12, 0x40);
876
877 /* Avoid power down at init time. */
878 write_nic_byte(dev, CONFIG4, priv->RFProgType);
879
880 u1bTmp = read_nic_byte(dev, 0x24E);
881 write_nic_byte(dev, 0x24E, (u1bTmp & (~(BIT5 | BIT6))));
882 break;
883 case eRfSleep:
884 for (QueueID = 0, i = 0; QueueID < 6;) {
885 if (get_curr_tx_free_desc(dev, QueueID) == priv->txringcount) {
886 QueueID++;
887 continue;
888 } else {
889 priv->TxPollingTimes++;
890 if (priv->TxPollingTimes >= LPS_MAX_SLEEP_WAITING_TIMES_87SE) {
891 bActionAllowed = false;
892 break;
893 } else
894 udelay(10);
895 }
896 }
897
898 if (bActionAllowed) {
899 /* turn off BB RXIQ matrix to cut off rx signal */
900 write_phy_ofdm(dev, 0x10, 0x00);
901 write_phy_ofdm(dev, 0x12, 0x00);
902
903 /* turn off RF */
904 RF_WriteReg(dev, 0x4, 0x0000);
905 RF_WriteReg(dev, 0x0, 0x0000);
906
907 /* turn off AFE except PLL */
908 write_nic_byte(dev, 0x62, 0xff);
909 write_nic_byte(dev, 0x54, 0xec);
910
911 mdelay(1);
912
913 {
914 int i = 0;
915 while (true) {
916 u8 tmp24F = read_nic_byte(dev, 0x24f);
917
918 if ((tmp24F == 0x01) || (tmp24F == 0x09)) {
919 bTurnOffBB = true;
920 break;
921 } else {
922 udelay(10);
923 i++;
924 priv->TxPollingTimes++;
925
926 if (priv->TxPollingTimes >= LPS_MAX_SLEEP_WAITING_TIMES_87SE) {
927 bTurnOffBB = false;
928 break;
929 } else
930 udelay(10);
931 }
932 }
933 }
934
935 if (bTurnOffBB) {
936 /* turn off BB */
937 u1bTmp = read_nic_byte(dev, 0x24E);
938 write_nic_byte(dev, 0x24E, (u1bTmp | BIT5 | BIT6));
939
940 /* turn off AFE PLL */
941 write_nic_byte(dev, 0x54, 0xFC);
942 write_nic_word(dev, 0x37C, 0x00FC);
943 }
944 }
945 break;
946 case eRfOff:
947 for (QueueID = 0, i = 0; QueueID < 6;) {
948 if (get_curr_tx_free_desc(dev, QueueID) == priv->txringcount) {
949 QueueID++;
950 continue;
951 } else {
952 udelay(10);
953 i++;
954 }
955
956 if (i >= MAX_DOZE_WAITING_TIMES_85B)
957 break;
958 }
959
960 /* turn off BB RXIQ matrix to cut off rx signal */
961 write_phy_ofdm(dev, 0x10, 0x00);
962 write_phy_ofdm(dev, 0x12, 0x00);
963
964 /* turn off RF */
965 RF_WriteReg(dev, 0x4, 0x0000);
966 RF_WriteReg(dev, 0x0, 0x0000);
967
968 /* turn off AFE except PLL */
969 write_nic_byte(dev, 0x62, 0xff);
970 write_nic_byte(dev, 0x54, 0xec);
971
972 mdelay(1);
973
974 {
975 int i = 0;
976
977 while (true) {
978 u8 tmp24F = read_nic_byte(dev, 0x24f);
979
980 if ((tmp24F == 0x01) || (tmp24F == 0x09)) {
981 bTurnOffBB = true;
982 break;
983 } else {
984 bTurnOffBB = false;
985 udelay(10);
986 i++;
987 }
988
989 if (i > MAX_POLLING_24F_TIMES_87SE)
990 break;
991 }
992 }
993
994 if (bTurnOffBB) {
995 /* turn off BB */
996 u1bTmp = read_nic_byte(dev, 0x24E);
997 write_nic_byte(dev, 0x24E, (u1bTmp | BIT5 | BIT6));
998
999 /* turn off AFE PLL (80M) */
1000 write_nic_byte(dev, 0x54, 0xFC);
1001 write_nic_word(dev, 0x37C, 0x00FC);
1002 }
1003 break;
1004 }
1005
1006 btConfig3 &= ~(CONFIG3_PARM_En);
1007 write_nic_byte(dev, CONFIG3, btConfig3);
1008
1009 btCR9346 &= ~(0xC0);
1010 write_nic_byte(dev, CR9346, btCR9346);
1011
1012 if (bResult && bActionAllowed)
1013 priv->eRFPowerState = eRFPowerState;
1014
1015 priv->SetRFPowerStateInProgress = false;
1016
1017 return bResult && bActionAllowed;
1018 }
1019
1020 void rtl8225z4_rf_sleep(struct net_device *dev)
1021 {
1022 MgntActSet_RF_State(dev, eRfSleep, RF_CHANGE_BY_PS);
1023 }
1024
1025 void rtl8225z4_rf_wakeup(struct net_device *dev)
1026 {
1027 MgntActSet_RF_State(dev, eRfOn, RF_CHANGE_BY_PS);
1028 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree