2 * Driver for the Conexant CX25821 PCIe bridge
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 * Based on Steven Toth <stoth@linuxtv.org> cx23885 driver
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/i2c.h>
25 #include <linux/slab.h>
27 #include "cx25821-sram.h"
28 #include "cx25821-video.h"
30 MODULE_DESCRIPTION("Driver for Athena cards");
31 MODULE_AUTHOR("Shu Lin - Hiep Huynh");
32 MODULE_LICENSE("GPL");
34 struct list_head cx25821_devlist
;
36 static unsigned int debug
;
37 module_param(debug
, int, 0644);
38 MODULE_PARM_DESC(debug
, "enable debug messages");
40 static unsigned int card
[] = {[0 ... (CX25821_MAXBOARDS
- 1)] = UNSET
};
41 module_param_array(card
, int, NULL
, 0444);
42 MODULE_PARM_DESC(card
, "card type");
44 static unsigned int cx25821_devcount
= 0;
46 static DEFINE_MUTEX(devlist
);
47 LIST_HEAD(cx25821_devlist
);
49 struct sram_channel cx25821_sram_channels
[] = {
53 .cmds_start
= VID_A_DOWN_CMDS
,
54 .ctrl_start
= VID_A_IQ
,
56 .fifo_start
= VID_A_DOWN_CLUSTER_1
,
57 .fifo_size
= (VID_CLUSTER_SIZE
<< 2),
58 .ptr1_reg
= DMA1_PTR1
,
59 .ptr2_reg
= DMA1_PTR2
,
60 .cnt1_reg
= DMA1_CNT1
,
61 .cnt2_reg
= DMA1_CNT2
,
62 .int_msk
= VID_A_INT_MSK
,
63 .int_stat
= VID_A_INT_STAT
,
64 .int_mstat
= VID_A_INT_MSTAT
,
65 .dma_ctl
= VID_DST_A_DMA_CTL
,
66 .gpcnt_ctl
= VID_DST_A_GPCNT_CTL
,
67 .gpcnt
= VID_DST_A_GPCNT
,
68 .vip_ctl
= VID_DST_A_VIP_CTL
,
69 .pix_frmt
= VID_DST_A_PIX_FRMT
,
75 .cmds_start
= VID_B_DOWN_CMDS
,
76 .ctrl_start
= VID_B_IQ
,
78 .fifo_start
= VID_B_DOWN_CLUSTER_1
,
79 .fifo_size
= (VID_CLUSTER_SIZE
<< 2),
80 .ptr1_reg
= DMA2_PTR1
,
81 .ptr2_reg
= DMA2_PTR2
,
82 .cnt1_reg
= DMA2_CNT1
,
83 .cnt2_reg
= DMA2_CNT2
,
84 .int_msk
= VID_B_INT_MSK
,
85 .int_stat
= VID_B_INT_STAT
,
86 .int_mstat
= VID_B_INT_MSTAT
,
87 .dma_ctl
= VID_DST_B_DMA_CTL
,
88 .gpcnt_ctl
= VID_DST_B_GPCNT_CTL
,
89 .gpcnt
= VID_DST_B_GPCNT
,
90 .vip_ctl
= VID_DST_B_VIP_CTL
,
91 .pix_frmt
= VID_DST_B_PIX_FRMT
,
97 .cmds_start
= VID_C_DOWN_CMDS
,
98 .ctrl_start
= VID_C_IQ
,
100 .fifo_start
= VID_C_DOWN_CLUSTER_1
,
101 .fifo_size
= (VID_CLUSTER_SIZE
<< 2),
102 .ptr1_reg
= DMA3_PTR1
,
103 .ptr2_reg
= DMA3_PTR2
,
104 .cnt1_reg
= DMA3_CNT1
,
105 .cnt2_reg
= DMA3_CNT2
,
106 .int_msk
= VID_C_INT_MSK
,
107 .int_stat
= VID_C_INT_STAT
,
108 .int_mstat
= VID_C_INT_MSTAT
,
109 .dma_ctl
= VID_DST_C_DMA_CTL
,
110 .gpcnt_ctl
= VID_DST_C_GPCNT_CTL
,
111 .gpcnt
= VID_DST_C_GPCNT
,
112 .vip_ctl
= VID_DST_C_VIP_CTL
,
113 .pix_frmt
= VID_DST_C_PIX_FRMT
,
119 .cmds_start
= VID_D_DOWN_CMDS
,
120 .ctrl_start
= VID_D_IQ
,
122 .fifo_start
= VID_D_DOWN_CLUSTER_1
,
123 .fifo_size
= (VID_CLUSTER_SIZE
<< 2),
124 .ptr1_reg
= DMA4_PTR1
,
125 .ptr2_reg
= DMA4_PTR2
,
126 .cnt1_reg
= DMA4_CNT1
,
127 .cnt2_reg
= DMA4_CNT2
,
128 .int_msk
= VID_D_INT_MSK
,
129 .int_stat
= VID_D_INT_STAT
,
130 .int_mstat
= VID_D_INT_MSTAT
,
131 .dma_ctl
= VID_DST_D_DMA_CTL
,
132 .gpcnt_ctl
= VID_DST_D_GPCNT_CTL
,
133 .gpcnt
= VID_DST_D_GPCNT
,
134 .vip_ctl
= VID_DST_D_VIP_CTL
,
135 .pix_frmt
= VID_DST_D_PIX_FRMT
,
141 .cmds_start
= VID_E_DOWN_CMDS
,
142 .ctrl_start
= VID_E_IQ
,
144 .fifo_start
= VID_E_DOWN_CLUSTER_1
,
145 .fifo_size
= (VID_CLUSTER_SIZE
<< 2),
146 .ptr1_reg
= DMA5_PTR1
,
147 .ptr2_reg
= DMA5_PTR2
,
148 .cnt1_reg
= DMA5_CNT1
,
149 .cnt2_reg
= DMA5_CNT2
,
150 .int_msk
= VID_E_INT_MSK
,
151 .int_stat
= VID_E_INT_STAT
,
152 .int_mstat
= VID_E_INT_MSTAT
,
153 .dma_ctl
= VID_DST_E_DMA_CTL
,
154 .gpcnt_ctl
= VID_DST_E_GPCNT_CTL
,
155 .gpcnt
= VID_DST_E_GPCNT
,
156 .vip_ctl
= VID_DST_E_VIP_CTL
,
157 .pix_frmt
= VID_DST_E_PIX_FRMT
,
163 .cmds_start
= VID_F_DOWN_CMDS
,
164 .ctrl_start
= VID_F_IQ
,
166 .fifo_start
= VID_F_DOWN_CLUSTER_1
,
167 .fifo_size
= (VID_CLUSTER_SIZE
<< 2),
168 .ptr1_reg
= DMA6_PTR1
,
169 .ptr2_reg
= DMA6_PTR2
,
170 .cnt1_reg
= DMA6_CNT1
,
171 .cnt2_reg
= DMA6_CNT2
,
172 .int_msk
= VID_F_INT_MSK
,
173 .int_stat
= VID_F_INT_STAT
,
174 .int_mstat
= VID_F_INT_MSTAT
,
175 .dma_ctl
= VID_DST_F_DMA_CTL
,
176 .gpcnt_ctl
= VID_DST_F_GPCNT_CTL
,
177 .gpcnt
= VID_DST_F_GPCNT
,
178 .vip_ctl
= VID_DST_F_VIP_CTL
,
179 .pix_frmt
= VID_DST_F_PIX_FRMT
,
185 .cmds_start
= VID_G_DOWN_CMDS
,
186 .ctrl_start
= VID_G_IQ
,
188 .fifo_start
= VID_G_DOWN_CLUSTER_1
,
189 .fifo_size
= (VID_CLUSTER_SIZE
<< 2),
190 .ptr1_reg
= DMA7_PTR1
,
191 .ptr2_reg
= DMA7_PTR2
,
192 .cnt1_reg
= DMA7_CNT1
,
193 .cnt2_reg
= DMA7_CNT2
,
194 .int_msk
= VID_G_INT_MSK
,
195 .int_stat
= VID_G_INT_STAT
,
196 .int_mstat
= VID_G_INT_MSTAT
,
197 .dma_ctl
= VID_DST_G_DMA_CTL
,
198 .gpcnt_ctl
= VID_DST_G_GPCNT_CTL
,
199 .gpcnt
= VID_DST_G_GPCNT
,
200 .vip_ctl
= VID_DST_G_VIP_CTL
,
201 .pix_frmt
= VID_DST_G_PIX_FRMT
,
207 .cmds_start
= VID_H_DOWN_CMDS
,
208 .ctrl_start
= VID_H_IQ
,
210 .fifo_start
= VID_H_DOWN_CLUSTER_1
,
211 .fifo_size
= (VID_CLUSTER_SIZE
<< 2),
212 .ptr1_reg
= DMA8_PTR1
,
213 .ptr2_reg
= DMA8_PTR2
,
214 .cnt1_reg
= DMA8_CNT1
,
215 .cnt2_reg
= DMA8_CNT2
,
216 .int_msk
= VID_H_INT_MSK
,
217 .int_stat
= VID_H_INT_STAT
,
218 .int_mstat
= VID_H_INT_MSTAT
,
219 .dma_ctl
= VID_DST_H_DMA_CTL
,
220 .gpcnt_ctl
= VID_DST_H_GPCNT_CTL
,
221 .gpcnt
= VID_DST_H_GPCNT
,
222 .vip_ctl
= VID_DST_H_VIP_CTL
,
223 .pix_frmt
= VID_DST_H_PIX_FRMT
,
227 .name
= "audio from",
228 .cmds_start
= AUD_A_DOWN_CMDS
,
229 .ctrl_start
= AUD_A_IQ
,
231 .fifo_start
= AUD_A_DOWN_CLUSTER_1
,
232 .fifo_size
= AUDIO_CLUSTER_SIZE
* 3,
233 .ptr1_reg
= DMA17_PTR1
,
234 .ptr2_reg
= DMA17_PTR2
,
235 .cnt1_reg
= DMA17_CNT1
,
236 .cnt2_reg
= DMA17_CNT2
,
241 .name
= "VID Upstream I",
242 .cmds_start
= VID_I_UP_CMDS
,
243 .ctrl_start
= VID_I_IQ
,
245 .fifo_start
= VID_I_UP_CLUSTER_1
,
246 .fifo_size
= (VID_CLUSTER_SIZE
<< 2),
247 .ptr1_reg
= DMA15_PTR1
,
248 .ptr2_reg
= DMA15_PTR2
,
249 .cnt1_reg
= DMA15_CNT1
,
250 .cnt2_reg
= DMA15_CNT2
,
251 .int_msk
= VID_I_INT_MSK
,
252 .int_stat
= VID_I_INT_STAT
,
253 .int_mstat
= VID_I_INT_MSTAT
,
254 .dma_ctl
= VID_SRC_I_DMA_CTL
,
255 .gpcnt_ctl
= VID_SRC_I_GPCNT_CTL
,
256 .gpcnt
= VID_SRC_I_GPCNT
,
258 .vid_fmt_ctl
= VID_SRC_I_FMT_CTL
,
259 .vid_active_ctl1
= VID_SRC_I_ACTIVE_CTL1
,
260 .vid_active_ctl2
= VID_SRC_I_ACTIVE_CTL2
,
261 .vid_cdt_size
= VID_SRC_I_CDT_SZ
,
267 .name
= "VID Upstream J",
268 .cmds_start
= VID_J_UP_CMDS
,
269 .ctrl_start
= VID_J_IQ
,
271 .fifo_start
= VID_J_UP_CLUSTER_1
,
272 .fifo_size
= (VID_CLUSTER_SIZE
<< 2),
273 .ptr1_reg
= DMA16_PTR1
,
274 .ptr2_reg
= DMA16_PTR2
,
275 .cnt1_reg
= DMA16_CNT1
,
276 .cnt2_reg
= DMA16_CNT2
,
277 .int_msk
= VID_J_INT_MSK
,
278 .int_stat
= VID_J_INT_STAT
,
279 .int_mstat
= VID_J_INT_MSTAT
,
280 .dma_ctl
= VID_SRC_J_DMA_CTL
,
281 .gpcnt_ctl
= VID_SRC_J_GPCNT_CTL
,
282 .gpcnt
= VID_SRC_J_GPCNT
,
284 .vid_fmt_ctl
= VID_SRC_J_FMT_CTL
,
285 .vid_active_ctl1
= VID_SRC_J_ACTIVE_CTL1
,
286 .vid_active_ctl2
= VID_SRC_J_ACTIVE_CTL2
,
287 .vid_cdt_size
= VID_SRC_J_CDT_SZ
,
293 .name
= "Audio Upstream Channel B",
294 .cmds_start
= AUD_B_UP_CMDS
,
295 .ctrl_start
= AUD_B_IQ
,
297 .fifo_start
= AUD_B_UP_CLUSTER_1
,
298 .fifo_size
= (AUDIO_CLUSTER_SIZE
* 3),
299 .ptr1_reg
= DMA22_PTR1
,
300 .ptr2_reg
= DMA22_PTR2
,
301 .cnt1_reg
= DMA22_CNT1
,
302 .cnt2_reg
= DMA22_CNT2
,
303 .int_msk
= AUD_B_INT_MSK
,
304 .int_stat
= AUD_B_INT_STAT
,
305 .int_mstat
= AUD_B_INT_MSTAT
,
306 .dma_ctl
= AUD_INT_DMA_CTL
,
307 .gpcnt_ctl
= AUD_B_GPCNT_CTL
,
308 .gpcnt
= AUD_B_GPCNT
,
309 .aud_length
= AUD_B_LNGTH
,
310 .aud_cfg
= AUD_B_CFG
,
311 .fld_aud_fifo_en
= FLD_AUD_SRC_B_FIFO_EN
,
312 .fld_aud_risc_en
= FLD_AUD_SRC_B_RISC_EN
,
317 struct sram_channel
*channel0
= &cx25821_sram_channels
[SRAM_CH00
];
318 struct sram_channel
*channel1
= &cx25821_sram_channels
[SRAM_CH01
];
319 struct sram_channel
*channel2
= &cx25821_sram_channels
[SRAM_CH02
];
320 struct sram_channel
*channel3
= &cx25821_sram_channels
[SRAM_CH03
];
321 struct sram_channel
*channel4
= &cx25821_sram_channels
[SRAM_CH04
];
322 struct sram_channel
*channel5
= &cx25821_sram_channels
[SRAM_CH05
];
323 struct sram_channel
*channel6
= &cx25821_sram_channels
[SRAM_CH06
];
324 struct sram_channel
*channel7
= &cx25821_sram_channels
[SRAM_CH07
];
325 struct sram_channel
*channel9
= &cx25821_sram_channels
[SRAM_CH09
];
326 struct sram_channel
*channel10
= &cx25821_sram_channels
[SRAM_CH10
];
327 struct sram_channel
*channel11
= &cx25821_sram_channels
[SRAM_CH11
];
329 struct cx25821_dmaqueue mpegq
;
331 static int cx25821_risc_decode(u32 risc
)
333 static char *instr
[16] = {
334 [RISC_SYNC
>> 28] = "sync",
335 [RISC_WRITE
>> 28] = "write",
336 [RISC_WRITEC
>> 28] = "writec",
337 [RISC_READ
>> 28] = "read",
338 [RISC_READC
>> 28] = "readc",
339 [RISC_JUMP
>> 28] = "jump",
340 [RISC_SKIP
>> 28] = "skip",
341 [RISC_WRITERM
>> 28] = "writerm",
342 [RISC_WRITECM
>> 28] = "writecm",
343 [RISC_WRITECR
>> 28] = "writecr",
345 static int incr
[16] = {
346 [RISC_WRITE
>> 28] = 3,
347 [RISC_JUMP
>> 28] = 3,
348 [RISC_SKIP
>> 28] = 1,
349 [RISC_SYNC
>> 28] = 1,
350 [RISC_WRITERM
>> 28] = 3,
351 [RISC_WRITECM
>> 28] = 3,
352 [RISC_WRITECR
>> 28] = 4,
354 static char *bits
[] = {
355 "12", "13", "14", "resync",
356 "cnt0", "cnt1", "18", "19",
357 "20", "21", "22", "23",
358 "irq1", "irq2", "eol", "sol",
362 printk("0x%08x [ %s", risc
,
363 instr
[risc
>> 28] ? instr
[risc
>> 28] : "INVALID");
364 for (i
= ARRAY_SIZE(bits
) - 1; i
>= 0; i
--) {
365 if (risc
& (1 << (i
+ 12)))
366 printk(" %s", bits
[i
]);
368 printk(" count=%d ]\n", risc
& 0xfff);
369 return incr
[risc
>> 28] ? incr
[risc
>> 28] : 1;
372 static inline int i2c_slave_did_ack(struct i2c_adapter
*i2c_adap
)
374 struct cx25821_i2c
*bus
= i2c_adap
->algo_data
;
375 struct cx25821_dev
*dev
= bus
->dev
;
376 return cx_read(bus
->reg_stat
) & 0x01;
379 void cx_i2c_read_print(struct cx25821_dev
*dev
, u32 reg
, const char *reg_string
)
384 value
= cx25821_i2c_read(&dev
->i2c_bus
[0], reg
, &tmp
);
387 static void cx25821_registers_init(struct cx25821_dev
*dev
)
391 // enable RUN_RISC in Pecos
392 cx_write(DEV_CNTRL2
, 0x20);
394 // Set the master PCI interrupt masks to enable video, audio, MBIF, and GPIO interrupts
395 // I2C interrupt masking is handled by the I2C objects themselves.
396 cx_write(PCI_INT_MSK
, 0x2001FFFF);
398 tmp
= cx_read(RDR_TLCTL0
);
399 tmp
&= ~FLD_CFG_RCB_CK_EN
; // Clear the RCB_CK_EN bit
400 cx_write(RDR_TLCTL0
, tmp
);
402 // PLL-A setting for the Audio Master Clock
403 cx_write(PLL_A_INT_FRAC
, 0x9807A58B);
405 // PLL_A_POST = 0x1C, PLL_A_OUT_TO_PIN = 0x1
406 cx_write(PLL_A_POST_STAT_BIST
, 0x8000019C);
408 // clear reset bit [31]
409 tmp
= cx_read(PLL_A_INT_FRAC
);
410 cx_write(PLL_A_INT_FRAC
, tmp
& 0x7FFFFFFF);
412 // PLL-B setting for Mobilygen Host Bus Interface
413 cx_write(PLL_B_INT_FRAC
, 0x9883A86F);
415 // PLL_B_POST = 0xD, PLL_B_OUT_TO_PIN = 0x0
416 cx_write(PLL_B_POST_STAT_BIST
, 0x8000018D);
418 // clear reset bit [31]
419 tmp
= cx_read(PLL_B_INT_FRAC
);
420 cx_write(PLL_B_INT_FRAC
, tmp
& 0x7FFFFFFF);
422 // PLL-C setting for video upstream channel
423 cx_write(PLL_C_INT_FRAC
, 0x96A0EA3F);
425 // PLL_C_POST = 0x3, PLL_C_OUT_TO_PIN = 0x0
426 cx_write(PLL_C_POST_STAT_BIST
, 0x80000103);
428 // clear reset bit [31]
429 tmp
= cx_read(PLL_C_INT_FRAC
);
430 cx_write(PLL_C_INT_FRAC
, tmp
& 0x7FFFFFFF);
432 // PLL-D setting for audio upstream channel
433 cx_write(PLL_D_INT_FRAC
, 0x98757F5B);
435 // PLL_D_POST = 0x13, PLL_D_OUT_TO_PIN = 0x0
436 cx_write(PLL_D_POST_STAT_BIST
, 0x80000113);
438 // clear reset bit [31]
439 tmp
= cx_read(PLL_D_INT_FRAC
);
440 cx_write(PLL_D_INT_FRAC
, tmp
& 0x7FFFFFFF);
442 // This selects the PLL C clock source for the video upstream channel I and J
443 tmp
= cx_read(VID_CH_CLK_SEL
);
444 cx_write(VID_CH_CLK_SEL
, (tmp
& 0x00FFFFFF) | 0x24000000);
446 // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C
447 //select 656/VIP DST for downstream Channel A - C
448 tmp
= cx_read(VID_CH_MODE_SEL
);
449 //cx_write( VID_CH_MODE_SEL, tmp | 0x1B0001FF);
450 cx_write(VID_CH_MODE_SEL
, tmp
& 0xFFFFFE00);
452 // enables 656 port I and J as output
453 tmp
= cx_read(CLK_RST
);
454 tmp
|= FLD_USE_ALT_PLL_REF
; // use external ALT_PLL_REF pin as its reference clock instead
455 cx_write(CLK_RST
, tmp
& ~(FLD_VID_I_CLK_NOE
| FLD_VID_J_CLK_NOE
));
460 int cx25821_sram_channel_setup(struct cx25821_dev
*dev
,
461 struct sram_channel
*ch
,
462 unsigned int bpl
, u32 risc
)
464 unsigned int i
, lines
;
467 if (ch
->cmds_start
== 0) {
468 cx_write(ch
->ptr1_reg
, 0);
469 cx_write(ch
->ptr2_reg
, 0);
470 cx_write(ch
->cnt2_reg
, 0);
471 cx_write(ch
->cnt1_reg
, 0);
475 bpl
= (bpl
+ 7) & ~7; /* alignment */
477 lines
= ch
->fifo_size
/ bpl
;
485 cx_write(8 + 0, RISC_JUMP
| RISC_IRQ1
| RISC_CNT_INC
);
490 for (i
= 0; i
< lines
; i
++) {
491 cx_write(cdt
+ 16 * i
, ch
->fifo_start
+ bpl
* i
);
492 cx_write(cdt
+ 16 * i
+ 4, 0);
493 cx_write(cdt
+ 16 * i
+ 8, 0);
494 cx_write(cdt
+ 16 * i
+ 12, 0);
497 //init the first cdt buffer
498 for (i
= 0; i
< 128; i
++)
499 cx_write(ch
->fifo_start
+ 4 * i
, i
);
503 cx_write(ch
->cmds_start
+ 0, 8);
505 cx_write(ch
->cmds_start
+ 0, risc
);
508 cx_write(ch
->cmds_start
+ 4, 0); /* 64 bits 63-32 */
509 cx_write(ch
->cmds_start
+ 8, cdt
);
510 cx_write(ch
->cmds_start
+ 12, (lines
* 16) >> 3);
511 cx_write(ch
->cmds_start
+ 16, ch
->ctrl_start
);
514 cx_write(ch
->cmds_start
+ 20, 0x80000000 | (64 >> 2));
516 cx_write(ch
->cmds_start
+ 20, 64 >> 2);
518 for (i
= 24; i
< 80; i
+= 4)
519 cx_write(ch
->cmds_start
+ i
, 0);
522 cx_write(ch
->ptr1_reg
, ch
->fifo_start
);
523 cx_write(ch
->ptr2_reg
, cdt
);
524 cx_write(ch
->cnt2_reg
, (lines
* 16) >> 3);
525 cx_write(ch
->cnt1_reg
, (bpl
>> 3) - 1);
530 int cx25821_sram_channel_setup_audio(struct cx25821_dev
*dev
,
531 struct sram_channel
*ch
,
532 unsigned int bpl
, u32 risc
)
534 unsigned int i
, lines
;
537 if (ch
->cmds_start
== 0) {
538 cx_write(ch
->ptr1_reg
, 0);
539 cx_write(ch
->ptr2_reg
, 0);
540 cx_write(ch
->cnt2_reg
, 0);
541 cx_write(ch
->cnt1_reg
, 0);
545 bpl
= (bpl
+ 7) & ~7; /* alignment */
547 lines
= ch
->fifo_size
/ bpl
;
550 lines
= 3; //for AUDIO
555 cx_write(8 + 0, RISC_JUMP
| RISC_IRQ1
| RISC_CNT_INC
);
560 for (i
= 0; i
< lines
; i
++) {
561 cx_write(cdt
+ 16 * i
, ch
->fifo_start
+ bpl
* i
);
562 cx_write(cdt
+ 16 * i
+ 4, 0);
563 cx_write(cdt
+ 16 * i
+ 8, 0);
564 cx_write(cdt
+ 16 * i
+ 12, 0);
569 cx_write(ch
->cmds_start
+ 0, 8);
571 cx_write(ch
->cmds_start
+ 0, risc
);
574 cx_write(ch
->cmds_start
+ 4, 0); /* 64 bits 63-32 */
575 cx_write(ch
->cmds_start
+ 8, cdt
);
576 cx_write(ch
->cmds_start
+ 12, (lines
* 16) >> 3);
577 cx_write(ch
->cmds_start
+ 16, ch
->ctrl_start
);
581 cx_write(ch
->cmds_start
+ 20, 0x80000000 | (64 >> 2));
583 cx_write(ch
->cmds_start
+ 20, 64 >> 2);
587 for (i
= 24; i
< 80; i
+= 4)
588 cx_write(ch
->cmds_start
+ i
, 0);
591 cx_write(ch
->ptr1_reg
, ch
->fifo_start
);
592 cx_write(ch
->ptr2_reg
, cdt
);
593 cx_write(ch
->cnt2_reg
, (lines
* 16) >> 3);
594 cx_write(ch
->cnt1_reg
, (bpl
>> 3) - 1);
599 void cx25821_sram_channel_dump(struct cx25821_dev
*dev
, struct sram_channel
*ch
)
601 static char *name
[] = {
618 unsigned int i
, j
, n
;
620 printk(KERN_WARNING
"%s: %s - dma channel status dump\n", dev
->name
,
622 for (i
= 0; i
< ARRAY_SIZE(name
); i
++)
623 printk(KERN_WARNING
"cmds + 0x%2x: %-15s: 0x%08x\n", i
* 4,
624 name
[i
], cx_read(ch
->cmds_start
+ 4 * i
));
627 for (i
= 0; i
< 4;) {
628 risc
= cx_read(ch
->cmds_start
+ 4 * (i
+ 14));
629 printk(KERN_WARNING
"cmds + 0x%2x: risc%d: ", j
+ i
* 4, i
);
630 i
+= cx25821_risc_decode(risc
);
633 for (i
= 0; i
< (64 >> 2); i
+= n
) {
634 risc
= cx_read(ch
->ctrl_start
+ 4 * i
);
635 /* No consideration for bits 63-32 */
637 printk(KERN_WARNING
"ctrl + 0x%2x (0x%08x): iq %x: ", i
* 4,
638 ch
->ctrl_start
+ 4 * i
, i
);
639 n
= cx25821_risc_decode(risc
);
640 for (j
= 1; j
< n
; j
++) {
641 risc
= cx_read(ch
->ctrl_start
+ 4 * (i
+ j
));
643 "ctrl + 0x%2x : iq %x: 0x%08x [ arg #%d ]\n",
644 4 * (i
+ j
), i
+ j
, risc
, j
);
648 printk(KERN_WARNING
" : fifo: 0x%08x -> 0x%x\n",
649 ch
->fifo_start
, ch
->fifo_start
+ ch
->fifo_size
);
650 printk(KERN_WARNING
" : ctrl: 0x%08x -> 0x%x\n",
651 ch
->ctrl_start
, ch
->ctrl_start
+ 6 * 16);
652 printk(KERN_WARNING
" : ptr1_reg: 0x%08x\n",
653 cx_read(ch
->ptr1_reg
));
654 printk(KERN_WARNING
" : ptr2_reg: 0x%08x\n",
655 cx_read(ch
->ptr2_reg
));
656 printk(KERN_WARNING
" : cnt1_reg: 0x%08x\n",
657 cx_read(ch
->cnt1_reg
));
658 printk(KERN_WARNING
" : cnt2_reg: 0x%08x\n",
659 cx_read(ch
->cnt2_reg
));
662 void cx25821_sram_channel_dump_audio(struct cx25821_dev
*dev
,
663 struct sram_channel
*ch
)
665 static char *name
[] = {
682 u32 risc
, value
, tmp
;
683 unsigned int i
, j
, n
;
685 printk(KERN_INFO
"\n%s: %s - dma Audio channel status dump\n",
686 dev
->name
, ch
->name
);
688 for (i
= 0; i
< ARRAY_SIZE(name
); i
++)
689 printk(KERN_INFO
"%s: cmds + 0x%2x: %-15s: 0x%08x\n",
690 dev
->name
, i
* 4, name
[i
],
691 cx_read(ch
->cmds_start
+ 4 * i
));
694 for (i
= 0; i
< 4;) {
695 risc
= cx_read(ch
->cmds_start
+ 4 * (i
+ 14));
696 printk(KERN_WARNING
"cmds + 0x%2x: risc%d: ", j
+ i
* 4, i
);
697 i
+= cx25821_risc_decode(risc
);
700 for (i
= 0; i
< (64 >> 2); i
+= n
) {
701 risc
= cx_read(ch
->ctrl_start
+ 4 * i
);
702 /* No consideration for bits 63-32 */
704 printk(KERN_WARNING
"ctrl + 0x%2x (0x%08x): iq %x: ", i
* 4,
705 ch
->ctrl_start
+ 4 * i
, i
);
706 n
= cx25821_risc_decode(risc
);
708 for (j
= 1; j
< n
; j
++) {
709 risc
= cx_read(ch
->ctrl_start
+ 4 * (i
+ j
));
711 "ctrl + 0x%2x : iq %x: 0x%08x [ arg #%d ]\n",
712 4 * (i
+ j
), i
+ j
, risc
, j
);
716 printk(KERN_WARNING
" : fifo: 0x%08x -> 0x%x\n",
717 ch
->fifo_start
, ch
->fifo_start
+ ch
->fifo_size
);
718 printk(KERN_WARNING
" : ctrl: 0x%08x -> 0x%x\n",
719 ch
->ctrl_start
, ch
->ctrl_start
+ 6 * 16);
720 printk(KERN_WARNING
" : ptr1_reg: 0x%08x\n",
721 cx_read(ch
->ptr1_reg
));
722 printk(KERN_WARNING
" : ptr2_reg: 0x%08x\n",
723 cx_read(ch
->ptr2_reg
));
724 printk(KERN_WARNING
" : cnt1_reg: 0x%08x\n",
725 cx_read(ch
->cnt1_reg
));
726 printk(KERN_WARNING
" : cnt2_reg: 0x%08x\n",
727 cx_read(ch
->cnt2_reg
));
729 for (i
= 0; i
< 4; i
++) {
730 risc
= cx_read(ch
->cmds_start
+ 56 + (i
* 4));
731 printk(KERN_WARNING
"instruction %d = 0x%x\n", i
, risc
);
734 //read data from the first cdt buffer
735 risc
= cx_read(AUD_A_CDT
);
736 printk(KERN_WARNING
"\nread cdt loc=0x%x\n", risc
);
737 for (i
= 0; i
< 8; i
++) {
738 n
= cx_read(risc
+ i
* 4);
739 printk(KERN_WARNING
"0x%x ", n
);
741 printk(KERN_WARNING
"\n\n");
743 value
= cx_read(CLK_RST
);
744 CX25821_INFO(" CLK_RST = 0x%x \n\n", value
);
746 value
= cx_read(PLL_A_POST_STAT_BIST
);
747 CX25821_INFO(" PLL_A_POST_STAT_BIST = 0x%x \n\n", value
);
748 value
= cx_read(PLL_A_INT_FRAC
);
749 CX25821_INFO(" PLL_A_INT_FRAC = 0x%x \n\n", value
);
751 value
= cx_read(PLL_B_POST_STAT_BIST
);
752 CX25821_INFO(" PLL_B_POST_STAT_BIST = 0x%x \n\n", value
);
753 value
= cx_read(PLL_B_INT_FRAC
);
754 CX25821_INFO(" PLL_B_INT_FRAC = 0x%x \n\n", value
);
756 value
= cx_read(PLL_C_POST_STAT_BIST
);
757 CX25821_INFO(" PLL_C_POST_STAT_BIST = 0x%x \n\n", value
);
758 value
= cx_read(PLL_C_INT_FRAC
);
759 CX25821_INFO(" PLL_C_INT_FRAC = 0x%x \n\n", value
);
761 value
= cx_read(PLL_D_POST_STAT_BIST
);
762 CX25821_INFO(" PLL_D_POST_STAT_BIST = 0x%x \n\n", value
);
763 value
= cx_read(PLL_D_INT_FRAC
);
764 CX25821_INFO(" PLL_D_INT_FRAC = 0x%x \n\n", value
);
766 value
= cx25821_i2c_read(&dev
->i2c_bus
[0], AFE_AB_DIAG_CTRL
, &tmp
);
767 CX25821_INFO(" AFE_AB_DIAG_CTRL (0x10900090) = 0x%x \n\n", value
);
770 static void cx25821_shutdown(struct cx25821_dev
*dev
)
774 /* disable RISC controller */
775 cx_write(DEV_CNTRL2
, 0);
777 /* Disable Video A/B activity */
778 for (i
= 0; i
< VID_CHANNEL_NUM
; i
++) {
779 cx_write(dev
->sram_channels
[i
].dma_ctl
, 0);
780 cx_write(dev
->sram_channels
[i
].int_msk
, 0);
783 for (i
= VID_UPSTREAM_SRAM_CHANNEL_I
; i
<= VID_UPSTREAM_SRAM_CHANNEL_J
;
785 cx_write(dev
->sram_channels
[i
].dma_ctl
, 0);
786 cx_write(dev
->sram_channels
[i
].int_msk
, 0);
789 /* Disable Audio activity */
790 cx_write(AUD_INT_DMA_CTL
, 0);
792 /* Disable Serial port */
793 cx_write(UART_CTL
, 0);
795 /* Disable Interrupts */
796 cx_write(PCI_INT_MSK
, 0);
797 cx_write(AUD_A_INT_MSK
, 0);
800 void cx25821_set_pixel_format(struct cx25821_dev
*dev
, int channel_select
,
803 struct sram_channel
*ch
;
805 if (channel_select
<= 7 && channel_select
>= 0) {
806 ch
= &cx25821_sram_channels
[channel_select
];
807 cx_write(ch
->pix_frmt
, format
);
808 dev
->pixel_formats
[channel_select
] = format
;
812 static void cx25821_set_vip_mode(struct cx25821_dev
*dev
,
813 struct sram_channel
*ch
)
815 cx_write(ch
->pix_frmt
, PIXEL_FRMT_422
);
816 cx_write(ch
->vip_ctl
, PIXEL_ENGINE_VIP1
);
819 static void cx25821_initialize(struct cx25821_dev
*dev
)
823 dprintk(1, "%s()\n", __func__
);
825 cx25821_shutdown(dev
);
826 cx_write(PCI_INT_STAT
, 0xffffffff);
828 for (i
= 0; i
< VID_CHANNEL_NUM
; i
++)
829 cx_write(dev
->sram_channels
[i
].int_stat
, 0xffffffff);
831 cx_write(AUD_A_INT_STAT
, 0xffffffff);
832 cx_write(AUD_B_INT_STAT
, 0xffffffff);
833 cx_write(AUD_C_INT_STAT
, 0xffffffff);
834 cx_write(AUD_D_INT_STAT
, 0xffffffff);
835 cx_write(AUD_E_INT_STAT
, 0xffffffff);
837 cx_write(CLK_DELAY
, cx_read(CLK_DELAY
) & 0x80000000);
838 cx_write(PAD_CTRL
, 0x12); //for I2C
839 cx25821_registers_init(dev
); //init Pecos registers
842 for (i
= 0; i
< VID_CHANNEL_NUM
; i
++) {
843 cx25821_set_vip_mode(dev
, &dev
->sram_channels
[i
]);
844 cx25821_sram_channel_setup(dev
, &dev
->sram_channels
[i
], 1440,
846 dev
->pixel_formats
[i
] = PIXEL_FRMT_422
;
847 dev
->use_cif_resolution
[i
] = FALSE
;
850 //Probably only affect Downstream
851 for (i
= VID_UPSTREAM_SRAM_CHANNEL_I
; i
<= VID_UPSTREAM_SRAM_CHANNEL_J
;
853 cx25821_set_vip_mode(dev
, &dev
->sram_channels
[i
]);
856 cx25821_sram_channel_setup_audio(dev
, &dev
->sram_channels
[SRAM_CH08
],
859 cx25821_gpio_init(dev
);
862 static int get_resources(struct cx25821_dev
*dev
)
864 if (request_mem_region
865 (pci_resource_start(dev
->pci
, 0), pci_resource_len(dev
->pci
, 0),
869 printk(KERN_ERR
"%s: can't get MMIO memory @ 0x%llx\n",
870 dev
->name
, (unsigned long long)pci_resource_start(dev
->pci
, 0));
875 static void cx25821_dev_checkrevision(struct cx25821_dev
*dev
)
877 dev
->hwrevision
= cx_read(RDR_CFG2
) & 0xff;
879 printk(KERN_INFO
"%s() Hardware revision = 0x%02x\n", __func__
,
883 static void cx25821_iounmap(struct cx25821_dev
*dev
)
888 /* Releasing IO memory */
889 if (dev
->lmmio
!= NULL
) {
890 CX25821_INFO("Releasing lmmio.\n");
896 static int cx25821_dev_setup(struct cx25821_dev
*dev
)
900 struct video_device
*video_template
[] = {
901 &cx25821_video_template0
,
902 &cx25821_video_template1
,
903 &cx25821_video_template2
,
904 &cx25821_video_template3
,
905 &cx25821_video_template4
,
906 &cx25821_video_template5
,
907 &cx25821_video_template6
,
908 &cx25821_video_template7
,
909 &cx25821_video_template9
,
910 &cx25821_video_template10
,
911 &cx25821_video_template11
,
912 &cx25821_videoioctl_template
,
915 printk(KERN_INFO
"\n***********************************\n");
916 printk(KERN_INFO
"cx25821 set up\n");
917 printk(KERN_INFO
"***********************************\n\n");
919 mutex_init(&dev
->lock
);
921 atomic_inc(&dev
->refcount
);
923 dev
->nr
= ++cx25821_devcount
;
924 sprintf(dev
->name
, "cx25821[%d]", dev
->nr
);
926 mutex_lock(&devlist
);
927 list_add_tail(&dev
->devlist
, &cx25821_devlist
);
928 mutex_unlock(&devlist
);
930 strcpy(cx25821_boards
[UNKNOWN_BOARD
].name
, "unknown");
931 strcpy(cx25821_boards
[CX25821_BOARD
].name
, "cx25821");
933 if (dev
->pci
->device
!= 0x8210) {
935 "%s() Exiting. Incorrect Hardware device = 0x%02x\n",
936 __func__
, dev
->pci
->device
);
939 printk(KERN_INFO
"Athena Hardware device = 0x%02x\n",
943 /* Apply a sensible clock frequency for the PCIe bridge */
944 dev
->clk_freq
= 28000000;
945 dev
->sram_channels
= cx25821_sram_channels
;
948 CX25821_INFO("dev->nr > 1!");
952 dev
->board
= 1; //card[dev->nr];
953 dev
->_max_num_decoders
= MAX_DECODERS
;
955 dev
->pci_bus
= dev
->pci
->bus
->number
;
956 dev
->pci_slot
= PCI_SLOT(dev
->pci
->devfn
);
957 dev
->pci_irqmask
= 0x001f00;
959 /* External Master 1 Bus */
960 dev
->i2c_bus
[0].nr
= 0;
961 dev
->i2c_bus
[0].dev
= dev
;
962 dev
->i2c_bus
[0].reg_stat
= I2C1_STAT
;
963 dev
->i2c_bus
[0].reg_ctrl
= I2C1_CTRL
;
964 dev
->i2c_bus
[0].reg_addr
= I2C1_ADDR
;
965 dev
->i2c_bus
[0].reg_rdata
= I2C1_RDATA
;
966 dev
->i2c_bus
[0].reg_wdata
= I2C1_WDATA
;
967 dev
->i2c_bus
[0].i2c_period
= (0x07 << 24); /* 1.95MHz */
970 if (get_resources(dev
) < 0) {
971 printk(KERN_ERR
"%s No more PCIe resources for "
972 "subsystem: %04x:%04x\n",
973 dev
->name
, dev
->pci
->subsystem_vendor
,
974 dev
->pci
->subsystem_device
);
981 dev
->base_io_addr
= pci_resource_start(dev
->pci
, 0);
982 io_size
= pci_resource_len(dev
->pci
, 0);
984 if (!dev
->base_io_addr
) {
985 CX25821_ERR("No PCI Memory resources, exiting!\n");
989 dev
->lmmio
= ioremap(dev
->base_io_addr
, pci_resource_len(dev
->pci
, 0));
993 ("ioremap failed, maybe increasing __VMALLOC_RESERVE in page.h\n");
994 cx25821_iounmap(dev
);
998 dev
->bmmio
= (u8 __iomem
*) dev
->lmmio
;
1000 printk(KERN_INFO
"%s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
1001 dev
->name
, dev
->pci
->subsystem_vendor
,
1002 dev
->pci
->subsystem_device
, cx25821_boards
[dev
->board
].name
,
1003 dev
->board
, card
[dev
->nr
] == dev
->board
?
1004 "insmod option" : "autodetected");
1007 cx25821_initialize(dev
);
1009 cx25821_i2c_register(&dev
->i2c_bus
[0]);
1010 // cx25821_i2c_register(&dev->i2c_bus[1]);
1011 // cx25821_i2c_register(&dev->i2c_bus[2]);
1013 CX25821_INFO("i2c register! bus->i2c_rc = %d\n",
1014 dev
->i2c_bus
[0].i2c_rc
);
1016 cx25821_card_setup(dev
);
1017 medusa_video_init(dev
);
1019 for (i
= 0; i
< VID_CHANNEL_NUM
; i
++) {
1020 if (cx25821_video_register(dev
, i
, video_template
[i
]) < 0) {
1022 "%s() Failed to register analog video adapters on VID channel %d\n",
1027 for (i
= VID_UPSTREAM_SRAM_CHANNEL_I
;
1028 i
<= AUDIO_UPSTREAM_SRAM_CHANNEL_B
; i
++) {
1029 //Since we don't have template8 for Audio Downstream
1030 if (cx25821_video_register(dev
, i
, video_template
[i
- 1]) < 0) {
1032 "%s() Failed to register analog video adapters for Upstream channel %d.\n",
1037 // register IOCTL device
1039 cx25821_vdev_init(dev
, dev
->pci
, video_template
[VIDEO_IOCTL_CH
],
1042 if (video_register_device
1043 (dev
->ioctl_dev
, VFL_TYPE_GRABBER
, VIDEO_IOCTL_CH
) < 0) {
1044 cx25821_videoioctl_unregister(dev
);
1046 "%s() Failed to register video adapter for IOCTL so releasing.\n",
1050 cx25821_dev_checkrevision(dev
);
1051 CX25821_INFO("cx25821 setup done!\n");
1056 void cx25821_start_upstream_video_ch1(struct cx25821_dev
*dev
,
1057 struct upstream_user_struct
*up_data
)
1059 dev
->_isNTSC
= !strcmp(dev
->vid_stdname
, "NTSC") ? 1 : 0;
1061 dev
->tvnorm
= !dev
->_isNTSC
? V4L2_STD_PAL_BG
: V4L2_STD_NTSC_M
;
1062 medusa_set_videostandard(dev
);
1064 cx25821_vidupstream_init_ch1(dev
, dev
->channel_select
,
1068 void cx25821_start_upstream_video_ch2(struct cx25821_dev
*dev
,
1069 struct upstream_user_struct
*up_data
)
1071 dev
->_isNTSC_ch2
= !strcmp(dev
->vid_stdname_ch2
, "NTSC") ? 1 : 0;
1073 dev
->tvnorm
= !dev
->_isNTSC_ch2
? V4L2_STD_PAL_BG
: V4L2_STD_NTSC_M
;
1074 medusa_set_videostandard(dev
);
1076 cx25821_vidupstream_init_ch2(dev
, dev
->channel_select_ch2
,
1077 dev
->pixel_format_ch2
);
1080 void cx25821_start_upstream_audio(struct cx25821_dev
*dev
,
1081 struct upstream_user_struct
*up_data
)
1083 cx25821_audio_upstream_init(dev
, AUDIO_UPSTREAM_SRAM_CHANNEL_B
);
1086 void cx25821_dev_unregister(struct cx25821_dev
*dev
)
1090 if (!dev
->base_io_addr
)
1093 cx25821_free_mem_upstream_ch1(dev
);
1094 cx25821_free_mem_upstream_ch2(dev
);
1095 cx25821_free_mem_upstream_audio(dev
);
1097 release_mem_region(dev
->base_io_addr
, pci_resource_len(dev
->pci
, 0));
1099 if (!atomic_dec_and_test(&dev
->refcount
))
1102 for (i
= 0; i
< VID_CHANNEL_NUM
; i
++)
1103 cx25821_video_unregister(dev
, i
);
1105 for (i
= VID_UPSTREAM_SRAM_CHANNEL_I
;
1106 i
<= AUDIO_UPSTREAM_SRAM_CHANNEL_B
; i
++) {
1107 cx25821_video_unregister(dev
, i
);
1110 cx25821_videoioctl_unregister(dev
);
1112 cx25821_i2c_unregister(&dev
->i2c_bus
[0]);
1113 cx25821_iounmap(dev
);
1116 static __le32
*cx25821_risc_field(__le32
* rp
, struct scatterlist
*sglist
,
1117 unsigned int offset
, u32 sync_line
,
1118 unsigned int bpl
, unsigned int padding
,
1121 struct scatterlist
*sg
;
1122 unsigned int line
, todo
;
1124 /* sync instruction */
1125 if (sync_line
!= NO_SYNC_LINE
) {
1126 *(rp
++) = cpu_to_le32(RISC_RESYNC
| sync_line
);
1131 for (line
= 0; line
< lines
; line
++) {
1132 while (offset
&& offset
>= sg_dma_len(sg
)) {
1133 offset
-= sg_dma_len(sg
);
1136 if (bpl
<= sg_dma_len(sg
) - offset
) {
1137 /* fits into current chunk */
1139 cpu_to_le32(RISC_WRITE
| RISC_SOL
| RISC_EOL
| bpl
);
1140 *(rp
++) = cpu_to_le32(sg_dma_address(sg
) + offset
);
1141 *(rp
++) = cpu_to_le32(0); /* bits 63-32 */
1144 /* scanline needs to be split */
1147 cpu_to_le32(RISC_WRITE
| RISC_SOL
|
1148 (sg_dma_len(sg
) - offset
));
1149 *(rp
++) = cpu_to_le32(sg_dma_address(sg
) + offset
);
1150 *(rp
++) = cpu_to_le32(0); /* bits 63-32 */
1151 todo
-= (sg_dma_len(sg
) - offset
);
1154 while (todo
> sg_dma_len(sg
)) {
1156 cpu_to_le32(RISC_WRITE
| sg_dma_len(sg
));
1157 *(rp
++) = cpu_to_le32(sg_dma_address(sg
));
1158 *(rp
++) = cpu_to_le32(0); /* bits 63-32 */
1159 todo
-= sg_dma_len(sg
);
1162 *(rp
++) = cpu_to_le32(RISC_WRITE
| RISC_EOL
| todo
);
1163 *(rp
++) = cpu_to_le32(sg_dma_address(sg
));
1164 *(rp
++) = cpu_to_le32(0); /* bits 63-32 */
1174 int cx25821_risc_buffer(struct pci_dev
*pci
, struct btcx_riscmem
*risc
,
1175 struct scatterlist
*sglist
, unsigned int top_offset
,
1176 unsigned int bottom_offset
, unsigned int bpl
,
1177 unsigned int padding
, unsigned int lines
)
1185 if (UNSET
!= top_offset
)
1187 if (UNSET
!= bottom_offset
)
1190 /* estimate risc mem: worst case is one write per page border +
1191 one write per scan line + syncs + jump (all 2 dwords). Padding
1192 can cause next bpl to start close to a page border. First DMA
1193 region may be smaller than PAGE_SIZE */
1194 /* write and jump need and extra dword */
1196 fields
* (1 + ((bpl
+ padding
) * lines
) / PAGE_SIZE
+ lines
);
1198 rc
= btcx_riscmem_alloc(pci
, risc
, instructions
* 12);
1203 /* write risc instructions */
1206 if (UNSET
!= top_offset
) {
1207 rp
= cx25821_risc_field(rp
, sglist
, top_offset
, 0, bpl
, padding
,
1211 if (UNSET
!= bottom_offset
) {
1212 rp
= cx25821_risc_field(rp
, sglist
, bottom_offset
, 0x200, bpl
,
1216 /* save pointer to jmp instruction address */
1218 BUG_ON((risc
->jmp
- risc
->cpu
+ 2) * sizeof(*risc
->cpu
) > risc
->size
);
1223 static __le32
*cx25821_risc_field_audio(__le32
* rp
, struct scatterlist
*sglist
,
1224 unsigned int offset
, u32 sync_line
,
1225 unsigned int bpl
, unsigned int padding
,
1226 unsigned int lines
, unsigned int lpi
)
1228 struct scatterlist
*sg
;
1229 unsigned int line
, todo
, sol
;
1231 /* sync instruction */
1232 if (sync_line
!= NO_SYNC_LINE
)
1233 *(rp
++) = cpu_to_le32(RISC_RESYNC
| sync_line
);
1237 for (line
= 0; line
< lines
; line
++) {
1238 while (offset
&& offset
>= sg_dma_len(sg
)) {
1239 offset
-= sg_dma_len(sg
);
1243 if (lpi
&& line
> 0 && !(line
% lpi
))
1244 sol
= RISC_SOL
| RISC_IRQ1
| RISC_CNT_INC
;
1248 if (bpl
<= sg_dma_len(sg
) - offset
) {
1249 /* fits into current chunk */
1251 cpu_to_le32(RISC_WRITE
| sol
| RISC_EOL
| bpl
);
1252 *(rp
++) = cpu_to_le32(sg_dma_address(sg
) + offset
);
1253 *(rp
++) = cpu_to_le32(0); /* bits 63-32 */
1256 /* scanline needs to be split */
1258 *(rp
++) = cpu_to_le32(RISC_WRITE
| sol
|
1259 (sg_dma_len(sg
) - offset
));
1260 *(rp
++) = cpu_to_le32(sg_dma_address(sg
) + offset
);
1261 *(rp
++) = cpu_to_le32(0); /* bits 63-32 */
1262 todo
-= (sg_dma_len(sg
) - offset
);
1265 while (todo
> sg_dma_len(sg
)) {
1266 *(rp
++) = cpu_to_le32(RISC_WRITE
|
1268 *(rp
++) = cpu_to_le32(sg_dma_address(sg
));
1269 *(rp
++) = cpu_to_le32(0); /* bits 63-32 */
1270 todo
-= sg_dma_len(sg
);
1273 *(rp
++) = cpu_to_le32(RISC_WRITE
| RISC_EOL
| todo
);
1274 *(rp
++) = cpu_to_le32(sg_dma_address(sg
));
1275 *(rp
++) = cpu_to_le32(0); /* bits 63-32 */
1284 int cx25821_risc_databuffer_audio(struct pci_dev
*pci
,
1285 struct btcx_riscmem
*risc
,
1286 struct scatterlist
*sglist
,
1288 unsigned int lines
, unsigned int lpi
)
1294 /* estimate risc mem: worst case is one write per page border +
1295 one write per scan line + syncs + jump (all 2 dwords). Here
1296 there is no padding and no sync. First DMA region may be smaller
1298 /* Jump and write need an extra dword */
1299 instructions
= 1 + (bpl
* lines
) / PAGE_SIZE
+ lines
;
1302 if ((rc
= btcx_riscmem_alloc(pci
, risc
, instructions
* 12)) < 0)
1305 /* write risc instructions */
1307 rp
= cx25821_risc_field_audio(rp
, sglist
, 0, NO_SYNC_LINE
, bpl
, 0,
1310 /* save pointer to jmp instruction address */
1312 BUG_ON((risc
->jmp
- risc
->cpu
+ 2) * sizeof(*risc
->cpu
) > risc
->size
);
1316 int cx25821_risc_stopper(struct pci_dev
*pci
, struct btcx_riscmem
*risc
,
1317 u32 reg
, u32 mask
, u32 value
)
1322 rc
= btcx_riscmem_alloc(pci
, risc
, 4 * 16);
1327 /* write risc instructions */
1330 *(rp
++) = cpu_to_le32(RISC_WRITECR
| RISC_IRQ1
);
1331 *(rp
++) = cpu_to_le32(reg
);
1332 *(rp
++) = cpu_to_le32(value
);
1333 *(rp
++) = cpu_to_le32(mask
);
1334 *(rp
++) = cpu_to_le32(RISC_JUMP
);
1335 *(rp
++) = cpu_to_le32(risc
->dma
);
1336 *(rp
++) = cpu_to_le32(0); /* bits 63-32 */
1340 void cx25821_free_buffer(struct videobuf_queue
*q
, struct cx25821_buffer
*buf
)
1342 struct videobuf_dmabuf
*dma
= videobuf_to_dma(&buf
->vb
);
1344 BUG_ON(in_interrupt());
1345 videobuf_waiton(&buf
->vb
, 0, 0);
1346 videobuf_dma_unmap(q
, dma
);
1347 videobuf_dma_free(dma
);
1348 btcx_riscmem_free(to_pci_dev(q
->dev
), &buf
->risc
);
1349 buf
->vb
.state
= VIDEOBUF_NEEDS_INIT
;
1352 static irqreturn_t
cx25821_irq(int irq
, void *dev_id
)
1354 struct cx25821_dev
*dev
= dev_id
;
1355 u32 pci_status
, pci_mask
;
1358 u32 mask
[8] = { 1, 2, 4, 8, 16, 32, 64, 128 };
1360 pci_status
= cx_read(PCI_INT_STAT
);
1361 pci_mask
= cx_read(PCI_INT_MSK
);
1363 if (pci_status
== 0)
1366 for (i
= 0; i
< VID_CHANNEL_NUM
; i
++) {
1367 if (pci_status
& mask
[i
]) {
1368 vid_status
= cx_read(dev
->sram_channels
[i
].int_stat
);
1372 cx25821_video_irq(dev
, i
, vid_status
);
1374 cx_write(PCI_INT_STAT
, mask
[i
]);
1379 return IRQ_RETVAL(handled
);
1382 void cx25821_print_irqbits(char *name
, char *tag
, char **strings
,
1383 int len
, u32 bits
, u32 mask
)
1387 printk(KERN_DEBUG
"%s: %s [0x%x]", name
, tag
, bits
);
1389 for (i
= 0; i
< len
; i
++) {
1390 if (!(bits
& (1 << i
)))
1393 printk(" %s", strings
[i
]);
1396 if (!(mask
& (1 << i
)))
1403 struct cx25821_dev
*cx25821_dev_get(struct pci_dev
*pci
)
1405 struct cx25821_dev
*dev
= pci_get_drvdata(pci
);
1409 static int __devinit
cx25821_initdev(struct pci_dev
*pci_dev
,
1410 const struct pci_device_id
*pci_id
)
1412 struct cx25821_dev
*dev
;
1415 dev
= kzalloc(sizeof(*dev
), GFP_KERNEL
);
1419 err
= v4l2_device_register(&pci_dev
->dev
, &dev
->v4l2_dev
);
1425 if (pci_enable_device(pci_dev
)) {
1428 printk(KERN_INFO
"pci enable failed! ");
1430 goto fail_unregister_device
;
1433 printk(KERN_INFO
"cx25821 Athena pci enable ! \n");
1435 if (cx25821_dev_setup(dev
) < 0) {
1437 goto fail_unregister_device
;
1440 /* print pci info */
1441 pci_read_config_byte(pci_dev
, PCI_CLASS_REVISION
, &dev
->pci_rev
);
1442 pci_read_config_byte(pci_dev
, PCI_LATENCY_TIMER
, &dev
->pci_lat
);
1443 printk(KERN_INFO
"%s/0: found at %s, rev: %d, irq: %d, "
1444 "latency: %d, mmio: 0x%llx\n", dev
->name
,
1445 pci_name(pci_dev
), dev
->pci_rev
, pci_dev
->irq
,
1446 dev
->pci_lat
, (unsigned long long)dev
->base_io_addr
);
1448 pci_set_master(pci_dev
);
1449 if (!pci_dma_supported(pci_dev
, 0xffffffff)) {
1450 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev
->name
);
1456 request_irq(pci_dev
->irq
, cx25821_irq
, IRQF_SHARED
| IRQF_DISABLED
,
1460 printk(KERN_ERR
"%s: can't get IRQ %d\n", dev
->name
,
1468 printk(KERN_INFO
"cx25821 cx25821_initdev() can't get IRQ ! \n");
1469 cx25821_dev_unregister(dev
);
1471 fail_unregister_device
:
1472 v4l2_device_unregister(&dev
->v4l2_dev
);
1479 static void __devexit
cx25821_finidev(struct pci_dev
*pci_dev
)
1481 struct v4l2_device
*v4l2_dev
= pci_get_drvdata(pci_dev
);
1482 struct cx25821_dev
*dev
= get_cx25821(v4l2_dev
);
1484 cx25821_shutdown(dev
);
1485 pci_disable_device(pci_dev
);
1487 /* unregister stuff */
1489 free_irq(pci_dev
->irq
, dev
);
1491 mutex_lock(&devlist
);
1492 list_del(&dev
->devlist
);
1493 mutex_unlock(&devlist
);
1495 cx25821_dev_unregister(dev
);
1496 v4l2_device_unregister(v4l2_dev
);
1500 static struct pci_device_id cx25821_pci_tbl
[] = {
1502 /* CX25821 Athena */
1505 .subvendor
= 0x14f1,
1506 .subdevice
= 0x0920,
1509 /* --- end of list --- */
1513 MODULE_DEVICE_TABLE(pci
, cx25821_pci_tbl
);
1515 static struct pci_driver cx25821_pci_driver
= {
1517 .id_table
= cx25821_pci_tbl
,
1518 .probe
= cx25821_initdev
,
1519 .remove
= __devexit_p(cx25821_finidev
),
1525 static int __init
cx25821_init(void)
1527 INIT_LIST_HEAD(&cx25821_devlist
);
1528 printk(KERN_INFO
"cx25821 driver version %d.%d.%d loaded\n",
1529 (CX25821_VERSION_CODE
>> 16) & 0xff,
1530 (CX25821_VERSION_CODE
>> 8) & 0xff, CX25821_VERSION_CODE
& 0xff);
1531 return pci_register_driver(&cx25821_pci_driver
);
1534 static void __exit
cx25821_fini(void)
1536 pci_unregister_driver(&cx25821_pci_driver
);
1539 EXPORT_SYMBOL(cx25821_devlist
);
1540 EXPORT_SYMBOL(cx25821_sram_channels
);
1541 EXPORT_SYMBOL(cx25821_print_irqbits
);
1542 EXPORT_SYMBOL(cx25821_dev_get
);
1543 EXPORT_SYMBOL(cx25821_dev_unregister
);
1544 EXPORT_SYMBOL(cx25821_sram_channel_setup
);
1545 EXPORT_SYMBOL(cx25821_sram_channel_dump
);
1546 EXPORT_SYMBOL(cx25821_sram_channel_setup_audio
);
1547 EXPORT_SYMBOL(cx25821_sram_channel_dump_audio
);
1548 EXPORT_SYMBOL(cx25821_risc_databuffer_audio
);
1549 EXPORT_SYMBOL(cx25821_set_gpiopin_direction
);
1551 module_init(cx25821_init
);
1552 module_exit(cx25821_fini
);