drivers/clocksource/sh_tmu.c

   1 /*
   2  * SuperH Timer Support - TMU
   3  *
   4  *  Copyright (C) 2009 Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/ioport.h>
  25 #include <linux/delay.h>
  26 #include <linux/io.h>
  27 #include <linux/clk.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/irq.h>
  30 #include <linux/err.h>
  31 #include <linux/clocksource.h>
  32 #include <linux/clockchips.h>
  33 #include <linux/sh_timer.h>
  34 #include <linux/slab.h>
  35
  36 struct sh_tmu_priv {
  37         void __iomem *mapbase;
  38         struct clk *clk;
  39         struct irqaction irqaction;
  40         struct platform_device *pdev;
  41         unsigned long rate;
  42         unsigned long periodic;
  43         struct clock_event_device ced;
  44         struct clocksource cs;
  45 };
  46
  47 static DEFINE_SPINLOCK(sh_tmu_lock);
  48
  49 #define TSTR -1 /* shared register */
  50 #define TCOR  0 /* channel register */
  51 #define TCNT 1 /* channel register */
  52 #define TCR 2 /* channel register */
  53
  54 static inline unsigned long sh_tmu_read(struct sh_tmu_priv *p, int reg_nr)
  55 {
  56         struct sh_timer_config *cfg = p->pdev->dev.platform_data;
  57         void __iomem *base = p->mapbase;
  58         unsigned long offs;
  59
  60         if (reg_nr == TSTR)
  61                 return ioread8(base - cfg->channel_offset);
  62
  63         offs = reg_nr << 2;
  64
  65         if (reg_nr == TCR)
  66                 return ioread16(base + offs);
  67         else
  68                 return ioread32(base + offs);
  69 }
  70
  71 static inline void sh_tmu_write(struct sh_tmu_priv *p, int reg_nr,
  72                                 unsigned long value)
  73 {
  74         struct sh_timer_config *cfg = p->pdev->dev.platform_data;
  75         void __iomem *base = p->mapbase;
  76         unsigned long offs;
  77
  78         if (reg_nr == TSTR) {
  79                 iowrite8(value, base - cfg->channel_offset);
  80                 return;
  81         }
  82
  83         offs = reg_nr << 2;
  84
  85         if (reg_nr == TCR)
  86                 iowrite16(value, base + offs);
  87         else
  88                 iowrite32(value, base + offs);
  89 }
  90
  91 static void sh_tmu_start_stop_ch(struct sh_tmu_priv *p, int start)
  92 {
  93         struct sh_timer_config *cfg = p->pdev->dev.platform_data;
  94         unsigned long flags, value;
  95
  96         /* start stop register shared by multiple timer channels */
  97         spin_lock_irqsave(&sh_tmu_lock, flags);
  98         value = sh_tmu_read(p, TSTR);
  99
 100         if (start)
 101                 value |= 1 << cfg->timer_bit;
 102         else
 103                 value &= ~(1 << cfg->timer_bit);
 104
 105         sh_tmu_write(p, TSTR, value);
 106         spin_unlock_irqrestore(&sh_tmu_lock, flags);
 107 }
 108
 109 static int sh_tmu_enable(struct sh_tmu_priv *p)
 110 {
 111         int ret;
 112
 113         /* wake up device and enable clock */
 114         pm_runtime_get_sync(&p->pdev->dev);
 115         ret = clk_enable(p->clk);
 116         if (ret) {
 117                 dev_err(&p->pdev->dev, "cannot enable clock\n");
 118                 pm_runtime_put_sync(&p->pdev->dev);
 119                 return ret;
 120         }
 121
 122         /* make sure channel is disabled */
 123         sh_tmu_start_stop_ch(p, 0);
 124
 125         /* maximum timeout */
 126         sh_tmu_write(p, TCOR, 0xffffffff);
 127         sh_tmu_write(p, TCNT, 0xffffffff);
 128
 129         /* configure channel to parent clock / 4, irq off */
 130         p->rate = clk_get_rate(p->clk) / 4;
 131         sh_tmu_write(p, TCR, 0x0000);
 132
 133         /* enable channel */
 134         sh_tmu_start_stop_ch(p, 1);
 135
 136         return 0;
 137 }
 138
 139 static void sh_tmu_disable(struct sh_tmu_priv *p)
 140 {
 141         /* disable channel */
 142         sh_tmu_start_stop_ch(p, 0);
 143
 144         /* disable interrupts in TMU block */
 145         sh_tmu_write(p, TCR, 0x0000);
 146
 147         /* stop clock and mark device as idle */
 148         clk_disable(p->clk);
 149         pm_runtime_put_sync(&p->pdev->dev);
 150 }
 151
 152 static void sh_tmu_set_next(struct sh_tmu_priv *p, unsigned long delta,
 153                             int periodic)
 154 {
 155         /* stop timer */
 156         sh_tmu_start_stop_ch(p, 0);
 157
 158         /* acknowledge interrupt */
 159         sh_tmu_read(p, TCR);
 160
 161         /* enable interrupt */
 162         sh_tmu_write(p, TCR, 0x0020);
 163
 164         /* reload delta value in case of periodic timer */
 165         if (periodic)
 166                 sh_tmu_write(p, TCOR, delta);
 167         else
 168                 sh_tmu_write(p, TCOR, 0xffffffff);
 169
 170         sh_tmu_write(p, TCNT, delta);
 171
 172         /* start timer */
 173         sh_tmu_start_stop_ch(p, 1);
 174 }
 175
 176 static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
 177 {
 178         struct sh_tmu_priv *p = dev_id;
 179
 180         /* disable or acknowledge interrupt */
 181         if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT)
 182                 sh_tmu_write(p, TCR, 0x0000);
 183         else
 184                 sh_tmu_write(p, TCR, 0x0020);
 185
 186         /* notify clockevent layer */
 187         p->ced.event_handler(&p->ced);
 188         return IRQ_HANDLED;
 189 }
 190
 191 static struct sh_tmu_priv *cs_to_sh_tmu(struct clocksource *cs)
 192 {
 193         return container_of(cs, struct sh_tmu_priv, cs);
 194 }
 195
 196 static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
 197 {
 198         struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
 199
 200         return sh_tmu_read(p, TCNT) ^ 0xffffffff;
 201 }
 202
 203 static int sh_tmu_clocksource_enable(struct clocksource *cs)
 204 {
 205         struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
 206         int ret;
 207
 208         ret = sh_tmu_enable(p);
 209         if (!ret)
 210                 __clocksource_updatefreq_hz(cs, p->rate);
 211         return ret;
 212 }
 213
 214 static void sh_tmu_clocksource_disable(struct clocksource *cs)
 215 {
 216         sh_tmu_disable(cs_to_sh_tmu(cs));
 217 }
 218
 219 static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
 220                                        char *name, unsigned long rating)
 221 {
 222         struct clocksource *cs = &p->cs;
 223
 224         cs->name = name;
 225         cs->rating = rating;
 226         cs->read = sh_tmu_clocksource_read;
 227         cs->enable = sh_tmu_clocksource_enable;
 228         cs->disable = sh_tmu_clocksource_disable;
 229         cs->mask = CLOCKSOURCE_MASK(32);
 230         cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
 231
 232         dev_info(&p->pdev->dev, "used as clock source\n");
 233
 234         /* Register with dummy 1 Hz value, gets updated in ->enable() */
 235         clocksource_register_hz(cs, 1);
 236         return 0;
 237 }
 238
 239 static struct sh_tmu_priv *ced_to_sh_tmu(struct clock_event_device *ced)
 240 {
 241         return container_of(ced, struct sh_tmu_priv, ced);
 242 }
 243
 244 static void sh_tmu_clock_event_start(struct sh_tmu_priv *p, int periodic)
 245 {
 246         struct clock_event_device *ced = &p->ced;
 247
 248         sh_tmu_enable(p);
 249
 250         /* TODO: calculate good shift from rate and counter bit width */
 251
 252         ced->shift = 32;
 253         ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
 254         ced->max_delta_ns = clockevent_delta2ns(0xffffffff, ced);
 255         ced->min_delta_ns = 5000;
 256
 257         if (periodic) {
 258                 p->periodic = (p->rate + HZ/2) / HZ;
 259                 sh_tmu_set_next(p, p->periodic, 1);
 260         }
 261 }
 262
 263 static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
 264                                     struct clock_event_device *ced)
 265 {
 266         struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
 267         int disabled = 0;
 268
 269         /* deal with old setting first */
 270         switch (ced->mode) {
 271         case CLOCK_EVT_MODE_PERIODIC:
 272         case CLOCK_EVT_MODE_ONESHOT:
 273                 sh_tmu_disable(p);
 274                 disabled = 1;
 275                 break;
 276         default:
 277                 break;
 278         }
 279
 280         switch (mode) {
 281         case CLOCK_EVT_MODE_PERIODIC:
 282                 dev_info(&p->pdev->dev, "used for periodic clock events\n");
 283                 sh_tmu_clock_event_start(p, 1);
 284                 break;
 285         case CLOCK_EVT_MODE_ONESHOT:
 286                 dev_info(&p->pdev->dev, "used for oneshot clock events\n");
 287                 sh_tmu_clock_event_start(p, 0);
 288                 break;
 289         case CLOCK_EVT_MODE_UNUSED:
 290                 if (!disabled)
 291                         sh_tmu_disable(p);
 292                 break;
 293         case CLOCK_EVT_MODE_SHUTDOWN:
 294         default:
 295                 break;
 296         }
 297 }
 298
 299 static int sh_tmu_clock_event_next(unsigned long delta,
 300                                    struct clock_event_device *ced)
 301 {
 302         struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
 303
 304         BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
 305
 306         /* program new delta value */
 307         sh_tmu_set_next(p, delta, 0);
 308         return 0;
 309 }
 310
 311 static void sh_tmu_register_clockevent(struct sh_tmu_priv *p,
 312                                        char *name, unsigned long rating)
 313 {
 314         struct clock_event_device *ced = &p->ced;
 315         int ret;
 316
 317         memset(ced, 0, sizeof(*ced));
 318
 319         ced->name = name;
 320         ced->features = CLOCK_EVT_FEAT_PERIODIC;
 321         ced->features |= CLOCK_EVT_FEAT_ONESHOT;
 322         ced->rating = rating;
 323         ced->cpumask = cpumask_of(0);
 324         ced->set_next_event = sh_tmu_clock_event_next;
 325         ced->set_mode = sh_tmu_clock_event_mode;
 326
 327         dev_info(&p->pdev->dev, "used for clock events\n");
 328         clockevents_register_device(ced);
 329
 330         ret = setup_irq(p->irqaction.irq, &p->irqaction);
 331         if (ret) {
 332                 dev_err(&p->pdev->dev, "failed to request irq %d\n",
 333                         p->irqaction.irq);
 334                 return;
 335         }
 336 }
 337
 338 static int sh_tmu_register(struct sh_tmu_priv *p, char *name,
 339                     unsigned long clockevent_rating,
 340                     unsigned long clocksource_rating)
 341 {
 342         if (clockevent_rating)
 343                 sh_tmu_register_clockevent(p, name, clockevent_rating);
 344         else if (clocksource_rating)
 345                 sh_tmu_register_clocksource(p, name, clocksource_rating);
 346
 347         return 0;
 348 }
 349
 350 static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
 351 {
 352         struct sh_timer_config *cfg = pdev->dev.platform_data;
 353         struct resource *res;
 354         int irq, ret;
 355         ret = -ENXIO;
 356
 357         memset(p, 0, sizeof(*p));
 358         p->pdev = pdev;
 359
 360         if (!cfg) {
 361                 dev_err(&p->pdev->dev, "missing platform data\n");
 362                 goto err0;
 363         }
 364
 365         platform_set_drvdata(pdev, p);
 366
 367         res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
 368         if (!res) {
 369                 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
 370                 goto err0;
 371         }
 372
 373         irq = platform_get_irq(p->pdev, 0);
 374         if (irq < 0) {
 375                 dev_err(&p->pdev->dev, "failed to get irq\n");
 376                 goto err0;
 377         }
 378
 379         /* map memory, let mapbase point to our channel */
 380         p->mapbase = ioremap_nocache(res->start, resource_size(res));
 381         if (p->mapbase == NULL) {
 382                 dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
 383                 goto err0;
 384         }
 385
 386         /* setup data for setup_irq() (too early for request_irq()) */
 387         p->irqaction.name = dev_name(&p->pdev->dev);
 388         p->irqaction.handler = sh_tmu_interrupt;
 389         p->irqaction.dev_id = p;
 390         p->irqaction.irq = irq;
 391         p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
 392                              IRQF_IRQPOLL  | IRQF_NOBALANCING;
 393
 394         /* get hold of clock */
 395         p->clk = clk_get(&p->pdev->dev, "tmu_fck");
 396         if (IS_ERR(p->clk)) {
 397                 dev_err(&p->pdev->dev, "cannot get clock\n");
 398                 ret = PTR_ERR(p->clk);
 399                 goto err1;
 400         }
 401
 402         return sh_tmu_register(p, (char *)dev_name(&p->pdev->dev),
 403                                cfg->clockevent_rating,
 404                                cfg->clocksource_rating);
 405  err1:
 406         iounmap(p->mapbase);
 407  err0:
 408         return ret;
 409 }
 410
 411 static int __devinit sh_tmu_probe(struct platform_device *pdev)
 412 {
 413         struct sh_tmu_priv *p = platform_get_drvdata(pdev);
 414         int ret;
 415
 416         if (p) {
 417                 dev_info(&pdev->dev, "kept as earlytimer\n");
 418                 pm_runtime_enable(&pdev->dev);
 419                 return 0;
 420         }
 421
 422         p = kmalloc(sizeof(*p), GFP_KERNEL);
 423         if (p == NULL) {
 424                 dev_err(&pdev->dev, "failed to allocate driver data\n");
 425                 return -ENOMEM;
 426         }
 427
 428         ret = sh_tmu_setup(p, pdev);
 429         if (ret) {
 430                 kfree(p);
 431                 platform_set_drvdata(pdev, NULL);
 432         }
 433
 434         if (!is_early_platform_device(pdev))
 435                 pm_runtime_enable(&pdev->dev);
 436         return ret;
 437 }
 438
 439 static int __devexit sh_tmu_remove(struct platform_device *pdev)
 440 {
 441         return -EBUSY; /* cannot unregister clockevent and clocksource */
 442 }
 443
 444 static struct platform_driver sh_tmu_device_driver = {
 445         .probe          = sh_tmu_probe,
 446         .remove         = __devexit_p(sh_tmu_remove),
 447         .driver         = {
 448                 .name   = "sh_tmu",
 449         }
 450 };
 451
 452 static int __init sh_tmu_init(void)
 453 {
 454         return platform_driver_register(&sh_tmu_device_driver);
 455 }
 456
 457 static void __exit sh_tmu_exit(void)
 458 {
 459         platform_driver_unregister(&sh_tmu_device_driver);
 460 }
 461
 462 early_platform_init("earlytimer", &sh_tmu_device_driver);
 463 module_init(sh_tmu_init);
 464 module_exit(sh_tmu_exit);
 465
 466 MODULE_AUTHOR("Magnus Damm");
 467 MODULE_DESCRIPTION("SuperH TMU Timer Driver");
 468 MODULE_LICENSE("GPL v2");