arch/arm/mach-ux500/cpu.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2010
   3  *
   4  * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
   5  * License terms: GNU General Public License (GPL) version 2
   6  */
   7
   8 #include <linux/platform_device.h>
   9 #include <linux/io.h>
  10 #include <linux/clk.h>
  11
  12 #include <asm/cacheflush.h>
  13 #include <asm/hardware/cache-l2x0.h>
  14 #include <asm/hardware/gic.h>
  15 #include <asm/mach/map.h>
  16 #include <asm/localtimer.h>
  17
  18 #include <plat/mtu.h>
  19 #include <mach/hardware.h>
  20 #include <mach/setup.h>
  21 #include <mach/devices.h>
  22 #include <mach/prcmu.h>
  23
  24 #include "clock.h"
  25
  26 #ifdef CONFIG_CACHE_L2X0
  27 static void __iomem *l2x0_base;
  28 #endif
  29
  30 void __init ux500_init_irq(void)
  31 {
  32         void __iomem *dist_base;
  33         void __iomem *cpu_base;
  34
  35         if (cpu_is_u5500()) {
  36                 dist_base = __io_address(U5500_GIC_DIST_BASE);
  37                 cpu_base = __io_address(U5500_GIC_CPU_BASE);
  38         } else if (cpu_is_u8500()) {
  39                 dist_base = __io_address(U8500_GIC_DIST_BASE);
  40                 cpu_base = __io_address(U8500_GIC_CPU_BASE);
  41         } else
  42                 ux500_unknown_soc();
  43
  44         gic_init(0, 29, dist_base, cpu_base);
  45
  46         /*
  47          * Init clocks here so that they are available for system timer
  48          * initialization.
  49          */
  50         if (cpu_is_u8500())
  51                 prcmu_early_init();
  52         clk_init();
  53 }
  54
  55 #ifdef CONFIG_CACHE_L2X0
  56 static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
  57 {
  58         /* wait for the operation to complete */
  59         while (readl_relaxed(reg) & mask)
  60                 ;
  61 }
  62
  63 static inline void ux500_cache_sync(void)
  64 {
  65         void __iomem *base = l2x0_base;
  66
  67         writel_relaxed(0, base + L2X0_CACHE_SYNC);
  68         ux500_cache_wait(base + L2X0_CACHE_SYNC, 1);
  69 }
  70
  71 /*
  72  * The L2 cache cannot be turned off in the non-secure world.
  73  * Dummy until a secure service is in place.
  74  */
  75 static void ux500_l2x0_disable(void)
  76 {
  77 }
  78
  79 /*
  80  * This is only called when doing a kexec, just after turning off the L2
  81  * and L1 cache, and it is surrounded by a spinlock in the generic version.
  82  * However, we're not really turning off the L2 cache right now and the
  83  * PL310 does not support exclusive accesses (used to implement the spinlock).
  84  * So, the invalidation needs to be done without the spinlock.
  85  */
  86 static void ux500_l2x0_inv_all(void)
  87 {
  88         void __iomem *base = l2x0_base;
  89         uint32_t l2x0_way_mask = (1<<16) - 1;   /* Bitmask of active ways */
  90
  91         /* invalidate all ways */
  92         writel_relaxed(l2x0_way_mask, base + L2X0_INV_WAY);
  93         ux500_cache_wait(base + L2X0_INV_WAY, l2x0_way_mask);
  94         ux500_cache_sync();
  95 }
  96
  97 static int ux500_l2x0_init(void)
  98 {
  99         if (cpu_is_u5500())
 100                 l2x0_base = __io_address(U5500_L2CC_BASE);
 101         else if (cpu_is_u8500())
 102                 l2x0_base = __io_address(U8500_L2CC_BASE);
 103         else
 104                 ux500_unknown_soc();
 105
 106         /* 64KB way size, 8 way associativity, force WA */
 107         l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
 108
 109         /* Override invalidate function */
 110         outer_cache.disable = ux500_l2x0_disable;
 111         outer_cache.inv_all = ux500_l2x0_inv_all;
 112
 113         return 0;
 114 }
 115 early_initcall(ux500_l2x0_init);
 116 #endif
 117
 118 static void __init ux500_timer_init(void)
 119 {
 120 #ifdef CONFIG_LOCAL_TIMERS
 121         /* Setup the local timer base */
 122         if (cpu_is_u5500())
 123                 twd_base = __io_address(U5500_TWD_BASE);
 124         else if (cpu_is_u8500())
 125                 twd_base = __io_address(U8500_TWD_BASE);
 126         else
 127                 ux500_unknown_soc();
 128 #endif
 129         if (cpu_is_u5500())
 130                 mtu_base = __io_address(U5500_MTU0_BASE);
 131         else if (cpu_is_u8500ed())
 132                 mtu_base = __io_address(U8500_MTU0_BASE_ED);
 133         else if (cpu_is_u8500())
 134                 mtu_base = __io_address(U8500_MTU0_BASE);
 135         else
 136                 ux500_unknown_soc();
 137
 138         nmdk_timer_init();
 139 }
 140
 141 struct sys_timer ux500_timer = {
 142         .init   = ux500_timer_init,
 143 };