2 * This file contains work-arounds for x86 and x86_64 platform bugs.
9 #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
11 static void __devinit
quirk_intel_irqbalance(struct pci_dev
*dev
)
16 /* BIOS may enable hardware IRQ balancing for
17 * E7520/E7320/E7525(revision ID 0x9 and below)
19 * Disable SW irqbalance/affinity on those platforms.
21 pci_read_config_byte(dev
, PCI_CLASS_REVISION
, &rev
);
25 /* enable access to config space*/
26 pci_read_config_byte(dev
, 0xf4, &config
);
27 pci_write_config_byte(dev
, 0xf4, config
|0x2);
30 * read xTPR register. We may not have a pci_dev for device 8
31 * because it might be hidden until the above write.
33 pci_bus_read_config_word(dev
->bus
, PCI_DEVFN(8, 0), 0x4c, &word
);
35 if (!(word
& (1 << 13))) {
36 dev_info(&dev
->dev
, "Intel E7520/7320/7525 detected; "
37 "disabling irq balancing and affinity\n");
38 #ifdef CONFIG_IRQBALANCE
39 irqbalance_disable("");
47 /* put back the original value for config space*/
49 pci_write_config_byte(dev
, 0xf4, config
);
51 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7320_MCH
,
52 quirk_intel_irqbalance
);
53 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7525_MCH
,
54 quirk_intel_irqbalance
);
55 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7520_MCH
,
56 quirk_intel_irqbalance
);
59 #if defined(CONFIG_HPET_TIMER)
60 unsigned long force_hpet_address
;
63 NONE_FORCE_HPET_RESUME
,
64 OLD_ICH_FORCE_HPET_RESUME
,
65 ICH_FORCE_HPET_RESUME
,
66 VT8237_FORCE_HPET_RESUME
,
67 NVIDIA_FORCE_HPET_RESUME
,
68 ATI_FORCE_HPET_RESUME
,
69 } force_hpet_resume_type
;
71 static void __iomem
*rcba_base
;
73 static void ich_force_hpet_resume(void)
77 if (!force_hpet_address
)
80 if (rcba_base
== NULL
)
83 /* read the Function Disable register, dword mode only */
84 val
= readl(rcba_base
+ 0x3404);
86 /* HPET disabled in HPTC. Trying to enable */
87 writel(val
| 0x80, rcba_base
+ 0x3404);
90 val
= readl(rcba_base
+ 0x3404);
94 printk(KERN_DEBUG
"Force enabled HPET at resume\n");
99 static void ich_force_enable_hpet(struct pci_dev
*dev
)
102 u32
uninitialized_var(rcba
);
105 if (hpet_address
|| force_hpet_address
)
108 pci_read_config_dword(dev
, 0xF0, &rcba
);
111 dev_printk(KERN_DEBUG
, &dev
->dev
, "RCBA disabled; "
112 "cannot force enable HPET\n");
116 /* use bits 31:14, 16 kB aligned */
117 rcba_base
= ioremap_nocache(rcba
, 0x4000);
118 if (rcba_base
== NULL
) {
119 dev_printk(KERN_DEBUG
, &dev
->dev
, "ioremap failed; "
120 "cannot force enable HPET\n");
124 /* read the Function Disable register, dword mode only */
125 val
= readl(rcba_base
+ 0x3404);
128 /* HPET is enabled in HPTC. Just not reported by BIOS */
130 force_hpet_address
= 0xFED00000 | (val
<< 12);
131 dev_printk(KERN_DEBUG
, &dev
->dev
, "Force enabled HPET at "
132 "0x%lx\n", force_hpet_address
);
137 /* HPET disabled in HPTC. Trying to enable */
138 writel(val
| 0x80, rcba_base
+ 0x3404);
140 val
= readl(rcba_base
+ 0x3404);
145 force_hpet_address
= 0xFED00000 | (val
<< 12);
149 force_hpet_address
= 0;
151 dev_printk(KERN_DEBUG
, &dev
->dev
,
152 "Failed to force enable HPET\n");
154 force_hpet_resume_type
= ICH_FORCE_HPET_RESUME
;
155 dev_printk(KERN_DEBUG
, &dev
->dev
, "Force enabled HPET at "
156 "0x%lx\n", force_hpet_address
);
160 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB2_0
,
161 ich_force_enable_hpet
);
162 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
,
163 ich_force_enable_hpet
);
164 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_0
,
165 ich_force_enable_hpet
);
166 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_1
,
167 ich_force_enable_hpet
);
168 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_31
,
169 ich_force_enable_hpet
);
170 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_1
,
171 ich_force_enable_hpet
);
172 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_7
,
173 ich_force_enable_hpet
);
176 static struct pci_dev
*cached_dev
;
178 static void old_ich_force_hpet_resume(void)
181 u32
uninitialized_var(gen_cntl
);
183 if (!force_hpet_address
|| !cached_dev
)
186 pci_read_config_dword(cached_dev
, 0xD0, &gen_cntl
);
187 gen_cntl
&= (~(0x7 << 15));
188 gen_cntl
|= (0x4 << 15);
190 pci_write_config_dword(cached_dev
, 0xD0, gen_cntl
);
191 pci_read_config_dword(cached_dev
, 0xD0, &gen_cntl
);
192 val
= gen_cntl
>> 15;
195 printk(KERN_DEBUG
"Force enabled HPET at resume\n");
200 static void old_ich_force_enable_hpet(struct pci_dev
*dev
)
203 u32
uninitialized_var(gen_cntl
);
205 if (hpet_address
|| force_hpet_address
)
208 pci_read_config_dword(dev
, 0xD0, &gen_cntl
);
210 * Bit 17 is HPET enable bit.
211 * Bit 16:15 control the HPET base address.
213 val
= gen_cntl
>> 15;
217 force_hpet_address
= 0xFED00000 | (val
<< 12);
218 dev_printk(KERN_DEBUG
, &dev
->dev
, "HPET at 0x%lx\n",
224 * HPET is disabled. Trying enabling at FED00000 and check
227 gen_cntl
&= (~(0x7 << 15));
228 gen_cntl
|= (0x4 << 15);
229 pci_write_config_dword(dev
, 0xD0, gen_cntl
);
231 pci_read_config_dword(dev
, 0xD0, &gen_cntl
);
233 val
= gen_cntl
>> 15;
236 /* HPET is enabled in HPTC. Just not reported by BIOS */
238 force_hpet_address
= 0xFED00000 | (val
<< 12);
239 dev_printk(KERN_DEBUG
, &dev
->dev
, "Force enabled HPET at "
240 "0x%lx\n", force_hpet_address
);
242 force_hpet_resume_type
= OLD_ICH_FORCE_HPET_RESUME
;
246 dev_printk(KERN_DEBUG
, &dev
->dev
, "Failed to force enable HPET\n");
250 * Undocumented chipset features. Make sure that the user enforced
253 static void old_ich_force_enable_hpet_user(struct pci_dev
*dev
)
256 old_ich_force_enable_hpet(dev
);
259 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
,
260 old_ich_force_enable_hpet_user
);
261 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
,
262 old_ich_force_enable_hpet_user
);
263 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
,
264 old_ich_force_enable_hpet_user
);
265 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
,
266 old_ich_force_enable_hpet_user
);
267 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
,
268 old_ich_force_enable_hpet
);
269 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_12
,
270 old_ich_force_enable_hpet
);
273 static void vt8237_force_hpet_resume(void)
277 if (!force_hpet_address
|| !cached_dev
)
280 val
= 0xfed00000 | 0x80;
281 pci_write_config_dword(cached_dev
, 0x68, val
);
283 pci_read_config_dword(cached_dev
, 0x68, &val
);
285 printk(KERN_DEBUG
"Force enabled HPET at resume\n");
290 static void vt8237_force_enable_hpet(struct pci_dev
*dev
)
292 u32
uninitialized_var(val
);
294 if (!hpet_force_user
|| hpet_address
|| force_hpet_address
)
297 pci_read_config_dword(dev
, 0x68, &val
);
299 * Bit 7 is HPET enable bit.
300 * Bit 31:10 is HPET base address (contrary to what datasheet claims)
303 force_hpet_address
= (val
& ~0x3ff);
304 dev_printk(KERN_DEBUG
, &dev
->dev
, "HPET at 0x%lx\n",
310 * HPET is disabled. Trying enabling at FED00000 and check
313 val
= 0xfed00000 | 0x80;
314 pci_write_config_dword(dev
, 0x68, val
);
316 pci_read_config_dword(dev
, 0x68, &val
);
318 force_hpet_address
= (val
& ~0x3ff);
319 dev_printk(KERN_DEBUG
, &dev
->dev
, "Force enabled HPET at "
320 "0x%lx\n", force_hpet_address
);
322 force_hpet_resume_type
= VT8237_FORCE_HPET_RESUME
;
326 dev_printk(KERN_DEBUG
, &dev
->dev
, "Failed to force enable HPET\n");
329 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235
,
330 vt8237_force_enable_hpet
);
331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
,
332 vt8237_force_enable_hpet
);
334 static void ati_force_hpet_resume(void)
336 pci_write_config_dword(cached_dev
, 0x14, 0xfed00000);
337 printk(KERN_DEBUG
"Force enabled HPET at resume\n");
340 static void ati_force_enable_hpet(struct pci_dev
*dev
)
342 u32
uninitialized_var(val
);
344 if (!hpet_force_user
|| hpet_address
|| force_hpet_address
)
347 pci_write_config_dword(dev
, 0x14, 0xfed00000);
348 pci_read_config_dword(dev
, 0x14, &val
);
349 force_hpet_address
= val
;
350 force_hpet_resume_type
= ATI_FORCE_HPET_RESUME
;
351 dev_printk(KERN_DEBUG
, &dev
->dev
, "Force enabled HPET at 0x%lx\n",
356 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP400_SMBUS
,
357 ati_force_enable_hpet
);
360 * Undocumented chipset feature taken from LinuxBIOS.
362 static void nvidia_force_hpet_resume(void)
364 pci_write_config_dword(cached_dev
, 0x44, 0xfed00001);
365 printk(KERN_DEBUG
"Force enabled HPET at resume\n");
368 static void nvidia_force_enable_hpet(struct pci_dev
*dev
)
370 u32
uninitialized_var(val
);
372 if (!hpet_force_user
|| hpet_address
|| force_hpet_address
)
375 pci_write_config_dword(dev
, 0x44, 0xfed00001);
376 pci_read_config_dword(dev
, 0x44, &val
);
377 force_hpet_address
= val
& 0xfffffffe;
378 force_hpet_resume_type
= NVIDIA_FORCE_HPET_RESUME
;
379 dev_printk(KERN_DEBUG
, &dev
->dev
, "Force enabled HPET at 0x%lx\n",
386 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA
, 0x0050,
387 nvidia_force_enable_hpet
);
388 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA
, 0x0051,
389 nvidia_force_enable_hpet
);
392 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA
, 0x0260,
393 nvidia_force_enable_hpet
);
394 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA
, 0x0360,
395 nvidia_force_enable_hpet
);
396 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA
, 0x0361,
397 nvidia_force_enable_hpet
);
398 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA
, 0x0362,
399 nvidia_force_enable_hpet
);
400 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA
, 0x0363,
401 nvidia_force_enable_hpet
);
402 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA
, 0x0364,
403 nvidia_force_enable_hpet
);
404 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA
, 0x0365,
405 nvidia_force_enable_hpet
);
406 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA
, 0x0366,
407 nvidia_force_enable_hpet
);
408 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA
, 0x0367,
409 nvidia_force_enable_hpet
);
411 void force_hpet_resume(void)
413 switch (force_hpet_resume_type
) {
414 case ICH_FORCE_HPET_RESUME
:
415 ich_force_hpet_resume();
417 case OLD_ICH_FORCE_HPET_RESUME
:
418 old_ich_force_hpet_resume();
420 case VT8237_FORCE_HPET_RESUME
:
421 vt8237_force_hpet_resume();
423 case NVIDIA_FORCE_HPET_RESUME
:
424 nvidia_force_hpet_resume();
426 case ATI_FORCE_HPET_RESUME
:
427 ati_force_hpet_resume();