drivers/hwmon/lis3lv02d.h

   1 /*
   2  *  lis3lv02d.h - ST LIS3LV02DL accelerometer driver
   3  *
   4  *  Copyright (C) 2007-2008 Yan Burman
   5  *  Copyright (C) 2008-2009 Eric Piel
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program; if not, write to the Free Software
  19  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/platform_device.h>
  22 #include <linux/input-polldev.h>
  23 #include <linux/regulator/consumer.h>
  24
  25 /*
  26  * This driver tries to support the "digital" accelerometer chips from
  27  * STMicroelectronics such as LIS3LV02DL, LIS302DL, LIS3L02DQ, LIS331DL,
  28  * LIS35DE, or LIS202DL. They are very similar in terms of programming, with
  29  * almost the same registers. In addition to differing on physical properties,
  30  * they differ on the number of axes (2/3), precision (8/12 bits), and special
  31  * features (freefall detection, click...). Unfortunately, not all the
  32  * differences can be probed via a register.
  33  * They can be connected either via I²C or SPI.
  34  */
  35
  36 #include <linux/lis3lv02d.h>
  37
  38 enum lis3_reg {
  39         WHO_AM_I        = 0x0F,
  40         OFFSET_X        = 0x16,
  41         OFFSET_Y        = 0x17,
  42         OFFSET_Z        = 0x18,
  43         GAIN_X          = 0x19,
  44         GAIN_Y          = 0x1A,
  45         GAIN_Z          = 0x1B,
  46         CTRL_REG1       = 0x20,
  47         CTRL_REG2       = 0x21,
  48         CTRL_REG3       = 0x22,
  49         CTRL_REG4       = 0x23,
  50         HP_FILTER_RESET = 0x23,
  51         STATUS_REG      = 0x27,
  52         OUTX_L          = 0x28,
  53         OUTX_H          = 0x29,
  54         OUTX            = 0x29,
  55         OUTY_L          = 0x2A,
  56         OUTY_H          = 0x2B,
  57         OUTY            = 0x2B,
  58         OUTZ_L          = 0x2C,
  59         OUTZ_H          = 0x2D,
  60         OUTZ            = 0x2D,
  61 };
  62
  63 enum lis302d_reg {
  64         FF_WU_CFG_1     = 0x30,
  65         FF_WU_SRC_1     = 0x31,
  66         FF_WU_THS_1     = 0x32,
  67         FF_WU_DURATION_1 = 0x33,
  68         FF_WU_CFG_2     = 0x34,
  69         FF_WU_SRC_2     = 0x35,
  70         FF_WU_THS_2     = 0x36,
  71         FF_WU_DURATION_2 = 0x37,
  72         CLICK_CFG       = 0x38,
  73         CLICK_SRC       = 0x39,
  74         CLICK_THSY_X    = 0x3B,
  75         CLICK_THSZ      = 0x3C,
  76         CLICK_TIMELIMIT = 0x3D,
  77         CLICK_LATENCY   = 0x3E,
  78         CLICK_WINDOW    = 0x3F,
  79 };
  80
  81 enum lis3lv02d_reg {
  82         FF_WU_CFG       = 0x30,
  83         FF_WU_SRC       = 0x31,
  84         FF_WU_ACK       = 0x32,
  85         FF_WU_THS_L     = 0x34,
  86         FF_WU_THS_H     = 0x35,
  87         FF_WU_DURATION  = 0x36,
  88         DD_CFG          = 0x38,
  89         DD_SRC          = 0x39,
  90         DD_ACK          = 0x3A,
  91         DD_THSI_L       = 0x3C,
  92         DD_THSI_H       = 0x3D,
  93         DD_THSE_L       = 0x3E,
  94         DD_THSE_H       = 0x3F,
  95 };
  96
  97 enum lis3_who_am_i {
  98         WAI_3DC         = 0x33, /* 8 bits: LIS3DC, HP3DC */
  99         WAI_12B         = 0x3A, /* 12 bits: LIS3LV02D[LQ]... */
 100         WAI_8B          = 0x3B, /* 8 bits: LIS[23]02D[LQ]... */
 101         WAI_6B          = 0x52, /* 6 bits: LIS331DLF - not supported */
 102 };
 103
 104 enum lis3lv02d_ctrl1_12b {
 105         CTRL1_Xen       = 0x01,
 106         CTRL1_Yen       = 0x02,
 107         CTRL1_Zen       = 0x04,
 108         CTRL1_ST        = 0x08,
 109         CTRL1_DF0       = 0x10,
 110         CTRL1_DF1       = 0x20,
 111         CTRL1_PD0       = 0x40,
 112         CTRL1_PD1       = 0x80,
 113 };
 114
 115 /* Delta to ctrl1_12b version */
 116 enum lis3lv02d_ctrl1_8b {
 117         CTRL1_STM       = 0x08,
 118         CTRL1_STP       = 0x10,
 119         CTRL1_FS        = 0x20,
 120         CTRL1_PD        = 0x40,
 121         CTRL1_DR        = 0x80,
 122 };
 123
 124 enum lis3lv02d_ctrl1_3dc {
 125         CTRL1_ODR0      = 0x10,
 126         CTRL1_ODR1      = 0x20,
 127         CTRL1_ODR2      = 0x40,
 128         CTRL1_ODR3      = 0x80,
 129 };
 130
 131 enum lis3lv02d_ctrl2 {
 132         CTRL2_DAS       = 0x01,
 133         CTRL2_SIM       = 0x02,
 134         CTRL2_DRDY      = 0x04,
 135         CTRL2_IEN       = 0x08,
 136         CTRL2_BOOT      = 0x10,
 137         CTRL2_BLE       = 0x20,
 138         CTRL2_BDU       = 0x40, /* Block Data Update */
 139         CTRL2_FS        = 0x80, /* Full Scale selection */
 140 };
 141
 142 enum lis3lv02d_ctrl4_3dc {
 143         CTRL4_SIM       = 0x01,
 144         CTRL4_ST0       = 0x02,
 145         CTRL4_ST1       = 0x04,
 146         CTRL4_FS0       = 0x10,
 147         CTRL4_FS1       = 0x20,
 148 };
 149
 150 enum lis302d_ctrl2 {
 151         HP_FF_WU2       = 0x08,
 152         HP_FF_WU1       = 0x04,
 153         CTRL2_BOOT_8B   = 0x40,
 154 };
 155
 156 enum lis3lv02d_ctrl3 {
 157         CTRL3_CFS0      = 0x01,
 158         CTRL3_CFS1      = 0x02,
 159         CTRL3_FDS       = 0x10,
 160         CTRL3_HPFF      = 0x20,
 161         CTRL3_HPDD      = 0x40,
 162         CTRL3_ECK       = 0x80,
 163 };
 164
 165 enum lis3lv02d_status_reg {
 166         STATUS_XDA      = 0x01,
 167         STATUS_YDA      = 0x02,
 168         STATUS_ZDA      = 0x04,
 169         STATUS_XYZDA    = 0x08,
 170         STATUS_XOR      = 0x10,
 171         STATUS_YOR      = 0x20,
 172         STATUS_ZOR      = 0x40,
 173         STATUS_XYZOR    = 0x80,
 174 };
 175
 176 enum lis3lv02d_ff_wu_cfg {
 177         FF_WU_CFG_XLIE  = 0x01,
 178         FF_WU_CFG_XHIE  = 0x02,
 179         FF_WU_CFG_YLIE  = 0x04,
 180         FF_WU_CFG_YHIE  = 0x08,
 181         FF_WU_CFG_ZLIE  = 0x10,
 182         FF_WU_CFG_ZHIE  = 0x20,
 183         FF_WU_CFG_LIR   = 0x40,
 184         FF_WU_CFG_AOI   = 0x80,
 185 };
 186
 187 enum lis3lv02d_ff_wu_src {
 188         FF_WU_SRC_XL    = 0x01,
 189         FF_WU_SRC_XH    = 0x02,
 190         FF_WU_SRC_YL    = 0x04,
 191         FF_WU_SRC_YH    = 0x08,
 192         FF_WU_SRC_ZL    = 0x10,
 193         FF_WU_SRC_ZH    = 0x20,
 194         FF_WU_SRC_IA    = 0x40,
 195 };
 196
 197 enum lis3lv02d_dd_cfg {
 198         DD_CFG_XLIE     = 0x01,
 199         DD_CFG_XHIE     = 0x02,
 200         DD_CFG_YLIE     = 0x04,
 201         DD_CFG_YHIE     = 0x08,
 202         DD_CFG_ZLIE     = 0x10,
 203         DD_CFG_ZHIE     = 0x20,
 204         DD_CFG_LIR      = 0x40,
 205         DD_CFG_IEND     = 0x80,
 206 };
 207
 208 enum lis3lv02d_dd_src {
 209         DD_SRC_XL       = 0x01,
 210         DD_SRC_XH       = 0x02,
 211         DD_SRC_YL       = 0x04,
 212         DD_SRC_YH       = 0x08,
 213         DD_SRC_ZL       = 0x10,
 214         DD_SRC_ZH       = 0x20,
 215         DD_SRC_IA       = 0x40,
 216 };
 217
 218 enum lis3lv02d_click_src_8b {
 219         CLICK_SINGLE_X  = 0x01,
 220         CLICK_DOUBLE_X  = 0x02,
 221         CLICK_SINGLE_Y  = 0x04,
 222         CLICK_DOUBLE_Y  = 0x08,
 223         CLICK_SINGLE_Z  = 0x10,
 224         CLICK_DOUBLE_Z  = 0x20,
 225         CLICK_IA        = 0x40,
 226 };
 227
 228 enum lis3lv02d_reg_state {
 229         LIS3_REG_OFF    = 0x00,
 230         LIS3_REG_ON     = 0x01,
 231 };
 232
 233 union axis_conversion {
 234         struct {
 235                 int x, y, z;
 236         };
 237         int as_array[3];
 238
 239 };
 240
 241 struct lis3lv02d {
 242         void                    *bus_priv; /* used by the bus layer only */
 243         struct device           *pm_dev; /* for pm_runtime purposes */
 244         int (*init) (struct lis3lv02d *lis3);
 245         int (*write) (struct lis3lv02d *lis3, int reg, u8 val);
 246         int (*read) (struct lis3lv02d *lis3, int reg, u8 *ret);
 247         int (*blkread) (struct lis3lv02d *lis3, int reg, int len, u8 *ret);
 248         int (*reg_ctrl) (struct lis3lv02d *lis3, bool state);
 249
 250         int                     *odrs;     /* Supported output data rates */
 251         u8                      *regs;     /* Regs to store / restore */
 252         int                     regs_size;
 253         u8                      *reg_cache;
 254         bool                    regs_stored;
 255         u8                      odr_mask;  /* ODR bit mask */
 256         u8                      whoami;    /* indicates measurement precision */
 257         s16 (*read_data) (struct lis3lv02d *lis3, int reg);
 258         int                     mdps_max_val;
 259         int                     pwron_delay;
 260         int                     scale; /*
 261                                         * relationship between 1 LBS and mG
 262                                         * (1/1000th of earth gravity)
 263                                         */
 264
 265         struct input_polled_dev *idev;     /* input device */
 266         struct platform_device  *pdev;     /* platform device */
 267         struct regulator_bulk_data regulators[2];
 268         atomic_t                count;     /* interrupt count after last read */
 269         union axis_conversion   ac;        /* hw -> logical axis */
 270         int                     mapped_btns[3];
 271
 272         u32                     irq;       /* IRQ number */
 273         struct fasync_struct    *async_queue; /* queue for the misc device */
 274         wait_queue_head_t       misc_wait; /* Wait queue for the misc device */
 275         unsigned long           misc_opened; /* bit0: whether the device is open */
 276         int                     data_ready_count[2];
 277         atomic_t                wake_thread;
 278         unsigned char           irq_cfg;
 279
 280         struct lis3lv02d_platform_data *pdata;  /* for passing board config */
 281         struct mutex            mutex;     /* Serialize poll and selftest */
 282 };
 283
 284 int lis3lv02d_init_device(struct lis3lv02d *lis3);
 285 int lis3lv02d_joystick_enable(void);
 286 void lis3lv02d_joystick_disable(void);
 287 void lis3lv02d_poweroff(struct lis3lv02d *lis3);
 288 void lis3lv02d_poweron(struct lis3lv02d *lis3);
 289 int lis3lv02d_remove_fs(struct lis3lv02d *lis3);
 290
 291 extern struct lis3lv02d lis3_dev;