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KVM: VMX: Allow the guest to own some cr0 bits
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / kvm / svm.c
blob3899c2d1983022e24a84d41cfa0b975db29237d1
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16 #include <linux/kvm_host.h>
17
18 #include "irq.h"
19 #include "mmu.h"
20 #include "kvm_cache_regs.h"
21 #include "x86.h"
22
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/vmalloc.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/ftrace_event.h>
29
30 #include <asm/desc.h>
31
32 #include <asm/virtext.h>
33 #include "trace.h"
34
35 #define __ex(x) __kvm_handle_fault_on_reboot(x)
36
37 MODULE_AUTHOR("Qumranet");
38 MODULE_LICENSE("GPL");
39
40 #define IOPM_ALLOC_ORDER 2
41 #define MSRPM_ALLOC_ORDER 1
42
43 #define SEG_TYPE_LDT 2
44 #define SEG_TYPE_BUSY_TSS16 3
45
46 #define SVM_FEATURE_NPT (1 << 0)
47 #define SVM_FEATURE_LBRV (1 << 1)
48 #define SVM_FEATURE_SVML (1 << 2)
49 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
50
51 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
52 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
53 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
54
55 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
56
57 static const u32 host_save_user_msrs[] = {
58 #ifdef CONFIG_X86_64
59 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
60 MSR_FS_BASE,
61 #endif
62 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
63 };
64
65 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
66
67 struct kvm_vcpu;
68
69 struct nested_state {
70 struct vmcb *hsave;
71 u64 hsave_msr;
72 u64 vmcb;
73
74 /* These are the merged vectors */
75 u32 *msrpm;
76
77 /* gpa pointers to the real vectors */
78 u64 vmcb_msrpm;
79
80 /* A VMEXIT is required but not yet emulated */
81 bool exit_required;
82
83 /* cache for intercepts of the guest */
84 u16 intercept_cr_read;
85 u16 intercept_cr_write;
86 u16 intercept_dr_read;
87 u16 intercept_dr_write;
88 u32 intercept_exceptions;
89 u64 intercept;
90
91 };
92
93 struct vcpu_svm {
94 struct kvm_vcpu vcpu;
95 struct vmcb *vmcb;
96 unsigned long vmcb_pa;
97 struct svm_cpu_data *svm_data;
98 uint64_t asid_generation;
99 uint64_t sysenter_esp;
100 uint64_t sysenter_eip;
101
102 u64 next_rip;
103
104 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
105 u64 host_gs_base;
106
107 u32 *msrpm;
108
109 struct nested_state nested;
110
111 bool nmi_singlestep;
112 };
113
114 /* enable NPT for AMD64 and X86 with PAE */
115 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
116 static bool npt_enabled = true;
117 #else
118 static bool npt_enabled = false;
119 #endif
120 static int npt = 1;
121
122 module_param(npt, int, S_IRUGO);
123
124 static int nested = 1;
125 module_param(nested, int, S_IRUGO);
126
127 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
128 static void svm_complete_interrupts(struct vcpu_svm *svm);
129
130 static int nested_svm_exit_handled(struct vcpu_svm *svm);
131 static int nested_svm_vmexit(struct vcpu_svm *svm);
132 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
133 bool has_error_code, u32 error_code);
134
135 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
136 {
137 return container_of(vcpu, struct vcpu_svm, vcpu);
138 }
139
140 static inline bool is_nested(struct vcpu_svm *svm)
141 {
142 return svm->nested.vmcb;
143 }
144
145 static inline void enable_gif(struct vcpu_svm *svm)
146 {
147 svm->vcpu.arch.hflags |= HF_GIF_MASK;
148 }
149
150 static inline void disable_gif(struct vcpu_svm *svm)
151 {
152 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
153 }
154
155 static inline bool gif_set(struct vcpu_svm *svm)
156 {
157 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
158 }
159
160 static unsigned long iopm_base;
161
162 struct kvm_ldttss_desc {
163 u16 limit0;
164 u16 base0;
165 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
166 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
167 u32 base3;
168 u32 zero1;
169 } __attribute__((packed));
170
171 struct svm_cpu_data {
172 int cpu;
173
174 u64 asid_generation;
175 u32 max_asid;
176 u32 next_asid;
177 struct kvm_ldttss_desc *tss_desc;
178
179 struct page *save_area;
180 };
181
182 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
183 static uint32_t svm_features;
184
185 struct svm_init_data {
186 int cpu;
187 int r;
188 };
189
190 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
191
192 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
193 #define MSRS_RANGE_SIZE 2048
194 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
195
196 #define MAX_INST_SIZE 15
197
198 static inline u32 svm_has(u32 feat)
199 {
200 return svm_features & feat;
201 }
202
203 static inline void clgi(void)
204 {
205 asm volatile (__ex(SVM_CLGI));
206 }
207
208 static inline void stgi(void)
209 {
210 asm volatile (__ex(SVM_STGI));
211 }
212
213 static inline void invlpga(unsigned long addr, u32 asid)
214 {
215 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
216 }
217
218 static inline void force_new_asid(struct kvm_vcpu *vcpu)
219 {
220 to_svm(vcpu)->asid_generation--;
221 }
222
223 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
224 {
225 force_new_asid(vcpu);
226 }
227
228 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
229 {
230 if (!npt_enabled && !(efer & EFER_LMA))
231 efer &= ~EFER_LME;
232
233 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
234 vcpu->arch.shadow_efer = efer;
235 }
236
237 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
238 bool has_error_code, u32 error_code)
239 {
240 struct vcpu_svm *svm = to_svm(vcpu);
241
242 /* If we are within a nested VM we'd better #VMEXIT and let the
243 guest handle the exception */
244 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
245 return;
246
247 svm->vmcb->control.event_inj = nr
248 | SVM_EVTINJ_VALID
249 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
250 | SVM_EVTINJ_TYPE_EXEPT;
251 svm->vmcb->control.event_inj_err = error_code;
252 }
253
254 static int is_external_interrupt(u32 info)
255 {
256 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
257 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
258 }
259
260 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
261 {
262 struct vcpu_svm *svm = to_svm(vcpu);
263 u32 ret = 0;
264
265 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
266 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
267 return ret & mask;
268 }
269
270 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
271 {
272 struct vcpu_svm *svm = to_svm(vcpu);
273
274 if (mask == 0)
275 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
276 else
277 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
278
279 }
280
281 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
282 {
283 struct vcpu_svm *svm = to_svm(vcpu);
284
285 if (!svm->next_rip) {
286 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
287 EMULATE_DONE)
288 printk(KERN_DEBUG "%s: NOP\n", __func__);
289 return;
290 }
291 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
292 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
293 __func__, kvm_rip_read(vcpu), svm->next_rip);
294
295 kvm_rip_write(vcpu, svm->next_rip);
296 svm_set_interrupt_shadow(vcpu, 0);
297 }
298
299 static int has_svm(void)
300 {
301 const char *msg;
302
303 if (!cpu_has_svm(&msg)) {
304 printk(KERN_INFO "has_svm: %s\n", msg);
305 return 0;
306 }
307
308 return 1;
309 }
310
311 static void svm_hardware_disable(void *garbage)
312 {
313 cpu_svm_disable();
314 }
315
316 static int svm_hardware_enable(void *garbage)
317 {
318
319 struct svm_cpu_data *sd;
320 uint64_t efer;
321 struct descriptor_table gdt_descr;
322 struct desc_struct *gdt;
323 int me = raw_smp_processor_id();
324
325 rdmsrl(MSR_EFER, efer);
326 if (efer & EFER_SVME)
327 return -EBUSY;
328
329 if (!has_svm()) {
330 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
331 me);
332 return -EINVAL;
333 }
334 sd = per_cpu(svm_data, me);
335
336 if (!sd) {
337 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
338 me);
339 return -EINVAL;
340 }
341
342 sd->asid_generation = 1;
343 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
344 sd->next_asid = sd->max_asid + 1;
345
346 kvm_get_gdt(&gdt_descr);
347 gdt = (struct desc_struct *)gdt_descr.base;
348 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
349
350 wrmsrl(MSR_EFER, efer | EFER_SVME);
351
352 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
353
354 return 0;
355 }
356
357 static void svm_cpu_uninit(int cpu)
358 {
359 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
360
361 if (!sd)
362 return;
363
364 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
365 __free_page(sd->save_area);
366 kfree(sd);
367 }
368
369 static int svm_cpu_init(int cpu)
370 {
371 struct svm_cpu_data *sd;
372 int r;
373
374 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
375 if (!sd)
376 return -ENOMEM;
377 sd->cpu = cpu;
378 sd->save_area = alloc_page(GFP_KERNEL);
379 r = -ENOMEM;
380 if (!sd->save_area)
381 goto err_1;
382
383 per_cpu(svm_data, cpu) = sd;
384
385 return 0;
386
387 err_1:
388 kfree(sd);
389 return r;
390
391 }
392
393 static void set_msr_interception(u32 *msrpm, unsigned msr,
394 int read, int write)
395 {
396 int i;
397
398 for (i = 0; i < NUM_MSR_MAPS; i++) {
399 if (msr >= msrpm_ranges[i] &&
400 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
401 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
402 msrpm_ranges[i]) * 2;
403
404 u32 *base = msrpm + (msr_offset / 32);
405 u32 msr_shift = msr_offset % 32;
406 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
407 *base = (*base & ~(0x3 << msr_shift)) |
408 (mask << msr_shift);
409 return;
410 }
411 }
412 BUG();
413 }
414
415 static void svm_vcpu_init_msrpm(u32 *msrpm)
416 {
417 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
418
419 #ifdef CONFIG_X86_64
420 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
421 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
422 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
423 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
424 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
425 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
426 #endif
427 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
428 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
429 }
430
431 static void svm_enable_lbrv(struct vcpu_svm *svm)
432 {
433 u32 *msrpm = svm->msrpm;
434
435 svm->vmcb->control.lbr_ctl = 1;
436 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
437 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
438 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
439 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
440 }
441
442 static void svm_disable_lbrv(struct vcpu_svm *svm)
443 {
444 u32 *msrpm = svm->msrpm;
445
446 svm->vmcb->control.lbr_ctl = 0;
447 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
448 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
449 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
450 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
451 }
452
453 static __init int svm_hardware_setup(void)
454 {
455 int cpu;
456 struct page *iopm_pages;
457 void *iopm_va;
458 int r;
459
460 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
461
462 if (!iopm_pages)
463 return -ENOMEM;
464
465 iopm_va = page_address(iopm_pages);
466 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
467 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
468
469 if (boot_cpu_has(X86_FEATURE_NX))
470 kvm_enable_efer_bits(EFER_NX);
471
472 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
473 kvm_enable_efer_bits(EFER_FFXSR);
474
475 if (nested) {
476 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
477 kvm_enable_efer_bits(EFER_SVME);
478 }
479
480 for_each_possible_cpu(cpu) {
481 r = svm_cpu_init(cpu);
482 if (r)
483 goto err;
484 }
485
486 svm_features = cpuid_edx(SVM_CPUID_FUNC);
487
488 if (!svm_has(SVM_FEATURE_NPT))
489 npt_enabled = false;
490
491 if (npt_enabled && !npt) {
492 printk(KERN_INFO "kvm: Nested Paging disabled\n");
493 npt_enabled = false;
494 }
495
496 if (npt_enabled) {
497 printk(KERN_INFO "kvm: Nested Paging enabled\n");
498 kvm_enable_tdp();
499 } else
500 kvm_disable_tdp();
501
502 return 0;
503
504 err:
505 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
506 iopm_base = 0;
507 return r;
508 }
509
510 static __exit void svm_hardware_unsetup(void)
511 {
512 int cpu;
513
514 for_each_possible_cpu(cpu)
515 svm_cpu_uninit(cpu);
516
517 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
518 iopm_base = 0;
519 }
520
521 static void init_seg(struct vmcb_seg *seg)
522 {
523 seg->selector = 0;
524 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
525 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
526 seg->limit = 0xffff;
527 seg->base = 0;
528 }
529
530 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
531 {
532 seg->selector = 0;
533 seg->attrib = SVM_SELECTOR_P_MASK | type;
534 seg->limit = 0xffff;
535 seg->base = 0;
536 }
537
538 static void init_vmcb(struct vcpu_svm *svm)
539 {
540 struct vmcb_control_area *control = &svm->vmcb->control;
541 struct vmcb_save_area *save = &svm->vmcb->save;
542
543 control->intercept_cr_read = INTERCEPT_CR0_MASK |
544 INTERCEPT_CR3_MASK |
545 INTERCEPT_CR4_MASK;
546
547 control->intercept_cr_write = INTERCEPT_CR0_MASK |
548 INTERCEPT_CR3_MASK |
549 INTERCEPT_CR4_MASK |
550 INTERCEPT_CR8_MASK;
551
552 control->intercept_dr_read = INTERCEPT_DR0_MASK |
553 INTERCEPT_DR1_MASK |
554 INTERCEPT_DR2_MASK |
555 INTERCEPT_DR3_MASK;
556
557 control->intercept_dr_write = INTERCEPT_DR0_MASK |
558 INTERCEPT_DR1_MASK |
559 INTERCEPT_DR2_MASK |
560 INTERCEPT_DR3_MASK |
561 INTERCEPT_DR5_MASK |
562 INTERCEPT_DR7_MASK;
563
564 control->intercept_exceptions = (1 << PF_VECTOR) |
565 (1 << UD_VECTOR) |
566 (1 << MC_VECTOR);
567
568
569 control->intercept = (1ULL << INTERCEPT_INTR) |
570 (1ULL << INTERCEPT_NMI) |
571 (1ULL << INTERCEPT_SMI) |
572 (1ULL << INTERCEPT_CPUID) |
573 (1ULL << INTERCEPT_INVD) |
574 (1ULL << INTERCEPT_HLT) |
575 (1ULL << INTERCEPT_INVLPG) |
576 (1ULL << INTERCEPT_INVLPGA) |
577 (1ULL << INTERCEPT_IOIO_PROT) |
578 (1ULL << INTERCEPT_MSR_PROT) |
579 (1ULL << INTERCEPT_TASK_SWITCH) |
580 (1ULL << INTERCEPT_SHUTDOWN) |
581 (1ULL << INTERCEPT_VMRUN) |
582 (1ULL << INTERCEPT_VMMCALL) |
583 (1ULL << INTERCEPT_VMLOAD) |
584 (1ULL << INTERCEPT_VMSAVE) |
585 (1ULL << INTERCEPT_STGI) |
586 (1ULL << INTERCEPT_CLGI) |
587 (1ULL << INTERCEPT_SKINIT) |
588 (1ULL << INTERCEPT_WBINVD) |
589 (1ULL << INTERCEPT_MONITOR) |
590 (1ULL << INTERCEPT_MWAIT);
591
592 control->iopm_base_pa = iopm_base;
593 control->msrpm_base_pa = __pa(svm->msrpm);
594 control->tsc_offset = 0;
595 control->int_ctl = V_INTR_MASKING_MASK;
596
597 init_seg(&save->es);
598 init_seg(&save->ss);
599 init_seg(&save->ds);
600 init_seg(&save->fs);
601 init_seg(&save->gs);
602
603 save->cs.selector = 0xf000;
604 /* Executable/Readable Code Segment */
605 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
606 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
607 save->cs.limit = 0xffff;
608 /*
609 * cs.base should really be 0xffff0000, but vmx can't handle that, so
610 * be consistent with it.
611 *
612 * Replace when we have real mode working for vmx.
613 */
614 save->cs.base = 0xf0000;
615
616 save->gdtr.limit = 0xffff;
617 save->idtr.limit = 0xffff;
618
619 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
620 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
621
622 save->efer = EFER_SVME;
623 save->dr6 = 0xffff0ff0;
624 save->dr7 = 0x400;
625 save->rflags = 2;
626 save->rip = 0x0000fff0;
627 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
628
629 /* This is the guest-visible cr0 value.
630 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
631 */
632 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
633 kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
634
635 save->cr4 = X86_CR4_PAE;
636 /* rdx = ?? */
637
638 if (npt_enabled) {
639 /* Setup VMCB for Nested Paging */
640 control->nested_ctl = 1;
641 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
642 (1ULL << INTERCEPT_INVLPG));
643 control->intercept_exceptions &= ~(1 << PF_VECTOR);
644 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
645 INTERCEPT_CR3_MASK);
646 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
647 INTERCEPT_CR3_MASK);
648 save->g_pat = 0x0007040600070406ULL;
649 save->cr3 = 0;
650 save->cr4 = 0;
651 }
652 force_new_asid(&svm->vcpu);
653
654 svm->nested.vmcb = 0;
655 svm->vcpu.arch.hflags = 0;
656
657 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
658 control->pause_filter_count = 3000;
659 control->intercept |= (1ULL << INTERCEPT_PAUSE);
660 }
661
662 enable_gif(svm);
663 }
664
665 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
666 {
667 struct vcpu_svm *svm = to_svm(vcpu);
668
669 init_vmcb(svm);
670
671 if (!kvm_vcpu_is_bsp(vcpu)) {
672 kvm_rip_write(vcpu, 0);
673 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
674 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
675 }
676 vcpu->arch.regs_avail = ~0;
677 vcpu->arch.regs_dirty = ~0;
678
679 return 0;
680 }
681
682 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
683 {
684 struct vcpu_svm *svm;
685 struct page *page;
686 struct page *msrpm_pages;
687 struct page *hsave_page;
688 struct page *nested_msrpm_pages;
689 int err;
690
691 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
692 if (!svm) {
693 err = -ENOMEM;
694 goto out;
695 }
696
697 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
698 if (err)
699 goto free_svm;
700
701 page = alloc_page(GFP_KERNEL);
702 if (!page) {
703 err = -ENOMEM;
704 goto uninit;
705 }
706
707 err = -ENOMEM;
708 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
709 if (!msrpm_pages)
710 goto uninit;
711
712 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
713 if (!nested_msrpm_pages)
714 goto uninit;
715
716 svm->msrpm = page_address(msrpm_pages);
717 svm_vcpu_init_msrpm(svm->msrpm);
718
719 hsave_page = alloc_page(GFP_KERNEL);
720 if (!hsave_page)
721 goto uninit;
722 svm->nested.hsave = page_address(hsave_page);
723
724 svm->nested.msrpm = page_address(nested_msrpm_pages);
725
726 svm->vmcb = page_address(page);
727 clear_page(svm->vmcb);
728 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
729 svm->asid_generation = 0;
730 init_vmcb(svm);
731
732 fx_init(&svm->vcpu);
733 svm->vcpu.fpu_active = 1;
734 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
735 if (kvm_vcpu_is_bsp(&svm->vcpu))
736 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
737
738 return &svm->vcpu;
739
740 uninit:
741 kvm_vcpu_uninit(&svm->vcpu);
742 free_svm:
743 kmem_cache_free(kvm_vcpu_cache, svm);
744 out:
745 return ERR_PTR(err);
746 }
747
748 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
749 {
750 struct vcpu_svm *svm = to_svm(vcpu);
751
752 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
753 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
754 __free_page(virt_to_page(svm->nested.hsave));
755 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
756 kvm_vcpu_uninit(vcpu);
757 kmem_cache_free(kvm_vcpu_cache, svm);
758 }
759
760 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
761 {
762 struct vcpu_svm *svm = to_svm(vcpu);
763 int i;
764
765 if (unlikely(cpu != vcpu->cpu)) {
766 u64 delta;
767
768 if (check_tsc_unstable()) {
769 /*
770 * Make sure that the guest sees a monotonically
771 * increasing TSC.
772 */
773 delta = vcpu->arch.host_tsc - native_read_tsc();
774 svm->vmcb->control.tsc_offset += delta;
775 if (is_nested(svm))
776 svm->nested.hsave->control.tsc_offset += delta;
777 }
778 vcpu->cpu = cpu;
779 kvm_migrate_timers(vcpu);
780 svm->asid_generation = 0;
781 }
782
783 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
784 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
785 }
786
787 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
788 {
789 struct vcpu_svm *svm = to_svm(vcpu);
790 int i;
791
792 ++vcpu->stat.host_state_reload;
793 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
794 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
795
796 vcpu->arch.host_tsc = native_read_tsc();
797 }
798
799 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
800 {
801 return to_svm(vcpu)->vmcb->save.rflags;
802 }
803
804 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
805 {
806 to_svm(vcpu)->vmcb->save.rflags = rflags;
807 }
808
809 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
810 {
811 switch (reg) {
812 case VCPU_EXREG_PDPTR:
813 BUG_ON(!npt_enabled);
814 load_pdptrs(vcpu, vcpu->arch.cr3);
815 break;
816 default:
817 BUG();
818 }
819 }
820
821 static void svm_set_vintr(struct vcpu_svm *svm)
822 {
823 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
824 }
825
826 static void svm_clear_vintr(struct vcpu_svm *svm)
827 {
828 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
829 }
830
831 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
832 {
833 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
834
835 switch (seg) {
836 case VCPU_SREG_CS: return &save->cs;
837 case VCPU_SREG_DS: return &save->ds;
838 case VCPU_SREG_ES: return &save->es;
839 case VCPU_SREG_FS: return &save->fs;
840 case VCPU_SREG_GS: return &save->gs;
841 case VCPU_SREG_SS: return &save->ss;
842 case VCPU_SREG_TR: return &save->tr;
843 case VCPU_SREG_LDTR: return &save->ldtr;
844 }
845 BUG();
846 return NULL;
847 }
848
849 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
850 {
851 struct vmcb_seg *s = svm_seg(vcpu, seg);
852
853 return s->base;
854 }
855
856 static void svm_get_segment(struct kvm_vcpu *vcpu,
857 struct kvm_segment *var, int seg)
858 {
859 struct vmcb_seg *s = svm_seg(vcpu, seg);
860
861 var->base = s->base;
862 var->limit = s->limit;
863 var->selector = s->selector;
864 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
865 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
866 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
867 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
868 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
869 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
870 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
871 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
872
873 /* AMD's VMCB does not have an explicit unusable field, so emulate it
874 * for cross vendor migration purposes by "not present"
875 */
876 var->unusable = !var->present || (var->type == 0);
877
878 switch (seg) {
879 case VCPU_SREG_CS:
880 /*
881 * SVM always stores 0 for the 'G' bit in the CS selector in
882 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
883 * Intel's VMENTRY has a check on the 'G' bit.
884 */
885 var->g = s->limit > 0xfffff;
886 break;
887 case VCPU_SREG_TR:
888 /*
889 * Work around a bug where the busy flag in the tr selector
890 * isn't exposed
891 */
892 var->type |= 0x2;
893 break;
894 case VCPU_SREG_DS:
895 case VCPU_SREG_ES:
896 case VCPU_SREG_FS:
897 case VCPU_SREG_GS:
898 /*
899 * The accessed bit must always be set in the segment
900 * descriptor cache, although it can be cleared in the
901 * descriptor, the cached bit always remains at 1. Since
902 * Intel has a check on this, set it here to support
903 * cross-vendor migration.
904 */
905 if (!var->unusable)
906 var->type |= 0x1;
907 break;
908 case VCPU_SREG_SS:
909 /* On AMD CPUs sometimes the DB bit in the segment
910 * descriptor is left as 1, although the whole segment has
911 * been made unusable. Clear it here to pass an Intel VMX
912 * entry check when cross vendor migrating.
913 */
914 if (var->unusable)
915 var->db = 0;
916 break;
917 }
918 }
919
920 static int svm_get_cpl(struct kvm_vcpu *vcpu)
921 {
922 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
923
924 return save->cpl;
925 }
926
927 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
928 {
929 struct vcpu_svm *svm = to_svm(vcpu);
930
931 dt->limit = svm->vmcb->save.idtr.limit;
932 dt->base = svm->vmcb->save.idtr.base;
933 }
934
935 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
936 {
937 struct vcpu_svm *svm = to_svm(vcpu);
938
939 svm->vmcb->save.idtr.limit = dt->limit;
940 svm->vmcb->save.idtr.base = dt->base ;
941 }
942
943 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
944 {
945 struct vcpu_svm *svm = to_svm(vcpu);
946
947 dt->limit = svm->vmcb->save.gdtr.limit;
948 dt->base = svm->vmcb->save.gdtr.base;
949 }
950
951 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
952 {
953 struct vcpu_svm *svm = to_svm(vcpu);
954
955 svm->vmcb->save.gdtr.limit = dt->limit;
956 svm->vmcb->save.gdtr.base = dt->base ;
957 }
958
959 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
960 {
961 }
962
963 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
964 {
965 }
966
967 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
968 {
969 struct vcpu_svm *svm = to_svm(vcpu);
970
971 #ifdef CONFIG_X86_64
972 if (vcpu->arch.shadow_efer & EFER_LME) {
973 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
974 vcpu->arch.shadow_efer |= EFER_LMA;
975 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
976 }
977
978 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
979 vcpu->arch.shadow_efer &= ~EFER_LMA;
980 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
981 }
982 }
983 #endif
984 if (npt_enabled)
985 goto set;
986
987 if (kvm_read_cr0_bits(vcpu, X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
988 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
989 vcpu->fpu_active = 1;
990 }
991
992 vcpu->arch.cr0 = cr0;
993 cr0 |= X86_CR0_PG | X86_CR0_WP;
994 if (!vcpu->fpu_active) {
995 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
996 cr0 |= X86_CR0_TS;
997 }
998 set:
999 /*
1000 * re-enable caching here because the QEMU bios
1001 * does not do it - this results in some delay at
1002 * reboot
1003 */
1004 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1005 svm->vmcb->save.cr0 = cr0;
1006 }
1007
1008 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1009 {
1010 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1011 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1012
1013 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1014 force_new_asid(vcpu);
1015
1016 vcpu->arch.cr4 = cr4;
1017 if (!npt_enabled)
1018 cr4 |= X86_CR4_PAE;
1019 cr4 |= host_cr4_mce;
1020 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1021 }
1022
1023 static void svm_set_segment(struct kvm_vcpu *vcpu,
1024 struct kvm_segment *var, int seg)
1025 {
1026 struct vcpu_svm *svm = to_svm(vcpu);
1027 struct vmcb_seg *s = svm_seg(vcpu, seg);
1028
1029 s->base = var->base;
1030 s->limit = var->limit;
1031 s->selector = var->selector;
1032 if (var->unusable)
1033 s->attrib = 0;
1034 else {
1035 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1036 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1037 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1038 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1039 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1040 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1041 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1042 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1043 }
1044 if (seg == VCPU_SREG_CS)
1045 svm->vmcb->save.cpl
1046 = (svm->vmcb->save.cs.attrib
1047 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1048
1049 }
1050
1051 static void update_db_intercept(struct kvm_vcpu *vcpu)
1052 {
1053 struct vcpu_svm *svm = to_svm(vcpu);
1054
1055 svm->vmcb->control.intercept_exceptions &=
1056 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1057
1058 if (svm->nmi_singlestep)
1059 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1060
1061 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1062 if (vcpu->guest_debug &
1063 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1064 svm->vmcb->control.intercept_exceptions |=
1065 1 << DB_VECTOR;
1066 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1067 svm->vmcb->control.intercept_exceptions |=
1068 1 << BP_VECTOR;
1069 } else
1070 vcpu->guest_debug = 0;
1071 }
1072
1073 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1074 {
1075 struct vcpu_svm *svm = to_svm(vcpu);
1076
1077 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1078 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1079 else
1080 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1081
1082 update_db_intercept(vcpu);
1083 }
1084
1085 static void load_host_msrs(struct kvm_vcpu *vcpu)
1086 {
1087 #ifdef CONFIG_X86_64
1088 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1089 #endif
1090 }
1091
1092 static void save_host_msrs(struct kvm_vcpu *vcpu)
1093 {
1094 #ifdef CONFIG_X86_64
1095 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1096 #endif
1097 }
1098
1099 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1100 {
1101 if (sd->next_asid > sd->max_asid) {
1102 ++sd->asid_generation;
1103 sd->next_asid = 1;
1104 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1105 }
1106
1107 svm->asid_generation = sd->asid_generation;
1108 svm->vmcb->control.asid = sd->next_asid++;
1109 }
1110
1111 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1112 {
1113 struct vcpu_svm *svm = to_svm(vcpu);
1114 unsigned long val;
1115
1116 switch (dr) {
1117 case 0 ... 3:
1118 val = vcpu->arch.db[dr];
1119 break;
1120 case 6:
1121 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1122 val = vcpu->arch.dr6;
1123 else
1124 val = svm->vmcb->save.dr6;
1125 break;
1126 case 7:
1127 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1128 val = vcpu->arch.dr7;
1129 else
1130 val = svm->vmcb->save.dr7;
1131 break;
1132 default:
1133 val = 0;
1134 }
1135
1136 return val;
1137 }
1138
1139 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1140 int *exception)
1141 {
1142 struct vcpu_svm *svm = to_svm(vcpu);
1143
1144 *exception = 0;
1145
1146 switch (dr) {
1147 case 0 ... 3:
1148 vcpu->arch.db[dr] = value;
1149 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1150 vcpu->arch.eff_db[dr] = value;
1151 return;
1152 case 4 ... 5:
1153 if (vcpu->arch.cr4 & X86_CR4_DE)
1154 *exception = UD_VECTOR;
1155 return;
1156 case 6:
1157 if (value & 0xffffffff00000000ULL) {
1158 *exception = GP_VECTOR;
1159 return;
1160 }
1161 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1162 return;
1163 case 7:
1164 if (value & 0xffffffff00000000ULL) {
1165 *exception = GP_VECTOR;
1166 return;
1167 }
1168 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1169 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1170 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1171 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1172 }
1173 return;
1174 default:
1175 /* FIXME: Possible case? */
1176 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1177 __func__, dr);
1178 *exception = UD_VECTOR;
1179 return;
1180 }
1181 }
1182
1183 static int pf_interception(struct vcpu_svm *svm)
1184 {
1185 u64 fault_address;
1186 u32 error_code;
1187
1188 fault_address = svm->vmcb->control.exit_info_2;
1189 error_code = svm->vmcb->control.exit_info_1;
1190
1191 trace_kvm_page_fault(fault_address, error_code);
1192 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1193 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1194 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1195 }
1196
1197 static int db_interception(struct vcpu_svm *svm)
1198 {
1199 struct kvm_run *kvm_run = svm->vcpu.run;
1200
1201 if (!(svm->vcpu.guest_debug &
1202 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1203 !svm->nmi_singlestep) {
1204 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1205 return 1;
1206 }
1207
1208 if (svm->nmi_singlestep) {
1209 svm->nmi_singlestep = false;
1210 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1211 svm->vmcb->save.rflags &=
1212 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1213 update_db_intercept(&svm->vcpu);
1214 }
1215
1216 if (svm->vcpu.guest_debug &
1217 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1218 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1219 kvm_run->debug.arch.pc =
1220 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1221 kvm_run->debug.arch.exception = DB_VECTOR;
1222 return 0;
1223 }
1224
1225 return 1;
1226 }
1227
1228 static int bp_interception(struct vcpu_svm *svm)
1229 {
1230 struct kvm_run *kvm_run = svm->vcpu.run;
1231
1232 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1233 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1234 kvm_run->debug.arch.exception = BP_VECTOR;
1235 return 0;
1236 }
1237
1238 static int ud_interception(struct vcpu_svm *svm)
1239 {
1240 int er;
1241
1242 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1243 if (er != EMULATE_DONE)
1244 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1245 return 1;
1246 }
1247
1248 static int nm_interception(struct vcpu_svm *svm)
1249 {
1250 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1251 if (!kvm_read_cr0_bits(&svm->vcpu, X86_CR0_TS))
1252 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1253 svm->vcpu.fpu_active = 1;
1254
1255 return 1;
1256 }
1257
1258 static int mc_interception(struct vcpu_svm *svm)
1259 {
1260 /*
1261 * On an #MC intercept the MCE handler is not called automatically in
1262 * the host. So do it by hand here.
1263 */
1264 asm volatile (
1265 "int $0x12\n");
1266 /* not sure if we ever come back to this point */
1267
1268 return 1;
1269 }
1270
1271 static int shutdown_interception(struct vcpu_svm *svm)
1272 {
1273 struct kvm_run *kvm_run = svm->vcpu.run;
1274
1275 /*
1276 * VMCB is undefined after a SHUTDOWN intercept
1277 * so reinitialize it.
1278 */
1279 clear_page(svm->vmcb);
1280 init_vmcb(svm);
1281
1282 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1283 return 0;
1284 }
1285
1286 static int io_interception(struct vcpu_svm *svm)
1287 {
1288 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1289 int size, in, string;
1290 unsigned port;
1291
1292 ++svm->vcpu.stat.io_exits;
1293
1294 svm->next_rip = svm->vmcb->control.exit_info_2;
1295
1296 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1297
1298 if (string) {
1299 if (emulate_instruction(&svm->vcpu,
1300 0, 0, 0) == EMULATE_DO_MMIO)
1301 return 0;
1302 return 1;
1303 }
1304
1305 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1306 port = io_info >> 16;
1307 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1308
1309 skip_emulated_instruction(&svm->vcpu);
1310 return kvm_emulate_pio(&svm->vcpu, in, size, port);
1311 }
1312
1313 static int nmi_interception(struct vcpu_svm *svm)
1314 {
1315 return 1;
1316 }
1317
1318 static int intr_interception(struct vcpu_svm *svm)
1319 {
1320 ++svm->vcpu.stat.irq_exits;
1321 return 1;
1322 }
1323
1324 static int nop_on_interception(struct vcpu_svm *svm)
1325 {
1326 return 1;
1327 }
1328
1329 static int halt_interception(struct vcpu_svm *svm)
1330 {
1331 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1332 skip_emulated_instruction(&svm->vcpu);
1333 return kvm_emulate_halt(&svm->vcpu);
1334 }
1335
1336 static int vmmcall_interception(struct vcpu_svm *svm)
1337 {
1338 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1339 skip_emulated_instruction(&svm->vcpu);
1340 kvm_emulate_hypercall(&svm->vcpu);
1341 return 1;
1342 }
1343
1344 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1345 {
1346 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1347 || !is_paging(&svm->vcpu)) {
1348 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1349 return 1;
1350 }
1351
1352 if (svm->vmcb->save.cpl) {
1353 kvm_inject_gp(&svm->vcpu, 0);
1354 return 1;
1355 }
1356
1357 return 0;
1358 }
1359
1360 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1361 bool has_error_code, u32 error_code)
1362 {
1363 if (!is_nested(svm))
1364 return 0;
1365
1366 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1367 svm->vmcb->control.exit_code_hi = 0;
1368 svm->vmcb->control.exit_info_1 = error_code;
1369 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1370
1371 return nested_svm_exit_handled(svm);
1372 }
1373
1374 static inline int nested_svm_intr(struct vcpu_svm *svm)
1375 {
1376 if (!is_nested(svm))
1377 return 0;
1378
1379 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1380 return 0;
1381
1382 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1383 return 0;
1384
1385 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1386
1387 if (svm->nested.intercept & 1ULL) {
1388 /*
1389 * The #vmexit can't be emulated here directly because this
1390 * code path runs with irqs and preemtion disabled. A
1391 * #vmexit emulation might sleep. Only signal request for
1392 * the #vmexit here.
1393 */
1394 svm->nested.exit_required = true;
1395 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1396 return 1;
1397 }
1398
1399 return 0;
1400 }
1401
1402 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1403 {
1404 struct page *page;
1405
1406 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1407 if (is_error_page(page))
1408 goto error;
1409
1410 return kmap_atomic(page, idx);
1411
1412 error:
1413 kvm_release_page_clean(page);
1414 kvm_inject_gp(&svm->vcpu, 0);
1415
1416 return NULL;
1417 }
1418
1419 static void nested_svm_unmap(void *addr, enum km_type idx)
1420 {
1421 struct page *page;
1422
1423 if (!addr)
1424 return;
1425
1426 page = kmap_atomic_to_page(addr);
1427
1428 kunmap_atomic(addr, idx);
1429 kvm_release_page_dirty(page);
1430 }
1431
1432 static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1433 {
1434 u32 param = svm->vmcb->control.exit_info_1 & 1;
1435 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1436 bool ret = false;
1437 u32 t0, t1;
1438 u8 *msrpm;
1439
1440 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1441 return false;
1442
1443 msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1444
1445 if (!msrpm)
1446 goto out;
1447
1448 switch (msr) {
1449 case 0 ... 0x1fff:
1450 t0 = (msr * 2) % 8;
1451 t1 = msr / 8;
1452 break;
1453 case 0xc0000000 ... 0xc0001fff:
1454 t0 = (8192 + msr - 0xc0000000) * 2;
1455 t1 = (t0 / 8);
1456 t0 %= 8;
1457 break;
1458 case 0xc0010000 ... 0xc0011fff:
1459 t0 = (16384 + msr - 0xc0010000) * 2;
1460 t1 = (t0 / 8);
1461 t0 %= 8;
1462 break;
1463 default:
1464 ret = true;
1465 goto out;
1466 }
1467
1468 ret = msrpm[t1] & ((1 << param) << t0);
1469
1470 out:
1471 nested_svm_unmap(msrpm, KM_USER0);
1472
1473 return ret;
1474 }
1475
1476 static int nested_svm_exit_special(struct vcpu_svm *svm)
1477 {
1478 u32 exit_code = svm->vmcb->control.exit_code;
1479
1480 switch (exit_code) {
1481 case SVM_EXIT_INTR:
1482 case SVM_EXIT_NMI:
1483 return NESTED_EXIT_HOST;
1484 /* For now we are always handling NPFs when using them */
1485 case SVM_EXIT_NPF:
1486 if (npt_enabled)
1487 return NESTED_EXIT_HOST;
1488 break;
1489 /* When we're shadowing, trap PFs */
1490 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1491 if (!npt_enabled)
1492 return NESTED_EXIT_HOST;
1493 break;
1494 default:
1495 break;
1496 }
1497
1498 return NESTED_EXIT_CONTINUE;
1499 }
1500
1501 /*
1502 * If this function returns true, this #vmexit was already handled
1503 */
1504 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1505 {
1506 u32 exit_code = svm->vmcb->control.exit_code;
1507 int vmexit = NESTED_EXIT_HOST;
1508
1509 switch (exit_code) {
1510 case SVM_EXIT_MSR:
1511 vmexit = nested_svm_exit_handled_msr(svm);
1512 break;
1513 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1514 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1515 if (svm->nested.intercept_cr_read & cr_bits)
1516 vmexit = NESTED_EXIT_DONE;
1517 break;
1518 }
1519 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1520 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1521 if (svm->nested.intercept_cr_write & cr_bits)
1522 vmexit = NESTED_EXIT_DONE;
1523 break;
1524 }
1525 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1526 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1527 if (svm->nested.intercept_dr_read & dr_bits)
1528 vmexit = NESTED_EXIT_DONE;
1529 break;
1530 }
1531 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1532 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1533 if (svm->nested.intercept_dr_write & dr_bits)
1534 vmexit = NESTED_EXIT_DONE;
1535 break;
1536 }
1537 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1538 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1539 if (svm->nested.intercept_exceptions & excp_bits)
1540 vmexit = NESTED_EXIT_DONE;
1541 break;
1542 }
1543 default: {
1544 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1545 if (svm->nested.intercept & exit_bits)
1546 vmexit = NESTED_EXIT_DONE;
1547 }
1548 }
1549
1550 if (vmexit == NESTED_EXIT_DONE) {
1551 nested_svm_vmexit(svm);
1552 }
1553
1554 return vmexit;
1555 }
1556
1557 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1558 {
1559 struct vmcb_control_area *dst = &dst_vmcb->control;
1560 struct vmcb_control_area *from = &from_vmcb->control;
1561
1562 dst->intercept_cr_read = from->intercept_cr_read;
1563 dst->intercept_cr_write = from->intercept_cr_write;
1564 dst->intercept_dr_read = from->intercept_dr_read;
1565 dst->intercept_dr_write = from->intercept_dr_write;
1566 dst->intercept_exceptions = from->intercept_exceptions;
1567 dst->intercept = from->intercept;
1568 dst->iopm_base_pa = from->iopm_base_pa;
1569 dst->msrpm_base_pa = from->msrpm_base_pa;
1570 dst->tsc_offset = from->tsc_offset;
1571 dst->asid = from->asid;
1572 dst->tlb_ctl = from->tlb_ctl;
1573 dst->int_ctl = from->int_ctl;
1574 dst->int_vector = from->int_vector;
1575 dst->int_state = from->int_state;
1576 dst->exit_code = from->exit_code;
1577 dst->exit_code_hi = from->exit_code_hi;
1578 dst->exit_info_1 = from->exit_info_1;
1579 dst->exit_info_2 = from->exit_info_2;
1580 dst->exit_int_info = from->exit_int_info;
1581 dst->exit_int_info_err = from->exit_int_info_err;
1582 dst->nested_ctl = from->nested_ctl;
1583 dst->event_inj = from->event_inj;
1584 dst->event_inj_err = from->event_inj_err;
1585 dst->nested_cr3 = from->nested_cr3;
1586 dst->lbr_ctl = from->lbr_ctl;
1587 }
1588
1589 static int nested_svm_vmexit(struct vcpu_svm *svm)
1590 {
1591 struct vmcb *nested_vmcb;
1592 struct vmcb *hsave = svm->nested.hsave;
1593 struct vmcb *vmcb = svm->vmcb;
1594
1595 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1596 vmcb->control.exit_info_1,
1597 vmcb->control.exit_info_2,
1598 vmcb->control.exit_int_info,
1599 vmcb->control.exit_int_info_err);
1600
1601 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1602 if (!nested_vmcb)
1603 return 1;
1604
1605 /* Give the current vmcb to the guest */
1606 disable_gif(svm);
1607
1608 nested_vmcb->save.es = vmcb->save.es;
1609 nested_vmcb->save.cs = vmcb->save.cs;
1610 nested_vmcb->save.ss = vmcb->save.ss;
1611 nested_vmcb->save.ds = vmcb->save.ds;
1612 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1613 nested_vmcb->save.idtr = vmcb->save.idtr;
1614 if (npt_enabled)
1615 nested_vmcb->save.cr3 = vmcb->save.cr3;
1616 nested_vmcb->save.cr2 = vmcb->save.cr2;
1617 nested_vmcb->save.rflags = vmcb->save.rflags;
1618 nested_vmcb->save.rip = vmcb->save.rip;
1619 nested_vmcb->save.rsp = vmcb->save.rsp;
1620 nested_vmcb->save.rax = vmcb->save.rax;
1621 nested_vmcb->save.dr7 = vmcb->save.dr7;
1622 nested_vmcb->save.dr6 = vmcb->save.dr6;
1623 nested_vmcb->save.cpl = vmcb->save.cpl;
1624
1625 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1626 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1627 nested_vmcb->control.int_state = vmcb->control.int_state;
1628 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1629 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1630 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1631 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1632 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1633 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1634
1635 /*
1636 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1637 * to make sure that we do not lose injected events. So check event_inj
1638 * here and copy it to exit_int_info if it is valid.
1639 * Exit_int_info and event_inj can't be both valid because the case
1640 * below only happens on a VMRUN instruction intercept which has
1641 * no valid exit_int_info set.
1642 */
1643 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1644 struct vmcb_control_area *nc = &nested_vmcb->control;
1645
1646 nc->exit_int_info = vmcb->control.event_inj;
1647 nc->exit_int_info_err = vmcb->control.event_inj_err;
1648 }
1649
1650 nested_vmcb->control.tlb_ctl = 0;
1651 nested_vmcb->control.event_inj = 0;
1652 nested_vmcb->control.event_inj_err = 0;
1653
1654 /* We always set V_INTR_MASKING and remember the old value in hflags */
1655 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1656 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1657
1658 /* Restore the original control entries */
1659 copy_vmcb_control_area(vmcb, hsave);
1660
1661 kvm_clear_exception_queue(&svm->vcpu);
1662 kvm_clear_interrupt_queue(&svm->vcpu);
1663
1664 /* Restore selected save entries */
1665 svm->vmcb->save.es = hsave->save.es;
1666 svm->vmcb->save.cs = hsave->save.cs;
1667 svm->vmcb->save.ss = hsave->save.ss;
1668 svm->vmcb->save.ds = hsave->save.ds;
1669 svm->vmcb->save.gdtr = hsave->save.gdtr;
1670 svm->vmcb->save.idtr = hsave->save.idtr;
1671 svm->vmcb->save.rflags = hsave->save.rflags;
1672 svm_set_efer(&svm->vcpu, hsave->save.efer);
1673 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1674 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1675 if (npt_enabled) {
1676 svm->vmcb->save.cr3 = hsave->save.cr3;
1677 svm->vcpu.arch.cr3 = hsave->save.cr3;
1678 } else {
1679 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1680 }
1681 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1682 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1683 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1684 svm->vmcb->save.dr7 = 0;
1685 svm->vmcb->save.cpl = 0;
1686 svm->vmcb->control.exit_int_info = 0;
1687
1688 /* Exit nested SVM mode */
1689 svm->nested.vmcb = 0;
1690
1691 nested_svm_unmap(nested_vmcb, KM_USER0);
1692
1693 kvm_mmu_reset_context(&svm->vcpu);
1694 kvm_mmu_load(&svm->vcpu);
1695
1696 return 0;
1697 }
1698
1699 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1700 {
1701 u32 *nested_msrpm;
1702 int i;
1703
1704 nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1705 if (!nested_msrpm)
1706 return false;
1707
1708 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1709 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1710
1711 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1712
1713 nested_svm_unmap(nested_msrpm, KM_USER0);
1714
1715 return true;
1716 }
1717
1718 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1719 {
1720 struct vmcb *nested_vmcb;
1721 struct vmcb *hsave = svm->nested.hsave;
1722 struct vmcb *vmcb = svm->vmcb;
1723
1724 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1725 if (!nested_vmcb)
1726 return false;
1727
1728 /* nested_vmcb is our indicator if nested SVM is activated */
1729 svm->nested.vmcb = svm->vmcb->save.rax;
1730
1731 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb,
1732 nested_vmcb->save.rip,
1733 nested_vmcb->control.int_ctl,
1734 nested_vmcb->control.event_inj,
1735 nested_vmcb->control.nested_ctl);
1736
1737 /* Clear internal status */
1738 kvm_clear_exception_queue(&svm->vcpu);
1739 kvm_clear_interrupt_queue(&svm->vcpu);
1740
1741 /* Save the old vmcb, so we don't need to pick what we save, but
1742 can restore everything when a VMEXIT occurs */
1743 hsave->save.es = vmcb->save.es;
1744 hsave->save.cs = vmcb->save.cs;
1745 hsave->save.ss = vmcb->save.ss;
1746 hsave->save.ds = vmcb->save.ds;
1747 hsave->save.gdtr = vmcb->save.gdtr;
1748 hsave->save.idtr = vmcb->save.idtr;
1749 hsave->save.efer = svm->vcpu.arch.shadow_efer;
1750 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
1751 hsave->save.cr4 = svm->vcpu.arch.cr4;
1752 hsave->save.rflags = vmcb->save.rflags;
1753 hsave->save.rip = svm->next_rip;
1754 hsave->save.rsp = vmcb->save.rsp;
1755 hsave->save.rax = vmcb->save.rax;
1756 if (npt_enabled)
1757 hsave->save.cr3 = vmcb->save.cr3;
1758 else
1759 hsave->save.cr3 = svm->vcpu.arch.cr3;
1760
1761 copy_vmcb_control_area(hsave, vmcb);
1762
1763 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1764 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1765 else
1766 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1767
1768 /* Load the nested guest state */
1769 svm->vmcb->save.es = nested_vmcb->save.es;
1770 svm->vmcb->save.cs = nested_vmcb->save.cs;
1771 svm->vmcb->save.ss = nested_vmcb->save.ss;
1772 svm->vmcb->save.ds = nested_vmcb->save.ds;
1773 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1774 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1775 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1776 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1777 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1778 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1779 if (npt_enabled) {
1780 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1781 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1782 } else {
1783 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1784 kvm_mmu_reset_context(&svm->vcpu);
1785 }
1786 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1787 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1788 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1789 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1790 /* In case we don't even reach vcpu_run, the fields are not updated */
1791 svm->vmcb->save.rax = nested_vmcb->save.rax;
1792 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1793 svm->vmcb->save.rip = nested_vmcb->save.rip;
1794 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1795 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1796 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1797
1798 /* We don't want a nested guest to be more powerful than the guest,
1799 so all intercepts are ORed */
1800 svm->vmcb->control.intercept_cr_read |=
1801 nested_vmcb->control.intercept_cr_read;
1802 svm->vmcb->control.intercept_cr_write |=
1803 nested_vmcb->control.intercept_cr_write;
1804 svm->vmcb->control.intercept_dr_read |=
1805 nested_vmcb->control.intercept_dr_read;
1806 svm->vmcb->control.intercept_dr_write |=
1807 nested_vmcb->control.intercept_dr_write;
1808 svm->vmcb->control.intercept_exceptions |=
1809 nested_vmcb->control.intercept_exceptions;
1810
1811 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1812
1813 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1814
1815 /* cache intercepts */
1816 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1817 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1818 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1819 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1820 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1821 svm->nested.intercept = nested_vmcb->control.intercept;
1822
1823 force_new_asid(&svm->vcpu);
1824 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1825 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1826 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1827 else
1828 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1829
1830 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1831 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1832 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1833 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1834 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1835
1836 nested_svm_unmap(nested_vmcb, KM_USER0);
1837
1838 enable_gif(svm);
1839
1840 return true;
1841 }
1842
1843 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1844 {
1845 to_vmcb->save.fs = from_vmcb->save.fs;
1846 to_vmcb->save.gs = from_vmcb->save.gs;
1847 to_vmcb->save.tr = from_vmcb->save.tr;
1848 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1849 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1850 to_vmcb->save.star = from_vmcb->save.star;
1851 to_vmcb->save.lstar = from_vmcb->save.lstar;
1852 to_vmcb->save.cstar = from_vmcb->save.cstar;
1853 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1854 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1855 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1856 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1857 }
1858
1859 static int vmload_interception(struct vcpu_svm *svm)
1860 {
1861 struct vmcb *nested_vmcb;
1862
1863 if (nested_svm_check_permissions(svm))
1864 return 1;
1865
1866 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1867 skip_emulated_instruction(&svm->vcpu);
1868
1869 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1870 if (!nested_vmcb)
1871 return 1;
1872
1873 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1874 nested_svm_unmap(nested_vmcb, KM_USER0);
1875
1876 return 1;
1877 }
1878
1879 static int vmsave_interception(struct vcpu_svm *svm)
1880 {
1881 struct vmcb *nested_vmcb;
1882
1883 if (nested_svm_check_permissions(svm))
1884 return 1;
1885
1886 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1887 skip_emulated_instruction(&svm->vcpu);
1888
1889 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1890 if (!nested_vmcb)
1891 return 1;
1892
1893 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1894 nested_svm_unmap(nested_vmcb, KM_USER0);
1895
1896 return 1;
1897 }
1898
1899 static int vmrun_interception(struct vcpu_svm *svm)
1900 {
1901 if (nested_svm_check_permissions(svm))
1902 return 1;
1903
1904 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1905 skip_emulated_instruction(&svm->vcpu);
1906
1907 if (!nested_svm_vmrun(svm))
1908 return 1;
1909
1910 if (!nested_svm_vmrun_msrpm(svm))
1911 goto failed;
1912
1913 return 1;
1914
1915 failed:
1916
1917 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
1918 svm->vmcb->control.exit_code_hi = 0;
1919 svm->vmcb->control.exit_info_1 = 0;
1920 svm->vmcb->control.exit_info_2 = 0;
1921
1922 nested_svm_vmexit(svm);
1923
1924 return 1;
1925 }
1926
1927 static int stgi_interception(struct vcpu_svm *svm)
1928 {
1929 if (nested_svm_check_permissions(svm))
1930 return 1;
1931
1932 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1933 skip_emulated_instruction(&svm->vcpu);
1934
1935 enable_gif(svm);
1936
1937 return 1;
1938 }
1939
1940 static int clgi_interception(struct vcpu_svm *svm)
1941 {
1942 if (nested_svm_check_permissions(svm))
1943 return 1;
1944
1945 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1946 skip_emulated_instruction(&svm->vcpu);
1947
1948 disable_gif(svm);
1949
1950 /* After a CLGI no interrupts should come */
1951 svm_clear_vintr(svm);
1952 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1953
1954 return 1;
1955 }
1956
1957 static int invlpga_interception(struct vcpu_svm *svm)
1958 {
1959 struct kvm_vcpu *vcpu = &svm->vcpu;
1960
1961 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
1962 vcpu->arch.regs[VCPU_REGS_RAX]);
1963
1964 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1965 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1966
1967 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1968 skip_emulated_instruction(&svm->vcpu);
1969 return 1;
1970 }
1971
1972 static int skinit_interception(struct vcpu_svm *svm)
1973 {
1974 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
1975
1976 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1977 return 1;
1978 }
1979
1980 static int invalid_op_interception(struct vcpu_svm *svm)
1981 {
1982 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1983 return 1;
1984 }
1985
1986 static int task_switch_interception(struct vcpu_svm *svm)
1987 {
1988 u16 tss_selector;
1989 int reason;
1990 int int_type = svm->vmcb->control.exit_int_info &
1991 SVM_EXITINTINFO_TYPE_MASK;
1992 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
1993 uint32_t type =
1994 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1995 uint32_t idt_v =
1996 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
1997
1998 tss_selector = (u16)svm->vmcb->control.exit_info_1;
1999
2000 if (svm->vmcb->control.exit_info_2 &
2001 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2002 reason = TASK_SWITCH_IRET;
2003 else if (svm->vmcb->control.exit_info_2 &
2004 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2005 reason = TASK_SWITCH_JMP;
2006 else if (idt_v)
2007 reason = TASK_SWITCH_GATE;
2008 else
2009 reason = TASK_SWITCH_CALL;
2010
2011 if (reason == TASK_SWITCH_GATE) {
2012 switch (type) {
2013 case SVM_EXITINTINFO_TYPE_NMI:
2014 svm->vcpu.arch.nmi_injected = false;
2015 break;
2016 case SVM_EXITINTINFO_TYPE_EXEPT:
2017 kvm_clear_exception_queue(&svm->vcpu);
2018 break;
2019 case SVM_EXITINTINFO_TYPE_INTR:
2020 kvm_clear_interrupt_queue(&svm->vcpu);
2021 break;
2022 default:
2023 break;
2024 }
2025 }
2026
2027 if (reason != TASK_SWITCH_GATE ||
2028 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2029 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2030 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2031 skip_emulated_instruction(&svm->vcpu);
2032
2033 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2034 }
2035
2036 static int cpuid_interception(struct vcpu_svm *svm)
2037 {
2038 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2039 kvm_emulate_cpuid(&svm->vcpu);
2040 return 1;
2041 }
2042
2043 static int iret_interception(struct vcpu_svm *svm)
2044 {
2045 ++svm->vcpu.stat.nmi_window_exits;
2046 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2047 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2048 return 1;
2049 }
2050
2051 static int invlpg_interception(struct vcpu_svm *svm)
2052 {
2053 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2054 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2055 return 1;
2056 }
2057
2058 static int emulate_on_interception(struct vcpu_svm *svm)
2059 {
2060 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2061 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2062 return 1;
2063 }
2064
2065 static int cr8_write_interception(struct vcpu_svm *svm)
2066 {
2067 struct kvm_run *kvm_run = svm->vcpu.run;
2068
2069 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2070 /* instruction emulation calls kvm_set_cr8() */
2071 emulate_instruction(&svm->vcpu, 0, 0, 0);
2072 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2073 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2074 return 1;
2075 }
2076 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2077 return 1;
2078 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2079 return 0;
2080 }
2081
2082 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2083 {
2084 struct vcpu_svm *svm = to_svm(vcpu);
2085
2086 switch (ecx) {
2087 case MSR_IA32_TSC: {
2088 u64 tsc_offset;
2089
2090 if (is_nested(svm))
2091 tsc_offset = svm->nested.hsave->control.tsc_offset;
2092 else
2093 tsc_offset = svm->vmcb->control.tsc_offset;
2094
2095 *data = tsc_offset + native_read_tsc();
2096 break;
2097 }
2098 case MSR_K6_STAR:
2099 *data = svm->vmcb->save.star;
2100 break;
2101 #ifdef CONFIG_X86_64
2102 case MSR_LSTAR:
2103 *data = svm->vmcb->save.lstar;
2104 break;
2105 case MSR_CSTAR:
2106 *data = svm->vmcb->save.cstar;
2107 break;
2108 case MSR_KERNEL_GS_BASE:
2109 *data = svm->vmcb->save.kernel_gs_base;
2110 break;
2111 case MSR_SYSCALL_MASK:
2112 *data = svm->vmcb->save.sfmask;
2113 break;
2114 #endif
2115 case MSR_IA32_SYSENTER_CS:
2116 *data = svm->vmcb->save.sysenter_cs;
2117 break;
2118 case MSR_IA32_SYSENTER_EIP:
2119 *data = svm->sysenter_eip;
2120 break;
2121 case MSR_IA32_SYSENTER_ESP:
2122 *data = svm->sysenter_esp;
2123 break;
2124 /* Nobody will change the following 5 values in the VMCB so
2125 we can safely return them on rdmsr. They will always be 0
2126 until LBRV is implemented. */
2127 case MSR_IA32_DEBUGCTLMSR:
2128 *data = svm->vmcb->save.dbgctl;
2129 break;
2130 case MSR_IA32_LASTBRANCHFROMIP:
2131 *data = svm->vmcb->save.br_from;
2132 break;
2133 case MSR_IA32_LASTBRANCHTOIP:
2134 *data = svm->vmcb->save.br_to;
2135 break;
2136 case MSR_IA32_LASTINTFROMIP:
2137 *data = svm->vmcb->save.last_excp_from;
2138 break;
2139 case MSR_IA32_LASTINTTOIP:
2140 *data = svm->vmcb->save.last_excp_to;
2141 break;
2142 case MSR_VM_HSAVE_PA:
2143 *data = svm->nested.hsave_msr;
2144 break;
2145 case MSR_VM_CR:
2146 *data = 0;
2147 break;
2148 case MSR_IA32_UCODE_REV:
2149 *data = 0x01000065;
2150 break;
2151 default:
2152 return kvm_get_msr_common(vcpu, ecx, data);
2153 }
2154 return 0;
2155 }
2156
2157 static int rdmsr_interception(struct vcpu_svm *svm)
2158 {
2159 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2160 u64 data;
2161
2162 if (svm_get_msr(&svm->vcpu, ecx, &data))
2163 kvm_inject_gp(&svm->vcpu, 0);
2164 else {
2165 trace_kvm_msr_read(ecx, data);
2166
2167 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2168 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2169 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2170 skip_emulated_instruction(&svm->vcpu);
2171 }
2172 return 1;
2173 }
2174
2175 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2176 {
2177 struct vcpu_svm *svm = to_svm(vcpu);
2178
2179 switch (ecx) {
2180 case MSR_IA32_TSC: {
2181 u64 tsc_offset = data - native_read_tsc();
2182 u64 g_tsc_offset = 0;
2183
2184 if (is_nested(svm)) {
2185 g_tsc_offset = svm->vmcb->control.tsc_offset -
2186 svm->nested.hsave->control.tsc_offset;
2187 svm->nested.hsave->control.tsc_offset = tsc_offset;
2188 }
2189
2190 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2191
2192 break;
2193 }
2194 case MSR_K6_STAR:
2195 svm->vmcb->save.star = data;
2196 break;
2197 #ifdef CONFIG_X86_64
2198 case MSR_LSTAR:
2199 svm->vmcb->save.lstar = data;
2200 break;
2201 case MSR_CSTAR:
2202 svm->vmcb->save.cstar = data;
2203 break;
2204 case MSR_KERNEL_GS_BASE:
2205 svm->vmcb->save.kernel_gs_base = data;
2206 break;
2207 case MSR_SYSCALL_MASK:
2208 svm->vmcb->save.sfmask = data;
2209 break;
2210 #endif
2211 case MSR_IA32_SYSENTER_CS:
2212 svm->vmcb->save.sysenter_cs = data;
2213 break;
2214 case MSR_IA32_SYSENTER_EIP:
2215 svm->sysenter_eip = data;
2216 svm->vmcb->save.sysenter_eip = data;
2217 break;
2218 case MSR_IA32_SYSENTER_ESP:
2219 svm->sysenter_esp = data;
2220 svm->vmcb->save.sysenter_esp = data;
2221 break;
2222 case MSR_IA32_DEBUGCTLMSR:
2223 if (!svm_has(SVM_FEATURE_LBRV)) {
2224 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2225 __func__, data);
2226 break;
2227 }
2228 if (data & DEBUGCTL_RESERVED_BITS)
2229 return 1;
2230
2231 svm->vmcb->save.dbgctl = data;
2232 if (data & (1ULL<<0))
2233 svm_enable_lbrv(svm);
2234 else
2235 svm_disable_lbrv(svm);
2236 break;
2237 case MSR_VM_HSAVE_PA:
2238 svm->nested.hsave_msr = data;
2239 break;
2240 case MSR_VM_CR:
2241 case MSR_VM_IGNNE:
2242 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2243 break;
2244 default:
2245 return kvm_set_msr_common(vcpu, ecx, data);
2246 }
2247 return 0;
2248 }
2249
2250 static int wrmsr_interception(struct vcpu_svm *svm)
2251 {
2252 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2253 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2254 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2255
2256 trace_kvm_msr_write(ecx, data);
2257
2258 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2259 if (svm_set_msr(&svm->vcpu, ecx, data))
2260 kvm_inject_gp(&svm->vcpu, 0);
2261 else
2262 skip_emulated_instruction(&svm->vcpu);
2263 return 1;
2264 }
2265
2266 static int msr_interception(struct vcpu_svm *svm)
2267 {
2268 if (svm->vmcb->control.exit_info_1)
2269 return wrmsr_interception(svm);
2270 else
2271 return rdmsr_interception(svm);
2272 }
2273
2274 static int interrupt_window_interception(struct vcpu_svm *svm)
2275 {
2276 struct kvm_run *kvm_run = svm->vcpu.run;
2277
2278 svm_clear_vintr(svm);
2279 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2280 /*
2281 * If the user space waits to inject interrupts, exit as soon as
2282 * possible
2283 */
2284 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2285 kvm_run->request_interrupt_window &&
2286 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2287 ++svm->vcpu.stat.irq_window_exits;
2288 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2289 return 0;
2290 }
2291
2292 return 1;
2293 }
2294
2295 static int pause_interception(struct vcpu_svm *svm)
2296 {
2297 kvm_vcpu_on_spin(&(svm->vcpu));
2298 return 1;
2299 }
2300
2301 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2302 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2303 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2304 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2305 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2306 /* for now: */
2307 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2308 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2309 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2310 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2311 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2312 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2313 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2314 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2315 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2316 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2317 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2318 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2319 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2320 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2321 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2322 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2323 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2324 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2325 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2326 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2327 [SVM_EXIT_INTR] = intr_interception,
2328 [SVM_EXIT_NMI] = nmi_interception,
2329 [SVM_EXIT_SMI] = nop_on_interception,
2330 [SVM_EXIT_INIT] = nop_on_interception,
2331 [SVM_EXIT_VINTR] = interrupt_window_interception,
2332 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2333 [SVM_EXIT_CPUID] = cpuid_interception,
2334 [SVM_EXIT_IRET] = iret_interception,
2335 [SVM_EXIT_INVD] = emulate_on_interception,
2336 [SVM_EXIT_PAUSE] = pause_interception,
2337 [SVM_EXIT_HLT] = halt_interception,
2338 [SVM_EXIT_INVLPG] = invlpg_interception,
2339 [SVM_EXIT_INVLPGA] = invlpga_interception,
2340 [SVM_EXIT_IOIO] = io_interception,
2341 [SVM_EXIT_MSR] = msr_interception,
2342 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2343 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2344 [SVM_EXIT_VMRUN] = vmrun_interception,
2345 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2346 [SVM_EXIT_VMLOAD] = vmload_interception,
2347 [SVM_EXIT_VMSAVE] = vmsave_interception,
2348 [SVM_EXIT_STGI] = stgi_interception,
2349 [SVM_EXIT_CLGI] = clgi_interception,
2350 [SVM_EXIT_SKINIT] = skinit_interception,
2351 [SVM_EXIT_WBINVD] = emulate_on_interception,
2352 [SVM_EXIT_MONITOR] = invalid_op_interception,
2353 [SVM_EXIT_MWAIT] = invalid_op_interception,
2354 [SVM_EXIT_NPF] = pf_interception,
2355 };
2356
2357 static int handle_exit(struct kvm_vcpu *vcpu)
2358 {
2359 struct vcpu_svm *svm = to_svm(vcpu);
2360 struct kvm_run *kvm_run = vcpu->run;
2361 u32 exit_code = svm->vmcb->control.exit_code;
2362
2363 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2364
2365 if (unlikely(svm->nested.exit_required)) {
2366 nested_svm_vmexit(svm);
2367 svm->nested.exit_required = false;
2368
2369 return 1;
2370 }
2371
2372 if (is_nested(svm)) {
2373 int vmexit;
2374
2375 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2376 svm->vmcb->control.exit_info_1,
2377 svm->vmcb->control.exit_info_2,
2378 svm->vmcb->control.exit_int_info,
2379 svm->vmcb->control.exit_int_info_err);
2380
2381 vmexit = nested_svm_exit_special(svm);
2382
2383 if (vmexit == NESTED_EXIT_CONTINUE)
2384 vmexit = nested_svm_exit_handled(svm);
2385
2386 if (vmexit == NESTED_EXIT_DONE)
2387 return 1;
2388 }
2389
2390 svm_complete_interrupts(svm);
2391
2392 if (npt_enabled) {
2393 int mmu_reload = 0;
2394 if ((kvm_read_cr0_bits(vcpu, X86_CR0_PG) ^ svm->vmcb->save.cr0)
2395 & X86_CR0_PG) {
2396 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2397 mmu_reload = 1;
2398 }
2399 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2400 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2401 if (mmu_reload) {
2402 kvm_mmu_reset_context(vcpu);
2403 kvm_mmu_load(vcpu);
2404 }
2405 }
2406
2407
2408 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2409 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2410 kvm_run->fail_entry.hardware_entry_failure_reason
2411 = svm->vmcb->control.exit_code;
2412 return 0;
2413 }
2414
2415 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2416 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2417 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2418 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2419 "exit_code 0x%x\n",
2420 __func__, svm->vmcb->control.exit_int_info,
2421 exit_code);
2422
2423 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2424 || !svm_exit_handlers[exit_code]) {
2425 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2426 kvm_run->hw.hardware_exit_reason = exit_code;
2427 return 0;
2428 }
2429
2430 return svm_exit_handlers[exit_code](svm);
2431 }
2432
2433 static void reload_tss(struct kvm_vcpu *vcpu)
2434 {
2435 int cpu = raw_smp_processor_id();
2436
2437 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2438 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2439 load_TR_desc();
2440 }
2441
2442 static void pre_svm_run(struct vcpu_svm *svm)
2443 {
2444 int cpu = raw_smp_processor_id();
2445
2446 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2447
2448 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2449 /* FIXME: handle wraparound of asid_generation */
2450 if (svm->asid_generation != sd->asid_generation)
2451 new_asid(svm, sd);
2452 }
2453
2454 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2455 {
2456 struct vcpu_svm *svm = to_svm(vcpu);
2457
2458 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2459 vcpu->arch.hflags |= HF_NMI_MASK;
2460 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2461 ++vcpu->stat.nmi_injections;
2462 }
2463
2464 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2465 {
2466 struct vmcb_control_area *control;
2467
2468 trace_kvm_inj_virq(irq);
2469
2470 ++svm->vcpu.stat.irq_injections;
2471 control = &svm->vmcb->control;
2472 control->int_vector = irq;
2473 control->int_ctl &= ~V_INTR_PRIO_MASK;
2474 control->int_ctl |= V_IRQ_MASK |
2475 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2476 }
2477
2478 static void svm_set_irq(struct kvm_vcpu *vcpu)
2479 {
2480 struct vcpu_svm *svm = to_svm(vcpu);
2481
2482 BUG_ON(!(gif_set(svm)));
2483
2484 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2485 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2486 }
2487
2488 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2489 {
2490 struct vcpu_svm *svm = to_svm(vcpu);
2491
2492 if (irr == -1)
2493 return;
2494
2495 if (tpr >= irr)
2496 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2497 }
2498
2499 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2500 {
2501 struct vcpu_svm *svm = to_svm(vcpu);
2502 struct vmcb *vmcb = svm->vmcb;
2503 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2504 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2505 }
2506
2507 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2508 {
2509 struct vcpu_svm *svm = to_svm(vcpu);
2510
2511 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2512 }
2513
2514 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2515 {
2516 struct vcpu_svm *svm = to_svm(vcpu);
2517
2518 if (masked) {
2519 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2520 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2521 } else {
2522 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2523 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2524 }
2525 }
2526
2527 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2528 {
2529 struct vcpu_svm *svm = to_svm(vcpu);
2530 struct vmcb *vmcb = svm->vmcb;
2531 int ret;
2532
2533 if (!gif_set(svm) ||
2534 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2535 return 0;
2536
2537 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2538
2539 if (is_nested(svm))
2540 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2541
2542 return ret;
2543 }
2544
2545 static void enable_irq_window(struct kvm_vcpu *vcpu)
2546 {
2547 struct vcpu_svm *svm = to_svm(vcpu);
2548
2549 nested_svm_intr(svm);
2550
2551 /* In case GIF=0 we can't rely on the CPU to tell us when
2552 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2553 * The next time we get that intercept, this function will be
2554 * called again though and we'll get the vintr intercept. */
2555 if (gif_set(svm)) {
2556 svm_set_vintr(svm);
2557 svm_inject_irq(svm, 0x0);
2558 }
2559 }
2560
2561 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2562 {
2563 struct vcpu_svm *svm = to_svm(vcpu);
2564
2565 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2566 == HF_NMI_MASK)
2567 return; /* IRET will cause a vm exit */
2568
2569 /* Something prevents NMI from been injected. Single step over
2570 possible problem (IRET or exception injection or interrupt
2571 shadow) */
2572 svm->nmi_singlestep = true;
2573 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2574 update_db_intercept(vcpu);
2575 }
2576
2577 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2578 {
2579 return 0;
2580 }
2581
2582 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2583 {
2584 force_new_asid(vcpu);
2585 }
2586
2587 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2588 {
2589 }
2590
2591 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2592 {
2593 struct vcpu_svm *svm = to_svm(vcpu);
2594
2595 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2596 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2597 kvm_set_cr8(vcpu, cr8);
2598 }
2599 }
2600
2601 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2602 {
2603 struct vcpu_svm *svm = to_svm(vcpu);
2604 u64 cr8;
2605
2606 cr8 = kvm_get_cr8(vcpu);
2607 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2608 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2609 }
2610
2611 static void svm_complete_interrupts(struct vcpu_svm *svm)
2612 {
2613 u8 vector;
2614 int type;
2615 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2616
2617 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2618 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2619
2620 svm->vcpu.arch.nmi_injected = false;
2621 kvm_clear_exception_queue(&svm->vcpu);
2622 kvm_clear_interrupt_queue(&svm->vcpu);
2623
2624 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2625 return;
2626
2627 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2628 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2629
2630 switch (type) {
2631 case SVM_EXITINTINFO_TYPE_NMI:
2632 svm->vcpu.arch.nmi_injected = true;
2633 break;
2634 case SVM_EXITINTINFO_TYPE_EXEPT:
2635 /* In case of software exception do not reinject an exception
2636 vector, but re-execute and instruction instead */
2637 if (is_nested(svm))
2638 break;
2639 if (kvm_exception_is_soft(vector))
2640 break;
2641 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2642 u32 err = svm->vmcb->control.exit_int_info_err;
2643 kvm_queue_exception_e(&svm->vcpu, vector, err);
2644
2645 } else
2646 kvm_queue_exception(&svm->vcpu, vector);
2647 break;
2648 case SVM_EXITINTINFO_TYPE_INTR:
2649 kvm_queue_interrupt(&svm->vcpu, vector, false);
2650 break;
2651 default:
2652 break;
2653 }
2654 }
2655
2656 #ifdef CONFIG_X86_64
2657 #define R "r"
2658 #else
2659 #define R "e"
2660 #endif
2661
2662 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
2663 {
2664 struct vcpu_svm *svm = to_svm(vcpu);
2665 u16 fs_selector;
2666 u16 gs_selector;
2667 u16 ldt_selector;
2668
2669 /*
2670 * A vmexit emulation is required before the vcpu can be executed
2671 * again.
2672 */
2673 if (unlikely(svm->nested.exit_required))
2674 return;
2675
2676 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2677 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2678 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2679
2680 pre_svm_run(svm);
2681
2682 sync_lapic_to_cr8(vcpu);
2683
2684 save_host_msrs(vcpu);
2685 fs_selector = kvm_read_fs();
2686 gs_selector = kvm_read_gs();
2687 ldt_selector = kvm_read_ldt();
2688 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2689 /* required for live migration with NPT */
2690 if (npt_enabled)
2691 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2692
2693 clgi();
2694
2695 local_irq_enable();
2696
2697 asm volatile (
2698 "push %%"R"bp; \n\t"
2699 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2700 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2701 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2702 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2703 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2704 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2705 #ifdef CONFIG_X86_64
2706 "mov %c[r8](%[svm]), %%r8 \n\t"
2707 "mov %c[r9](%[svm]), %%r9 \n\t"
2708 "mov %c[r10](%[svm]), %%r10 \n\t"
2709 "mov %c[r11](%[svm]), %%r11 \n\t"
2710 "mov %c[r12](%[svm]), %%r12 \n\t"
2711 "mov %c[r13](%[svm]), %%r13 \n\t"
2712 "mov %c[r14](%[svm]), %%r14 \n\t"
2713 "mov %c[r15](%[svm]), %%r15 \n\t"
2714 #endif
2715
2716 /* Enter guest mode */
2717 "push %%"R"ax \n\t"
2718 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2719 __ex(SVM_VMLOAD) "\n\t"
2720 __ex(SVM_VMRUN) "\n\t"
2721 __ex(SVM_VMSAVE) "\n\t"
2722 "pop %%"R"ax \n\t"
2723
2724 /* Save guest registers, load host registers */
2725 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2726 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2727 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2728 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2729 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2730 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2731 #ifdef CONFIG_X86_64
2732 "mov %%r8, %c[r8](%[svm]) \n\t"
2733 "mov %%r9, %c[r9](%[svm]) \n\t"
2734 "mov %%r10, %c[r10](%[svm]) \n\t"
2735 "mov %%r11, %c[r11](%[svm]) \n\t"
2736 "mov %%r12, %c[r12](%[svm]) \n\t"
2737 "mov %%r13, %c[r13](%[svm]) \n\t"
2738 "mov %%r14, %c[r14](%[svm]) \n\t"
2739 "mov %%r15, %c[r15](%[svm]) \n\t"
2740 #endif
2741 "pop %%"R"bp"
2742 :
2743 : [svm]"a"(svm),
2744 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2745 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2746 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2747 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2748 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2749 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2750 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2751 #ifdef CONFIG_X86_64
2752 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2753 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2754 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2755 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2756 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2757 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2758 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2759 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2760 #endif
2761 : "cc", "memory"
2762 , R"bx", R"cx", R"dx", R"si", R"di"
2763 #ifdef CONFIG_X86_64
2764 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2765 #endif
2766 );
2767
2768 vcpu->arch.cr2 = svm->vmcb->save.cr2;
2769 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2770 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2771 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2772
2773 kvm_load_fs(fs_selector);
2774 kvm_load_gs(gs_selector);
2775 kvm_load_ldt(ldt_selector);
2776 load_host_msrs(vcpu);
2777
2778 reload_tss(vcpu);
2779
2780 local_irq_disable();
2781
2782 stgi();
2783
2784 sync_cr8_to_lapic(vcpu);
2785
2786 svm->next_rip = 0;
2787
2788 if (npt_enabled) {
2789 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2790 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2791 }
2792 }
2793
2794 #undef R
2795
2796 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2797 {
2798 struct vcpu_svm *svm = to_svm(vcpu);
2799
2800 if (npt_enabled) {
2801 svm->vmcb->control.nested_cr3 = root;
2802 force_new_asid(vcpu);
2803 return;
2804 }
2805
2806 svm->vmcb->save.cr3 = root;
2807 force_new_asid(vcpu);
2808
2809 if (vcpu->fpu_active) {
2810 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2811 svm->vmcb->save.cr0 |= X86_CR0_TS;
2812 vcpu->fpu_active = 0;
2813 }
2814 }
2815
2816 static int is_disabled(void)
2817 {
2818 u64 vm_cr;
2819
2820 rdmsrl(MSR_VM_CR, vm_cr);
2821 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2822 return 1;
2823
2824 return 0;
2825 }
2826
2827 static void
2828 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2829 {
2830 /*
2831 * Patch in the VMMCALL instruction:
2832 */
2833 hypercall[0] = 0x0f;
2834 hypercall[1] = 0x01;
2835 hypercall[2] = 0xd9;
2836 }
2837
2838 static void svm_check_processor_compat(void *rtn)
2839 {
2840 *(int *)rtn = 0;
2841 }
2842
2843 static bool svm_cpu_has_accelerated_tpr(void)
2844 {
2845 return false;
2846 }
2847
2848 static int get_npt_level(void)
2849 {
2850 #ifdef CONFIG_X86_64
2851 return PT64_ROOT_LEVEL;
2852 #else
2853 return PT32E_ROOT_LEVEL;
2854 #endif
2855 }
2856
2857 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2858 {
2859 return 0;
2860 }
2861
2862 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
2863 {
2864 }
2865
2866 static const struct trace_print_flags svm_exit_reasons_str[] = {
2867 { SVM_EXIT_READ_CR0, "read_cr0" },
2868 { SVM_EXIT_READ_CR3, "read_cr3" },
2869 { SVM_EXIT_READ_CR4, "read_cr4" },
2870 { SVM_EXIT_READ_CR8, "read_cr8" },
2871 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2872 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2873 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2874 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2875 { SVM_EXIT_READ_DR0, "read_dr0" },
2876 { SVM_EXIT_READ_DR1, "read_dr1" },
2877 { SVM_EXIT_READ_DR2, "read_dr2" },
2878 { SVM_EXIT_READ_DR3, "read_dr3" },
2879 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2880 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2881 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2882 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2883 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2884 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2885 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2886 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2887 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2888 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2889 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2890 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2891 { SVM_EXIT_INTR, "interrupt" },
2892 { SVM_EXIT_NMI, "nmi" },
2893 { SVM_EXIT_SMI, "smi" },
2894 { SVM_EXIT_INIT, "init" },
2895 { SVM_EXIT_VINTR, "vintr" },
2896 { SVM_EXIT_CPUID, "cpuid" },
2897 { SVM_EXIT_INVD, "invd" },
2898 { SVM_EXIT_HLT, "hlt" },
2899 { SVM_EXIT_INVLPG, "invlpg" },
2900 { SVM_EXIT_INVLPGA, "invlpga" },
2901 { SVM_EXIT_IOIO, "io" },
2902 { SVM_EXIT_MSR, "msr" },
2903 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2904 { SVM_EXIT_SHUTDOWN, "shutdown" },
2905 { SVM_EXIT_VMRUN, "vmrun" },
2906 { SVM_EXIT_VMMCALL, "hypercall" },
2907 { SVM_EXIT_VMLOAD, "vmload" },
2908 { SVM_EXIT_VMSAVE, "vmsave" },
2909 { SVM_EXIT_STGI, "stgi" },
2910 { SVM_EXIT_CLGI, "clgi" },
2911 { SVM_EXIT_SKINIT, "skinit" },
2912 { SVM_EXIT_WBINVD, "wbinvd" },
2913 { SVM_EXIT_MONITOR, "monitor" },
2914 { SVM_EXIT_MWAIT, "mwait" },
2915 { SVM_EXIT_NPF, "npf" },
2916 { -1, NULL }
2917 };
2918
2919 static int svm_get_lpage_level(void)
2920 {
2921 return PT_PDPE_LEVEL;
2922 }
2923
2924 static bool svm_rdtscp_supported(void)
2925 {
2926 return false;
2927 }
2928
2929 static struct kvm_x86_ops svm_x86_ops = {
2930 .cpu_has_kvm_support = has_svm,
2931 .disabled_by_bios = is_disabled,
2932 .hardware_setup = svm_hardware_setup,
2933 .hardware_unsetup = svm_hardware_unsetup,
2934 .check_processor_compatibility = svm_check_processor_compat,
2935 .hardware_enable = svm_hardware_enable,
2936 .hardware_disable = svm_hardware_disable,
2937 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2938
2939 .vcpu_create = svm_create_vcpu,
2940 .vcpu_free = svm_free_vcpu,
2941 .vcpu_reset = svm_vcpu_reset,
2942
2943 .prepare_guest_switch = svm_prepare_guest_switch,
2944 .vcpu_load = svm_vcpu_load,
2945 .vcpu_put = svm_vcpu_put,
2946
2947 .set_guest_debug = svm_guest_debug,
2948 .get_msr = svm_get_msr,
2949 .set_msr = svm_set_msr,
2950 .get_segment_base = svm_get_segment_base,
2951 .get_segment = svm_get_segment,
2952 .set_segment = svm_set_segment,
2953 .get_cpl = svm_get_cpl,
2954 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2955 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
2956 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2957 .set_cr0 = svm_set_cr0,
2958 .set_cr3 = svm_set_cr3,
2959 .set_cr4 = svm_set_cr4,
2960 .set_efer = svm_set_efer,
2961 .get_idt = svm_get_idt,
2962 .set_idt = svm_set_idt,
2963 .get_gdt = svm_get_gdt,
2964 .set_gdt = svm_set_gdt,
2965 .get_dr = svm_get_dr,
2966 .set_dr = svm_set_dr,
2967 .cache_reg = svm_cache_reg,
2968 .get_rflags = svm_get_rflags,
2969 .set_rflags = svm_set_rflags,
2970
2971 .tlb_flush = svm_flush_tlb,
2972
2973 .run = svm_vcpu_run,
2974 .handle_exit = handle_exit,
2975 .skip_emulated_instruction = skip_emulated_instruction,
2976 .set_interrupt_shadow = svm_set_interrupt_shadow,
2977 .get_interrupt_shadow = svm_get_interrupt_shadow,
2978 .patch_hypercall = svm_patch_hypercall,
2979 .set_irq = svm_set_irq,
2980 .set_nmi = svm_inject_nmi,
2981 .queue_exception = svm_queue_exception,
2982 .interrupt_allowed = svm_interrupt_allowed,
2983 .nmi_allowed = svm_nmi_allowed,
2984 .get_nmi_mask = svm_get_nmi_mask,
2985 .set_nmi_mask = svm_set_nmi_mask,
2986 .enable_nmi_window = enable_nmi_window,
2987 .enable_irq_window = enable_irq_window,
2988 .update_cr8_intercept = update_cr8_intercept,
2989
2990 .set_tss_addr = svm_set_tss_addr,
2991 .get_tdp_level = get_npt_level,
2992 .get_mt_mask = svm_get_mt_mask,
2993
2994 .exit_reasons_str = svm_exit_reasons_str,
2995 .get_lpage_level = svm_get_lpage_level,
2996
2997 .cpuid_update = svm_cpuid_update,
2998
2999 .rdtscp_supported = svm_rdtscp_supported,
3000 };
3001
3002 static int __init svm_init(void)
3003 {
3004 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3005 THIS_MODULE);
3006 }
3007
3008 static void __exit svm_exit(void)
3009 {
3010 kvm_exit();
3011 }
3012
3013 module_init(svm_init)
3014 module_exit(svm_exit)
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree