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drm/radeon/kms: R600/RV770 remove dead code and print message for wrong BIOS
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / radeon / rv770.c
blob295cf14e3c53c1d9fce8de13f7d9a89954d29f27
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/firmware.h>
29 #include <linux/platform_device.h>
30 #include "drmP.h"
31 #include "radeon.h"
32 #include "radeon_drm.h"
33 #include "rv770d.h"
34 #include "atom.h"
35 #include "avivod.h"
36
37 #define R700_PFP_UCODE_SIZE 848
38 #define R700_PM4_UCODE_SIZE 1360
39
40 static void rv770_gpu_init(struct radeon_device *rdev);
41 void rv770_fini(struct radeon_device *rdev);
42
43
44 /*
45 * GART
46 */
47 int rv770_pcie_gart_enable(struct radeon_device *rdev)
48 {
49 u32 tmp;
50 int r, i;
51
52 if (rdev->gart.table.vram.robj == NULL) {
53 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
54 return -EINVAL;
55 }
56 r = radeon_gart_table_vram_pin(rdev);
57 if (r)
58 return r;
59 /* Setup L2 cache */
60 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
61 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
62 EFFECTIVE_L2_QUEUE_SIZE(7));
63 WREG32(VM_L2_CNTL2, 0);
64 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
65 /* Setup TLB control */
66 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
67 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
68 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
69 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
70 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
71 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
72 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
73 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
74 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
75 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
76 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
77 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
78 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12);
79 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
80 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
81 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
82 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
83 (u32)(rdev->dummy_page.addr >> 12));
84 for (i = 1; i < 7; i++)
85 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
86
87 r600_pcie_gart_tlb_flush(rdev);
88 rdev->gart.ready = true;
89 return 0;
90 }
91
92 void rv770_pcie_gart_disable(struct radeon_device *rdev)
93 {
94 u32 tmp;
95 int i;
96
97 /* Disable all tables */
98 for (i = 0; i < 7; i++)
99 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
100
101 /* Setup L2 cache */
102 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
103 EFFECTIVE_L2_QUEUE_SIZE(7));
104 WREG32(VM_L2_CNTL2, 0);
105 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
106 /* Setup TLB control */
107 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
108 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
109 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
110 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
111 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
112 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
113 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
114 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
115 if (rdev->gart.table.vram.robj) {
116 radeon_object_kunmap(rdev->gart.table.vram.robj);
117 radeon_object_unpin(rdev->gart.table.vram.robj);
118 }
119 }
120
121 void rv770_pcie_gart_fini(struct radeon_device *rdev)
122 {
123 rv770_pcie_gart_disable(rdev);
124 radeon_gart_table_vram_free(rdev);
125 radeon_gart_fini(rdev);
126 }
127
128
129 /*
130 * MC
131 */
132 static void rv770_mc_program(struct radeon_device *rdev)
133 {
134 struct rv515_mc_save save;
135 u32 tmp;
136 int i, j;
137
138 /* Initialize HDP */
139 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
140 WREG32((0x2c14 + j), 0x00000000);
141 WREG32((0x2c18 + j), 0x00000000);
142 WREG32((0x2c1c + j), 0x00000000);
143 WREG32((0x2c20 + j), 0x00000000);
144 WREG32((0x2c24 + j), 0x00000000);
145 }
146 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
147
148 rv515_mc_stop(rdev, &save);
149 if (r600_mc_wait_for_idle(rdev)) {
150 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
151 }
152 /* Lockout access through VGA aperture*/
153 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
154 /* Update configuration */
155 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
156 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12);
157 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
158 tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16;
159 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
160 WREG32(MC_VM_FB_LOCATION, tmp);
161 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
162 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
163 WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
164 if (rdev->flags & RADEON_IS_AGP) {
165 WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16);
166 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
167 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
168 } else {
169 WREG32(MC_VM_AGP_BASE, 0);
170 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
171 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
172 }
173 if (r600_mc_wait_for_idle(rdev)) {
174 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
175 }
176 rv515_mc_resume(rdev, &save);
177 /* we need to own VRAM, so turn off the VGA renderer here
178 * to stop it overwriting our objects */
179 rv515_vga_render_disable(rdev);
180 }
181
182
183 /*
184 * CP.
185 */
186 void r700_cp_stop(struct radeon_device *rdev)
187 {
188 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
189 }
190
191
192 static int rv770_cp_load_microcode(struct radeon_device *rdev)
193 {
194 const __be32 *fw_data;
195 int i;
196
197 if (!rdev->me_fw || !rdev->pfp_fw)
198 return -EINVAL;
199
200 r700_cp_stop(rdev);
201 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
202
203 /* Reset cp */
204 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
205 RREG32(GRBM_SOFT_RESET);
206 mdelay(15);
207 WREG32(GRBM_SOFT_RESET, 0);
208
209 fw_data = (const __be32 *)rdev->pfp_fw->data;
210 WREG32(CP_PFP_UCODE_ADDR, 0);
211 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
212 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
213 WREG32(CP_PFP_UCODE_ADDR, 0);
214
215 fw_data = (const __be32 *)rdev->me_fw->data;
216 WREG32(CP_ME_RAM_WADDR, 0);
217 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
218 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
219
220 WREG32(CP_PFP_UCODE_ADDR, 0);
221 WREG32(CP_ME_RAM_WADDR, 0);
222 WREG32(CP_ME_RAM_RADDR, 0);
223 return 0;
224 }
225
226
227 /*
228 * Core functions
229 */
230 static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
231 u32 num_backends,
232 u32 backend_disable_mask)
233 {
234 u32 backend_map = 0;
235 u32 enabled_backends_mask;
236 u32 enabled_backends_count;
237 u32 cur_pipe;
238 u32 swizzle_pipe[R7XX_MAX_PIPES];
239 u32 cur_backend;
240 u32 i;
241
242 if (num_tile_pipes > R7XX_MAX_PIPES)
243 num_tile_pipes = R7XX_MAX_PIPES;
244 if (num_tile_pipes < 1)
245 num_tile_pipes = 1;
246 if (num_backends > R7XX_MAX_BACKENDS)
247 num_backends = R7XX_MAX_BACKENDS;
248 if (num_backends < 1)
249 num_backends = 1;
250
251 enabled_backends_mask = 0;
252 enabled_backends_count = 0;
253 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
254 if (((backend_disable_mask >> i) & 1) == 0) {
255 enabled_backends_mask |= (1 << i);
256 ++enabled_backends_count;
257 }
258 if (enabled_backends_count == num_backends)
259 break;
260 }
261
262 if (enabled_backends_count == 0) {
263 enabled_backends_mask = 1;
264 enabled_backends_count = 1;
265 }
266
267 if (enabled_backends_count != num_backends)
268 num_backends = enabled_backends_count;
269
270 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
271 switch (num_tile_pipes) {
272 case 1:
273 swizzle_pipe[0] = 0;
274 break;
275 case 2:
276 swizzle_pipe[0] = 0;
277 swizzle_pipe[1] = 1;
278 break;
279 case 3:
280 swizzle_pipe[0] = 0;
281 swizzle_pipe[1] = 2;
282 swizzle_pipe[2] = 1;
283 break;
284 case 4:
285 swizzle_pipe[0] = 0;
286 swizzle_pipe[1] = 2;
287 swizzle_pipe[2] = 3;
288 swizzle_pipe[3] = 1;
289 break;
290 case 5:
291 swizzle_pipe[0] = 0;
292 swizzle_pipe[1] = 2;
293 swizzle_pipe[2] = 4;
294 swizzle_pipe[3] = 1;
295 swizzle_pipe[4] = 3;
296 break;
297 case 6:
298 swizzle_pipe[0] = 0;
299 swizzle_pipe[1] = 2;
300 swizzle_pipe[2] = 4;
301 swizzle_pipe[3] = 5;
302 swizzle_pipe[4] = 3;
303 swizzle_pipe[5] = 1;
304 break;
305 case 7:
306 swizzle_pipe[0] = 0;
307 swizzle_pipe[1] = 2;
308 swizzle_pipe[2] = 4;
309 swizzle_pipe[3] = 6;
310 swizzle_pipe[4] = 3;
311 swizzle_pipe[5] = 1;
312 swizzle_pipe[6] = 5;
313 break;
314 case 8:
315 swizzle_pipe[0] = 0;
316 swizzle_pipe[1] = 2;
317 swizzle_pipe[2] = 4;
318 swizzle_pipe[3] = 6;
319 swizzle_pipe[4] = 3;
320 swizzle_pipe[5] = 1;
321 swizzle_pipe[6] = 7;
322 swizzle_pipe[7] = 5;
323 break;
324 }
325
326 cur_backend = 0;
327 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
328 while (((1 << cur_backend) & enabled_backends_mask) == 0)
329 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
330
331 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
332
333 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
334 }
335
336 return backend_map;
337 }
338
339 static void rv770_gpu_init(struct radeon_device *rdev)
340 {
341 int i, j, num_qd_pipes;
342 u32 sx_debug_1;
343 u32 smx_dc_ctl0;
344 u32 num_gs_verts_per_thread;
345 u32 vgt_gs_per_es;
346 u32 gs_prim_buffer_depth = 0;
347 u32 sq_ms_fifo_sizes;
348 u32 sq_config;
349 u32 sq_thread_resource_mgmt;
350 u32 hdp_host_path_cntl;
351 u32 sq_dyn_gpr_size_simd_ab_0;
352 u32 backend_map;
353 u32 gb_tiling_config = 0;
354 u32 cc_rb_backend_disable = 0;
355 u32 cc_gc_shader_pipe_config = 0;
356 u32 mc_arb_ramcfg;
357 u32 db_debug4;
358
359 /* setup chip specs */
360 switch (rdev->family) {
361 case CHIP_RV770:
362 rdev->config.rv770.max_pipes = 4;
363 rdev->config.rv770.max_tile_pipes = 8;
364 rdev->config.rv770.max_simds = 10;
365 rdev->config.rv770.max_backends = 4;
366 rdev->config.rv770.max_gprs = 256;
367 rdev->config.rv770.max_threads = 248;
368 rdev->config.rv770.max_stack_entries = 512;
369 rdev->config.rv770.max_hw_contexts = 8;
370 rdev->config.rv770.max_gs_threads = 16 * 2;
371 rdev->config.rv770.sx_max_export_size = 128;
372 rdev->config.rv770.sx_max_export_pos_size = 16;
373 rdev->config.rv770.sx_max_export_smx_size = 112;
374 rdev->config.rv770.sq_num_cf_insts = 2;
375
376 rdev->config.rv770.sx_num_of_sets = 7;
377 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
378 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
379 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
380 break;
381 case CHIP_RV730:
382 rdev->config.rv770.max_pipes = 2;
383 rdev->config.rv770.max_tile_pipes = 4;
384 rdev->config.rv770.max_simds = 8;
385 rdev->config.rv770.max_backends = 2;
386 rdev->config.rv770.max_gprs = 128;
387 rdev->config.rv770.max_threads = 248;
388 rdev->config.rv770.max_stack_entries = 256;
389 rdev->config.rv770.max_hw_contexts = 8;
390 rdev->config.rv770.max_gs_threads = 16 * 2;
391 rdev->config.rv770.sx_max_export_size = 256;
392 rdev->config.rv770.sx_max_export_pos_size = 32;
393 rdev->config.rv770.sx_max_export_smx_size = 224;
394 rdev->config.rv770.sq_num_cf_insts = 2;
395
396 rdev->config.rv770.sx_num_of_sets = 7;
397 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
398 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
399 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
400 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
401 rdev->config.rv770.sx_max_export_pos_size -= 16;
402 rdev->config.rv770.sx_max_export_smx_size += 16;
403 }
404 break;
405 case CHIP_RV710:
406 rdev->config.rv770.max_pipes = 2;
407 rdev->config.rv770.max_tile_pipes = 2;
408 rdev->config.rv770.max_simds = 2;
409 rdev->config.rv770.max_backends = 1;
410 rdev->config.rv770.max_gprs = 256;
411 rdev->config.rv770.max_threads = 192;
412 rdev->config.rv770.max_stack_entries = 256;
413 rdev->config.rv770.max_hw_contexts = 4;
414 rdev->config.rv770.max_gs_threads = 8 * 2;
415 rdev->config.rv770.sx_max_export_size = 128;
416 rdev->config.rv770.sx_max_export_pos_size = 16;
417 rdev->config.rv770.sx_max_export_smx_size = 112;
418 rdev->config.rv770.sq_num_cf_insts = 1;
419
420 rdev->config.rv770.sx_num_of_sets = 7;
421 rdev->config.rv770.sc_prim_fifo_size = 0x40;
422 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
423 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
424 break;
425 case CHIP_RV740:
426 rdev->config.rv770.max_pipes = 4;
427 rdev->config.rv770.max_tile_pipes = 4;
428 rdev->config.rv770.max_simds = 8;
429 rdev->config.rv770.max_backends = 4;
430 rdev->config.rv770.max_gprs = 256;
431 rdev->config.rv770.max_threads = 248;
432 rdev->config.rv770.max_stack_entries = 512;
433 rdev->config.rv770.max_hw_contexts = 8;
434 rdev->config.rv770.max_gs_threads = 16 * 2;
435 rdev->config.rv770.sx_max_export_size = 256;
436 rdev->config.rv770.sx_max_export_pos_size = 32;
437 rdev->config.rv770.sx_max_export_smx_size = 224;
438 rdev->config.rv770.sq_num_cf_insts = 2;
439
440 rdev->config.rv770.sx_num_of_sets = 7;
441 rdev->config.rv770.sc_prim_fifo_size = 0x100;
442 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
443 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
444
445 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
446 rdev->config.rv770.sx_max_export_pos_size -= 16;
447 rdev->config.rv770.sx_max_export_smx_size += 16;
448 }
449 break;
450 default:
451 break;
452 }
453
454 /* Initialize HDP */
455 j = 0;
456 for (i = 0; i < 32; i++) {
457 WREG32((0x2c14 + j), 0x00000000);
458 WREG32((0x2c18 + j), 0x00000000);
459 WREG32((0x2c1c + j), 0x00000000);
460 WREG32((0x2c20 + j), 0x00000000);
461 WREG32((0x2c24 + j), 0x00000000);
462 j += 0x18;
463 }
464
465 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
466
467 /* setup tiling, simd, pipe config */
468 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
469
470 switch (rdev->config.rv770.max_tile_pipes) {
471 case 1:
472 gb_tiling_config |= PIPE_TILING(0);
473 break;
474 case 2:
475 gb_tiling_config |= PIPE_TILING(1);
476 break;
477 case 4:
478 gb_tiling_config |= PIPE_TILING(2);
479 break;
480 case 8:
481 gb_tiling_config |= PIPE_TILING(3);
482 break;
483 default:
484 break;
485 }
486
487 if (rdev->family == CHIP_RV770)
488 gb_tiling_config |= BANK_TILING(1);
489 else
490 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_SHIFT) >> NOOFBANK_MASK);
491
492 gb_tiling_config |= GROUP_SIZE(0);
493
494 if (((mc_arb_ramcfg & NOOFROWS_MASK) & NOOFROWS_SHIFT) > 3) {
495 gb_tiling_config |= ROW_TILING(3);
496 gb_tiling_config |= SAMPLE_SPLIT(3);
497 } else {
498 gb_tiling_config |=
499 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
500 gb_tiling_config |=
501 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
502 }
503
504 gb_tiling_config |= BANK_SWAPS(1);
505
506 backend_map = r700_get_tile_pipe_to_backend_map(rdev->config.rv770.max_tile_pipes,
507 rdev->config.rv770.max_backends,
508 (0xff << rdev->config.rv770.max_backends) & 0xff);
509 gb_tiling_config |= BACKEND_MAP(backend_map);
510
511 cc_gc_shader_pipe_config =
512 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
513 cc_gc_shader_pipe_config |=
514 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
515
516 cc_rb_backend_disable =
517 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
518
519 WREG32(GB_TILING_CONFIG, gb_tiling_config);
520 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
521 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
522
523 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
524 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
525 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
526
527 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
528 WREG32(CGTS_SYS_TCC_DISABLE, 0);
529 WREG32(CGTS_TCC_DISABLE, 0);
530 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
531 WREG32(CGTS_USER_TCC_DISABLE, 0);
532
533 num_qd_pipes =
534 R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK);
535 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
536 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
537
538 /* set HW defaults for 3D engine */
539 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
540 ROQ_IB2_START(0x2b)));
541
542 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
543
544 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
545 SYNC_GRADIENT |
546 SYNC_WALKER |
547 SYNC_ALIGNER));
548
549 sx_debug_1 = RREG32(SX_DEBUG_1);
550 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
551 WREG32(SX_DEBUG_1, sx_debug_1);
552
553 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
554 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
555 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
556 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
557
558 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
559 GS_FLUSH_CTL(4) |
560 ACK_FLUSH_CTL(3) |
561 SYNC_FLUSH_CTL));
562
563 if (rdev->family == CHIP_RV770)
564 WREG32(DB_DEBUG3, DB_CLK_OFF_DELAY(0x1f));
565 else {
566 db_debug4 = RREG32(DB_DEBUG4);
567 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
568 WREG32(DB_DEBUG4, db_debug4);
569 }
570
571 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
572 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
573 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
574
575 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
576 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
577 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
578
579 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
580
581 WREG32(VGT_NUM_INSTANCES, 1);
582
583 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
584
585 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
586
587 WREG32(CP_PERFMON_CNTL, 0);
588
589 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
590 DONE_FIFO_HIWATER(0xe0) |
591 ALU_UPDATE_FIFO_HIWATER(0x8));
592 switch (rdev->family) {
593 case CHIP_RV770:
594 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
595 break;
596 case CHIP_RV730:
597 case CHIP_RV710:
598 case CHIP_RV740:
599 default:
600 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
601 break;
602 }
603 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
604
605 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
606 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
607 */
608 sq_config = RREG32(SQ_CONFIG);
609 sq_config &= ~(PS_PRIO(3) |
610 VS_PRIO(3) |
611 GS_PRIO(3) |
612 ES_PRIO(3));
613 sq_config |= (DX9_CONSTS |
614 VC_ENABLE |
615 EXPORT_SRC_C |
616 PS_PRIO(0) |
617 VS_PRIO(1) |
618 GS_PRIO(2) |
619 ES_PRIO(3));
620 if (rdev->family == CHIP_RV710)
621 /* no vertex cache */
622 sq_config &= ~VC_ENABLE;
623
624 WREG32(SQ_CONFIG, sq_config);
625
626 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
627 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
628 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
629
630 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
631 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
632
633 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
634 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
635 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
636 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
637 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
638 else
639 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
640 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
641
642 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
643 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
644
645 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
646 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
647
648 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
649 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
650 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
651 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
652
653 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
654 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
655 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
656 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
657 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
658 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
659 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
660 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
661
662 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
663 FORCE_EOV_MAX_REZ_CNT(255)));
664
665 if (rdev->family == CHIP_RV710)
666 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
667 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
668 else
669 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
670 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
671
672 switch (rdev->family) {
673 case CHIP_RV770:
674 case CHIP_RV730:
675 case CHIP_RV740:
676 gs_prim_buffer_depth = 384;
677 break;
678 case CHIP_RV710:
679 gs_prim_buffer_depth = 128;
680 break;
681 default:
682 break;
683 }
684
685 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
686 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
687 /* Max value for this is 256 */
688 if (vgt_gs_per_es > 256)
689 vgt_gs_per_es = 256;
690
691 WREG32(VGT_ES_PER_GS, 128);
692 WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
693 WREG32(VGT_GS_PER_VS, 2);
694
695 /* more default values. 2D/3D driver should adjust as needed */
696 WREG32(VGT_GS_VERTEX_REUSE, 16);
697 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
698 WREG32(VGT_STRMOUT_EN, 0);
699 WREG32(SX_MISC, 0);
700 WREG32(PA_SC_MODE_CNTL, 0);
701 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
702 WREG32(PA_SC_AA_CONFIG, 0);
703 WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
704 WREG32(PA_SC_LINE_STIPPLE, 0);
705 WREG32(SPI_INPUT_Z, 0);
706 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
707 WREG32(CB_COLOR7_FRAG, 0);
708
709 /* clear render buffer base addresses */
710 WREG32(CB_COLOR0_BASE, 0);
711 WREG32(CB_COLOR1_BASE, 0);
712 WREG32(CB_COLOR2_BASE, 0);
713 WREG32(CB_COLOR3_BASE, 0);
714 WREG32(CB_COLOR4_BASE, 0);
715 WREG32(CB_COLOR5_BASE, 0);
716 WREG32(CB_COLOR6_BASE, 0);
717 WREG32(CB_COLOR7_BASE, 0);
718
719 WREG32(TCP_CNTL, 0);
720
721 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
722 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
723
724 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
725
726 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
727 NUM_CLIP_SEQ(3)));
728
729 }
730
731 int rv770_mc_init(struct radeon_device *rdev)
732 {
733 fixed20_12 a;
734 u32 tmp;
735 int r;
736
737 /* Get VRAM informations */
738 /* FIXME: Don't know how to determine vram width, need to check
739 * vram_width usage
740 */
741 rdev->mc.vram_width = 128;
742 rdev->mc.vram_is_ddr = true;
743 /* Could aper size report 0 ? */
744 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
745 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
746 /* Setup GPU memory space */
747 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
748 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
749
750 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
751 rdev->mc.mc_vram_size = rdev->mc.aper_size;
752
753 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
754 rdev->mc.real_vram_size = rdev->mc.aper_size;
755
756 if (rdev->flags & RADEON_IS_AGP) {
757 r = radeon_agp_init(rdev);
758 if (r)
759 return r;
760 /* gtt_size is setup by radeon_agp_init */
761 rdev->mc.gtt_location = rdev->mc.agp_base;
762 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
763 /* Try to put vram before or after AGP because we
764 * we want SYSTEM_APERTURE to cover both VRAM and
765 * AGP so that GPU can catch out of VRAM/AGP access
766 */
767 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
768 /* Enought place before */
769 rdev->mc.vram_location = rdev->mc.gtt_location -
770 rdev->mc.mc_vram_size;
771 } else if (tmp > rdev->mc.mc_vram_size) {
772 /* Enought place after */
773 rdev->mc.vram_location = rdev->mc.gtt_location +
774 rdev->mc.gtt_size;
775 } else {
776 /* Try to setup VRAM then AGP might not
777 * not work on some card
778 */
779 rdev->mc.vram_location = 0x00000000UL;
780 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
781 }
782 } else {
783 rdev->mc.vram_location = 0x00000000UL;
784 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
785 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
786 }
787 rdev->mc.vram_start = rdev->mc.vram_location;
788 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size;
789 rdev->mc.gtt_start = rdev->mc.gtt_location;
790 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size;
791 /* FIXME: we should enforce default clock in case GPU is not in
792 * default setup
793 */
794 a.full = rfixed_const(100);
795 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
796 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
797 return 0;
798 }
799 int rv770_gpu_reset(struct radeon_device *rdev)
800 {
801 /* FIXME: implement any rv770 specific bits */
802 return r600_gpu_reset(rdev);
803 }
804
805 static int rv770_startup(struct radeon_device *rdev)
806 {
807 int r;
808
809 rv770_mc_program(rdev);
810 r = rv770_pcie_gart_enable(rdev);
811 if (r)
812 return r;
813 rv770_gpu_init(rdev);
814
815 r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
816 &rdev->r600_blit.shader_gpu_addr);
817 if (r) {
818 DRM_ERROR("failed to pin blit object %d\n", r);
819 return r;
820 }
821
822 r = radeon_ring_init(rdev, rdev->cp.ring_size);
823 if (r)
824 return r;
825 r = rv770_cp_load_microcode(rdev);
826 if (r)
827 return r;
828 r = r600_cp_resume(rdev);
829 if (r)
830 return r;
831 /* write back buffer are not vital so don't worry about failure */
832 r600_wb_enable(rdev);
833 return 0;
834 }
835
836 int rv770_resume(struct radeon_device *rdev)
837 {
838 int r;
839
840 if (rv770_gpu_reset(rdev)) {
841 /* FIXME: what do we want to do here ? */
842 }
843 /* post card */
844 atom_asic_init(rdev->mode_info.atom_context);
845 /* Initialize clocks */
846 r = radeon_clocks_init(rdev);
847 if (r) {
848 return r;
849 }
850
851 r = rv770_startup(rdev);
852 if (r) {
853 DRM_ERROR("r600 startup failed on resume\n");
854 return r;
855 }
856
857 r = r600_ib_test(rdev);
858 if (r) {
859 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
860 return r;
861 }
862 return r;
863
864 }
865
866 int rv770_suspend(struct radeon_device *rdev)
867 {
868 /* FIXME: we should wait for ring to be empty */
869 r700_cp_stop(rdev);
870 rdev->cp.ready = false;
871 r600_wb_disable(rdev);
872 rv770_pcie_gart_disable(rdev);
873 /* unpin shaders bo */
874 radeon_object_unpin(rdev->r600_blit.shader_obj);
875 return 0;
876 }
877
878 /* Plan is to move initialization in that function and use
879 * helper function so that radeon_device_init pretty much
880 * do nothing more than calling asic specific function. This
881 * should also allow to remove a bunch of callback function
882 * like vram_info.
883 */
884 int rv770_init(struct radeon_device *rdev)
885 {
886 int r;
887
888 r = radeon_dummy_page_init(rdev);
889 if (r)
890 return r;
891 /* This don't do much */
892 r = radeon_gem_init(rdev);
893 if (r)
894 return r;
895 /* Read BIOS */
896 if (!radeon_get_bios(rdev)) {
897 if (ASIC_IS_AVIVO(rdev))
898 return -EINVAL;
899 }
900 /* Must be an ATOMBIOS */
901 if (!rdev->is_atom_bios) {
902 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
903 return -EINVAL;
904 }
905 r = radeon_atombios_init(rdev);
906 if (r)
907 return r;
908 /* Post card if necessary */
909 if (!r600_card_posted(rdev) && rdev->bios) {
910 DRM_INFO("GPU not posted. posting now...\n");
911 atom_asic_init(rdev->mode_info.atom_context);
912 }
913 /* Initialize scratch registers */
914 r600_scratch_init(rdev);
915 /* Initialize surface registers */
916 radeon_surface_init(rdev);
917 radeon_get_clock_info(rdev->ddev);
918 r = radeon_clocks_init(rdev);
919 if (r)
920 return r;
921 /* Fence driver */
922 r = radeon_fence_driver_init(rdev);
923 if (r)
924 return r;
925 r = rv770_mc_init(rdev);
926 if (r) {
927 if (rdev->flags & RADEON_IS_AGP) {
928 /* Retry with disabling AGP */
929 rv770_fini(rdev);
930 rdev->flags &= ~RADEON_IS_AGP;
931 return rv770_init(rdev);
932 }
933 return r;
934 }
935 /* Memory manager */
936 r = radeon_object_init(rdev);
937 if (r)
938 return r;
939 rdev->cp.ring_obj = NULL;
940 r600_ring_init(rdev, 1024 * 1024);
941
942 if (!rdev->me_fw || !rdev->pfp_fw) {
943 r = r600_cp_init_microcode(rdev);
944 if (r) {
945 DRM_ERROR("Failed to load firmware!\n");
946 return r;
947 }
948 }
949
950 r = r600_pcie_gart_init(rdev);
951 if (r)
952 return r;
953
954 rdev->accel_working = true;
955 r = r600_blit_init(rdev);
956 if (r) {
957 DRM_ERROR("radeon: failled blitter (%d).\n", r);
958 rdev->accel_working = false;
959 }
960
961 r = rv770_startup(rdev);
962 if (r) {
963 if (rdev->flags & RADEON_IS_AGP) {
964 /* Retry with disabling AGP */
965 rv770_fini(rdev);
966 rdev->flags &= ~RADEON_IS_AGP;
967 return rv770_init(rdev);
968 }
969 rv770_suspend(rdev);
970 r600_wb_fini(rdev);
971 radeon_ib_pool_fini(rdev);
972 radeon_ring_fini(rdev);
973 rv770_pcie_gart_fini(rdev);
974 rdev->accel_working = false;
975 }
976 if (rdev->accel_working) {
977 r = radeon_ib_pool_init(rdev);
978 if (r) {
979 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
980 rdev->accel_working = false;
981 }
982 r = r600_ib_test(rdev);
983 if (r) {
984 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
985 rdev->accel_working = false;
986 }
987 }
988 return 0;
989 }
990
991 void rv770_fini(struct radeon_device *rdev)
992 {
993 rv770_suspend(rdev);
994
995 r600_blit_fini(rdev);
996 radeon_ring_fini(rdev);
997 r600_wb_fini(rdev);
998 rv770_pcie_gart_fini(rdev);
999 radeon_gem_fini(rdev);
1000 radeon_fence_driver_fini(rdev);
1001 radeon_clocks_fini(rdev);
1002 #if __OS_HAS_AGP
1003 if (rdev->flags & RADEON_IS_AGP)
1004 radeon_agp_fini(rdev);
1005 #endif
1006 radeon_object_fini(rdev);
1007 radeon_atombios_fini(rdev);
1008 kfree(rdev->bios);
1009 rdev->bios = NULL;
1010 radeon_dummy_page_fini(rdev);
1011 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree