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drm/radeon/kms/DCE3+: switch pads to ddc mode when going i2c
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / radeon / radeon_i2c.c
blob0cd2704e9a486ee1886ffd041237c8175558149c
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29 #include "atom.h"
30
31 /**
32 * radeon_ddc_probe
33 *
34 */
35 bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
36 {
37 u8 out_buf[] = { 0x0, 0x0};
38 u8 buf[2];
39 int ret;
40 struct i2c_msg msgs[] = {
41 {
42 .addr = 0x50,
43 .flags = 0,
44 .len = 1,
45 .buf = out_buf,
46 },
47 {
48 .addr = 0x50,
49 .flags = I2C_M_RD,
50 .len = 1,
51 .buf = buf,
52 }
53 };
54
55 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
56 if (ret == 2)
57 return true;
58
59 return false;
60 }
61
62 /* bit banging i2c */
63
64 static void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state)
65 {
66 struct radeon_device *rdev = i2c->dev->dev_private;
67 struct radeon_i2c_bus_rec *rec = &i2c->rec;
68 uint32_t temp;
69
70 /* RV410 appears to have a bug where the hw i2c in reset
71 * holds the i2c port in a bad state - switch hw i2c away before
72 * doing DDC - do this for all r200s/r300s/r400s for safety sake
73 */
74 if (rec->hw_capable) {
75 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
76 u32 reg;
77
78 if (rdev->family >= CHIP_RV350)
79 reg = RADEON_GPIO_MONID;
80 else if ((rdev->family == CHIP_R300) ||
81 (rdev->family == CHIP_R350))
82 reg = RADEON_GPIO_DVI_DDC;
83 else
84 reg = RADEON_GPIO_CRT2_DDC;
85
86 mutex_lock(&rdev->dc_hw_i2c_mutex);
87 if (rec->a_clk_reg == reg) {
88 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
89 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
90 } else {
91 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
92 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
93 }
94 mutex_unlock(&rdev->dc_hw_i2c_mutex);
95 }
96 }
97
98 /* switch the pads to ddc mode */
99 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) {
100 temp = RREG32(rec->mask_clk_reg);
101 temp &= ~(1 << 16);
102 WREG32(rec->mask_clk_reg, temp);
103 }
104
105 /* clear the output pin values */
106 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
107 WREG32(rec->a_clk_reg, temp);
108
109 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
110 WREG32(rec->a_data_reg, temp);
111
112 /* set the pins to input */
113 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
114 WREG32(rec->en_clk_reg, temp);
115
116 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
117 WREG32(rec->en_data_reg, temp);
118
119 /* mask the gpio pins for software use */
120 temp = RREG32(rec->mask_clk_reg);
121 if (lock_state)
122 temp |= rec->mask_clk_mask;
123 else
124 temp &= ~rec->mask_clk_mask;
125 WREG32(rec->mask_clk_reg, temp);
126 temp = RREG32(rec->mask_clk_reg);
127
128 temp = RREG32(rec->mask_data_reg);
129 if (lock_state)
130 temp |= rec->mask_data_mask;
131 else
132 temp &= ~rec->mask_data_mask;
133 WREG32(rec->mask_data_reg, temp);
134 temp = RREG32(rec->mask_data_reg);
135 }
136
137 static int get_clock(void *i2c_priv)
138 {
139 struct radeon_i2c_chan *i2c = i2c_priv;
140 struct radeon_device *rdev = i2c->dev->dev_private;
141 struct radeon_i2c_bus_rec *rec = &i2c->rec;
142 uint32_t val;
143
144 /* read the value off the pin */
145 val = RREG32(rec->y_clk_reg);
146 val &= rec->y_clk_mask;
147
148 return (val != 0);
149 }
150
151
152 static int get_data(void *i2c_priv)
153 {
154 struct radeon_i2c_chan *i2c = i2c_priv;
155 struct radeon_device *rdev = i2c->dev->dev_private;
156 struct radeon_i2c_bus_rec *rec = &i2c->rec;
157 uint32_t val;
158
159 /* read the value off the pin */
160 val = RREG32(rec->y_data_reg);
161 val &= rec->y_data_mask;
162
163 return (val != 0);
164 }
165
166 static void set_clock(void *i2c_priv, int clock)
167 {
168 struct radeon_i2c_chan *i2c = i2c_priv;
169 struct radeon_device *rdev = i2c->dev->dev_private;
170 struct radeon_i2c_bus_rec *rec = &i2c->rec;
171 uint32_t val;
172
173 /* set pin direction */
174 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
175 val |= clock ? 0 : rec->en_clk_mask;
176 WREG32(rec->en_clk_reg, val);
177 }
178
179 static void set_data(void *i2c_priv, int data)
180 {
181 struct radeon_i2c_chan *i2c = i2c_priv;
182 struct radeon_device *rdev = i2c->dev->dev_private;
183 struct radeon_i2c_bus_rec *rec = &i2c->rec;
184 uint32_t val;
185
186 /* set pin direction */
187 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
188 val |= data ? 0 : rec->en_data_mask;
189 WREG32(rec->en_data_reg, val);
190 }
191
192 static int pre_xfer(struct i2c_adapter *i2c_adap)
193 {
194 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
195
196 radeon_i2c_do_lock(i2c, 1);
197
198 return 0;
199 }
200
201 static void post_xfer(struct i2c_adapter *i2c_adap)
202 {
203 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
204
205 radeon_i2c_do_lock(i2c, 0);
206 }
207
208 /* hw i2c */
209
210 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
211 {
212 u32 sclk = radeon_get_engine_clock(rdev);
213 u32 prescale = 0;
214 u32 nm;
215 u8 n, m, loop;
216 int i2c_clock;
217
218 switch (rdev->family) {
219 case CHIP_R100:
220 case CHIP_RV100:
221 case CHIP_RS100:
222 case CHIP_RV200:
223 case CHIP_RS200:
224 case CHIP_R200:
225 case CHIP_RV250:
226 case CHIP_RS300:
227 case CHIP_RV280:
228 case CHIP_R300:
229 case CHIP_R350:
230 case CHIP_RV350:
231 i2c_clock = 60;
232 nm = (sclk * 10) / (i2c_clock * 4);
233 for (loop = 1; loop < 255; loop++) {
234 if ((nm / loop) < loop)
235 break;
236 }
237 n = loop - 1;
238 m = loop - 2;
239 prescale = m | (n << 8);
240 break;
241 case CHIP_RV380:
242 case CHIP_RS400:
243 case CHIP_RS480:
244 case CHIP_R420:
245 case CHIP_R423:
246 case CHIP_RV410:
247 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
248 break;
249 case CHIP_RS600:
250 case CHIP_RS690:
251 case CHIP_RS740:
252 /* todo */
253 break;
254 case CHIP_RV515:
255 case CHIP_R520:
256 case CHIP_RV530:
257 case CHIP_RV560:
258 case CHIP_RV570:
259 case CHIP_R580:
260 i2c_clock = 50;
261 if (rdev->family == CHIP_R520)
262 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
263 else
264 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
265 break;
266 case CHIP_R600:
267 case CHIP_RV610:
268 case CHIP_RV630:
269 case CHIP_RV670:
270 /* todo */
271 break;
272 case CHIP_RV620:
273 case CHIP_RV635:
274 case CHIP_RS780:
275 case CHIP_RS880:
276 case CHIP_RV770:
277 case CHIP_RV730:
278 case CHIP_RV710:
279 case CHIP_RV740:
280 /* todo */
281 break;
282 case CHIP_CEDAR:
283 case CHIP_REDWOOD:
284 case CHIP_JUNIPER:
285 case CHIP_CYPRESS:
286 case CHIP_HEMLOCK:
287 /* todo */
288 break;
289 default:
290 DRM_ERROR("i2c: unhandled radeon chip\n");
291 break;
292 }
293 return prescale;
294 }
295
296
297 /* hw i2c engine for r1xx-4xx hardware
298 * hw can buffer up to 15 bytes
299 */
300 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
301 struct i2c_msg *msgs, int num)
302 {
303 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
304 struct radeon_device *rdev = i2c->dev->dev_private;
305 struct radeon_i2c_bus_rec *rec = &i2c->rec;
306 struct i2c_msg *p;
307 int i, j, k, ret = num;
308 u32 prescale;
309 u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
310 u32 tmp, reg;
311
312 mutex_lock(&rdev->dc_hw_i2c_mutex);
313 /* take the pm lock since we need a constant sclk */
314 mutex_lock(&rdev->pm.mutex);
315
316 prescale = radeon_get_i2c_prescale(rdev);
317
318 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
319 RADEON_I2C_DRIVE_EN |
320 RADEON_I2C_START |
321 RADEON_I2C_STOP |
322 RADEON_I2C_GO);
323
324 if (rdev->is_atom_bios) {
325 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
326 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
327 }
328
329 if (rec->mm_i2c) {
330 i2c_cntl_0 = RADEON_I2C_CNTL_0;
331 i2c_cntl_1 = RADEON_I2C_CNTL_1;
332 i2c_data = RADEON_I2C_DATA;
333 } else {
334 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
335 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
336 i2c_data = RADEON_DVI_I2C_DATA;
337
338 switch (rdev->family) {
339 case CHIP_R100:
340 case CHIP_RV100:
341 case CHIP_RS100:
342 case CHIP_RV200:
343 case CHIP_RS200:
344 case CHIP_RS300:
345 switch (rec->mask_clk_reg) {
346 case RADEON_GPIO_DVI_DDC:
347 /* no gpio select bit */
348 break;
349 default:
350 DRM_ERROR("gpio not supported with hw i2c\n");
351 ret = -EINVAL;
352 goto done;
353 }
354 break;
355 case CHIP_R200:
356 /* only bit 4 on r200 */
357 switch (rec->mask_clk_reg) {
358 case RADEON_GPIO_DVI_DDC:
359 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
360 break;
361 case RADEON_GPIO_MONID:
362 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
363 break;
364 default:
365 DRM_ERROR("gpio not supported with hw i2c\n");
366 ret = -EINVAL;
367 goto done;
368 }
369 break;
370 case CHIP_RV250:
371 case CHIP_RV280:
372 /* bits 3 and 4 */
373 switch (rec->mask_clk_reg) {
374 case RADEON_GPIO_DVI_DDC:
375 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
376 break;
377 case RADEON_GPIO_VGA_DDC:
378 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
379 break;
380 case RADEON_GPIO_CRT2_DDC:
381 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
382 break;
383 default:
384 DRM_ERROR("gpio not supported with hw i2c\n");
385 ret = -EINVAL;
386 goto done;
387 }
388 break;
389 case CHIP_R300:
390 case CHIP_R350:
391 /* only bit 4 on r300/r350 */
392 switch (rec->mask_clk_reg) {
393 case RADEON_GPIO_VGA_DDC:
394 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
395 break;
396 case RADEON_GPIO_DVI_DDC:
397 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
398 break;
399 default:
400 DRM_ERROR("gpio not supported with hw i2c\n");
401 ret = -EINVAL;
402 goto done;
403 }
404 break;
405 case CHIP_RV350:
406 case CHIP_RV380:
407 case CHIP_R420:
408 case CHIP_R423:
409 case CHIP_RV410:
410 case CHIP_RS400:
411 case CHIP_RS480:
412 /* bits 3 and 4 */
413 switch (rec->mask_clk_reg) {
414 case RADEON_GPIO_VGA_DDC:
415 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
416 break;
417 case RADEON_GPIO_DVI_DDC:
418 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
419 break;
420 case RADEON_GPIO_MONID:
421 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
422 break;
423 default:
424 DRM_ERROR("gpio not supported with hw i2c\n");
425 ret = -EINVAL;
426 goto done;
427 }
428 break;
429 default:
430 DRM_ERROR("unsupported asic\n");
431 ret = -EINVAL;
432 goto done;
433 break;
434 }
435 }
436
437 /* check for bus probe */
438 p = &msgs[0];
439 if ((num == 1) && (p->len == 0)) {
440 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
441 RADEON_I2C_NACK |
442 RADEON_I2C_HALT |
443 RADEON_I2C_SOFT_RST));
444 WREG32(i2c_data, (p->addr << 1) & 0xff);
445 WREG32(i2c_data, 0);
446 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
447 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
448 RADEON_I2C_EN |
449 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
450 WREG32(i2c_cntl_0, reg);
451 for (k = 0; k < 32; k++) {
452 udelay(10);
453 tmp = RREG32(i2c_cntl_0);
454 if (tmp & RADEON_I2C_GO)
455 continue;
456 tmp = RREG32(i2c_cntl_0);
457 if (tmp & RADEON_I2C_DONE)
458 break;
459 else {
460 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
461 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
462 ret = -EIO;
463 goto done;
464 }
465 }
466 goto done;
467 }
468
469 for (i = 0; i < num; i++) {
470 p = &msgs[i];
471 for (j = 0; j < p->len; j++) {
472 if (p->flags & I2C_M_RD) {
473 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
474 RADEON_I2C_NACK |
475 RADEON_I2C_HALT |
476 RADEON_I2C_SOFT_RST));
477 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);
478 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
479 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
480 RADEON_I2C_EN |
481 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
482 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
483 for (k = 0; k < 32; k++) {
484 udelay(10);
485 tmp = RREG32(i2c_cntl_0);
486 if (tmp & RADEON_I2C_GO)
487 continue;
488 tmp = RREG32(i2c_cntl_0);
489 if (tmp & RADEON_I2C_DONE)
490 break;
491 else {
492 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
493 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
494 ret = -EIO;
495 goto done;
496 }
497 }
498 p->buf[j] = RREG32(i2c_data) & 0xff;
499 } else {
500 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
501 RADEON_I2C_NACK |
502 RADEON_I2C_HALT |
503 RADEON_I2C_SOFT_RST));
504 WREG32(i2c_data, (p->addr << 1) & 0xff);
505 WREG32(i2c_data, p->buf[j]);
506 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
507 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
508 RADEON_I2C_EN |
509 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
510 WREG32(i2c_cntl_0, reg);
511 for (k = 0; k < 32; k++) {
512 udelay(10);
513 tmp = RREG32(i2c_cntl_0);
514 if (tmp & RADEON_I2C_GO)
515 continue;
516 tmp = RREG32(i2c_cntl_0);
517 if (tmp & RADEON_I2C_DONE)
518 break;
519 else {
520 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
521 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
522 ret = -EIO;
523 goto done;
524 }
525 }
526 }
527 }
528 }
529
530 done:
531 WREG32(i2c_cntl_0, 0);
532 WREG32(i2c_cntl_1, 0);
533 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
534 RADEON_I2C_NACK |
535 RADEON_I2C_HALT |
536 RADEON_I2C_SOFT_RST));
537
538 if (rdev->is_atom_bios) {
539 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
540 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
541 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
542 }
543
544 mutex_unlock(&rdev->pm.mutex);
545 mutex_unlock(&rdev->dc_hw_i2c_mutex);
546
547 return ret;
548 }
549
550 /* hw i2c engine for r5xx hardware
551 * hw can buffer up to 15 bytes
552 */
553 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
554 struct i2c_msg *msgs, int num)
555 {
556 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
557 struct radeon_device *rdev = i2c->dev->dev_private;
558 struct radeon_i2c_bus_rec *rec = &i2c->rec;
559 struct i2c_msg *p;
560 int i, j, remaining, current_count, buffer_offset, ret = num;
561 u32 prescale;
562 u32 tmp, reg;
563 u32 saved1, saved2;
564
565 mutex_lock(&rdev->dc_hw_i2c_mutex);
566 /* take the pm lock since we need a constant sclk */
567 mutex_lock(&rdev->pm.mutex);
568
569 prescale = radeon_get_i2c_prescale(rdev);
570
571 /* clear gpio mask bits */
572 tmp = RREG32(rec->mask_clk_reg);
573 tmp &= ~rec->mask_clk_mask;
574 WREG32(rec->mask_clk_reg, tmp);
575 tmp = RREG32(rec->mask_clk_reg);
576
577 tmp = RREG32(rec->mask_data_reg);
578 tmp &= ~rec->mask_data_mask;
579 WREG32(rec->mask_data_reg, tmp);
580 tmp = RREG32(rec->mask_data_reg);
581
582 /* clear pin values */
583 tmp = RREG32(rec->a_clk_reg);
584 tmp &= ~rec->a_clk_mask;
585 WREG32(rec->a_clk_reg, tmp);
586 tmp = RREG32(rec->a_clk_reg);
587
588 tmp = RREG32(rec->a_data_reg);
589 tmp &= ~rec->a_data_mask;
590 WREG32(rec->a_data_reg, tmp);
591 tmp = RREG32(rec->a_data_reg);
592
593 /* set the pins to input */
594 tmp = RREG32(rec->en_clk_reg);
595 tmp &= ~rec->en_clk_mask;
596 WREG32(rec->en_clk_reg, tmp);
597 tmp = RREG32(rec->en_clk_reg);
598
599 tmp = RREG32(rec->en_data_reg);
600 tmp &= ~rec->en_data_mask;
601 WREG32(rec->en_data_reg, tmp);
602 tmp = RREG32(rec->en_data_reg);
603
604 /* */
605 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
606 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
607 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
608 saved2 = RREG32(0x494);
609 WREG32(0x494, saved2 | 0x1);
610
611 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
612 for (i = 0; i < 50; i++) {
613 udelay(1);
614 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
615 break;
616 }
617 if (i == 50) {
618 DRM_ERROR("failed to get i2c bus\n");
619 ret = -EBUSY;
620 goto done;
621 }
622
623 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;
624 switch (rec->mask_clk_reg) {
625 case AVIVO_DC_GPIO_DDC1_MASK:
626 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
627 break;
628 case AVIVO_DC_GPIO_DDC2_MASK:
629 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
630 break;
631 case AVIVO_DC_GPIO_DDC3_MASK:
632 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
633 break;
634 default:
635 DRM_ERROR("gpio not supported with hw i2c\n");
636 ret = -EINVAL;
637 goto done;
638 }
639
640 /* check for bus probe */
641 p = &msgs[0];
642 if ((num == 1) && (p->len == 0)) {
643 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
644 AVIVO_DC_I2C_NACK |
645 AVIVO_DC_I2C_HALT));
646 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
647 udelay(1);
648 WREG32(AVIVO_DC_I2C_RESET, 0);
649
650 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
651 WREG32(AVIVO_DC_I2C_DATA, 0);
652
653 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
654 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
655 AVIVO_DC_I2C_DATA_COUNT(1) |
656 (prescale << 16)));
657 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
658 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
659 for (j = 0; j < 200; j++) {
660 udelay(50);
661 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
662 if (tmp & AVIVO_DC_I2C_GO)
663 continue;
664 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
665 if (tmp & AVIVO_DC_I2C_DONE)
666 break;
667 else {
668 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
669 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
670 ret = -EIO;
671 goto done;
672 }
673 }
674 goto done;
675 }
676
677 for (i = 0; i < num; i++) {
678 p = &msgs[i];
679 remaining = p->len;
680 buffer_offset = 0;
681 if (p->flags & I2C_M_RD) {
682 while (remaining) {
683 if (remaining > 15)
684 current_count = 15;
685 else
686 current_count = remaining;
687 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
688 AVIVO_DC_I2C_NACK |
689 AVIVO_DC_I2C_HALT));
690 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
691 udelay(1);
692 WREG32(AVIVO_DC_I2C_RESET, 0);
693
694 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);
695 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
696 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
697 AVIVO_DC_I2C_DATA_COUNT(current_count) |
698 (prescale << 16)));
699 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
700 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
701 for (j = 0; j < 200; j++) {
702 udelay(50);
703 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
704 if (tmp & AVIVO_DC_I2C_GO)
705 continue;
706 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
707 if (tmp & AVIVO_DC_I2C_DONE)
708 break;
709 else {
710 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
711 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
712 ret = -EIO;
713 goto done;
714 }
715 }
716 for (j = 0; j < current_count; j++)
717 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
718 remaining -= current_count;
719 buffer_offset += current_count;
720 }
721 } else {
722 while (remaining) {
723 if (remaining > 15)
724 current_count = 15;
725 else
726 current_count = remaining;
727 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
728 AVIVO_DC_I2C_NACK |
729 AVIVO_DC_I2C_HALT));
730 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
731 udelay(1);
732 WREG32(AVIVO_DC_I2C_RESET, 0);
733
734 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
735 for (j = 0; j < current_count; j++)
736 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
737
738 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
739 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
740 AVIVO_DC_I2C_DATA_COUNT(current_count) |
741 (prescale << 16)));
742 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
743 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
744 for (j = 0; j < 200; j++) {
745 udelay(50);
746 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
747 if (tmp & AVIVO_DC_I2C_GO)
748 continue;
749 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
750 if (tmp & AVIVO_DC_I2C_DONE)
751 break;
752 else {
753 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
754 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
755 ret = -EIO;
756 goto done;
757 }
758 }
759 remaining -= current_count;
760 buffer_offset += current_count;
761 }
762 }
763 }
764
765 done:
766 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
767 AVIVO_DC_I2C_NACK |
768 AVIVO_DC_I2C_HALT));
769 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
770 udelay(1);
771 WREG32(AVIVO_DC_I2C_RESET, 0);
772
773 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
774 WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
775 WREG32(0x494, saved2);
776 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
777 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
778 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
779
780 mutex_unlock(&rdev->pm.mutex);
781 mutex_unlock(&rdev->dc_hw_i2c_mutex);
782
783 return ret;
784 }
785
786 static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
787 struct i2c_msg *msgs, int num)
788 {
789 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
790 struct radeon_device *rdev = i2c->dev->dev_private;
791 struct radeon_i2c_bus_rec *rec = &i2c->rec;
792 int ret = 0;
793
794 switch (rdev->family) {
795 case CHIP_R100:
796 case CHIP_RV100:
797 case CHIP_RS100:
798 case CHIP_RV200:
799 case CHIP_RS200:
800 case CHIP_R200:
801 case CHIP_RV250:
802 case CHIP_RS300:
803 case CHIP_RV280:
804 case CHIP_R300:
805 case CHIP_R350:
806 case CHIP_RV350:
807 case CHIP_RV380:
808 case CHIP_R420:
809 case CHIP_R423:
810 case CHIP_RV410:
811 case CHIP_RS400:
812 case CHIP_RS480:
813 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
814 break;
815 case CHIP_RS600:
816 case CHIP_RS690:
817 case CHIP_RS740:
818 /* XXX fill in hw i2c implementation */
819 break;
820 case CHIP_RV515:
821 case CHIP_R520:
822 case CHIP_RV530:
823 case CHIP_RV560:
824 case CHIP_RV570:
825 case CHIP_R580:
826 if (rec->mm_i2c)
827 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
828 else
829 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
830 break;
831 case CHIP_R600:
832 case CHIP_RV610:
833 case CHIP_RV630:
834 case CHIP_RV670:
835 /* XXX fill in hw i2c implementation */
836 break;
837 case CHIP_RV620:
838 case CHIP_RV635:
839 case CHIP_RS780:
840 case CHIP_RS880:
841 case CHIP_RV770:
842 case CHIP_RV730:
843 case CHIP_RV710:
844 case CHIP_RV740:
845 /* XXX fill in hw i2c implementation */
846 break;
847 case CHIP_CEDAR:
848 case CHIP_REDWOOD:
849 case CHIP_JUNIPER:
850 case CHIP_CYPRESS:
851 case CHIP_HEMLOCK:
852 /* XXX fill in hw i2c implementation */
853 break;
854 default:
855 DRM_ERROR("i2c: unhandled radeon chip\n");
856 ret = -EIO;
857 break;
858 }
859
860 return ret;
861 }
862
863 static u32 radeon_hw_i2c_func(struct i2c_adapter *adap)
864 {
865 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
866 }
867
868 static const struct i2c_algorithm radeon_i2c_algo = {
869 .master_xfer = radeon_hw_i2c_xfer,
870 .functionality = radeon_hw_i2c_func,
871 };
872
873 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
874 struct radeon_i2c_bus_rec *rec,
875 const char *name)
876 {
877 struct radeon_device *rdev = dev->dev_private;
878 struct radeon_i2c_chan *i2c;
879 int ret;
880
881 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
882 if (i2c == NULL)
883 return NULL;
884
885 i2c->rec = *rec;
886 i2c->adapter.owner = THIS_MODULE;
887 i2c->dev = dev;
888 i2c_set_adapdata(&i2c->adapter, i2c);
889 if (rec->mm_i2c ||
890 (rec->hw_capable &&
891 radeon_hw_i2c &&
892 ((rdev->family <= CHIP_RS480) ||
893 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) {
894 /* set the radeon hw i2c adapter */
895 sprintf(i2c->adapter.name, "Radeon i2c hw bus %s", name);
896 i2c->adapter.algo = &radeon_i2c_algo;
897 ret = i2c_add_adapter(&i2c->adapter);
898 if (ret) {
899 DRM_ERROR("Failed to register hw i2c %s\n", name);
900 goto out_free;
901 }
902 } else {
903 /* set the radeon bit adapter */
904 sprintf(i2c->adapter.name, "Radeon i2c bit bus %s", name);
905 i2c->adapter.algo_data = &i2c->algo.bit;
906 i2c->algo.bit.pre_xfer = pre_xfer;
907 i2c->algo.bit.post_xfer = post_xfer;
908 i2c->algo.bit.setsda = set_data;
909 i2c->algo.bit.setscl = set_clock;
910 i2c->algo.bit.getsda = get_data;
911 i2c->algo.bit.getscl = get_clock;
912 i2c->algo.bit.udelay = 20;
913 /* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always
914 * make this, 2 jiffies is a lot more reliable */
915 i2c->algo.bit.timeout = 2;
916 i2c->algo.bit.data = i2c;
917 ret = i2c_bit_add_bus(&i2c->adapter);
918 if (ret) {
919 DRM_ERROR("Failed to register bit i2c %s\n", name);
920 goto out_free;
921 }
922 }
923
924 return i2c;
925 out_free:
926 kfree(i2c);
927 return NULL;
928
929 }
930
931 struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
932 struct radeon_i2c_bus_rec *rec,
933 const char *name)
934 {
935 struct radeon_i2c_chan *i2c;
936 int ret;
937
938 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
939 if (i2c == NULL)
940 return NULL;
941
942 i2c->rec = *rec;
943 i2c->adapter.owner = THIS_MODULE;
944 i2c->dev = dev;
945 i2c_set_adapdata(&i2c->adapter, i2c);
946 i2c->adapter.algo_data = &i2c->algo.dp;
947 i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch;
948 i2c->algo.dp.address = 0;
949 ret = i2c_dp_aux_add_bus(&i2c->adapter);
950 if (ret) {
951 DRM_INFO("Failed to register i2c %s\n", name);
952 goto out_free;
953 }
954
955 return i2c;
956 out_free:
957 kfree(i2c);
958 return NULL;
959
960 }
961
962 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
963 {
964 if (!i2c)
965 return;
966 i2c_del_adapter(&i2c->adapter);
967 kfree(i2c);
968 }
969
970 struct drm_encoder *radeon_best_encoder(struct drm_connector *connector)
971 {
972 return NULL;
973 }
974
975 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
976 u8 slave_addr,
977 u8 addr,
978 u8 *val)
979 {
980 u8 out_buf[2];
981 u8 in_buf[2];
982 struct i2c_msg msgs[] = {
983 {
984 .addr = slave_addr,
985 .flags = 0,
986 .len = 1,
987 .buf = out_buf,
988 },
989 {
990 .addr = slave_addr,
991 .flags = I2C_M_RD,
992 .len = 1,
993 .buf = in_buf,
994 }
995 };
996
997 out_buf[0] = addr;
998 out_buf[1] = 0;
999
1000 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
1001 *val = in_buf[0];
1002 DRM_DEBUG("val = 0x%02x\n", *val);
1003 } else {
1004 DRM_ERROR("i2c 0x%02x 0x%02x read failed\n",
1005 addr, *val);
1006 }
1007 }
1008
1009 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1010 u8 slave_addr,
1011 u8 addr,
1012 u8 val)
1013 {
1014 uint8_t out_buf[2];
1015 struct i2c_msg msg = {
1016 .addr = slave_addr,
1017 .flags = 0,
1018 .len = 2,
1019 .buf = out_buf,
1020 };
1021
1022 out_buf[0] = addr;
1023 out_buf[1] = val;
1024
1025 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
1026 DRM_ERROR("i2c 0x%02x 0x%02x write failed\n",
1027 addr, val);
1028 }
1029
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree