arch/cris/arch-v32/kernel/time.c

   1 /*
   2  *  linux/arch/cris/arch-v32/kernel/time.c
   3  *
   4  *  Copyright (C) 2003-2007 Axis Communications AB
   5  *
   6  */
   7
   8 #include <linux/timex.h>
   9 #include <linux/time.h>
  10 #include <linux/jiffies.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/swap.h>
  13 #include <linux/sched.h>
  14 #include <linux/init.h>
  15 #include <linux/threads.h>
  16 #include <linux/cpufreq.h>
  17 #include <asm/types.h>
  18 #include <asm/signal.h>
  19 #include <asm/io.h>
  20 #include <asm/delay.h>
  21 #include <asm/rtc.h>
  22 #include <asm/irq.h>
  23 #include <asm/irq_regs.h>
  24
  25 #include <hwregs/reg_map.h>
  26 #include <hwregs/reg_rdwr.h>
  27 #include <hwregs/timer_defs.h>
  28 #include <hwregs/intr_vect_defs.h>
  29 #ifdef CONFIG_CRIS_MACH_ARTPEC3
  30 #include <hwregs/clkgen_defs.h>
  31 #endif
  32
  33 /* Watchdog defines */
  34 #define ETRAX_WD_KEY_MASK       0x7F /* key is 7 bit */
  35 #define ETRAX_WD_HZ             763 /* watchdog counts at 763 Hz */
  36 /* Number of 763 counts before watchdog bites */
  37 #define ETRAX_WD_CNT            ((2*ETRAX_WD_HZ)/HZ + 1)
  38
  39 unsigned long timer_regs[NR_CPUS] =
  40 {
  41         regi_timer0,
  42 #ifdef CONFIG_SMP
  43         regi_timer2
  44 #endif
  45 };
  46
  47 extern void update_xtime_from_cmos(void);
  48 extern int set_rtc_mmss(unsigned long nowtime);
  49 extern int have_rtc;
  50
  51 #ifdef CONFIG_CPU_FREQ
  52 static int
  53 cris_time_freq_notifier(struct notifier_block *nb, unsigned long val,
  54                         void *data);
  55
  56 static struct notifier_block cris_time_freq_notifier_block = {
  57         .notifier_call = cris_time_freq_notifier,
  58 };
  59 #endif
  60
  61 unsigned long get_ns_in_jiffie(void)
  62 {
  63         reg_timer_r_tmr0_data data;
  64         unsigned long ns;
  65
  66         data = REG_RD(timer, regi_timer0, r_tmr0_data);
  67         ns = (TIMER0_DIV - data) * 10;
  68         return ns;
  69 }
  70
  71 unsigned long do_slow_gettimeoffset(void)
  72 {
  73         unsigned long count;
  74         unsigned long usec_count = 0;
  75
  76         /* For the first call after boot */
  77         static unsigned long count_p = TIMER0_DIV;
  78         static unsigned long jiffies_p = 0;
  79
  80         /* Cache volatile jiffies temporarily; we have IRQs turned off. */
  81         unsigned long jiffies_t;
  82
  83         /* The timer interrupt comes from Etrax timer 0. In order to get
  84          * better precision, we check the current value. It might have
  85          * underflowed already though. */
  86         count = REG_RD(timer, regi_timer0, r_tmr0_data);
  87         jiffies_t = jiffies;
  88
  89         /* Avoiding timer inconsistencies (they are rare, but they happen)
  90          * There is one problem that must be avoided here:
  91          *      1. the timer counter underflows
  92          */
  93         if( jiffies_t == jiffies_p ) {
  94                 if( count > count_p ) {
  95                         /* Timer wrapped, use new count and prescale.
  96                          * Increase the time corresponding to one jiffy.
  97                          */
  98                         usec_count = 1000000/HZ;
  99                 }
 100         } else
 101                 jiffies_p = jiffies_t;
 102         count_p = count;
 103         /* Convert timer value to usec */
 104         /* 100 MHz timer, divide by 100 to get usec */
 105         usec_count +=  (TIMER0_DIV - count) / 100;
 106         return usec_count;
 107 }
 108
 109 /* From timer MDS describing the hardware watchdog:
 110  * 4.3.1 Watchdog Operation
 111  * The watchdog timer is an 8-bit timer with a configurable start value.
 112  * Once started the watchdog counts downwards with a frequency of 763 Hz
 113  * (100/131072 MHz). When the watchdog counts down to 1, it generates an
 114  * NMI (Non Maskable Interrupt), and when it counts down to 0, it resets the
 115  * chip.
 116  */
 117 /* This gives us 1.3 ms to do something useful when the NMI comes */
 118
 119 /* Right now, starting the watchdog is the same as resetting it */
 120 #define start_watchdog reset_watchdog
 121
 122 #if defined(CONFIG_ETRAX_WATCHDOG)
 123 static short int watchdog_key = 42;  /* arbitrary 7 bit number */
 124 #endif
 125
 126 /* Number of pages to consider "out of memory". It is normal that the memory
 127  * is used though, so set this really low. */
 128 #define WATCHDOG_MIN_FREE_PAGES 8
 129
 130 void
 131 reset_watchdog(void)
 132 {
 133 #if defined(CONFIG_ETRAX_WATCHDOG)
 134         reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
 135
 136         /* Only keep watchdog happy as long as we have memory left! */
 137         if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
 138                 /* Reset the watchdog with the inverse of the old key */
 139                 /* Invert key, which is 7 bits */
 140                 watchdog_key ^= ETRAX_WD_KEY_MASK;
 141                 wd_ctrl.cnt = ETRAX_WD_CNT;
 142                 wd_ctrl.cmd = regk_timer_start;
 143                 wd_ctrl.key = watchdog_key;
 144                 REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
 145         }
 146 #endif
 147 }
 148
 149 /* stop the watchdog - we still need the correct key */
 150
 151 void
 152 stop_watchdog(void)
 153 {
 154 #if defined(CONFIG_ETRAX_WATCHDOG)
 155         reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
 156         watchdog_key ^= ETRAX_WD_KEY_MASK; /* invert key, which is 7 bits */
 157         wd_ctrl.cnt = ETRAX_WD_CNT;
 158         wd_ctrl.cmd = regk_timer_stop;
 159         wd_ctrl.key = watchdog_key;
 160         REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
 161 #endif
 162 }
 163
 164 extern void show_registers(struct pt_regs *regs);
 165
 166 void
 167 handle_watchdog_bite(struct pt_regs* regs)
 168 {
 169 #if defined(CONFIG_ETRAX_WATCHDOG)
 170         extern int cause_of_death;
 171
 172         oops_in_progress = 1;
 173         printk(KERN_WARNING "Watchdog bite\n");
 174
 175         /* Check if forced restart or unexpected watchdog */
 176         if (cause_of_death == 0xbedead) {
 177 #ifdef CONFIG_CRIS_MACH_ARTPEC3
 178                 /* There is a bug in Artpec-3 (voodoo TR 78) that requires
 179                  * us to go to lower frequency for the reset to be reliable
 180                  */
 181                 reg_clkgen_rw_clk_ctrl ctrl =
 182                         REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
 183                 ctrl.pll = 0;
 184                 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, ctrl);
 185 #endif
 186                 while(1);
 187         }
 188
 189         /* Unexpected watchdog, stop the watchdog and dump registers. */
 190         stop_watchdog();
 191         printk(KERN_WARNING "Oops: bitten by watchdog\n");
 192         show_registers(regs);
 193         oops_in_progress = 0;
 194 #ifndef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
 195         reset_watchdog();
 196 #endif
 197         while(1) /* nothing */;
 198 #endif
 199 }
 200
 201 /* Last time the cmos clock got updated. */
 202 static long last_rtc_update = 0;
 203
 204 /*
 205  * timer_interrupt() needs to keep up the real-time clock,
 206  * as well as call the "do_timer()" routine every clocktick.
 207  */
 208 extern void cris_do_profile(struct pt_regs *regs);
 209
 210 static inline irqreturn_t
 211 timer_interrupt(int irq, void *dev_id)
 212 {
 213         struct pt_regs *regs = get_irq_regs();
 214         int cpu = smp_processor_id();
 215         reg_timer_r_masked_intr masked_intr;
 216         reg_timer_rw_ack_intr ack_intr = { 0 };
 217
 218         /* Check if the timer interrupt is for us (a tmr0 int) */
 219         masked_intr = REG_RD(timer, timer_regs[cpu], r_masked_intr);
 220         if (!masked_intr.tmr0)
 221                 return IRQ_NONE;
 222
 223         /* Acknowledge the timer irq. */
 224         ack_intr.tmr0 = 1;
 225         REG_WR(timer, timer_regs[cpu], rw_ack_intr, ack_intr);
 226
 227         /* Reset watchdog otherwise it resets us! */
 228         reset_watchdog();
 229
 230         /* Update statistics. */
 231         update_process_times(user_mode(regs));
 232
 233         cris_do_profile(regs); /* Save profiling information */
 234
 235         /* The master CPU is responsible for the time keeping. */
 236         if (cpu != 0)
 237                 return IRQ_HANDLED;
 238
 239         /* Call the real timer interrupt handler */
 240         do_timer(1);
 241
 242         /*
 243          * If we have an externally synchronized Linux clock, then update
 244          * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
 245          * called as close as possible to 500 ms before the new second starts.
 246          *
 247          * The division here is not time critical since it will run once in
 248          * 11 minutes
 249          */
 250         if ((time_status & STA_UNSYNC) == 0 &&
 251             xtime.tv_sec > last_rtc_update + 660 &&
 252             (xtime.tv_nsec / 1000) >= 500000 - (tick_nsec / 1000) / 2 &&
 253             (xtime.tv_nsec / 1000) <= 500000 + (tick_nsec / 1000) / 2) {
 254                 if (set_rtc_mmss(xtime.tv_sec) == 0)
 255                         last_rtc_update = xtime.tv_sec;
 256                 else
 257                         /* Do it again in 60 s */
 258                         last_rtc_update = xtime.tv_sec - 600;
 259         }
 260         return IRQ_HANDLED;
 261 }
 262
 263 /* Timer is IRQF_SHARED so drivers can add stuff to the timer irq chain.
 264  * It needs to be IRQF_DISABLED to make the jiffies update work properly.
 265  */
 266 static struct irqaction irq_timer = {
 267         .handler = timer_interrupt,
 268         .flags = IRQF_SHARED | IRQF_DISABLED,
 269         .name = "timer"
 270 };
 271
 272 void __init
 273 cris_timer_init(void)
 274 {
 275         int cpu = smp_processor_id();
 276         reg_timer_rw_tmr0_ctrl tmr0_ctrl = { 0 };
 277         reg_timer_rw_tmr0_div tmr0_div = TIMER0_DIV;
 278         reg_timer_rw_intr_mask timer_intr_mask;
 279
 280         /* Setup the etrax timers.
 281          * Base frequency is 100MHz, divider 1000000 -> 100 HZ
 282          * We use timer0, so timer1 is free.
 283          * The trig timer is used by the fasttimer API if enabled.
 284          */
 285
 286         tmr0_ctrl.op = regk_timer_ld;
 287         tmr0_ctrl.freq = regk_timer_f100;
 288         REG_WR(timer, timer_regs[cpu], rw_tmr0_div, tmr0_div);
 289         REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Load */
 290         tmr0_ctrl.op = regk_timer_run;
 291         REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Start */
 292
 293         /* Enable the timer irq. */
 294         timer_intr_mask = REG_RD(timer, timer_regs[cpu], rw_intr_mask);
 295         timer_intr_mask.tmr0 = 1;
 296         REG_WR(timer, timer_regs[cpu], rw_intr_mask, timer_intr_mask);
 297 }
 298
 299 void __init
 300 time_init(void)
 301 {
 302         reg_intr_vect_rw_mask intr_mask;
 303
 304         /* Probe for the RTC and read it if it exists.
 305          * Before the RTC can be probed the loops_per_usec variable needs
 306          * to be initialized to make usleep work. A better value for
 307          * loops_per_usec is calculated by the kernel later once the
 308          * clock has started.
 309          */
 310         loops_per_usec = 50;
 311
 312         if(RTC_INIT() < 0) {
 313                 /* No RTC, start at 1980 */
 314                 xtime.tv_sec = 0;
 315                 xtime.tv_nsec = 0;
 316                 have_rtc = 0;
 317         } else {
 318                 /* Get the current time */
 319                 have_rtc = 1;
 320                 update_xtime_from_cmos();
 321         }
 322
 323         /*
 324          * Initialize wall_to_monotonic such that adding it to
 325          * xtime will yield zero, the tv_nsec field must be normalized
 326          * (i.e., 0 <= nsec < NSEC_PER_SEC).
 327          */
 328         set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec);
 329
 330         /* Start CPU local timer. */
 331         cris_timer_init();
 332
 333         /* Enable the timer irq in global config. */
 334         intr_mask = REG_RD_VECT(intr_vect, regi_irq, rw_mask, 1);
 335         intr_mask.timer0 = 1;
 336         REG_WR_VECT(intr_vect, regi_irq, rw_mask, 1, intr_mask);
 337
 338         /* Now actually register the timer irq handler that calls
 339          * timer_interrupt(). */
 340         setup_irq(TIMER0_INTR_VECT, &irq_timer);
 341
 342         /* Enable watchdog if we should use one. */
 343
 344 #if defined(CONFIG_ETRAX_WATCHDOG)
 345         printk(KERN_INFO "Enabling watchdog...\n");
 346         start_watchdog();
 347
 348         /* If we use the hardware watchdog, we want to trap it as an NMI
 349          * and dump registers before it resets us.  For this to happen, we
 350          * must set the "m" NMI enable flag (which once set, is unset only
 351          * when an NMI is taken). */
 352         {
 353                 unsigned long flags;
 354                 local_save_flags(flags);
 355                 flags |= (1<<30); /* NMI M flag is at bit 30 */
 356                 local_irq_restore(flags);
 357         }
 358 #endif
 359
 360 #ifdef CONFIG_CPU_FREQ
 361         cpufreq_register_notifier(&cris_time_freq_notifier_block,
 362                 CPUFREQ_TRANSITION_NOTIFIER);
 363 #endif
 364 }
 365
 366 #ifdef CONFIG_CPU_FREQ
 367 static int
 368 cris_time_freq_notifier(struct notifier_block *nb, unsigned long val,
 369                         void *data)
 370 {
 371         struct cpufreq_freqs *freqs = data;
 372         if (val == CPUFREQ_POSTCHANGE) {
 373                 reg_timer_r_tmr0_data data;
 374                 reg_timer_rw_tmr0_div div = (freqs->new * 500) / HZ;
 375                 do {
 376                         data = REG_RD(timer, timer_regs[freqs->cpu],
 377                                 r_tmr0_data);
 378                 } while (data > 20);
 379                 REG_WR(timer, timer_regs[freqs->cpu], rw_tmr0_div, div);
 380         }
 381         return 0;
 382 }
 383 #endif