2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/module.h>
27 #include <linux/sysdev.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/dmar.h>
31 #include <linux/init.h>
32 #include <linux/cpu.h>
33 #include <linux/dmi.h>
34 #include <linux/nmi.h>
35 #include <linux/smp.h>
38 #include <asm/perf_event.h>
39 #include <asm/x86_init.h>
40 #include <asm/pgalloc.h>
41 #include <asm/atomic.h>
42 #include <asm/mpspec.h>
43 #include <asm/i8253.h>
44 #include <asm/i8259.h>
45 #include <asm/proto.h>
53 #include <asm/kvm_para.h>
55 unsigned int num_processors
;
57 unsigned disabled_cpus __cpuinitdata
;
59 /* Processor that is doing the boot up */
60 unsigned int boot_cpu_physical_apicid
= -1U;
63 * The highest APIC ID seen during enumeration.
65 * On AMD, this determines the messaging protocol we can use: if all APIC IDs
66 * are in the 0 ... 7 range, then we can use logical addressing which
67 * has some performance advantages (better broadcasting).
69 * If there's an APIC ID above 8, we use physical addressing.
71 unsigned int max_physical_apicid
;
74 * Bitmask of physically existing CPUs:
76 physid_mask_t phys_cpu_present_map
;
79 * Map cpu index to physical APIC ID
81 DEFINE_EARLY_PER_CPU(u16
, x86_cpu_to_apicid
, BAD_APICID
);
82 DEFINE_EARLY_PER_CPU(u16
, x86_bios_cpu_apicid
, BAD_APICID
);
83 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid
);
84 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid
);
88 * Knob to control our willingness to enable the local APIC.
92 static int force_enable_local_apic
;
94 * APIC command line parameters
96 static int __init
parse_lapic(char *arg
)
98 force_enable_local_apic
= 1;
101 early_param("lapic", parse_lapic
);
102 /* Local APIC was disabled by the BIOS and enabled by the kernel */
103 static int enabled_via_apicbase
;
106 * Handle interrupt mode configuration register (IMCR).
107 * This register controls whether the interrupt signals
108 * that reach the BSP come from the master PIC or from the
109 * local APIC. Before entering Symmetric I/O Mode, either
110 * the BIOS or the operating system must switch out of
111 * PIC Mode by changing the IMCR.
113 static inline void imcr_pic_to_apic(void)
115 /* select IMCR register */
117 /* NMI and 8259 INTR go through APIC */
121 static inline void imcr_apic_to_pic(void)
123 /* select IMCR register */
125 /* NMI and 8259 INTR go directly to BSP */
131 static int apic_calibrate_pmtmr __initdata
;
132 static __init
int setup_apicpmtimer(char *s
)
134 apic_calibrate_pmtmr
= 1;
138 __setup("apicpmtimer", setup_apicpmtimer
);
142 #ifdef CONFIG_X86_X2APIC
143 /* x2apic enabled before OS handover */
144 static int x2apic_preenabled
;
145 static __init
int setup_nox2apic(char *str
)
147 if (x2apic_enabled()) {
148 pr_warning("Bios already enabled x2apic, "
149 "can't enforce nox2apic");
153 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
156 early_param("nox2apic", setup_nox2apic
);
159 unsigned long mp_lapic_addr
;
161 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
162 static int disable_apic_timer __cpuinitdata
;
163 /* Local APIC timer works in C2 */
164 int local_apic_timer_c2_ok
;
165 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
167 int first_system_vector
= 0xfe;
170 * Debug level, exported for io_apic.c
172 unsigned int apic_verbosity
;
176 /* Have we found an MP table */
177 int smp_found_config
;
179 static struct resource lapic_resource
= {
180 .name
= "Local APIC",
181 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
184 static unsigned int calibration_result
;
186 static int lapic_next_event(unsigned long delta
,
187 struct clock_event_device
*evt
);
188 static void lapic_timer_setup(enum clock_event_mode mode
,
189 struct clock_event_device
*evt
);
190 static void lapic_timer_broadcast(const struct cpumask
*mask
);
191 static void apic_pm_activate(void);
194 * The local apic timer can be used for any function which is CPU local.
196 static struct clock_event_device lapic_clockevent
= {
198 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
199 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
201 .set_mode
= lapic_timer_setup
,
202 .set_next_event
= lapic_next_event
,
203 .broadcast
= lapic_timer_broadcast
,
207 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
209 static unsigned long apic_phys
;
212 * Get the LAPIC version
214 static inline int lapic_get_version(void)
216 return GET_APIC_VERSION(apic_read(APIC_LVR
));
220 * Check, if the APIC is integrated or a separate chip
222 static inline int lapic_is_integrated(void)
227 return APIC_INTEGRATED(lapic_get_version());
232 * Check, whether this is a modern or a first generation APIC
234 static int modern_apic(void)
236 /* AMD systems use old APIC versions, so check the CPU */
237 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
238 boot_cpu_data
.x86
>= 0xf)
240 return lapic_get_version() >= 0x14;
244 * right after this call apic become NOOP driven
245 * so apic->write/read doesn't do anything
247 void apic_disable(void)
249 pr_info("APIC: switched to apic NOOP\n");
253 void native_apic_wait_icr_idle(void)
255 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
259 u32
native_safe_apic_wait_icr_idle(void)
266 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
270 } while (timeout
++ < 1000);
275 void native_apic_icr_write(u32 low
, u32 id
)
277 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
278 apic_write(APIC_ICR
, low
);
281 u64
native_apic_icr_read(void)
285 icr2
= apic_read(APIC_ICR2
);
286 icr1
= apic_read(APIC_ICR
);
288 return icr1
| ((u64
)icr2
<< 32);
292 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
294 void __cpuinit
enable_NMI_through_LVT0(void)
298 /* unmask and set to NMI */
301 /* Level triggered for 82489DX (32bit mode) */
302 if (!lapic_is_integrated())
303 v
|= APIC_LVT_LEVEL_TRIGGER
;
305 apic_write(APIC_LVT0
, v
);
310 * get_physical_broadcast - Get number of physical broadcast IDs
312 int get_physical_broadcast(void)
314 return modern_apic() ? 0xff : 0xf;
319 * lapic_get_maxlvt - get the maximum number of local vector table entries
321 int lapic_get_maxlvt(void)
325 v
= apic_read(APIC_LVR
);
327 * - we always have APIC integrated on 64bit mode
328 * - 82489DXs do not report # of LVT entries
330 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
338 #define APIC_DIVISOR 16
341 * This function sets up the local APIC timer, with a timeout of
342 * 'clocks' APIC bus clock. During calibration we actually call
343 * this function twice on the boot CPU, once with a bogus timeout
344 * value, second time for real. The other (noncalibrating) CPUs
345 * call this function only once, with the real, calibrated value.
347 * We do reads before writes even if unnecessary, to get around the
348 * P5 APIC double write bug.
350 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
352 unsigned int lvtt_value
, tmp_value
;
354 lvtt_value
= LOCAL_TIMER_VECTOR
;
356 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
357 if (!lapic_is_integrated())
358 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
361 lvtt_value
|= APIC_LVT_MASKED
;
363 apic_write(APIC_LVTT
, lvtt_value
);
368 tmp_value
= apic_read(APIC_TDCR
);
369 apic_write(APIC_TDCR
,
370 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
374 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
378 * Setup extended LVT, AMD specific (K8, family 10h)
380 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
381 * MCE interrupts are supported. Thus MCE offset must be set to 0.
383 * If mask=1, the LVT entry does not generate interrupts while mask=0
384 * enables the vector. See also the BKDGs.
387 #define APIC_EILVT_LVTOFF_MCE 0
388 #define APIC_EILVT_LVTOFF_IBS 1
390 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
392 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVTn(0);
393 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
398 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
400 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
401 return APIC_EILVT_LVTOFF_MCE
;
404 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
406 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
407 return APIC_EILVT_LVTOFF_IBS
;
409 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
412 * Program the next event, relative to now
414 static int lapic_next_event(unsigned long delta
,
415 struct clock_event_device
*evt
)
417 apic_write(APIC_TMICT
, delta
);
422 * Setup the lapic timer in periodic or oneshot mode
424 static void lapic_timer_setup(enum clock_event_mode mode
,
425 struct clock_event_device
*evt
)
430 /* Lapic used as dummy for broadcast ? */
431 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
434 local_irq_save(flags
);
437 case CLOCK_EVT_MODE_PERIODIC
:
438 case CLOCK_EVT_MODE_ONESHOT
:
439 __setup_APIC_LVTT(calibration_result
,
440 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
442 case CLOCK_EVT_MODE_UNUSED
:
443 case CLOCK_EVT_MODE_SHUTDOWN
:
444 v
= apic_read(APIC_LVTT
);
445 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
446 apic_write(APIC_LVTT
, v
);
447 apic_write(APIC_TMICT
, 0);
449 case CLOCK_EVT_MODE_RESUME
:
450 /* Nothing to do here */
454 local_irq_restore(flags
);
458 * Local APIC timer broadcast function
460 static void lapic_timer_broadcast(const struct cpumask
*mask
)
463 apic
->send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
468 * Setup the local APIC timer for this CPU. Copy the initilized values
469 * of the boot CPU and register the clock event in the framework.
471 static void __cpuinit
setup_APIC_timer(void)
473 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
475 if (cpu_has(¤t_cpu_data
, X86_FEATURE_ARAT
)) {
476 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_C3STOP
;
477 /* Make LAPIC timer preferrable over percpu HPET */
478 lapic_clockevent
.rating
= 150;
481 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
482 levt
->cpumask
= cpumask_of(smp_processor_id());
484 clockevents_register_device(levt
);
488 * In this functions we calibrate APIC bus clocks to the external timer.
490 * We want to do the calibration only once since we want to have local timer
491 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
494 * This was previously done by reading the PIT/HPET and waiting for a wrap
495 * around to find out, that a tick has elapsed. I have a box, where the PIT
496 * readout is broken, so it never gets out of the wait loop again. This was
497 * also reported by others.
499 * Monitoring the jiffies value is inaccurate and the clockevents
500 * infrastructure allows us to do a simple substitution of the interrupt
503 * The calibration routine also uses the pm_timer when possible, as the PIT
504 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
505 * back to normal later in the boot process).
508 #define LAPIC_CAL_LOOPS (HZ/10)
510 static __initdata
int lapic_cal_loops
= -1;
511 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
512 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
513 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
514 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
517 * Temporary interrupt handler.
519 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
521 unsigned long long tsc
= 0;
522 long tapic
= apic_read(APIC_TMCCT
);
523 unsigned long pm
= acpi_pm_read_early();
528 switch (lapic_cal_loops
++) {
530 lapic_cal_t1
= tapic
;
531 lapic_cal_tsc1
= tsc
;
533 lapic_cal_j1
= jiffies
;
536 case LAPIC_CAL_LOOPS
:
537 lapic_cal_t2
= tapic
;
538 lapic_cal_tsc2
= tsc
;
539 if (pm
< lapic_cal_pm1
)
540 pm
+= ACPI_PM_OVRRUN
;
542 lapic_cal_j2
= jiffies
;
548 calibrate_by_pmtimer(long deltapm
, long *delta
, long *deltatsc
)
550 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
551 const long pm_thresh
= pm_100ms
/ 100;
555 #ifndef CONFIG_X86_PM_TIMER
559 apic_printk(APIC_VERBOSE
, "... PM-Timer delta = %ld\n", deltapm
);
561 /* Check, if the PM timer is available */
565 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
567 if (deltapm
> (pm_100ms
- pm_thresh
) &&
568 deltapm
< (pm_100ms
+ pm_thresh
)) {
569 apic_printk(APIC_VERBOSE
, "... PM-Timer result ok\n");
573 res
= (((u64
)deltapm
) * mult
) >> 22;
574 do_div(res
, 1000000);
575 pr_warning("APIC calibration not consistent "
576 "with PM-Timer: %ldms instead of 100ms\n",(long)res
);
578 /* Correct the lapic counter value */
579 res
= (((u64
)(*delta
)) * pm_100ms
);
580 do_div(res
, deltapm
);
581 pr_info("APIC delta adjusted to PM-Timer: "
582 "%lu (%ld)\n", (unsigned long)res
, *delta
);
585 /* Correct the tsc counter value */
587 res
= (((u64
)(*deltatsc
)) * pm_100ms
);
588 do_div(res
, deltapm
);
589 apic_printk(APIC_VERBOSE
, "TSC delta adjusted to "
590 "PM-Timer: %lu (%ld) \n",
591 (unsigned long)res
, *deltatsc
);
592 *deltatsc
= (long)res
;
598 static int __init
calibrate_APIC_clock(void)
600 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
601 void (*real_handler
)(struct clock_event_device
*dev
);
602 unsigned long deltaj
;
603 long delta
, deltatsc
;
604 int pm_referenced
= 0;
608 /* Replace the global interrupt handler */
609 real_handler
= global_clock_event
->event_handler
;
610 global_clock_event
->event_handler
= lapic_cal_handler
;
613 * Setup the APIC counter to maximum. There is no way the lapic
614 * can underflow in the 100ms detection time frame
616 __setup_APIC_LVTT(0xffffffff, 0, 0);
618 /* Let the interrupts run */
621 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
626 /* Restore the real event handler */
627 global_clock_event
->event_handler
= real_handler
;
629 /* Build delta t1-t2 as apic timer counts down */
630 delta
= lapic_cal_t1
- lapic_cal_t2
;
631 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
633 deltatsc
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
635 /* we trust the PM based calibration if possible */
636 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
639 /* Calculate the scaled math multiplication factor */
640 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
641 lapic_clockevent
.shift
);
642 lapic_clockevent
.max_delta_ns
=
643 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
644 lapic_clockevent
.min_delta_ns
=
645 clockevent_delta2ns(0xF, &lapic_clockevent
);
647 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
649 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
650 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
651 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
655 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
657 (deltatsc
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
658 (deltatsc
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
661 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
663 calibration_result
/ (1000000 / HZ
),
664 calibration_result
% (1000000 / HZ
));
667 * Do a sanity check on the APIC calibration result
669 if (calibration_result
< (1000000 / HZ
)) {
671 pr_warning("APIC frequency too slow, disabling apic timer\n");
675 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
678 * PM timer calibration failed or not turned on
679 * so lets try APIC timer based calibration
681 if (!pm_referenced
) {
682 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
685 * Setup the apic timer manually
687 levt
->event_handler
= lapic_cal_handler
;
688 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
689 lapic_cal_loops
= -1;
691 /* Let the interrupts run */
694 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
697 /* Stop the lapic timer */
698 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
701 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
702 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
704 /* Check, if the jiffies result is consistent */
705 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
706 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
708 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
712 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
713 pr_warning("APIC timer disabled due to verification failure\n");
721 * Setup the boot APIC
723 * Calibrate and verify the result.
725 void __init
setup_boot_APIC_clock(void)
728 * The local apic timer can be disabled via the kernel
729 * commandline or from the CPU detection code. Register the lapic
730 * timer as a dummy clock event source on SMP systems, so the
731 * broadcast mechanism is used. On UP systems simply ignore it.
733 if (disable_apic_timer
) {
734 pr_info("Disabling APIC timer\n");
735 /* No broadcast on UP ! */
736 if (num_possible_cpus() > 1) {
737 lapic_clockevent
.mult
= 1;
743 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
744 "calibrating APIC timer ...\n");
746 if (calibrate_APIC_clock()) {
747 /* No broadcast on UP ! */
748 if (num_possible_cpus() > 1)
754 * If nmi_watchdog is set to IO_APIC, we need the
755 * PIT/HPET going. Otherwise register lapic as a dummy
758 if (nmi_watchdog
!= NMI_IO_APIC
)
759 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
761 pr_warning("APIC timer registered as dummy,"
762 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
764 /* Setup the lapic or request the broadcast */
768 void __cpuinit
setup_secondary_APIC_clock(void)
774 * The guts of the apic timer interrupt
776 static void local_apic_timer_interrupt(void)
778 int cpu
= smp_processor_id();
779 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
782 * Normally we should not be here till LAPIC has been initialized but
783 * in some cases like kdump, its possible that there is a pending LAPIC
784 * timer interrupt from previous kernel's context and is delivered in
785 * new kernel the moment interrupts are enabled.
787 * Interrupts are enabled early and LAPIC is setup much later, hence
788 * its possible that when we get here evt->event_handler is NULL.
789 * Check for event_handler being NULL and discard the interrupt as
792 if (!evt
->event_handler
) {
793 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
795 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
800 * the NMI deadlock-detector uses this.
802 inc_irq_stat(apic_timer_irqs
);
804 evt
->event_handler(evt
);
808 * Local APIC timer interrupt. This is the most natural way for doing
809 * local interrupts, but local timer interrupts can be emulated by
810 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
812 * [ if a single-CPU system runs an SMP kernel then we call the local
813 * interrupt as well. Thus we cannot inline the local irq ... ]
815 void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
817 struct pt_regs
*old_regs
= set_irq_regs(regs
);
820 * NOTE! We'd better ACK the irq immediately,
821 * because timer handling can be slow.
825 * update_process_times() expects us to have done irq_enter().
826 * Besides, if we don't timer interrupts ignore the global
827 * interrupt lock, which is the WrongThing (tm) to do.
831 local_apic_timer_interrupt();
834 set_irq_regs(old_regs
);
837 int setup_profiling_timer(unsigned int multiplier
)
843 * Local APIC start and shutdown
847 * clear_local_APIC - shutdown the local APIC
849 * This is called, when a CPU is disabled and before rebooting, so the state of
850 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
851 * leftovers during boot.
853 void clear_local_APIC(void)
858 /* APIC hasn't been mapped yet */
859 if (!x2apic_mode
&& !apic_phys
)
862 maxlvt
= lapic_get_maxlvt();
864 * Masking an LVT entry can trigger a local APIC error
865 * if the vector is zero. Mask LVTERR first to prevent this.
868 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
869 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
872 * Careful: we have to set masks only first to deassert
873 * any level-triggered sources.
875 v
= apic_read(APIC_LVTT
);
876 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
877 v
= apic_read(APIC_LVT0
);
878 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
879 v
= apic_read(APIC_LVT1
);
880 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
882 v
= apic_read(APIC_LVTPC
);
883 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
886 /* lets not touch this if we didn't frob it */
887 #ifdef CONFIG_X86_THERMAL_VECTOR
889 v
= apic_read(APIC_LVTTHMR
);
890 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
893 #ifdef CONFIG_X86_MCE_INTEL
895 v
= apic_read(APIC_LVTCMCI
);
896 if (!(v
& APIC_LVT_MASKED
))
897 apic_write(APIC_LVTCMCI
, v
| APIC_LVT_MASKED
);
902 * Clean APIC state for other OSs:
904 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
905 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
906 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
908 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
910 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
912 /* Integrated APIC (!82489DX) ? */
913 if (lapic_is_integrated()) {
915 /* Clear ESR due to Pentium errata 3AP and 11AP */
916 apic_write(APIC_ESR
, 0);
922 * disable_local_APIC - clear and disable the local APIC
924 void disable_local_APIC(void)
928 /* APIC hasn't been mapped yet */
935 * Disable APIC (implies clearing of registers
938 value
= apic_read(APIC_SPIV
);
939 value
&= ~APIC_SPIV_APIC_ENABLED
;
940 apic_write(APIC_SPIV
, value
);
944 * When LAPIC was disabled by the BIOS and enabled by the kernel,
945 * restore the disabled state.
947 if (enabled_via_apicbase
) {
950 rdmsr(MSR_IA32_APICBASE
, l
, h
);
951 l
&= ~MSR_IA32_APICBASE_ENABLE
;
952 wrmsr(MSR_IA32_APICBASE
, l
, h
);
958 * If Linux enabled the LAPIC against the BIOS default disable it down before
959 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
960 * not power-off. Additionally clear all LVT entries before disable_local_APIC
961 * for the case where Linux didn't enable the LAPIC.
963 void lapic_shutdown(void)
967 if (!cpu_has_apic
&& !apic_from_smp_config())
970 local_irq_save(flags
);
973 if (!enabled_via_apicbase
)
977 disable_local_APIC();
980 local_irq_restore(flags
);
984 * This is to verify that we're looking at a real local APIC.
985 * Check these against your board if the CPUs aren't getting
986 * started for no apparent reason.
988 int __init
verify_local_APIC(void)
990 unsigned int reg0
, reg1
;
993 * The version register is read-only in a real APIC.
995 reg0
= apic_read(APIC_LVR
);
996 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
997 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
998 reg1
= apic_read(APIC_LVR
);
999 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
1002 * The two version reads above should print the same
1003 * numbers. If the second one is different, then we
1004 * poke at a non-APIC.
1010 * Check if the version looks reasonably.
1012 reg1
= GET_APIC_VERSION(reg0
);
1013 if (reg1
== 0x00 || reg1
== 0xff)
1015 reg1
= lapic_get_maxlvt();
1016 if (reg1
< 0x02 || reg1
== 0xff)
1020 * The ID register is read/write in a real APIC.
1022 reg0
= apic_read(APIC_ID
);
1023 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
1024 apic_write(APIC_ID
, reg0
^ apic
->apic_id_mask
);
1025 reg1
= apic_read(APIC_ID
);
1026 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
1027 apic_write(APIC_ID
, reg0
);
1028 if (reg1
!= (reg0
^ apic
->apic_id_mask
))
1032 * The next two are just to see if we have sane values.
1033 * They're only really relevant if we're in Virtual Wire
1034 * compatibility mode, but most boxes are anymore.
1036 reg0
= apic_read(APIC_LVT0
);
1037 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1038 reg1
= apic_read(APIC_LVT1
);
1039 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1045 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1047 void __init
sync_Arb_IDs(void)
1050 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1053 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1059 apic_wait_icr_idle();
1061 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1062 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1063 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1067 * An initial setup of the virtual wire mode.
1069 void __init
init_bsp_APIC(void)
1074 * Don't do the setup now if we have a SMP BIOS as the
1075 * through-I/O-APIC virtual wire mode might be active.
1077 if (smp_found_config
|| !cpu_has_apic
)
1081 * Do not trust the local APIC being empty at bootup.
1088 value
= apic_read(APIC_SPIV
);
1089 value
&= ~APIC_VECTOR_MASK
;
1090 value
|= APIC_SPIV_APIC_ENABLED
;
1092 #ifdef CONFIG_X86_32
1093 /* This bit is reserved on P4/Xeon and should be cleared */
1094 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1095 (boot_cpu_data
.x86
== 15))
1096 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1099 value
|= APIC_SPIV_FOCUS_DISABLED
;
1100 value
|= SPURIOUS_APIC_VECTOR
;
1101 apic_write(APIC_SPIV
, value
);
1104 * Set up the virtual wire mode.
1106 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1107 value
= APIC_DM_NMI
;
1108 if (!lapic_is_integrated()) /* 82489DX */
1109 value
|= APIC_LVT_LEVEL_TRIGGER
;
1110 apic_write(APIC_LVT1
, value
);
1113 static void __cpuinit
lapic_setup_esr(void)
1115 unsigned int oldvalue
, value
, maxlvt
;
1117 if (!lapic_is_integrated()) {
1118 pr_info("No ESR for 82489DX.\n");
1122 if (apic
->disable_esr
) {
1124 * Something untraceable is creating bad interrupts on
1125 * secondary quads ... for the moment, just leave the
1126 * ESR disabled - we can't do anything useful with the
1127 * errors anyway - mbligh
1129 pr_info("Leaving ESR disabled.\n");
1133 maxlvt
= lapic_get_maxlvt();
1134 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1135 apic_write(APIC_ESR
, 0);
1136 oldvalue
= apic_read(APIC_ESR
);
1138 /* enables sending errors */
1139 value
= ERROR_APIC_VECTOR
;
1140 apic_write(APIC_LVTERR
, value
);
1143 * spec says clear errors after enabling vector.
1146 apic_write(APIC_ESR
, 0);
1147 value
= apic_read(APIC_ESR
);
1148 if (value
!= oldvalue
)
1149 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1150 "vector: 0x%08x after: 0x%08x\n",
1156 * setup_local_APIC - setup the local APIC
1158 void __cpuinit
setup_local_APIC(void)
1164 arch_disable_smp_support();
1168 #ifdef CONFIG_X86_32
1169 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1170 if (lapic_is_integrated() && apic
->disable_esr
) {
1171 apic_write(APIC_ESR
, 0);
1172 apic_write(APIC_ESR
, 0);
1173 apic_write(APIC_ESR
, 0);
1174 apic_write(APIC_ESR
, 0);
1177 perf_events_lapic_init();
1182 * Double-check whether this APIC is really registered.
1183 * This is meaningless in clustered apic mode, so we skip it.
1185 BUG_ON(!apic
->apic_id_registered());
1188 * Intel recommends to set DFR, LDR and TPR before enabling
1189 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1190 * document number 292116). So here it goes...
1192 apic
->init_apic_ldr();
1195 * Set Task Priority to 'accept all'. We never change this
1198 value
= apic_read(APIC_TASKPRI
);
1199 value
&= ~APIC_TPRI_MASK
;
1200 apic_write(APIC_TASKPRI
, value
);
1203 * After a crash, we no longer service the interrupts and a pending
1204 * interrupt from previous kernel might still have ISR bit set.
1206 * Most probably by now CPU has serviced that pending interrupt and
1207 * it might not have done the ack_APIC_irq() because it thought,
1208 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1209 * does not clear the ISR bit and cpu thinks it has already serivced
1210 * the interrupt. Hence a vector might get locked. It was noticed
1211 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1213 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1214 value
= apic_read(APIC_ISR
+ i
*0x10);
1215 for (j
= 31; j
>= 0; j
--) {
1222 * Now that we are all set up, enable the APIC
1224 value
= apic_read(APIC_SPIV
);
1225 value
&= ~APIC_VECTOR_MASK
;
1229 value
|= APIC_SPIV_APIC_ENABLED
;
1231 #ifdef CONFIG_X86_32
1233 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1234 * certain networking cards. If high frequency interrupts are
1235 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1236 * entry is masked/unmasked at a high rate as well then sooner or
1237 * later IOAPIC line gets 'stuck', no more interrupts are received
1238 * from the device. If focus CPU is disabled then the hang goes
1241 * [ This bug can be reproduced easily with a level-triggered
1242 * PCI Ne2000 networking cards and PII/PIII processors, dual
1246 * Actually disabling the focus CPU check just makes the hang less
1247 * frequent as it makes the interrupt distributon model be more
1248 * like LRU than MRU (the short-term load is more even across CPUs).
1249 * See also the comment in end_level_ioapic_irq(). --macro
1253 * - enable focus processor (bit==0)
1254 * - 64bit mode always use processor focus
1255 * so no need to set it
1257 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1261 * Set spurious IRQ vector
1263 value
|= SPURIOUS_APIC_VECTOR
;
1264 apic_write(APIC_SPIV
, value
);
1267 * Set up LVT0, LVT1:
1269 * set up through-local-APIC on the BP's LINT0. This is not
1270 * strictly necessary in pure symmetric-IO mode, but sometimes
1271 * we delegate interrupts to the 8259A.
1274 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1276 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1277 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1278 value
= APIC_DM_EXTINT
;
1279 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1280 smp_processor_id());
1282 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1283 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1284 smp_processor_id());
1286 apic_write(APIC_LVT0
, value
);
1289 * only the BP should see the LINT1 NMI signal, obviously.
1291 if (!smp_processor_id())
1292 value
= APIC_DM_NMI
;
1294 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1295 if (!lapic_is_integrated()) /* 82489DX */
1296 value
|= APIC_LVT_LEVEL_TRIGGER
;
1297 apic_write(APIC_LVT1
, value
);
1301 #ifdef CONFIG_X86_MCE_INTEL
1302 /* Recheck CMCI information after local APIC is up on CPU #0 */
1303 if (smp_processor_id() == 0)
1308 void __cpuinit
end_local_APIC_setup(void)
1312 #ifdef CONFIG_X86_32
1315 /* Disable the local apic timer */
1316 value
= apic_read(APIC_LVTT
);
1317 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1318 apic_write(APIC_LVTT
, value
);
1322 setup_apic_nmi_watchdog(NULL
);
1326 #ifdef CONFIG_X86_X2APIC
1327 void check_x2apic(void)
1329 if (x2apic_enabled()) {
1330 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1331 x2apic_preenabled
= x2apic_mode
= 1;
1335 void enable_x2apic(void)
1342 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1343 if (!(msr
& X2APIC_ENABLE
)) {
1344 pr_info("Enabling x2apic\n");
1345 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1348 #endif /* CONFIG_X86_X2APIC */
1350 int __init
enable_IR(void)
1352 #ifdef CONFIG_INTR_REMAP
1353 if (!intr_remapping_supported()) {
1354 pr_debug("intr-remapping not supported\n");
1358 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1359 pr_info("Skipped enabling intr-remap because of skipping "
1364 if (enable_intr_remapping(x2apic_supported()))
1367 pr_info("Enabled Interrupt-remapping\n");
1375 void __init
enable_IR_x2apic(void)
1377 unsigned long flags
;
1378 struct IO_APIC_route_entry
**ioapic_entries
= NULL
;
1379 int ret
, x2apic_enabled
= 0;
1380 int dmar_table_init_ret
;
1382 dmar_table_init_ret
= dmar_table_init();
1383 if (dmar_table_init_ret
&& !x2apic_supported())
1386 ioapic_entries
= alloc_ioapic_entries();
1387 if (!ioapic_entries
) {
1388 pr_err("Allocate ioapic_entries failed\n");
1392 ret
= save_IO_APIC_setup(ioapic_entries
);
1394 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1398 local_irq_save(flags
);
1400 mask_IO_APIC_setup(ioapic_entries
);
1402 if (dmar_table_init_ret
)
1408 /* IR is required if there is APIC ID > 255 even when running
1411 if (max_physical_apicid
> 255 || !kvm_para_available())
1414 * without IR all CPUs can be addressed by IOAPIC/MSI
1415 * only in physical mode
1417 x2apic_force_phys();
1422 if (x2apic_supported() && !x2apic_mode
) {
1425 pr_info("Enabled x2apic\n");
1429 if (!ret
) /* IR enabling failed */
1430 restore_IO_APIC_setup(ioapic_entries
);
1432 local_irq_restore(flags
);
1436 free_ioapic_entries(ioapic_entries
);
1441 if (x2apic_preenabled
)
1442 panic("x2apic: enabled by BIOS but kernel init failed.");
1443 else if (cpu_has_x2apic
)
1444 pr_info("Not enabling x2apic, Intr-remapping init failed.\n");
1447 #ifdef CONFIG_X86_64
1449 * Detect and enable local APICs on non-SMP boards.
1450 * Original code written by Keir Fraser.
1451 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1452 * not correctly set up (usually the APIC timer won't work etc.)
1454 static int __init
detect_init_APIC(void)
1456 if (!cpu_has_apic
) {
1457 pr_info("No local APIC present\n");
1461 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1466 * Detect and initialize APIC
1468 static int __init
detect_init_APIC(void)
1472 /* Disabled by kernel option? */
1476 switch (boot_cpu_data
.x86_vendor
) {
1477 case X86_VENDOR_AMD
:
1478 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1479 (boot_cpu_data
.x86
>= 15))
1482 case X86_VENDOR_INTEL
:
1483 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1484 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1491 if (!cpu_has_apic
) {
1493 * Over-ride BIOS and try to enable the local APIC only if
1494 * "lapic" specified.
1496 if (!force_enable_local_apic
) {
1497 pr_info("Local APIC disabled by BIOS -- "
1498 "you can enable it with \"lapic\"\n");
1502 * Some BIOSes disable the local APIC in the APIC_BASE
1503 * MSR. This can only be done in software for Intel P6 or later
1504 * and AMD K7 (Model > 1) or later.
1506 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1507 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1508 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1509 l
&= ~MSR_IA32_APICBASE_BASE
;
1510 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1511 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1512 enabled_via_apicbase
= 1;
1516 * The APIC feature bit should now be enabled
1519 features
= cpuid_edx(1);
1520 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1521 pr_warning("Could not enable APIC!\n");
1524 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1525 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1527 /* The BIOS may have set up the APIC at some other address */
1528 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1529 if (l
& MSR_IA32_APICBASE_ENABLE
)
1530 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1532 pr_info("Found and enabled local APIC!\n");
1539 pr_info("No local APIC present or hardware disabled\n");
1544 #ifdef CONFIG_X86_64
1545 void __init
early_init_lapic_mapping(void)
1548 * If no local APIC can be found then go out
1549 * : it means there is no mpatable and MADT
1551 if (!smp_found_config
)
1554 set_fixmap_nocache(FIX_APIC_BASE
, mp_lapic_addr
);
1555 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1556 APIC_BASE
, mp_lapic_addr
);
1559 * Fetch the APIC ID of the BSP in case we have a
1560 * default configuration (or the MP table is broken).
1562 boot_cpu_physical_apicid
= read_apic_id();
1567 * init_apic_mappings - initialize APIC mappings
1569 void __init
init_apic_mappings(void)
1571 unsigned int new_apicid
;
1574 boot_cpu_physical_apicid
= read_apic_id();
1578 /* If no local APIC can be found return early */
1579 if (!smp_found_config
&& detect_init_APIC()) {
1580 /* lets NOP'ify apic operations */
1581 pr_info("APIC: disable apic facility\n");
1584 apic_phys
= mp_lapic_addr
;
1587 * acpi lapic path already maps that address in
1588 * acpi_register_lapic_address()
1591 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1593 apic_printk(APIC_VERBOSE
, "mapped APIC to %08lx (%08lx)\n",
1594 APIC_BASE
, apic_phys
);
1598 * Fetch the APIC ID of the BSP in case we have a
1599 * default configuration (or the MP table is broken).
1601 new_apicid
= read_apic_id();
1602 if (boot_cpu_physical_apicid
!= new_apicid
) {
1603 boot_cpu_physical_apicid
= new_apicid
;
1605 * yeah -- we lie about apic_version
1606 * in case if apic was disabled via boot option
1607 * but it's not a problem for SMP compiled kernel
1608 * since smp_sanity_check is prepared for such a case
1609 * and disable smp mode
1611 apic_version
[new_apicid
] =
1612 GET_APIC_VERSION(apic_read(APIC_LVR
));
1617 * This initializes the IO-APIC and APIC hardware if this is
1620 int apic_version
[MAX_APICS
];
1622 int __init
APIC_init_uniprocessor(void)
1625 pr_info("Apic disabled\n");
1628 #ifdef CONFIG_X86_64
1629 if (!cpu_has_apic
) {
1631 pr_info("Apic disabled by BIOS\n");
1635 if (!smp_found_config
&& !cpu_has_apic
)
1639 * Complain if the BIOS pretends there is one.
1641 if (!cpu_has_apic
&&
1642 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1643 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1644 boot_cpu_physical_apicid
);
1650 #ifdef CONFIG_X86_64
1651 default_setup_apic_routing();
1654 verify_local_APIC();
1657 #ifdef CONFIG_X86_64
1658 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1661 * Hack: In case of kdump, after a crash, kernel might be booting
1662 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1663 * might be zero if read from MP tables. Get it from LAPIC.
1665 # ifdef CONFIG_CRASH_DUMP
1666 boot_cpu_physical_apicid
= read_apic_id();
1669 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1672 #ifdef CONFIG_X86_IO_APIC
1674 * Now enable IO-APICs, actually call clear_IO_APIC
1675 * We need clear_IO_APIC before enabling error vector
1677 if (!skip_ioapic_setup
&& nr_ioapics
)
1681 end_local_APIC_setup();
1683 #ifdef CONFIG_X86_IO_APIC
1684 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1688 localise_nmi_watchdog();
1691 localise_nmi_watchdog();
1694 x86_init
.timers
.setup_percpu_clockev();
1695 #ifdef CONFIG_X86_64
1696 check_nmi_watchdog();
1703 * Local APIC interrupts
1707 * This interrupt should _never_ happen with our APIC/SMP architecture
1709 void smp_spurious_interrupt(struct pt_regs
*regs
)
1716 * Check if this really is a spurious interrupt and ACK it
1717 * if it is a vectored one. Just in case...
1718 * Spurious interrupts should not be ACKed.
1720 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1721 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1724 inc_irq_stat(irq_spurious_count
);
1726 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1727 pr_info("spurious APIC interrupt on CPU#%d, "
1728 "should never happen.\n", smp_processor_id());
1733 * This interrupt should never happen with our APIC/SMP architecture
1735 void smp_error_interrupt(struct pt_regs
*regs
)
1741 /* First tickle the hardware, only then report what went on. -- REW */
1742 v
= apic_read(APIC_ESR
);
1743 apic_write(APIC_ESR
, 0);
1744 v1
= apic_read(APIC_ESR
);
1746 atomic_inc(&irq_err_count
);
1749 * Here is what the APIC error bits mean:
1751 * 1: Receive CS error
1752 * 2: Send accept error
1753 * 3: Receive accept error
1755 * 5: Send illegal vector
1756 * 6: Received illegal vector
1757 * 7: Illegal register address
1759 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1760 smp_processor_id(), v
, v1
);
1765 * connect_bsp_APIC - attach the APIC to the interrupt system
1767 void __init
connect_bsp_APIC(void)
1769 #ifdef CONFIG_X86_32
1772 * Do not trust the local APIC being empty at bootup.
1776 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1777 * local APIC to INT and NMI lines.
1779 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1780 "enabling APIC mode.\n");
1784 if (apic
->enable_apic_mode
)
1785 apic
->enable_apic_mode();
1789 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1790 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1792 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1795 void disconnect_bsp_APIC(int virt_wire_setup
)
1799 #ifdef CONFIG_X86_32
1802 * Put the board back into PIC mode (has an effect only on
1803 * certain older boards). Note that APIC interrupts, including
1804 * IPIs, won't work beyond this point! The only exception are
1807 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1808 "entering PIC mode.\n");
1814 /* Go back to Virtual Wire compatibility mode */
1816 /* For the spurious interrupt use vector F, and enable it */
1817 value
= apic_read(APIC_SPIV
);
1818 value
&= ~APIC_VECTOR_MASK
;
1819 value
|= APIC_SPIV_APIC_ENABLED
;
1821 apic_write(APIC_SPIV
, value
);
1823 if (!virt_wire_setup
) {
1825 * For LVT0 make it edge triggered, active high,
1826 * external and enabled
1828 value
= apic_read(APIC_LVT0
);
1829 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1830 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1831 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1832 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1833 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1834 apic_write(APIC_LVT0
, value
);
1837 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1841 * For LVT1 make it edge triggered, active high,
1844 value
= apic_read(APIC_LVT1
);
1845 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1846 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1847 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1848 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1849 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1850 apic_write(APIC_LVT1
, value
);
1853 void __cpuinit
generic_processor_info(int apicid
, int version
)
1860 if (version
== 0x0) {
1861 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1862 "fixing up to 0x10. (tell your hw vendor)\n",
1866 apic_version
[apicid
] = version
;
1868 if (num_processors
>= nr_cpu_ids
) {
1869 int max
= nr_cpu_ids
;
1870 int thiscpu
= max
+ disabled_cpus
;
1873 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1874 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
1881 cpu
= cpumask_next_zero(-1, cpu_present_mask
);
1883 if (version
!= apic_version
[boot_cpu_physical_apicid
])
1885 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1886 apic_version
[boot_cpu_physical_apicid
], cpu
, version
);
1888 physid_set(apicid
, phys_cpu_present_map
);
1889 if (apicid
== boot_cpu_physical_apicid
) {
1891 * x86_bios_cpu_apicid is required to have processors listed
1892 * in same order as logical cpu numbers. Hence the first
1893 * entry is BSP, and so on.
1897 if (apicid
> max_physical_apicid
)
1898 max_physical_apicid
= apicid
;
1900 #ifdef CONFIG_X86_32
1901 switch (boot_cpu_data
.x86_vendor
) {
1902 case X86_VENDOR_INTEL
:
1903 if (num_processors
> 8)
1906 case X86_VENDOR_AMD
:
1907 if (max_physical_apicid
>= 8)
1912 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1913 early_per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1914 early_per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1917 set_cpu_possible(cpu
, true);
1918 set_cpu_present(cpu
, true);
1921 int hard_smp_processor_id(void)
1923 return read_apic_id();
1926 void default_init_apic_ldr(void)
1930 apic_write(APIC_DFR
, APIC_DFR_VALUE
);
1931 val
= apic_read(APIC_LDR
) & ~APIC_LDR_MASK
;
1932 val
|= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1933 apic_write(APIC_LDR
, val
);
1936 #ifdef CONFIG_X86_32
1937 int default_apicid_to_node(int logical_apicid
)
1940 return apicid_2_node
[hard_smp_processor_id()];
1954 * 'active' is true if the local APIC was enabled by us and
1955 * not the BIOS; this signifies that we are also responsible
1956 * for disabling it before entering apm/acpi suspend
1959 /* r/w apic fields */
1960 unsigned int apic_id
;
1961 unsigned int apic_taskpri
;
1962 unsigned int apic_ldr
;
1963 unsigned int apic_dfr
;
1964 unsigned int apic_spiv
;
1965 unsigned int apic_lvtt
;
1966 unsigned int apic_lvtpc
;
1967 unsigned int apic_lvt0
;
1968 unsigned int apic_lvt1
;
1969 unsigned int apic_lvterr
;
1970 unsigned int apic_tmict
;
1971 unsigned int apic_tdcr
;
1972 unsigned int apic_thmr
;
1975 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1977 unsigned long flags
;
1980 if (!apic_pm_state
.active
)
1983 maxlvt
= lapic_get_maxlvt();
1985 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1986 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1987 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1988 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1989 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1990 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1992 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1993 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1994 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1995 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1996 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1997 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1998 #ifdef CONFIG_X86_THERMAL_VECTOR
2000 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
2003 local_irq_save(flags
);
2004 disable_local_APIC();
2006 if (intr_remapping_enabled
)
2007 disable_intr_remapping();
2009 local_irq_restore(flags
);
2013 static int lapic_resume(struct sys_device
*dev
)
2016 unsigned long flags
;
2019 struct IO_APIC_route_entry
**ioapic_entries
= NULL
;
2021 if (!apic_pm_state
.active
)
2024 local_irq_save(flags
);
2025 if (intr_remapping_enabled
) {
2026 ioapic_entries
= alloc_ioapic_entries();
2027 if (!ioapic_entries
) {
2028 WARN(1, "Alloc ioapic_entries in lapic resume failed.");
2033 ret
= save_IO_APIC_setup(ioapic_entries
);
2035 WARN(1, "Saving IO-APIC state failed: %d\n", ret
);
2036 free_ioapic_entries(ioapic_entries
);
2040 mask_IO_APIC_setup(ioapic_entries
);
2048 * Make sure the APICBASE points to the right address
2050 * FIXME! This will be wrong if we ever support suspend on
2051 * SMP! We'll need to do this as part of the CPU restore!
2053 rdmsr(MSR_IA32_APICBASE
, l
, h
);
2054 l
&= ~MSR_IA32_APICBASE_BASE
;
2055 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
2056 wrmsr(MSR_IA32_APICBASE
, l
, h
);
2059 maxlvt
= lapic_get_maxlvt();
2060 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
2061 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
2062 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
2063 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2064 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2065 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2066 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2067 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2068 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2070 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2073 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2074 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2075 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2076 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2077 apic_write(APIC_ESR
, 0);
2078 apic_read(APIC_ESR
);
2079 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2080 apic_write(APIC_ESR
, 0);
2081 apic_read(APIC_ESR
);
2083 if (intr_remapping_enabled
) {
2084 reenable_intr_remapping(x2apic_mode
);
2086 restore_IO_APIC_setup(ioapic_entries
);
2087 free_ioapic_entries(ioapic_entries
);
2090 local_irq_restore(flags
);
2096 * This device has no shutdown method - fully functioning local APICs
2097 * are needed on every CPU up until machine_halt/restart/poweroff.
2100 static struct sysdev_class lapic_sysclass
= {
2102 .resume
= lapic_resume
,
2103 .suspend
= lapic_suspend
,
2106 static struct sys_device device_lapic
= {
2108 .cls
= &lapic_sysclass
,
2111 static void __cpuinit
apic_pm_activate(void)
2113 apic_pm_state
.active
= 1;
2116 static int __init
init_lapic_sysfs(void)
2122 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2124 error
= sysdev_class_register(&lapic_sysclass
);
2126 error
= sysdev_register(&device_lapic
);
2130 /* local apic needs to resume before other devices access its registers. */
2131 core_initcall(init_lapic_sysfs
);
2133 #else /* CONFIG_PM */
2135 static void apic_pm_activate(void) { }
2137 #endif /* CONFIG_PM */
2139 #ifdef CONFIG_X86_64
2141 static int __cpuinit
apic_cluster_num(void)
2143 int i
, clusters
, zeros
;
2145 u16
*bios_cpu_apicid
;
2146 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2148 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2149 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2151 for (i
= 0; i
< nr_cpu_ids
; i
++) {
2152 /* are we being called early in kernel startup? */
2153 if (bios_cpu_apicid
) {
2154 id
= bios_cpu_apicid
[i
];
2155 } else if (i
< nr_cpu_ids
) {
2157 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2163 if (id
!= BAD_APICID
)
2164 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2167 /* Problem: Partially populated chassis may not have CPUs in some of
2168 * the APIC clusters they have been allocated. Only present CPUs have
2169 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2170 * Since clusters are allocated sequentially, count zeros only if
2171 * they are bounded by ones.
2175 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2176 if (test_bit(i
, clustermap
)) {
2177 clusters
+= 1 + zeros
;
2186 static int __cpuinitdata multi_checked
;
2187 static int __cpuinitdata multi
;
2189 static int __cpuinit
set_multi(const struct dmi_system_id
*d
)
2193 pr_info("APIC: %s detected, Multi Chassis\n", d
->ident
);
2198 static const __cpuinitconst
struct dmi_system_id multi_dmi_table
[] = {
2200 .callback
= set_multi
,
2201 .ident
= "IBM System Summit2",
2203 DMI_MATCH(DMI_SYS_VENDOR
, "IBM"),
2204 DMI_MATCH(DMI_PRODUCT_NAME
, "Summit2"),
2210 static void __cpuinit
dmi_check_multi(void)
2215 dmi_check_system(multi_dmi_table
);
2220 * apic_is_clustered_box() -- Check if we can expect good TSC
2222 * Thus far, the major user of this is IBM's Summit2 series:
2223 * Clustered boxes may have unsynced TSC problems if they are
2225 * Use DMI to check them
2227 __cpuinit
int apic_is_clustered_box(void)
2237 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2238 * not guaranteed to be synced between boards
2240 if (apic_cluster_num() > 1)
2248 * APIC command line parameters
2250 static int __init
setup_disableapic(char *arg
)
2253 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2256 early_param("disableapic", setup_disableapic
);
2258 /* same as disableapic, for compatibility */
2259 static int __init
setup_nolapic(char *arg
)
2261 return setup_disableapic(arg
);
2263 early_param("nolapic", setup_nolapic
);
2265 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2267 local_apic_timer_c2_ok
= 1;
2270 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2272 static int __init
parse_disable_apic_timer(char *arg
)
2274 disable_apic_timer
= 1;
2277 early_param("noapictimer", parse_disable_apic_timer
);
2279 static int __init
parse_nolapic_timer(char *arg
)
2281 disable_apic_timer
= 1;
2284 early_param("nolapic_timer", parse_nolapic_timer
);
2286 static int __init
apic_set_verbosity(char *arg
)
2289 #ifdef CONFIG_X86_64
2290 skip_ioapic_setup
= 0;
2296 if (strcmp("debug", arg
) == 0)
2297 apic_verbosity
= APIC_DEBUG
;
2298 else if (strcmp("verbose", arg
) == 0)
2299 apic_verbosity
= APIC_VERBOSE
;
2301 pr_warning("APIC Verbosity level %s not recognised"
2302 " use apic=verbose or apic=debug\n", arg
);
2308 early_param("apic", apic_set_verbosity
);
2310 static int __init
lapic_insert_resource(void)
2315 /* Put local APIC into the resource map. */
2316 lapic_resource
.start
= apic_phys
;
2317 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2318 insert_resource(&iomem_resource
, &lapic_resource
);
2324 * need call insert after e820_reserve_resources()
2325 * that is using request_resource
2327 late_initcall(lapic_insert_resource
);