2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2011 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mdio.h>
36 #include <linux/mii.h>
37 #include <linux/phy.h>
38 #include <linux/brcmphy.h>
39 #include <linux/if_vlan.h>
41 #include <linux/tcp.h>
42 #include <linux/workqueue.h>
43 #include <linux/prefetch.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/firmware.h>
47 #include <net/checksum.h>
50 #include <asm/system.h>
52 #include <asm/byteorder.h>
53 #include <linux/uaccess.h>
56 #include <asm/idprom.h>
65 #define DRV_MODULE_NAME "tg3"
67 #define TG3_MIN_NUM 117
68 #define DRV_MODULE_VERSION \
69 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
70 #define DRV_MODULE_RELDATE "January 25, 2011"
72 #define TG3_DEF_MAC_MODE 0
73 #define TG3_DEF_RX_MODE 0
74 #define TG3_DEF_TX_MODE 0
75 #define TG3_DEF_MSG_ENABLE \
85 /* length of time before we decide the hardware is borked,
86 * and dev->tx_timeout() should be called to fix the problem
88 #define TG3_TX_TIMEOUT (5 * HZ)
90 /* hardware minimum and maximum for a single frame's data payload */
91 #define TG3_MIN_MTU 60
92 #define TG3_MAX_MTU(tp) \
93 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
95 /* These numbers seem to be hard coded in the NIC firmware somehow.
96 * You can't change the ring sizes, but you can change where you place
97 * them in the NIC onboard memory.
99 #define TG3_RX_STD_RING_SIZE(tp) \
100 ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
101 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JMB_RING_SIZE(tp) \
104 ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
105 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
106 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
107 #define TG3_RSS_INDIR_TBL_SIZE 128
109 /* Do not place this n-ring entries value into the tp struct itself,
110 * we really want to expose these constants to GCC so that modulo et
111 * al. operations are done with shifts and masks instead of with
112 * hw multiply/modulo instructions. Another solution would be to
113 * replace things like '% foo' with '& (foo - 1)'.
116 #define TG3_TX_RING_SIZE 512
117 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119 #define TG3_RX_STD_RING_BYTES(tp) \
120 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
121 #define TG3_RX_JMB_RING_BYTES(tp) \
122 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
123 #define TG3_RX_RCB_RING_BYTES(tp) \
124 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
125 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129 #define TG3_DMA_BYTE_ENAB 64
131 #define TG3_RX_STD_DMA_SZ 1536
132 #define TG3_RX_JMB_DMA_SZ 9046
134 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
137 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
139 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
140 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
142 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
143 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
145 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
146 * that are at least dword aligned when used in PCIX mode. The driver
147 * works around this bug by double copying the packet. This workaround
148 * is built into the normal double copy length check for efficiency.
150 * However, the double copy is only necessary on those architectures
151 * where unaligned memory accesses are inefficient. For those architectures
152 * where unaligned memory accesses incur little penalty, we can reintegrate
153 * the 5701 in the normal rx path. Doing so saves a device structure
154 * dereference by hardcoding the double copy threshold in place.
156 #define TG3_RX_COPY_THRESHOLD 256
157 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
158 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
160 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
163 /* minimum number of free TX descriptors required to wake up TX process */
164 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
166 #define TG3_RAW_IP_ALIGN 2
168 /* number of ETHTOOL_GSTATS u64's */
169 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
171 #define TG3_NUM_TEST 6
173 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
175 #define FIRMWARE_TG3 "tigon/tg3.bin"
176 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
177 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
179 static char version
[] __devinitdata
=
180 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")";
182 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
183 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
184 MODULE_LICENSE("GPL");
185 MODULE_VERSION(DRV_MODULE_VERSION
);
186 MODULE_FIRMWARE(FIRMWARE_TG3
);
187 MODULE_FIRMWARE(FIRMWARE_TG3TSO
);
188 MODULE_FIRMWARE(FIRMWARE_TG3TSO5
);
190 static int tg3_debug
= -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
191 module_param(tg3_debug
, int, 0);
192 MODULE_PARM_DESC(tg3_debug
, "Tigon3 bitmapped debugging message enable value");
194 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl
) = {
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5700
)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5701
)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702
)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703
)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704
)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702FE
)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705
)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705_2
)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M
)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M_2
)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702X
)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703X
)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S
)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702A3
)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703A3
)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5782
)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5788
)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5789
)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901
)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901_2
)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S_2
)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705F
)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5721
)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5722
)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751
)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751M
)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751F
)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752
)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752M
)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753
)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753M
)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753F
)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754
)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754M
)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755
)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755M
)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5756
)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5786
)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787
)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787M
)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787F
)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714
)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714S
)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715
)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715S
)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780
)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780S
)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5781
)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906
)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906M
)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5784
)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5764
)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5723
)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761
)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761E
)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761S
)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761SE
)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5785_G
)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5785_F
)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57780
)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57760
)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57790
)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57788
)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5717
)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5718
)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57781
)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57785
)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57761
)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57765
)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57791
)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57795
)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5719
)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5720
)},
268 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9DXX
)},
269 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9MXX
)},
270 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1000
)},
271 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1001
)},
272 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1003
)},
273 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC9100
)},
274 {PCI_DEVICE(PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_TIGON3
)},
278 MODULE_DEVICE_TABLE(pci
, tg3_pci_tbl
);
280 static const struct {
281 const char string
[ETH_GSTRING_LEN
];
282 } ethtool_stats_keys
[TG3_NUM_STATS
] = {
285 { "rx_ucast_packets" },
286 { "rx_mcast_packets" },
287 { "rx_bcast_packets" },
289 { "rx_align_errors" },
290 { "rx_xon_pause_rcvd" },
291 { "rx_xoff_pause_rcvd" },
292 { "rx_mac_ctrl_rcvd" },
293 { "rx_xoff_entered" },
294 { "rx_frame_too_long_errors" },
296 { "rx_undersize_packets" },
297 { "rx_in_length_errors" },
298 { "rx_out_length_errors" },
299 { "rx_64_or_less_octet_packets" },
300 { "rx_65_to_127_octet_packets" },
301 { "rx_128_to_255_octet_packets" },
302 { "rx_256_to_511_octet_packets" },
303 { "rx_512_to_1023_octet_packets" },
304 { "rx_1024_to_1522_octet_packets" },
305 { "rx_1523_to_2047_octet_packets" },
306 { "rx_2048_to_4095_octet_packets" },
307 { "rx_4096_to_8191_octet_packets" },
308 { "rx_8192_to_9022_octet_packets" },
315 { "tx_flow_control" },
317 { "tx_single_collisions" },
318 { "tx_mult_collisions" },
320 { "tx_excessive_collisions" },
321 { "tx_late_collisions" },
322 { "tx_collide_2times" },
323 { "tx_collide_3times" },
324 { "tx_collide_4times" },
325 { "tx_collide_5times" },
326 { "tx_collide_6times" },
327 { "tx_collide_7times" },
328 { "tx_collide_8times" },
329 { "tx_collide_9times" },
330 { "tx_collide_10times" },
331 { "tx_collide_11times" },
332 { "tx_collide_12times" },
333 { "tx_collide_13times" },
334 { "tx_collide_14times" },
335 { "tx_collide_15times" },
336 { "tx_ucast_packets" },
337 { "tx_mcast_packets" },
338 { "tx_bcast_packets" },
339 { "tx_carrier_sense_errors" },
343 { "dma_writeq_full" },
344 { "dma_write_prioq_full" },
348 { "rx_threshold_hit" },
350 { "dma_readq_full" },
351 { "dma_read_prioq_full" },
352 { "tx_comp_queue_full" },
354 { "ring_set_send_prod_index" },
355 { "ring_status_update" },
357 { "nic_avoided_irqs" },
358 { "nic_tx_threshold_hit" }
361 static const struct {
362 const char string
[ETH_GSTRING_LEN
];
363 } ethtool_test_keys
[TG3_NUM_TEST
] = {
364 { "nvram test (online) " },
365 { "link test (online) " },
366 { "register test (offline)" },
367 { "memory test (offline)" },
368 { "loopback test (offline)" },
369 { "interrupt test (offline)" },
372 static void tg3_write32(struct tg3
*tp
, u32 off
, u32 val
)
374 writel(val
, tp
->regs
+ off
);
377 static u32
tg3_read32(struct tg3
*tp
, u32 off
)
379 return readl(tp
->regs
+ off
);
382 static void tg3_ape_write32(struct tg3
*tp
, u32 off
, u32 val
)
384 writel(val
, tp
->aperegs
+ off
);
387 static u32
tg3_ape_read32(struct tg3
*tp
, u32 off
)
389 return readl(tp
->aperegs
+ off
);
392 static void tg3_write_indirect_reg32(struct tg3
*tp
, u32 off
, u32 val
)
396 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
397 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
398 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
399 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
402 static void tg3_write_flush_reg32(struct tg3
*tp
, u32 off
, u32 val
)
404 writel(val
, tp
->regs
+ off
);
405 readl(tp
->regs
+ off
);
408 static u32
tg3_read_indirect_reg32(struct tg3
*tp
, u32 off
)
413 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
414 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
415 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
416 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
420 static void tg3_write_indirect_mbox(struct tg3
*tp
, u32 off
, u32 val
)
424 if (off
== (MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
)) {
425 pci_write_config_dword(tp
->pdev
, TG3PCI_RCV_RET_RING_CON_IDX
+
426 TG3_64BIT_REG_LOW
, val
);
429 if (off
== TG3_RX_STD_PROD_IDX_REG
) {
430 pci_write_config_dword(tp
->pdev
, TG3PCI_STD_RING_PROD_IDX
+
431 TG3_64BIT_REG_LOW
, val
);
435 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
436 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
437 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
438 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
440 /* In indirect mode when disabling interrupts, we also need
441 * to clear the interrupt bit in the GRC local ctrl register.
443 if ((off
== (MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
)) &&
445 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_LOCAL_CTRL
,
446 tp
->grc_local_ctrl
|GRC_LCLCTRL_CLEARINT
);
450 static u32
tg3_read_indirect_mbox(struct tg3
*tp
, u32 off
)
455 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
456 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
457 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
458 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
462 /* usec_wait specifies the wait time in usec when writing to certain registers
463 * where it is unsafe to read back the register without some delay.
464 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
465 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
467 static void _tw32_flush(struct tg3
*tp
, u32 off
, u32 val
, u32 usec_wait
)
469 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) ||
470 (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
471 /* Non-posted methods */
472 tp
->write32(tp
, off
, val
);
475 tg3_write32(tp
, off
, val
);
480 /* Wait again after the read for the posted method to guarantee that
481 * the wait time is met.
487 static inline void tw32_mailbox_flush(struct tg3
*tp
, u32 off
, u32 val
)
489 tp
->write32_mbox(tp
, off
, val
);
490 if (!(tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) &&
491 !(tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
492 tp
->read32_mbox(tp
, off
);
495 static void tg3_write32_tx_mbox(struct tg3
*tp
, u32 off
, u32 val
)
497 void __iomem
*mbox
= tp
->regs
+ off
;
499 if (tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
)
501 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
505 static u32
tg3_read32_mbox_5906(struct tg3
*tp
, u32 off
)
507 return readl(tp
->regs
+ off
+ GRCMBOX_BASE
);
510 static void tg3_write32_mbox_5906(struct tg3
*tp
, u32 off
, u32 val
)
512 writel(val
, tp
->regs
+ off
+ GRCMBOX_BASE
);
515 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
516 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
517 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
518 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
519 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
521 #define tw32(reg, val) tp->write32(tp, reg, val)
522 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
523 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
524 #define tr32(reg) tp->read32(tp, reg)
526 static void tg3_write_mem(struct tg3
*tp
, u32 off
, u32 val
)
530 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
531 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
))
534 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
535 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
536 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
537 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
539 /* Always leave this as zero. */
540 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
542 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
543 tw32_f(TG3PCI_MEM_WIN_DATA
, val
);
545 /* Always leave this as zero. */
546 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
548 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
551 static void tg3_read_mem(struct tg3
*tp
, u32 off
, u32
*val
)
555 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
556 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
)) {
561 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
562 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
563 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
564 pci_read_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
566 /* Always leave this as zero. */
567 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
569 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
570 *val
= tr32(TG3PCI_MEM_WIN_DATA
);
572 /* Always leave this as zero. */
573 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
575 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
578 static void tg3_ape_lock_init(struct tg3
*tp
)
583 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
584 regbase
= TG3_APE_LOCK_GRANT
;
586 regbase
= TG3_APE_PER_LOCK_GRANT
;
588 /* Make sure the driver hasn't any stale locks. */
589 for (i
= 0; i
< 8; i
++)
590 tg3_ape_write32(tp
, regbase
+ 4 * i
, APE_LOCK_GRANT_DRIVER
);
593 static int tg3_ape_lock(struct tg3
*tp
, int locknum
)
597 u32 status
, req
, gnt
;
599 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
603 case TG3_APE_LOCK_GRC
:
604 case TG3_APE_LOCK_MEM
:
610 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
) {
611 req
= TG3_APE_LOCK_REQ
;
612 gnt
= TG3_APE_LOCK_GRANT
;
614 req
= TG3_APE_PER_LOCK_REQ
;
615 gnt
= TG3_APE_PER_LOCK_GRANT
;
620 tg3_ape_write32(tp
, req
+ off
, APE_LOCK_REQ_DRIVER
);
622 /* Wait for up to 1 millisecond to acquire lock. */
623 for (i
= 0; i
< 100; i
++) {
624 status
= tg3_ape_read32(tp
, gnt
+ off
);
625 if (status
== APE_LOCK_GRANT_DRIVER
)
630 if (status
!= APE_LOCK_GRANT_DRIVER
) {
631 /* Revoke the lock request. */
632 tg3_ape_write32(tp
, gnt
+ off
,
633 APE_LOCK_GRANT_DRIVER
);
641 static void tg3_ape_unlock(struct tg3
*tp
, int locknum
)
645 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
649 case TG3_APE_LOCK_GRC
:
650 case TG3_APE_LOCK_MEM
:
656 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
657 gnt
= TG3_APE_LOCK_GRANT
;
659 gnt
= TG3_APE_PER_LOCK_GRANT
;
661 tg3_ape_write32(tp
, gnt
+ 4 * locknum
, APE_LOCK_GRANT_DRIVER
);
664 static void tg3_disable_ints(struct tg3
*tp
)
668 tw32(TG3PCI_MISC_HOST_CTRL
,
669 (tp
->misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
));
670 for (i
= 0; i
< tp
->irq_max
; i
++)
671 tw32_mailbox_f(tp
->napi
[i
].int_mbox
, 0x00000001);
674 static void tg3_enable_ints(struct tg3
*tp
)
681 tw32(TG3PCI_MISC_HOST_CTRL
,
682 (tp
->misc_host_ctrl
& ~MISC_HOST_CTRL_MASK_PCI_INT
));
684 tp
->coal_now
= tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
;
685 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
686 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
688 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
689 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
690 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
692 tp
->coal_now
|= tnapi
->coal_now
;
695 /* Force an initial interrupt */
696 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
697 (tp
->napi
[0].hw_status
->status
& SD_STATUS_UPDATED
))
698 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
700 tw32(HOSTCC_MODE
, tp
->coal_now
);
702 tp
->coal_now
&= ~(tp
->napi
[0].coal_now
| tp
->napi
[1].coal_now
);
705 static inline unsigned int tg3_has_work(struct tg3_napi
*tnapi
)
707 struct tg3
*tp
= tnapi
->tp
;
708 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
709 unsigned int work_exists
= 0;
711 /* check for phy events */
712 if (!(tp
->tg3_flags
&
713 (TG3_FLAG_USE_LINKCHG_REG
|
714 TG3_FLAG_POLL_SERDES
))) {
715 if (sblk
->status
& SD_STATUS_LINK_CHG
)
718 /* check for RX/TX work to do */
719 if (sblk
->idx
[0].tx_consumer
!= tnapi
->tx_cons
||
720 *(tnapi
->rx_rcb_prod_idx
) != tnapi
->rx_rcb_ptr
)
727 * similar to tg3_enable_ints, but it accurately determines whether there
728 * is new work pending and can return without flushing the PIO write
729 * which reenables interrupts
731 static void tg3_int_reenable(struct tg3_napi
*tnapi
)
733 struct tg3
*tp
= tnapi
->tp
;
735 tw32_mailbox(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
738 /* When doing tagged status, this work check is unnecessary.
739 * The last_tag we write above tells the chip which piece of
740 * work we've completed.
742 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
744 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
745 HOSTCC_MODE_ENABLE
| tnapi
->coal_now
);
748 static void tg3_switch_clocks(struct tg3
*tp
)
753 if ((tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
754 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
757 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
);
759 orig_clock_ctrl
= clock_ctrl
;
760 clock_ctrl
&= (CLOCK_CTRL_FORCE_CLKRUN
|
761 CLOCK_CTRL_CLKRUN_OENABLE
|
763 tp
->pci_clock_ctrl
= clock_ctrl
;
765 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
766 if (orig_clock_ctrl
& CLOCK_CTRL_625_CORE
) {
767 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
768 clock_ctrl
| CLOCK_CTRL_625_CORE
, 40);
770 } else if ((orig_clock_ctrl
& CLOCK_CTRL_44MHZ_CORE
) != 0) {
771 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
773 (CLOCK_CTRL_44MHZ_CORE
| CLOCK_CTRL_ALTCLK
),
775 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
776 clock_ctrl
| (CLOCK_CTRL_ALTCLK
),
779 tw32_wait_f(TG3PCI_CLOCK_CTRL
, clock_ctrl
, 40);
782 #define PHY_BUSY_LOOPS 5000
784 static int tg3_readphy(struct tg3
*tp
, int reg
, u32
*val
)
790 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
792 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
798 frame_val
= ((tp
->phy_addr
<< MI_COM_PHY_ADDR_SHIFT
) &
799 MI_COM_PHY_ADDR_MASK
);
800 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
801 MI_COM_REG_ADDR_MASK
);
802 frame_val
|= (MI_COM_CMD_READ
| MI_COM_START
);
804 tw32_f(MAC_MI_COM
, frame_val
);
806 loops
= PHY_BUSY_LOOPS
;
809 frame_val
= tr32(MAC_MI_COM
);
811 if ((frame_val
& MI_COM_BUSY
) == 0) {
813 frame_val
= tr32(MAC_MI_COM
);
821 *val
= frame_val
& MI_COM_DATA_MASK
;
825 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
826 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
833 static int tg3_writephy(struct tg3
*tp
, int reg
, u32 val
)
839 if ((tp
->phy_flags
& TG3_PHYFLG_IS_FET
) &&
840 (reg
== MII_TG3_CTRL
|| reg
== MII_TG3_AUX_CTRL
))
843 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
845 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
849 frame_val
= ((tp
->phy_addr
<< MI_COM_PHY_ADDR_SHIFT
) &
850 MI_COM_PHY_ADDR_MASK
);
851 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
852 MI_COM_REG_ADDR_MASK
);
853 frame_val
|= (val
& MI_COM_DATA_MASK
);
854 frame_val
|= (MI_COM_CMD_WRITE
| MI_COM_START
);
856 tw32_f(MAC_MI_COM
, frame_val
);
858 loops
= PHY_BUSY_LOOPS
;
861 frame_val
= tr32(MAC_MI_COM
);
862 if ((frame_val
& MI_COM_BUSY
) == 0) {
864 frame_val
= tr32(MAC_MI_COM
);
874 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
875 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
882 static int tg3_bmcr_reset(struct tg3
*tp
)
887 /* OK, reset it, and poll the BMCR_RESET bit until it
888 * clears or we time out.
890 phy_control
= BMCR_RESET
;
891 err
= tg3_writephy(tp
, MII_BMCR
, phy_control
);
897 err
= tg3_readphy(tp
, MII_BMCR
, &phy_control
);
901 if ((phy_control
& BMCR_RESET
) == 0) {
913 static int tg3_mdio_read(struct mii_bus
*bp
, int mii_id
, int reg
)
915 struct tg3
*tp
= bp
->priv
;
918 spin_lock_bh(&tp
->lock
);
920 if (tg3_readphy(tp
, reg
, &val
))
923 spin_unlock_bh(&tp
->lock
);
928 static int tg3_mdio_write(struct mii_bus
*bp
, int mii_id
, int reg
, u16 val
)
930 struct tg3
*tp
= bp
->priv
;
933 spin_lock_bh(&tp
->lock
);
935 if (tg3_writephy(tp
, reg
, val
))
938 spin_unlock_bh(&tp
->lock
);
943 static int tg3_mdio_reset(struct mii_bus
*bp
)
948 static void tg3_mdio_config_5785(struct tg3
*tp
)
951 struct phy_device
*phydev
;
953 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
954 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
955 case PHY_ID_BCM50610
:
956 case PHY_ID_BCM50610M
:
957 val
= MAC_PHYCFG2_50610_LED_MODES
;
959 case PHY_ID_BCMAC131
:
960 val
= MAC_PHYCFG2_AC131_LED_MODES
;
962 case PHY_ID_RTL8211C
:
963 val
= MAC_PHYCFG2_RTL8211C_LED_MODES
;
965 case PHY_ID_RTL8201E
:
966 val
= MAC_PHYCFG2_RTL8201E_LED_MODES
;
972 if (phydev
->interface
!= PHY_INTERFACE_MODE_RGMII
) {
973 tw32(MAC_PHYCFG2
, val
);
975 val
= tr32(MAC_PHYCFG1
);
976 val
&= ~(MAC_PHYCFG1_RGMII_INT
|
977 MAC_PHYCFG1_RXCLK_TO_MASK
| MAC_PHYCFG1_TXCLK_TO_MASK
);
978 val
|= MAC_PHYCFG1_RXCLK_TIMEOUT
| MAC_PHYCFG1_TXCLK_TIMEOUT
;
979 tw32(MAC_PHYCFG1
, val
);
984 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
))
985 val
|= MAC_PHYCFG2_EMODE_MASK_MASK
|
986 MAC_PHYCFG2_FMODE_MASK_MASK
|
987 MAC_PHYCFG2_GMODE_MASK_MASK
|
988 MAC_PHYCFG2_ACT_MASK_MASK
|
989 MAC_PHYCFG2_QUAL_MASK_MASK
|
990 MAC_PHYCFG2_INBAND_ENABLE
;
992 tw32(MAC_PHYCFG2
, val
);
994 val
= tr32(MAC_PHYCFG1
);
995 val
&= ~(MAC_PHYCFG1_RXCLK_TO_MASK
| MAC_PHYCFG1_TXCLK_TO_MASK
|
996 MAC_PHYCFG1_RGMII_EXT_RX_DEC
| MAC_PHYCFG1_RGMII_SND_STAT_EN
);
997 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
)) {
998 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
999 val
|= MAC_PHYCFG1_RGMII_EXT_RX_DEC
;
1000 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1001 val
|= MAC_PHYCFG1_RGMII_SND_STAT_EN
;
1003 val
|= MAC_PHYCFG1_RXCLK_TIMEOUT
| MAC_PHYCFG1_TXCLK_TIMEOUT
|
1004 MAC_PHYCFG1_RGMII_INT
| MAC_PHYCFG1_TXC_DRV
;
1005 tw32(MAC_PHYCFG1
, val
);
1007 val
= tr32(MAC_EXT_RGMII_MODE
);
1008 val
&= ~(MAC_RGMII_MODE_RX_INT_B
|
1009 MAC_RGMII_MODE_RX_QUALITY
|
1010 MAC_RGMII_MODE_RX_ACTIVITY
|
1011 MAC_RGMII_MODE_RX_ENG_DET
|
1012 MAC_RGMII_MODE_TX_ENABLE
|
1013 MAC_RGMII_MODE_TX_LOWPWR
|
1014 MAC_RGMII_MODE_TX_RESET
);
1015 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
)) {
1016 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1017 val
|= MAC_RGMII_MODE_RX_INT_B
|
1018 MAC_RGMII_MODE_RX_QUALITY
|
1019 MAC_RGMII_MODE_RX_ACTIVITY
|
1020 MAC_RGMII_MODE_RX_ENG_DET
;
1021 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1022 val
|= MAC_RGMII_MODE_TX_ENABLE
|
1023 MAC_RGMII_MODE_TX_LOWPWR
|
1024 MAC_RGMII_MODE_TX_RESET
;
1026 tw32(MAC_EXT_RGMII_MODE
, val
);
1029 static void tg3_mdio_start(struct tg3
*tp
)
1031 tp
->mi_mode
&= ~MAC_MI_MODE_AUTO_POLL
;
1032 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
1035 if ((tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) &&
1036 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
1037 tg3_mdio_config_5785(tp
);
1040 static int tg3_mdio_init(struct tg3
*tp
)
1044 struct phy_device
*phydev
;
1046 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) {
1049 tp
->phy_addr
= PCI_FUNC(tp
->pdev
->devfn
) + 1;
1051 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5717_A0
)
1052 is_serdes
= tr32(SG_DIG_STATUS
) & SG_DIG_IS_SERDES
;
1054 is_serdes
= tr32(TG3_CPMU_PHY_STRAP
) &
1055 TG3_CPMU_PHY_STRAP_IS_SERDES
;
1059 tp
->phy_addr
= TG3_PHY_MII_ADDR
;
1063 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) ||
1064 (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
))
1067 tp
->mdio_bus
= mdiobus_alloc();
1068 if (tp
->mdio_bus
== NULL
)
1071 tp
->mdio_bus
->name
= "tg3 mdio bus";
1072 snprintf(tp
->mdio_bus
->id
, MII_BUS_ID_SIZE
, "%x",
1073 (tp
->pdev
->bus
->number
<< 8) | tp
->pdev
->devfn
);
1074 tp
->mdio_bus
->priv
= tp
;
1075 tp
->mdio_bus
->parent
= &tp
->pdev
->dev
;
1076 tp
->mdio_bus
->read
= &tg3_mdio_read
;
1077 tp
->mdio_bus
->write
= &tg3_mdio_write
;
1078 tp
->mdio_bus
->reset
= &tg3_mdio_reset
;
1079 tp
->mdio_bus
->phy_mask
= ~(1 << TG3_PHY_MII_ADDR
);
1080 tp
->mdio_bus
->irq
= &tp
->mdio_irq
[0];
1082 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1083 tp
->mdio_bus
->irq
[i
] = PHY_POLL
;
1085 /* The bus registration will look for all the PHYs on the mdio bus.
1086 * Unfortunately, it does not ensure the PHY is powered up before
1087 * accessing the PHY ID registers. A chip reset is the
1088 * quickest way to bring the device back to an operational state..
1090 if (tg3_readphy(tp
, MII_BMCR
, ®
) || (reg
& BMCR_PDOWN
))
1093 i
= mdiobus_register(tp
->mdio_bus
);
1095 dev_warn(&tp
->pdev
->dev
, "mdiobus_reg failed (0x%x)\n", i
);
1096 mdiobus_free(tp
->mdio_bus
);
1100 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1102 if (!phydev
|| !phydev
->drv
) {
1103 dev_warn(&tp
->pdev
->dev
, "No PHY devices\n");
1104 mdiobus_unregister(tp
->mdio_bus
);
1105 mdiobus_free(tp
->mdio_bus
);
1109 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
1110 case PHY_ID_BCM57780
:
1111 phydev
->interface
= PHY_INTERFACE_MODE_GMII
;
1112 phydev
->dev_flags
|= PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1114 case PHY_ID_BCM50610
:
1115 case PHY_ID_BCM50610M
:
1116 phydev
->dev_flags
|= PHY_BRCM_CLEAR_RGMII_MODE
|
1117 PHY_BRCM_RX_REFCLK_UNUSED
|
1118 PHY_BRCM_DIS_TXCRXC_NOENRGY
|
1119 PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1120 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
)
1121 phydev
->dev_flags
|= PHY_BRCM_STD_IBND_DISABLE
;
1122 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1123 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_RX_ENABLE
;
1124 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1125 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_TX_ENABLE
;
1127 case PHY_ID_RTL8211C
:
1128 phydev
->interface
= PHY_INTERFACE_MODE_RGMII
;
1130 case PHY_ID_RTL8201E
:
1131 case PHY_ID_BCMAC131
:
1132 phydev
->interface
= PHY_INTERFACE_MODE_MII
;
1133 phydev
->dev_flags
|= PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1134 tp
->phy_flags
|= TG3_PHYFLG_IS_FET
;
1138 tp
->tg3_flags3
|= TG3_FLG3_MDIOBUS_INITED
;
1140 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
1141 tg3_mdio_config_5785(tp
);
1146 static void tg3_mdio_fini(struct tg3
*tp
)
1148 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) {
1149 tp
->tg3_flags3
&= ~TG3_FLG3_MDIOBUS_INITED
;
1150 mdiobus_unregister(tp
->mdio_bus
);
1151 mdiobus_free(tp
->mdio_bus
);
1155 static int tg3_phy_cl45_write(struct tg3
*tp
, u32 devad
, u32 addr
, u32 val
)
1159 err
= tg3_writephy(tp
, MII_TG3_MMD_CTRL
, devad
);
1163 err
= tg3_writephy(tp
, MII_TG3_MMD_ADDRESS
, addr
);
1167 err
= tg3_writephy(tp
, MII_TG3_MMD_CTRL
,
1168 MII_TG3_MMD_CTRL_DATA_NOINC
| devad
);
1172 err
= tg3_writephy(tp
, MII_TG3_MMD_ADDRESS
, val
);
1178 static int tg3_phy_cl45_read(struct tg3
*tp
, u32 devad
, u32 addr
, u32
*val
)
1182 err
= tg3_writephy(tp
, MII_TG3_MMD_CTRL
, devad
);
1186 err
= tg3_writephy(tp
, MII_TG3_MMD_ADDRESS
, addr
);
1190 err
= tg3_writephy(tp
, MII_TG3_MMD_CTRL
,
1191 MII_TG3_MMD_CTRL_DATA_NOINC
| devad
);
1195 err
= tg3_readphy(tp
, MII_TG3_MMD_ADDRESS
, val
);
1201 /* tp->lock is held. */
1202 static inline void tg3_generate_fw_event(struct tg3
*tp
)
1206 val
= tr32(GRC_RX_CPU_EVENT
);
1207 val
|= GRC_RX_CPU_DRIVER_EVENT
;
1208 tw32_f(GRC_RX_CPU_EVENT
, val
);
1210 tp
->last_event_jiffies
= jiffies
;
1213 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1215 /* tp->lock is held. */
1216 static void tg3_wait_for_event_ack(struct tg3
*tp
)
1219 unsigned int delay_cnt
;
1222 /* If enough time has passed, no wait is necessary. */
1223 time_remain
= (long)(tp
->last_event_jiffies
+ 1 +
1224 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC
)) -
1226 if (time_remain
< 0)
1229 /* Check if we can shorten the wait time. */
1230 delay_cnt
= jiffies_to_usecs(time_remain
);
1231 if (delay_cnt
> TG3_FW_EVENT_TIMEOUT_USEC
)
1232 delay_cnt
= TG3_FW_EVENT_TIMEOUT_USEC
;
1233 delay_cnt
= (delay_cnt
>> 3) + 1;
1235 for (i
= 0; i
< delay_cnt
; i
++) {
1236 if (!(tr32(GRC_RX_CPU_EVENT
) & GRC_RX_CPU_DRIVER_EVENT
))
1242 /* tp->lock is held. */
1243 static void tg3_ump_link_report(struct tg3
*tp
)
1248 if (!(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
1249 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
1252 tg3_wait_for_event_ack(tp
);
1254 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_LINK_UPDATE
);
1256 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 14);
1259 if (!tg3_readphy(tp
, MII_BMCR
, ®
))
1261 if (!tg3_readphy(tp
, MII_BMSR
, ®
))
1262 val
|= (reg
& 0xffff);
1263 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
, val
);
1266 if (!tg3_readphy(tp
, MII_ADVERTISE
, ®
))
1268 if (!tg3_readphy(tp
, MII_LPA
, ®
))
1269 val
|= (reg
& 0xffff);
1270 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 4, val
);
1273 if (!(tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)) {
1274 if (!tg3_readphy(tp
, MII_CTRL1000
, ®
))
1276 if (!tg3_readphy(tp
, MII_STAT1000
, ®
))
1277 val
|= (reg
& 0xffff);
1279 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 8, val
);
1281 if (!tg3_readphy(tp
, MII_PHYADDR
, ®
))
1285 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 12, val
);
1287 tg3_generate_fw_event(tp
);
1290 static void tg3_link_report(struct tg3
*tp
)
1292 if (!netif_carrier_ok(tp
->dev
)) {
1293 netif_info(tp
, link
, tp
->dev
, "Link is down\n");
1294 tg3_ump_link_report(tp
);
1295 } else if (netif_msg_link(tp
)) {
1296 netdev_info(tp
->dev
, "Link is up at %d Mbps, %s duplex\n",
1297 (tp
->link_config
.active_speed
== SPEED_1000
?
1299 (tp
->link_config
.active_speed
== SPEED_100
?
1301 (tp
->link_config
.active_duplex
== DUPLEX_FULL
?
1304 netdev_info(tp
->dev
, "Flow control is %s for TX and %s for RX\n",
1305 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
) ?
1307 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
) ?
1309 tg3_ump_link_report(tp
);
1313 static u16
tg3_advert_flowctrl_1000T(u8 flow_ctrl
)
1317 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1318 miireg
= ADVERTISE_PAUSE_CAP
;
1319 else if (flow_ctrl
& FLOW_CTRL_TX
)
1320 miireg
= ADVERTISE_PAUSE_ASYM
;
1321 else if (flow_ctrl
& FLOW_CTRL_RX
)
1322 miireg
= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1329 static u16
tg3_advert_flowctrl_1000X(u8 flow_ctrl
)
1333 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1334 miireg
= ADVERTISE_1000XPAUSE
;
1335 else if (flow_ctrl
& FLOW_CTRL_TX
)
1336 miireg
= ADVERTISE_1000XPSE_ASYM
;
1337 else if (flow_ctrl
& FLOW_CTRL_RX
)
1338 miireg
= ADVERTISE_1000XPAUSE
| ADVERTISE_1000XPSE_ASYM
;
1345 static u8
tg3_resolve_flowctrl_1000X(u16 lcladv
, u16 rmtadv
)
1349 if (lcladv
& ADVERTISE_1000XPAUSE
) {
1350 if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1351 if (rmtadv
& LPA_1000XPAUSE
)
1352 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1353 else if (rmtadv
& LPA_1000XPAUSE_ASYM
)
1356 if (rmtadv
& LPA_1000XPAUSE
)
1357 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1359 } else if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1360 if ((rmtadv
& LPA_1000XPAUSE
) && (rmtadv
& LPA_1000XPAUSE_ASYM
))
1367 static void tg3_setup_flow_control(struct tg3
*tp
, u32 lcladv
, u32 rmtadv
)
1371 u32 old_rx_mode
= tp
->rx_mode
;
1372 u32 old_tx_mode
= tp
->tx_mode
;
1374 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
1375 autoneg
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]->autoneg
;
1377 autoneg
= tp
->link_config
.autoneg
;
1379 if (autoneg
== AUTONEG_ENABLE
&&
1380 (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)) {
1381 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
1382 flowctrl
= tg3_resolve_flowctrl_1000X(lcladv
, rmtadv
);
1384 flowctrl
= mii_resolve_flowctrl_fdx(lcladv
, rmtadv
);
1386 flowctrl
= tp
->link_config
.flowctrl
;
1388 tp
->link_config
.active_flowctrl
= flowctrl
;
1390 if (flowctrl
& FLOW_CTRL_RX
)
1391 tp
->rx_mode
|= RX_MODE_FLOW_CTRL_ENABLE
;
1393 tp
->rx_mode
&= ~RX_MODE_FLOW_CTRL_ENABLE
;
1395 if (old_rx_mode
!= tp
->rx_mode
)
1396 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
1398 if (flowctrl
& FLOW_CTRL_TX
)
1399 tp
->tx_mode
|= TX_MODE_FLOW_CTRL_ENABLE
;
1401 tp
->tx_mode
&= ~TX_MODE_FLOW_CTRL_ENABLE
;
1403 if (old_tx_mode
!= tp
->tx_mode
)
1404 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
1407 static void tg3_adjust_link(struct net_device
*dev
)
1409 u8 oldflowctrl
, linkmesg
= 0;
1410 u32 mac_mode
, lcl_adv
, rmt_adv
;
1411 struct tg3
*tp
= netdev_priv(dev
);
1412 struct phy_device
*phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1414 spin_lock_bh(&tp
->lock
);
1416 mac_mode
= tp
->mac_mode
& ~(MAC_MODE_PORT_MODE_MASK
|
1417 MAC_MODE_HALF_DUPLEX
);
1419 oldflowctrl
= tp
->link_config
.active_flowctrl
;
1425 if (phydev
->speed
== SPEED_100
|| phydev
->speed
== SPEED_10
)
1426 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
1427 else if (phydev
->speed
== SPEED_1000
||
1428 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
)
1429 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1431 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
1433 if (phydev
->duplex
== DUPLEX_HALF
)
1434 mac_mode
|= MAC_MODE_HALF_DUPLEX
;
1436 lcl_adv
= tg3_advert_flowctrl_1000T(
1437 tp
->link_config
.flowctrl
);
1440 rmt_adv
= LPA_PAUSE_CAP
;
1441 if (phydev
->asym_pause
)
1442 rmt_adv
|= LPA_PAUSE_ASYM
;
1445 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
1447 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1449 if (mac_mode
!= tp
->mac_mode
) {
1450 tp
->mac_mode
= mac_mode
;
1451 tw32_f(MAC_MODE
, tp
->mac_mode
);
1455 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
1456 if (phydev
->speed
== SPEED_10
)
1458 MAC_MI_STAT_10MBPS_MODE
|
1459 MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1461 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1464 if (phydev
->speed
== SPEED_1000
&& phydev
->duplex
== DUPLEX_HALF
)
1465 tw32(MAC_TX_LENGTHS
,
1466 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1467 (6 << TX_LENGTHS_IPG_SHIFT
) |
1468 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1470 tw32(MAC_TX_LENGTHS
,
1471 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1472 (6 << TX_LENGTHS_IPG_SHIFT
) |
1473 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1475 if ((phydev
->link
&& tp
->link_config
.active_speed
== SPEED_INVALID
) ||
1476 (!phydev
->link
&& tp
->link_config
.active_speed
!= SPEED_INVALID
) ||
1477 phydev
->speed
!= tp
->link_config
.active_speed
||
1478 phydev
->duplex
!= tp
->link_config
.active_duplex
||
1479 oldflowctrl
!= tp
->link_config
.active_flowctrl
)
1482 tp
->link_config
.active_speed
= phydev
->speed
;
1483 tp
->link_config
.active_duplex
= phydev
->duplex
;
1485 spin_unlock_bh(&tp
->lock
);
1488 tg3_link_report(tp
);
1491 static int tg3_phy_init(struct tg3
*tp
)
1493 struct phy_device
*phydev
;
1495 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
)
1498 /* Bring the PHY back to a known state. */
1501 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1503 /* Attach the MAC to the PHY. */
1504 phydev
= phy_connect(tp
->dev
, dev_name(&phydev
->dev
), tg3_adjust_link
,
1505 phydev
->dev_flags
, phydev
->interface
);
1506 if (IS_ERR(phydev
)) {
1507 dev_err(&tp
->pdev
->dev
, "Could not attach to PHY\n");
1508 return PTR_ERR(phydev
);
1511 /* Mask with MAC supported features. */
1512 switch (phydev
->interface
) {
1513 case PHY_INTERFACE_MODE_GMII
:
1514 case PHY_INTERFACE_MODE_RGMII
:
1515 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
1516 phydev
->supported
&= (PHY_GBIT_FEATURES
|
1518 SUPPORTED_Asym_Pause
);
1522 case PHY_INTERFACE_MODE_MII
:
1523 phydev
->supported
&= (PHY_BASIC_FEATURES
|
1525 SUPPORTED_Asym_Pause
);
1528 phy_disconnect(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1532 tp
->phy_flags
|= TG3_PHYFLG_IS_CONNECTED
;
1534 phydev
->advertising
= phydev
->supported
;
1539 static void tg3_phy_start(struct tg3
*tp
)
1541 struct phy_device
*phydev
;
1543 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
1546 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1548 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
) {
1549 tp
->phy_flags
&= ~TG3_PHYFLG_IS_LOW_POWER
;
1550 phydev
->speed
= tp
->link_config
.orig_speed
;
1551 phydev
->duplex
= tp
->link_config
.orig_duplex
;
1552 phydev
->autoneg
= tp
->link_config
.orig_autoneg
;
1553 phydev
->advertising
= tp
->link_config
.orig_advertising
;
1558 phy_start_aneg(phydev
);
1561 static void tg3_phy_stop(struct tg3
*tp
)
1563 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
1566 phy_stop(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1569 static void tg3_phy_fini(struct tg3
*tp
)
1571 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) {
1572 phy_disconnect(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1573 tp
->phy_flags
&= ~TG3_PHYFLG_IS_CONNECTED
;
1577 static int tg3_phydsp_read(struct tg3
*tp
, u32 reg
, u32
*val
)
1581 err
= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, reg
);
1583 err
= tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, val
);
1588 static int tg3_phydsp_write(struct tg3
*tp
, u32 reg
, u32 val
)
1592 err
= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, reg
);
1594 err
= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, val
);
1599 static void tg3_phy_fet_toggle_apd(struct tg3
*tp
, bool enable
)
1603 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &phytest
)) {
1606 tg3_writephy(tp
, MII_TG3_FET_TEST
,
1607 phytest
| MII_TG3_FET_SHADOW_EN
);
1608 if (!tg3_readphy(tp
, MII_TG3_FET_SHDW_AUXSTAT2
, &phy
)) {
1610 phy
|= MII_TG3_FET_SHDW_AUXSTAT2_APD
;
1612 phy
&= ~MII_TG3_FET_SHDW_AUXSTAT2_APD
;
1613 tg3_writephy(tp
, MII_TG3_FET_SHDW_AUXSTAT2
, phy
);
1615 tg3_writephy(tp
, MII_TG3_FET_TEST
, phytest
);
1619 static void tg3_phy_toggle_apd(struct tg3
*tp
, bool enable
)
1623 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
1624 ((tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) &&
1625 (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)))
1628 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
1629 tg3_phy_fet_toggle_apd(tp
, enable
);
1633 reg
= MII_TG3_MISC_SHDW_WREN
|
1634 MII_TG3_MISC_SHDW_SCR5_SEL
|
1635 MII_TG3_MISC_SHDW_SCR5_LPED
|
1636 MII_TG3_MISC_SHDW_SCR5_DLPTLM
|
1637 MII_TG3_MISC_SHDW_SCR5_SDTL
|
1638 MII_TG3_MISC_SHDW_SCR5_C125OE
;
1639 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
|| !enable
)
1640 reg
|= MII_TG3_MISC_SHDW_SCR5_DLLAPD
;
1642 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1645 reg
= MII_TG3_MISC_SHDW_WREN
|
1646 MII_TG3_MISC_SHDW_APD_SEL
|
1647 MII_TG3_MISC_SHDW_APD_WKTM_84MS
;
1649 reg
|= MII_TG3_MISC_SHDW_APD_ENABLE
;
1651 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1654 static void tg3_phy_toggle_automdix(struct tg3
*tp
, int enable
)
1658 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
1659 (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
1662 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
1665 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &ephy
)) {
1666 u32 reg
= MII_TG3_FET_SHDW_MISCCTRL
;
1668 tg3_writephy(tp
, MII_TG3_FET_TEST
,
1669 ephy
| MII_TG3_FET_SHADOW_EN
);
1670 if (!tg3_readphy(tp
, reg
, &phy
)) {
1672 phy
|= MII_TG3_FET_SHDW_MISCCTRL_MDIX
;
1674 phy
&= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX
;
1675 tg3_writephy(tp
, reg
, phy
);
1677 tg3_writephy(tp
, MII_TG3_FET_TEST
, ephy
);
1680 phy
= MII_TG3_AUXCTL_MISC_RDSEL_MISC
|
1681 MII_TG3_AUXCTL_SHDWSEL_MISC
;
1682 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
) &&
1683 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &phy
)) {
1685 phy
|= MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1687 phy
&= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1688 phy
|= MII_TG3_AUXCTL_MISC_WREN
;
1689 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1694 static void tg3_phy_set_wirespeed(struct tg3
*tp
)
1698 if (tp
->phy_flags
& TG3_PHYFLG_NO_ETH_WIRE_SPEED
)
1701 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x7007) &&
1702 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
))
1703 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
1704 (val
| (1 << 15) | (1 << 4)));
1707 static void tg3_phy_apply_otp(struct tg3
*tp
)
1716 /* Enable SM_DSP clock and tx 6dB coding. */
1717 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1718 MII_TG3_AUXCTL_ACTL_SMDSP_ENA
|
1719 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1720 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1722 phy
= ((otp
& TG3_OTP_AGCTGT_MASK
) >> TG3_OTP_AGCTGT_SHIFT
);
1723 phy
|= MII_TG3_DSP_TAP1_AGCTGT_DFLT
;
1724 tg3_phydsp_write(tp
, MII_TG3_DSP_TAP1
, phy
);
1726 phy
= ((otp
& TG3_OTP_HPFFLTR_MASK
) >> TG3_OTP_HPFFLTR_SHIFT
) |
1727 ((otp
& TG3_OTP_HPFOVER_MASK
) >> TG3_OTP_HPFOVER_SHIFT
);
1728 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH0
, phy
);
1730 phy
= ((otp
& TG3_OTP_LPFDIS_MASK
) >> TG3_OTP_LPFDIS_SHIFT
);
1731 phy
|= MII_TG3_DSP_AADJ1CH3_ADCCKADJ
;
1732 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH3
, phy
);
1734 phy
= ((otp
& TG3_OTP_VDAC_MASK
) >> TG3_OTP_VDAC_SHIFT
);
1735 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP75
, phy
);
1737 phy
= ((otp
& TG3_OTP_10BTAMP_MASK
) >> TG3_OTP_10BTAMP_SHIFT
);
1738 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP96
, phy
);
1740 phy
= ((otp
& TG3_OTP_ROFF_MASK
) >> TG3_OTP_ROFF_SHIFT
) |
1741 ((otp
& TG3_OTP_RCOFF_MASK
) >> TG3_OTP_RCOFF_SHIFT
);
1742 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP97
, phy
);
1744 /* Turn off SM_DSP clock. */
1745 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1746 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1747 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1750 static void tg3_phy_eee_adjust(struct tg3
*tp
, u32 current_link_up
)
1754 if (!(tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
))
1759 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
&&
1760 current_link_up
== 1 &&
1761 tp
->link_config
.active_duplex
== DUPLEX_FULL
&&
1762 (tp
->link_config
.active_speed
== SPEED_100
||
1763 tp
->link_config
.active_speed
== SPEED_1000
)) {
1766 if (tp
->link_config
.active_speed
== SPEED_1000
)
1767 eeectl
= TG3_CPMU_EEE_CTRL_EXIT_16_5_US
;
1769 eeectl
= TG3_CPMU_EEE_CTRL_EXIT_36_US
;
1771 tw32(TG3_CPMU_EEE_CTRL
, eeectl
);
1773 tg3_phy_cl45_read(tp
, MDIO_MMD_AN
,
1774 TG3_CL45_D7_EEERES_STAT
, &val
);
1777 case TG3_CL45_D7_EEERES_STAT_LP_1000T
:
1778 switch (GET_ASIC_REV(tp
->pci_chip_rev_id
)) {
1781 case ASIC_REV_57765
:
1782 /* Enable SM_DSP clock and tx 6dB coding. */
1783 val
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1784 MII_TG3_AUXCTL_ACTL_SMDSP_ENA
|
1785 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1786 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, val
);
1788 tg3_phydsp_write(tp
, MII_TG3_DSP_TAP26
, 0x0000);
1790 /* Turn off SM_DSP clock. */
1791 val
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1792 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1793 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, val
);
1796 case TG3_CL45_D7_EEERES_STAT_LP_100TX
:
1801 if (!tp
->setlpicnt
) {
1802 val
= tr32(TG3_CPMU_EEE_MODE
);
1803 tw32(TG3_CPMU_EEE_MODE
, val
& ~TG3_CPMU_EEEMD_LPI_ENABLE
);
1807 static int tg3_wait_macro_done(struct tg3
*tp
)
1814 if (!tg3_readphy(tp
, MII_TG3_DSP_CONTROL
, &tmp32
)) {
1815 if ((tmp32
& 0x1000) == 0)
1825 static int tg3_phy_write_and_check_testpat(struct tg3
*tp
, int *resetp
)
1827 static const u32 test_pat
[4][6] = {
1828 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1829 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1830 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1831 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1835 for (chan
= 0; chan
< 4; chan
++) {
1838 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1839 (chan
* 0x2000) | 0x0200);
1840 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0002);
1842 for (i
= 0; i
< 6; i
++)
1843 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
,
1846 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0202);
1847 if (tg3_wait_macro_done(tp
)) {
1852 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1853 (chan
* 0x2000) | 0x0200);
1854 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0082);
1855 if (tg3_wait_macro_done(tp
)) {
1860 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0802);
1861 if (tg3_wait_macro_done(tp
)) {
1866 for (i
= 0; i
< 6; i
+= 2) {
1869 if (tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &low
) ||
1870 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &high
) ||
1871 tg3_wait_macro_done(tp
)) {
1877 if (low
!= test_pat
[chan
][i
] ||
1878 high
!= test_pat
[chan
][i
+1]) {
1879 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000b);
1880 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4001);
1881 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4005);
1891 static int tg3_phy_reset_chanpat(struct tg3
*tp
)
1895 for (chan
= 0; chan
< 4; chan
++) {
1898 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1899 (chan
* 0x2000) | 0x0200);
1900 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0002);
1901 for (i
= 0; i
< 6; i
++)
1902 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x000);
1903 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0202);
1904 if (tg3_wait_macro_done(tp
))
1911 static int tg3_phy_reset_5703_4_5(struct tg3
*tp
)
1913 u32 reg32
, phy9_orig
;
1914 int retries
, do_phy_reset
, err
;
1920 err
= tg3_bmcr_reset(tp
);
1926 /* Disable transmitter and interrupt. */
1927 if (tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
))
1931 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1933 /* Set full-duplex, 1000 mbps. */
1934 tg3_writephy(tp
, MII_BMCR
,
1935 BMCR_FULLDPLX
| TG3_BMCR_SPEED1000
);
1937 /* Set to master mode. */
1938 if (tg3_readphy(tp
, MII_TG3_CTRL
, &phy9_orig
))
1941 tg3_writephy(tp
, MII_TG3_CTRL
,
1942 (MII_TG3_CTRL_AS_MASTER
|
1943 MII_TG3_CTRL_ENABLE_AS_MASTER
));
1945 /* Enable SM_DSP_CLOCK and 6dB. */
1946 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1948 /* Block the PHY control access. */
1949 tg3_phydsp_write(tp
, 0x8005, 0x0800);
1951 err
= tg3_phy_write_and_check_testpat(tp
, &do_phy_reset
);
1954 } while (--retries
);
1956 err
= tg3_phy_reset_chanpat(tp
);
1960 tg3_phydsp_write(tp
, 0x8005, 0x0000);
1962 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8200);
1963 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0000);
1965 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1966 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
1967 /* Set Extended packet length bit for jumbo frames */
1968 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4400);
1970 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1973 tg3_writephy(tp
, MII_TG3_CTRL
, phy9_orig
);
1975 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
)) {
1977 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1984 /* This will reset the tigon3 PHY if there is no valid
1985 * link unless the FORCE argument is non-zero.
1987 static int tg3_phy_reset(struct tg3
*tp
)
1992 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
1993 val
= tr32(GRC_MISC_CFG
);
1994 tw32_f(GRC_MISC_CFG
, val
& ~GRC_MISC_CFG_EPHY_IDDQ
);
1997 err
= tg3_readphy(tp
, MII_BMSR
, &val
);
1998 err
|= tg3_readphy(tp
, MII_BMSR
, &val
);
2002 if (netif_running(tp
->dev
) && netif_carrier_ok(tp
->dev
)) {
2003 netif_carrier_off(tp
->dev
);
2004 tg3_link_report(tp
);
2007 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
2008 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2009 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
2010 err
= tg3_phy_reset_5703_4_5(tp
);
2017 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
2018 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
2019 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
2020 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
)
2022 cpmuctrl
& ~CPMU_CTRL_GPHY_10MB_RXONLY
);
2025 err
= tg3_bmcr_reset(tp
);
2029 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
) {
2030 val
= MII_TG3_DSP_EXP8_AEDW
| MII_TG3_DSP_EXP8_REJ2MHz
;
2031 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP8
, val
);
2033 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
2036 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
2037 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
2038 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
2039 if ((val
& CPMU_LSPD_1000MB_MACCLK_MASK
) ==
2040 CPMU_LSPD_1000MB_MACCLK_12_5
) {
2041 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
2043 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
2047 if ((tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) &&
2048 (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
))
2051 tg3_phy_apply_otp(tp
);
2053 if (tp
->phy_flags
& TG3_PHYFLG_ENABLE_APD
)
2054 tg3_phy_toggle_apd(tp
, true);
2056 tg3_phy_toggle_apd(tp
, false);
2059 if (tp
->phy_flags
& TG3_PHYFLG_ADC_BUG
) {
2060 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
2061 tg3_phydsp_write(tp
, 0x201f, 0x2aaa);
2062 tg3_phydsp_write(tp
, 0x000a, 0x0323);
2063 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
2065 if (tp
->phy_flags
& TG3_PHYFLG_5704_A0_BUG
) {
2066 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8d68);
2067 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8d68);
2069 if (tp
->phy_flags
& TG3_PHYFLG_BER_BUG
) {
2070 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
2071 tg3_phydsp_write(tp
, 0x000a, 0x310b);
2072 tg3_phydsp_write(tp
, 0x201f, 0x9506);
2073 tg3_phydsp_write(tp
, 0x401f, 0x14e2);
2074 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
2075 } else if (tp
->phy_flags
& TG3_PHYFLG_JITTER_BUG
) {
2076 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
2077 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
2078 if (tp
->phy_flags
& TG3_PHYFLG_ADJUST_TRIM
) {
2079 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x110b);
2080 tg3_writephy(tp
, MII_TG3_TEST1
,
2081 MII_TG3_TEST1_TRIM_EN
| 0x4);
2083 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x010b);
2084 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
2086 /* Set Extended packet length bit (bit 14) on all chips that */
2087 /* support jumbo frames */
2088 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
2089 /* Cannot do read-modify-write on 5401 */
2090 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
2091 } else if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
2092 /* Set bit 14 with read-modify-write to preserve other bits */
2093 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0007) &&
2094 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
))
2095 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, val
| 0x4000);
2098 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2099 * jumbo frames transmission.
2101 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
2102 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, &val
))
2103 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
2104 val
| MII_TG3_EXT_CTRL_FIFO_ELASTIC
);
2107 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2108 /* adjust output voltage */
2109 tg3_writephy(tp
, MII_TG3_FET_PTEST
, 0x12);
2112 tg3_phy_toggle_automdix(tp
, 1);
2113 tg3_phy_set_wirespeed(tp
);
2117 static void tg3_frob_aux_power(struct tg3
*tp
)
2119 bool need_vaux
= false;
2121 /* The GPIOs do something completely different on 57765. */
2122 if ((tp
->tg3_flags2
& TG3_FLG2_IS_NIC
) == 0 ||
2123 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
2124 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
2127 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2128 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
||
2129 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
2130 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
) &&
2131 tp
->pdev_peer
!= tp
->pdev
) {
2132 struct net_device
*dev_peer
;
2134 dev_peer
= pci_get_drvdata(tp
->pdev_peer
);
2136 /* remove_one() may have been run on the peer. */
2138 struct tg3
*tp_peer
= netdev_priv(dev_peer
);
2140 if (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)
2143 if ((tp_peer
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) ||
2144 (tp_peer
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
2149 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) ||
2150 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
2154 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2155 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2156 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2157 (GRC_LCLCTRL_GPIO_OE0
|
2158 GRC_LCLCTRL_GPIO_OE1
|
2159 GRC_LCLCTRL_GPIO_OE2
|
2160 GRC_LCLCTRL_GPIO_OUTPUT0
|
2161 GRC_LCLCTRL_GPIO_OUTPUT1
),
2163 } else if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
2164 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
2165 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2166 u32 grc_local_ctrl
= GRC_LCLCTRL_GPIO_OE0
|
2167 GRC_LCLCTRL_GPIO_OE1
|
2168 GRC_LCLCTRL_GPIO_OE2
|
2169 GRC_LCLCTRL_GPIO_OUTPUT0
|
2170 GRC_LCLCTRL_GPIO_OUTPUT1
|
2172 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2174 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT2
;
2175 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2177 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT0
;
2178 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2181 u32 grc_local_ctrl
= 0;
2183 /* Workaround to prevent overdrawing Amps. */
2184 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
2186 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
2187 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2188 grc_local_ctrl
, 100);
2191 /* On 5753 and variants, GPIO2 cannot be used. */
2192 no_gpio2
= tp
->nic_sram_data_cfg
&
2193 NIC_SRAM_DATA_CFG_NO_GPIO2
;
2195 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
2196 GRC_LCLCTRL_GPIO_OE1
|
2197 GRC_LCLCTRL_GPIO_OE2
|
2198 GRC_LCLCTRL_GPIO_OUTPUT1
|
2199 GRC_LCLCTRL_GPIO_OUTPUT2
;
2201 grc_local_ctrl
&= ~(GRC_LCLCTRL_GPIO_OE2
|
2202 GRC_LCLCTRL_GPIO_OUTPUT2
);
2204 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2205 grc_local_ctrl
, 100);
2207 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT0
;
2209 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2210 grc_local_ctrl
, 100);
2213 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT2
;
2214 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2215 grc_local_ctrl
, 100);
2219 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
2220 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
2221 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2222 (GRC_LCLCTRL_GPIO_OE1
|
2223 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2225 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2226 GRC_LCLCTRL_GPIO_OE1
, 100);
2228 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2229 (GRC_LCLCTRL_GPIO_OE1
|
2230 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2235 static int tg3_5700_link_polarity(struct tg3
*tp
, u32 speed
)
2237 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_2
)
2239 else if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5411
) {
2240 if (speed
!= SPEED_10
)
2242 } else if (speed
== SPEED_10
)
2248 static int tg3_setup_phy(struct tg3
*, int);
2250 #define RESET_KIND_SHUTDOWN 0
2251 #define RESET_KIND_INIT 1
2252 #define RESET_KIND_SUSPEND 2
2254 static void tg3_write_sig_post_reset(struct tg3
*, int);
2255 static int tg3_halt_cpu(struct tg3
*, u32
);
2257 static void tg3_power_down_phy(struct tg3
*tp
, bool do_low_power
)
2261 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
2262 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2263 u32 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
2264 u32 serdes_cfg
= tr32(MAC_SERDES_CFG
);
2267 SG_DIG_USING_HW_AUTONEG
| SG_DIG_SOFT_RESET
;
2268 tw32(SG_DIG_CTRL
, sg_dig_ctrl
);
2269 tw32(MAC_SERDES_CFG
, serdes_cfg
| (1 << 15));
2274 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2276 val
= tr32(GRC_MISC_CFG
);
2277 tw32_f(GRC_MISC_CFG
, val
| GRC_MISC_CFG_EPHY_IDDQ
);
2280 } else if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
2282 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &phytest
)) {
2285 tg3_writephy(tp
, MII_ADVERTISE
, 0);
2286 tg3_writephy(tp
, MII_BMCR
,
2287 BMCR_ANENABLE
| BMCR_ANRESTART
);
2289 tg3_writephy(tp
, MII_TG3_FET_TEST
,
2290 phytest
| MII_TG3_FET_SHADOW_EN
);
2291 if (!tg3_readphy(tp
, MII_TG3_FET_SHDW_AUXMODE4
, &phy
)) {
2292 phy
|= MII_TG3_FET_SHDW_AUXMODE4_SBPD
;
2294 MII_TG3_FET_SHDW_AUXMODE4
,
2297 tg3_writephy(tp
, MII_TG3_FET_TEST
, phytest
);
2300 } else if (do_low_power
) {
2301 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
2302 MII_TG3_EXT_CTRL_FORCE_LED_OFF
);
2304 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
2305 MII_TG3_AUXCTL_SHDWSEL_PWRCTL
|
2306 MII_TG3_AUXCTL_PCTL_100TX_LPWR
|
2307 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE
|
2308 MII_TG3_AUXCTL_PCTL_VREG_11V
);
2311 /* The PHY should not be powered down on some chips because
2314 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2315 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2316 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
&&
2317 (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)))
2320 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
2321 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
2322 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
2323 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
2324 val
|= CPMU_LSPD_1000MB_MACCLK_12_5
;
2325 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
2328 tg3_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
2331 /* tp->lock is held. */
2332 static int tg3_nvram_lock(struct tg3
*tp
)
2334 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
2337 if (tp
->nvram_lock_cnt
== 0) {
2338 tw32(NVRAM_SWARB
, SWARB_REQ_SET1
);
2339 for (i
= 0; i
< 8000; i
++) {
2340 if (tr32(NVRAM_SWARB
) & SWARB_GNT1
)
2345 tw32(NVRAM_SWARB
, SWARB_REQ_CLR1
);
2349 tp
->nvram_lock_cnt
++;
2354 /* tp->lock is held. */
2355 static void tg3_nvram_unlock(struct tg3
*tp
)
2357 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
2358 if (tp
->nvram_lock_cnt
> 0)
2359 tp
->nvram_lock_cnt
--;
2360 if (tp
->nvram_lock_cnt
== 0)
2361 tw32_f(NVRAM_SWARB
, SWARB_REQ_CLR1
);
2365 /* tp->lock is held. */
2366 static void tg3_enable_nvram_access(struct tg3
*tp
)
2368 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2369 !(tp
->tg3_flags3
& TG3_FLG3_PROTECTED_NVRAM
)) {
2370 u32 nvaccess
= tr32(NVRAM_ACCESS
);
2372 tw32(NVRAM_ACCESS
, nvaccess
| ACCESS_ENABLE
);
2376 /* tp->lock is held. */
2377 static void tg3_disable_nvram_access(struct tg3
*tp
)
2379 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2380 !(tp
->tg3_flags3
& TG3_FLG3_PROTECTED_NVRAM
)) {
2381 u32 nvaccess
= tr32(NVRAM_ACCESS
);
2383 tw32(NVRAM_ACCESS
, nvaccess
& ~ACCESS_ENABLE
);
2387 static int tg3_nvram_read_using_eeprom(struct tg3
*tp
,
2388 u32 offset
, u32
*val
)
2393 if (offset
> EEPROM_ADDR_ADDR_MASK
|| (offset
% 4) != 0)
2396 tmp
= tr32(GRC_EEPROM_ADDR
) & ~(EEPROM_ADDR_ADDR_MASK
|
2397 EEPROM_ADDR_DEVID_MASK
|
2399 tw32(GRC_EEPROM_ADDR
,
2401 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
2402 ((offset
<< EEPROM_ADDR_ADDR_SHIFT
) &
2403 EEPROM_ADDR_ADDR_MASK
) |
2404 EEPROM_ADDR_READ
| EEPROM_ADDR_START
);
2406 for (i
= 0; i
< 1000; i
++) {
2407 tmp
= tr32(GRC_EEPROM_ADDR
);
2409 if (tmp
& EEPROM_ADDR_COMPLETE
)
2413 if (!(tmp
& EEPROM_ADDR_COMPLETE
))
2416 tmp
= tr32(GRC_EEPROM_DATA
);
2419 * The data will always be opposite the native endian
2420 * format. Perform a blind byteswap to compensate.
2427 #define NVRAM_CMD_TIMEOUT 10000
2429 static int tg3_nvram_exec_cmd(struct tg3
*tp
, u32 nvram_cmd
)
2433 tw32(NVRAM_CMD
, nvram_cmd
);
2434 for (i
= 0; i
< NVRAM_CMD_TIMEOUT
; i
++) {
2436 if (tr32(NVRAM_CMD
) & NVRAM_CMD_DONE
) {
2442 if (i
== NVRAM_CMD_TIMEOUT
)
2448 static u32
tg3_nvram_phys_addr(struct tg3
*tp
, u32 addr
)
2450 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
2451 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
2452 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
2453 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
2454 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
2456 addr
= ((addr
/ tp
->nvram_pagesize
) <<
2457 ATMEL_AT45DB0X1B_PAGE_POS
) +
2458 (addr
% tp
->nvram_pagesize
);
2463 static u32
tg3_nvram_logical_addr(struct tg3
*tp
, u32 addr
)
2465 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
2466 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
2467 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
2468 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
2469 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
2471 addr
= ((addr
>> ATMEL_AT45DB0X1B_PAGE_POS
) *
2472 tp
->nvram_pagesize
) +
2473 (addr
& ((1 << ATMEL_AT45DB0X1B_PAGE_POS
) - 1));
2478 /* NOTE: Data read in from NVRAM is byteswapped according to
2479 * the byteswapping settings for all other register accesses.
2480 * tg3 devices are BE devices, so on a BE machine, the data
2481 * returned will be exactly as it is seen in NVRAM. On a LE
2482 * machine, the 32-bit value will be byteswapped.
2484 static int tg3_nvram_read(struct tg3
*tp
, u32 offset
, u32
*val
)
2488 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
))
2489 return tg3_nvram_read_using_eeprom(tp
, offset
, val
);
2491 offset
= tg3_nvram_phys_addr(tp
, offset
);
2493 if (offset
> NVRAM_ADDR_MSK
)
2496 ret
= tg3_nvram_lock(tp
);
2500 tg3_enable_nvram_access(tp
);
2502 tw32(NVRAM_ADDR
, offset
);
2503 ret
= tg3_nvram_exec_cmd(tp
, NVRAM_CMD_RD
| NVRAM_CMD_GO
|
2504 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_DONE
);
2507 *val
= tr32(NVRAM_RDDATA
);
2509 tg3_disable_nvram_access(tp
);
2511 tg3_nvram_unlock(tp
);
2516 /* Ensures NVRAM data is in bytestream format. */
2517 static int tg3_nvram_read_be32(struct tg3
*tp
, u32 offset
, __be32
*val
)
2520 int res
= tg3_nvram_read(tp
, offset
, &v
);
2522 *val
= cpu_to_be32(v
);
2526 /* tp->lock is held. */
2527 static void __tg3_set_mac_addr(struct tg3
*tp
, int skip_mac_1
)
2529 u32 addr_high
, addr_low
;
2532 addr_high
= ((tp
->dev
->dev_addr
[0] << 8) |
2533 tp
->dev
->dev_addr
[1]);
2534 addr_low
= ((tp
->dev
->dev_addr
[2] << 24) |
2535 (tp
->dev
->dev_addr
[3] << 16) |
2536 (tp
->dev
->dev_addr
[4] << 8) |
2537 (tp
->dev
->dev_addr
[5] << 0));
2538 for (i
= 0; i
< 4; i
++) {
2539 if (i
== 1 && skip_mac_1
)
2541 tw32(MAC_ADDR_0_HIGH
+ (i
* 8), addr_high
);
2542 tw32(MAC_ADDR_0_LOW
+ (i
* 8), addr_low
);
2545 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
2546 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2547 for (i
= 0; i
< 12; i
++) {
2548 tw32(MAC_EXTADDR_0_HIGH
+ (i
* 8), addr_high
);
2549 tw32(MAC_EXTADDR_0_LOW
+ (i
* 8), addr_low
);
2553 addr_high
= (tp
->dev
->dev_addr
[0] +
2554 tp
->dev
->dev_addr
[1] +
2555 tp
->dev
->dev_addr
[2] +
2556 tp
->dev
->dev_addr
[3] +
2557 tp
->dev
->dev_addr
[4] +
2558 tp
->dev
->dev_addr
[5]) &
2559 TX_BACKOFF_SEED_MASK
;
2560 tw32(MAC_TX_BACKOFF_SEED
, addr_high
);
2563 static void tg3_enable_register_access(struct tg3
*tp
)
2566 * Make sure register accesses (indirect or otherwise) will function
2569 pci_write_config_dword(tp
->pdev
,
2570 TG3PCI_MISC_HOST_CTRL
, tp
->misc_host_ctrl
);
2573 static int tg3_power_up(struct tg3
*tp
)
2575 tg3_enable_register_access(tp
);
2577 pci_set_power_state(tp
->pdev
, PCI_D0
);
2579 /* Switch out of Vaux if it is a NIC */
2580 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
2581 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
, 100);
2586 static int tg3_power_down_prepare(struct tg3
*tp
)
2589 bool device_should_wake
, do_low_power
;
2591 tg3_enable_register_access(tp
);
2593 /* Restore the CLKREQ setting. */
2594 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
2597 pci_read_config_word(tp
->pdev
,
2598 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2600 lnkctl
|= PCI_EXP_LNKCTL_CLKREQ_EN
;
2601 pci_write_config_word(tp
->pdev
,
2602 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2606 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
2607 tw32(TG3PCI_MISC_HOST_CTRL
,
2608 misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
);
2610 device_should_wake
= device_may_wakeup(&tp
->pdev
->dev
) &&
2611 (tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
2613 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
2614 do_low_power
= false;
2615 if ((tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) &&
2616 !(tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)) {
2617 struct phy_device
*phydev
;
2618 u32 phyid
, advertising
;
2620 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
2622 tp
->phy_flags
|= TG3_PHYFLG_IS_LOW_POWER
;
2624 tp
->link_config
.orig_speed
= phydev
->speed
;
2625 tp
->link_config
.orig_duplex
= phydev
->duplex
;
2626 tp
->link_config
.orig_autoneg
= phydev
->autoneg
;
2627 tp
->link_config
.orig_advertising
= phydev
->advertising
;
2629 advertising
= ADVERTISED_TP
|
2631 ADVERTISED_Autoneg
|
2632 ADVERTISED_10baseT_Half
;
2634 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2635 device_should_wake
) {
2636 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2638 ADVERTISED_100baseT_Half
|
2639 ADVERTISED_100baseT_Full
|
2640 ADVERTISED_10baseT_Full
;
2642 advertising
|= ADVERTISED_10baseT_Full
;
2645 phydev
->advertising
= advertising
;
2647 phy_start_aneg(phydev
);
2649 phyid
= phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
;
2650 if (phyid
!= PHY_ID_BCMAC131
) {
2651 phyid
&= PHY_BCM_OUI_MASK
;
2652 if (phyid
== PHY_BCM_OUI_1
||
2653 phyid
== PHY_BCM_OUI_2
||
2654 phyid
== PHY_BCM_OUI_3
)
2655 do_low_power
= true;
2659 do_low_power
= true;
2661 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)) {
2662 tp
->phy_flags
|= TG3_PHYFLG_IS_LOW_POWER
;
2663 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
2664 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
2665 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
2668 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)) {
2669 tp
->link_config
.speed
= SPEED_10
;
2670 tp
->link_config
.duplex
= DUPLEX_HALF
;
2671 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
2672 tg3_setup_phy(tp
, 0);
2676 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2679 val
= tr32(GRC_VCPU_EXT_CTRL
);
2680 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_DISABLE_WOL
);
2681 } else if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2685 for (i
= 0; i
< 200; i
++) {
2686 tg3_read_mem(tp
, NIC_SRAM_FW_ASF_STATUS_MBOX
, &val
);
2687 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
2692 if (tp
->tg3_flags
& TG3_FLAG_WOL_CAP
)
2693 tg3_write_mem(tp
, NIC_SRAM_WOL_MBOX
, WOL_SIGNATURE
|
2694 WOL_DRV_STATE_SHUTDOWN
|
2698 if (device_should_wake
) {
2701 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)) {
2703 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x5a);
2707 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)
2708 mac_mode
= MAC_MODE_PORT_MODE_GMII
;
2710 mac_mode
= MAC_MODE_PORT_MODE_MII
;
2712 mac_mode
|= tp
->mac_mode
& MAC_MODE_LINK_POLARITY
;
2713 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
2715 u32 speed
= (tp
->tg3_flags
&
2716 TG3_FLAG_WOL_SPEED_100MB
) ?
2717 SPEED_100
: SPEED_10
;
2718 if (tg3_5700_link_polarity(tp
, speed
))
2719 mac_mode
|= MAC_MODE_LINK_POLARITY
;
2721 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
2724 mac_mode
= MAC_MODE_PORT_MODE_TBI
;
2727 if (!(tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
2728 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
2730 mac_mode
|= MAC_MODE_MAGIC_PKT_ENABLE
;
2731 if (((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
2732 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) &&
2733 ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2734 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)))
2735 mac_mode
|= MAC_MODE_KEEP_FRAME_IN_WOL
;
2737 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
2738 mac_mode
|= MAC_MODE_APE_TX_EN
|
2739 MAC_MODE_APE_RX_EN
|
2740 MAC_MODE_TDE_ENABLE
;
2742 tw32_f(MAC_MODE
, mac_mode
);
2745 tw32_f(MAC_RX_MODE
, RX_MODE_ENABLE
);
2749 if (!(tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
) &&
2750 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2751 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
2754 base_val
= tp
->pci_clock_ctrl
;
2755 base_val
|= (CLOCK_CTRL_RXCLK_DISABLE
|
2756 CLOCK_CTRL_TXCLK_DISABLE
);
2758 tw32_wait_f(TG3PCI_CLOCK_CTRL
, base_val
| CLOCK_CTRL_ALTCLK
|
2759 CLOCK_CTRL_PWRDOWN_PLL133
, 40);
2760 } else if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
2761 (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
2762 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)) {
2764 } else if (!((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2765 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))) {
2766 u32 newbits1
, newbits2
;
2768 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2769 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2770 newbits1
= (CLOCK_CTRL_RXCLK_DISABLE
|
2771 CLOCK_CTRL_TXCLK_DISABLE
|
2773 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2774 } else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
2775 newbits1
= CLOCK_CTRL_625_CORE
;
2776 newbits2
= newbits1
| CLOCK_CTRL_ALTCLK
;
2778 newbits1
= CLOCK_CTRL_ALTCLK
;
2779 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2782 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits1
,
2785 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits2
,
2788 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
2791 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2792 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2793 newbits3
= (CLOCK_CTRL_RXCLK_DISABLE
|
2794 CLOCK_CTRL_TXCLK_DISABLE
|
2795 CLOCK_CTRL_44MHZ_CORE
);
2797 newbits3
= CLOCK_CTRL_44MHZ_CORE
;
2800 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
2801 tp
->pci_clock_ctrl
| newbits3
, 40);
2805 if (!(device_should_wake
) &&
2806 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
2807 tg3_power_down_phy(tp
, do_low_power
);
2809 tg3_frob_aux_power(tp
);
2811 /* Workaround for unstable PLL clock */
2812 if ((GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
) ||
2813 (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
)) {
2814 u32 val
= tr32(0x7d00);
2816 val
&= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2818 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2821 err
= tg3_nvram_lock(tp
);
2822 tg3_halt_cpu(tp
, RX_CPU_BASE
);
2824 tg3_nvram_unlock(tp
);
2828 tg3_write_sig_post_reset(tp
, RESET_KIND_SHUTDOWN
);
2833 static void tg3_power_down(struct tg3
*tp
)
2835 tg3_power_down_prepare(tp
);
2837 pci_wake_from_d3(tp
->pdev
, tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
2838 pci_set_power_state(tp
->pdev
, PCI_D3hot
);
2841 static void tg3_aux_stat_to_speed_duplex(struct tg3
*tp
, u32 val
, u16
*speed
, u8
*duplex
)
2843 switch (val
& MII_TG3_AUX_STAT_SPDMASK
) {
2844 case MII_TG3_AUX_STAT_10HALF
:
2846 *duplex
= DUPLEX_HALF
;
2849 case MII_TG3_AUX_STAT_10FULL
:
2851 *duplex
= DUPLEX_FULL
;
2854 case MII_TG3_AUX_STAT_100HALF
:
2856 *duplex
= DUPLEX_HALF
;
2859 case MII_TG3_AUX_STAT_100FULL
:
2861 *duplex
= DUPLEX_FULL
;
2864 case MII_TG3_AUX_STAT_1000HALF
:
2865 *speed
= SPEED_1000
;
2866 *duplex
= DUPLEX_HALF
;
2869 case MII_TG3_AUX_STAT_1000FULL
:
2870 *speed
= SPEED_1000
;
2871 *duplex
= DUPLEX_FULL
;
2875 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
2876 *speed
= (val
& MII_TG3_AUX_STAT_100
) ? SPEED_100
:
2878 *duplex
= (val
& MII_TG3_AUX_STAT_FULL
) ? DUPLEX_FULL
:
2882 *speed
= SPEED_INVALID
;
2883 *duplex
= DUPLEX_INVALID
;
2888 static void tg3_phy_copper_begin(struct tg3
*tp
)
2893 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
) {
2894 /* Entering low power mode. Disable gigabit and
2895 * 100baseT advertisements.
2897 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2899 new_adv
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
2900 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
2901 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2902 new_adv
|= (ADVERTISE_100HALF
| ADVERTISE_100FULL
);
2904 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2905 } else if (tp
->link_config
.speed
== SPEED_INVALID
) {
2906 if (tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)
2907 tp
->link_config
.advertising
&=
2908 ~(ADVERTISED_1000baseT_Half
|
2909 ADVERTISED_1000baseT_Full
);
2911 new_adv
= ADVERTISE_CSMA
;
2912 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Half
)
2913 new_adv
|= ADVERTISE_10HALF
;
2914 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Full
)
2915 new_adv
|= ADVERTISE_10FULL
;
2916 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Half
)
2917 new_adv
|= ADVERTISE_100HALF
;
2918 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Full
)
2919 new_adv
|= ADVERTISE_100FULL
;
2921 new_adv
|= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2923 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2925 if (tp
->link_config
.advertising
&
2926 (ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
)) {
2928 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
2929 new_adv
|= MII_TG3_CTRL_ADV_1000_HALF
;
2930 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
2931 new_adv
|= MII_TG3_CTRL_ADV_1000_FULL
;
2932 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
) &&
2933 (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2934 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
))
2935 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2936 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2937 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2939 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2942 new_adv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2943 new_adv
|= ADVERTISE_CSMA
;
2945 /* Asking for a specific link mode. */
2946 if (tp
->link_config
.speed
== SPEED_1000
) {
2947 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2949 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2950 new_adv
= MII_TG3_CTRL_ADV_1000_FULL
;
2952 new_adv
= MII_TG3_CTRL_ADV_1000_HALF
;
2953 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2954 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
2955 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2956 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2958 if (tp
->link_config
.speed
== SPEED_100
) {
2959 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2960 new_adv
|= ADVERTISE_100FULL
;
2962 new_adv
|= ADVERTISE_100HALF
;
2964 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2965 new_adv
|= ADVERTISE_10FULL
;
2967 new_adv
|= ADVERTISE_10HALF
;
2969 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2974 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2977 if (tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
) {
2980 tw32(TG3_CPMU_EEE_MODE
,
2981 tr32(TG3_CPMU_EEE_MODE
) & ~TG3_CPMU_EEEMD_LPI_ENABLE
);
2983 /* Enable SM_DSP clock and tx 6dB coding. */
2984 val
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
2985 MII_TG3_AUXCTL_ACTL_SMDSP_ENA
|
2986 MII_TG3_AUXCTL_ACTL_TX_6DB
;
2987 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, val
);
2989 switch (GET_ASIC_REV(tp
->pci_chip_rev_id
)) {
2991 case ASIC_REV_57765
:
2992 if (!tg3_phydsp_read(tp
, MII_TG3_DSP_CH34TP2
, &val
))
2993 tg3_phydsp_write(tp
, MII_TG3_DSP_CH34TP2
, val
|
2994 MII_TG3_DSP_CH34TP2_HIBW01
);
2997 val
= MII_TG3_DSP_TAP26_ALNOKO
|
2998 MII_TG3_DSP_TAP26_RMRXSTO
|
2999 MII_TG3_DSP_TAP26_OPCSINPT
;
3000 tg3_phydsp_write(tp
, MII_TG3_DSP_TAP26
, val
);
3004 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3005 /* Advertise 100-BaseTX EEE ability */
3006 if (tp
->link_config
.advertising
&
3007 ADVERTISED_100baseT_Full
)
3008 val
|= MDIO_AN_EEE_ADV_100TX
;
3009 /* Advertise 1000-BaseT EEE ability */
3010 if (tp
->link_config
.advertising
&
3011 ADVERTISED_1000baseT_Full
)
3012 val
|= MDIO_AN_EEE_ADV_1000T
;
3014 tg3_phy_cl45_write(tp
, MDIO_MMD_AN
, MDIO_AN_EEE_ADV
, val
);
3016 /* Turn off SM_DSP clock. */
3017 val
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
3018 MII_TG3_AUXCTL_ACTL_TX_6DB
;
3019 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, val
);
3022 if (tp
->link_config
.autoneg
== AUTONEG_DISABLE
&&
3023 tp
->link_config
.speed
!= SPEED_INVALID
) {
3024 u32 bmcr
, orig_bmcr
;
3026 tp
->link_config
.active_speed
= tp
->link_config
.speed
;
3027 tp
->link_config
.active_duplex
= tp
->link_config
.duplex
;
3030 switch (tp
->link_config
.speed
) {
3036 bmcr
|= BMCR_SPEED100
;
3040 bmcr
|= TG3_BMCR_SPEED1000
;
3044 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
3045 bmcr
|= BMCR_FULLDPLX
;
3047 if (!tg3_readphy(tp
, MII_BMCR
, &orig_bmcr
) &&
3048 (bmcr
!= orig_bmcr
)) {
3049 tg3_writephy(tp
, MII_BMCR
, BMCR_LOOPBACK
);
3050 for (i
= 0; i
< 1500; i
++) {
3054 if (tg3_readphy(tp
, MII_BMSR
, &tmp
) ||
3055 tg3_readphy(tp
, MII_BMSR
, &tmp
))
3057 if (!(tmp
& BMSR_LSTATUS
)) {
3062 tg3_writephy(tp
, MII_BMCR
, bmcr
);
3066 tg3_writephy(tp
, MII_BMCR
,
3067 BMCR_ANENABLE
| BMCR_ANRESTART
);
3071 static int tg3_init_5401phy_dsp(struct tg3
*tp
)
3075 /* Turn off tap power management. */
3076 /* Set Extended packet length bit */
3077 err
= tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
3079 err
|= tg3_phydsp_write(tp
, 0x0012, 0x1804);
3080 err
|= tg3_phydsp_write(tp
, 0x0013, 0x1204);
3081 err
|= tg3_phydsp_write(tp
, 0x8006, 0x0132);
3082 err
|= tg3_phydsp_write(tp
, 0x8006, 0x0232);
3083 err
|= tg3_phydsp_write(tp
, 0x201f, 0x0a20);
3090 static int tg3_copper_is_advertising_all(struct tg3
*tp
, u32 mask
)
3092 u32 adv_reg
, all_mask
= 0;
3094 if (mask
& ADVERTISED_10baseT_Half
)
3095 all_mask
|= ADVERTISE_10HALF
;
3096 if (mask
& ADVERTISED_10baseT_Full
)
3097 all_mask
|= ADVERTISE_10FULL
;
3098 if (mask
& ADVERTISED_100baseT_Half
)
3099 all_mask
|= ADVERTISE_100HALF
;
3100 if (mask
& ADVERTISED_100baseT_Full
)
3101 all_mask
|= ADVERTISE_100FULL
;
3103 if (tg3_readphy(tp
, MII_ADVERTISE
, &adv_reg
))
3106 if ((adv_reg
& all_mask
) != all_mask
)
3108 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
3112 if (mask
& ADVERTISED_1000baseT_Half
)
3113 all_mask
|= ADVERTISE_1000HALF
;
3114 if (mask
& ADVERTISED_1000baseT_Full
)
3115 all_mask
|= ADVERTISE_1000FULL
;
3117 if (tg3_readphy(tp
, MII_TG3_CTRL
, &tg3_ctrl
))
3120 if ((tg3_ctrl
& all_mask
) != all_mask
)
3126 static int tg3_adv_1000T_flowctrl_ok(struct tg3
*tp
, u32
*lcladv
, u32
*rmtadv
)
3130 if (tg3_readphy(tp
, MII_ADVERTISE
, lcladv
))
3133 curadv
= *lcladv
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
3134 reqadv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
3136 if (tp
->link_config
.active_duplex
== DUPLEX_FULL
) {
3137 if (curadv
!= reqadv
)
3140 if (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)
3141 tg3_readphy(tp
, MII_LPA
, rmtadv
);
3143 /* Reprogram the advertisement register, even if it
3144 * does not affect the current link. If the link
3145 * gets renegotiated in the future, we can save an
3146 * additional renegotiation cycle by advertising
3147 * it correctly in the first place.
3149 if (curadv
!= reqadv
) {
3150 *lcladv
&= ~(ADVERTISE_PAUSE_CAP
|
3151 ADVERTISE_PAUSE_ASYM
);
3152 tg3_writephy(tp
, MII_ADVERTISE
, *lcladv
| reqadv
);
3159 static int tg3_setup_copper_phy(struct tg3
*tp
, int force_reset
)
3161 int current_link_up
;
3163 u32 lcl_adv
, rmt_adv
;
3171 (MAC_STATUS_SYNC_CHANGED
|
3172 MAC_STATUS_CFG_CHANGED
|
3173 MAC_STATUS_MI_COMPLETION
|
3174 MAC_STATUS_LNKSTATE_CHANGED
));
3177 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
3179 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
3183 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x02);
3185 /* Some third-party PHYs need to be reset on link going
3188 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
3189 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
3190 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
3191 netif_carrier_ok(tp
->dev
)) {
3192 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3193 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3194 !(bmsr
& BMSR_LSTATUS
))
3200 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
3201 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3202 if (tg3_readphy(tp
, MII_BMSR
, &bmsr
) ||
3203 !(tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
))
3206 if (!(bmsr
& BMSR_LSTATUS
)) {
3207 err
= tg3_init_5401phy_dsp(tp
);
3211 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3212 for (i
= 0; i
< 1000; i
++) {
3214 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3215 (bmsr
& BMSR_LSTATUS
)) {
3221 if ((tp
->phy_id
& TG3_PHY_ID_REV_MASK
) ==
3222 TG3_PHY_REV_BCM5401_B0
&&
3223 !(bmsr
& BMSR_LSTATUS
) &&
3224 tp
->link_config
.active_speed
== SPEED_1000
) {
3225 err
= tg3_phy_reset(tp
);
3227 err
= tg3_init_5401phy_dsp(tp
);
3232 } else if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
3233 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
) {
3234 /* 5701 {A0,B0} CRC bug workaround */
3235 tg3_writephy(tp
, 0x15, 0x0a75);
3236 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8c68);
3237 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8d68);
3238 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8c68);
3241 /* Clear pending interrupts... */
3242 tg3_readphy(tp
, MII_TG3_ISTAT
, &val
);
3243 tg3_readphy(tp
, MII_TG3_ISTAT
, &val
);
3245 if (tp
->phy_flags
& TG3_PHYFLG_USE_MI_INTERRUPT
)
3246 tg3_writephy(tp
, MII_TG3_IMASK
, ~MII_TG3_INT_LINKCHG
);
3247 else if (!(tp
->phy_flags
& TG3_PHYFLG_IS_FET
))
3248 tg3_writephy(tp
, MII_TG3_IMASK
, ~0);
3250 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
3251 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
3252 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_1
)
3253 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
3254 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
3256 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, 0);
3259 current_link_up
= 0;
3260 current_speed
= SPEED_INVALID
;
3261 current_duplex
= DUPLEX_INVALID
;
3263 if (tp
->phy_flags
& TG3_PHYFLG_CAPACITIVE_COUPLING
) {
3264 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4007);
3265 tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
);
3266 if (!(val
& (1 << 10))) {
3268 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, val
);
3274 for (i
= 0; i
< 100; i
++) {
3275 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3276 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3277 (bmsr
& BMSR_LSTATUS
))
3282 if (bmsr
& BMSR_LSTATUS
) {
3285 tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
);
3286 for (i
= 0; i
< 2000; i
++) {
3288 if (!tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
) &&
3293 tg3_aux_stat_to_speed_duplex(tp
, aux_stat
,
3298 for (i
= 0; i
< 200; i
++) {
3299 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
3300 if (tg3_readphy(tp
, MII_BMCR
, &bmcr
))
3302 if (bmcr
&& bmcr
!= 0x7fff)
3310 tp
->link_config
.active_speed
= current_speed
;
3311 tp
->link_config
.active_duplex
= current_duplex
;
3313 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3314 if ((bmcr
& BMCR_ANENABLE
) &&
3315 tg3_copper_is_advertising_all(tp
,
3316 tp
->link_config
.advertising
)) {
3317 if (tg3_adv_1000T_flowctrl_ok(tp
, &lcl_adv
,
3319 current_link_up
= 1;
3322 if (!(bmcr
& BMCR_ANENABLE
) &&
3323 tp
->link_config
.speed
== current_speed
&&
3324 tp
->link_config
.duplex
== current_duplex
&&
3325 tp
->link_config
.flowctrl
==
3326 tp
->link_config
.active_flowctrl
) {
3327 current_link_up
= 1;
3331 if (current_link_up
== 1 &&
3332 tp
->link_config
.active_duplex
== DUPLEX_FULL
)
3333 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
3337 if (current_link_up
== 0 || (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)) {
3338 tg3_phy_copper_begin(tp
);
3340 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3341 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3342 (bmsr
& BMSR_LSTATUS
))
3343 current_link_up
= 1;
3346 tp
->mac_mode
&= ~MAC_MODE_PORT_MODE_MASK
;
3347 if (current_link_up
== 1) {
3348 if (tp
->link_config
.active_speed
== SPEED_100
||
3349 tp
->link_config
.active_speed
== SPEED_10
)
3350 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
3352 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3353 } else if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
)
3354 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
3356 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3358 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
3359 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
3360 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
3362 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
3363 if (current_link_up
== 1 &&
3364 tg3_5700_link_polarity(tp
, tp
->link_config
.active_speed
))
3365 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
3367 tp
->mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
3370 /* ??? Without this setting Netgear GA302T PHY does not
3371 * ??? send/receive packets...
3373 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5411
&&
3374 tp
->pci_chip_rev_id
== CHIPREV_ID_5700_ALTIMA
) {
3375 tp
->mi_mode
|= MAC_MI_MODE_AUTO_POLL
;
3376 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
3380 tw32_f(MAC_MODE
, tp
->mac_mode
);
3383 tg3_phy_eee_adjust(tp
, current_link_up
);
3385 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
3386 /* Polled via timer. */
3387 tw32_f(MAC_EVENT
, 0);
3389 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3393 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
&&
3394 current_link_up
== 1 &&
3395 tp
->link_config
.active_speed
== SPEED_1000
&&
3396 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) ||
3397 (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
))) {
3400 (MAC_STATUS_SYNC_CHANGED
|
3401 MAC_STATUS_CFG_CHANGED
));
3404 NIC_SRAM_FIRMWARE_MBOX
,
3405 NIC_SRAM_FIRMWARE_MBOX_MAGIC2
);
3408 /* Prevent send BD corruption. */
3409 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
3410 u16 oldlnkctl
, newlnkctl
;
3412 pci_read_config_word(tp
->pdev
,
3413 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
3415 if (tp
->link_config
.active_speed
== SPEED_100
||
3416 tp
->link_config
.active_speed
== SPEED_10
)
3417 newlnkctl
= oldlnkctl
& ~PCI_EXP_LNKCTL_CLKREQ_EN
;
3419 newlnkctl
= oldlnkctl
| PCI_EXP_LNKCTL_CLKREQ_EN
;
3420 if (newlnkctl
!= oldlnkctl
)
3421 pci_write_config_word(tp
->pdev
,
3422 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
3426 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
3427 if (current_link_up
)
3428 netif_carrier_on(tp
->dev
);
3430 netif_carrier_off(tp
->dev
);
3431 tg3_link_report(tp
);
3437 struct tg3_fiber_aneginfo
{
3439 #define ANEG_STATE_UNKNOWN 0
3440 #define ANEG_STATE_AN_ENABLE 1
3441 #define ANEG_STATE_RESTART_INIT 2
3442 #define ANEG_STATE_RESTART 3
3443 #define ANEG_STATE_DISABLE_LINK_OK 4
3444 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3445 #define ANEG_STATE_ABILITY_DETECT 6
3446 #define ANEG_STATE_ACK_DETECT_INIT 7
3447 #define ANEG_STATE_ACK_DETECT 8
3448 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3449 #define ANEG_STATE_COMPLETE_ACK 10
3450 #define ANEG_STATE_IDLE_DETECT_INIT 11
3451 #define ANEG_STATE_IDLE_DETECT 12
3452 #define ANEG_STATE_LINK_OK 13
3453 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3454 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3457 #define MR_AN_ENABLE 0x00000001
3458 #define MR_RESTART_AN 0x00000002
3459 #define MR_AN_COMPLETE 0x00000004
3460 #define MR_PAGE_RX 0x00000008
3461 #define MR_NP_LOADED 0x00000010
3462 #define MR_TOGGLE_TX 0x00000020
3463 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3464 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3465 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3466 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3467 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3468 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3469 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3470 #define MR_TOGGLE_RX 0x00002000
3471 #define MR_NP_RX 0x00004000
3473 #define MR_LINK_OK 0x80000000
3475 unsigned long link_time
, cur_time
;
3477 u32 ability_match_cfg
;
3478 int ability_match_count
;
3480 char ability_match
, idle_match
, ack_match
;
3482 u32 txconfig
, rxconfig
;
3483 #define ANEG_CFG_NP 0x00000080
3484 #define ANEG_CFG_ACK 0x00000040
3485 #define ANEG_CFG_RF2 0x00000020
3486 #define ANEG_CFG_RF1 0x00000010
3487 #define ANEG_CFG_PS2 0x00000001
3488 #define ANEG_CFG_PS1 0x00008000
3489 #define ANEG_CFG_HD 0x00004000
3490 #define ANEG_CFG_FD 0x00002000
3491 #define ANEG_CFG_INVAL 0x00001f06
3496 #define ANEG_TIMER_ENAB 2
3497 #define ANEG_FAILED -1
3499 #define ANEG_STATE_SETTLE_TIME 10000
3501 static int tg3_fiber_aneg_smachine(struct tg3
*tp
,
3502 struct tg3_fiber_aneginfo
*ap
)
3505 unsigned long delta
;
3509 if (ap
->state
== ANEG_STATE_UNKNOWN
) {
3513 ap
->ability_match_cfg
= 0;
3514 ap
->ability_match_count
= 0;
3515 ap
->ability_match
= 0;
3521 if (tr32(MAC_STATUS
) & MAC_STATUS_RCVD_CFG
) {
3522 rx_cfg_reg
= tr32(MAC_RX_AUTO_NEG
);
3524 if (rx_cfg_reg
!= ap
->ability_match_cfg
) {
3525 ap
->ability_match_cfg
= rx_cfg_reg
;
3526 ap
->ability_match
= 0;
3527 ap
->ability_match_count
= 0;
3529 if (++ap
->ability_match_count
> 1) {
3530 ap
->ability_match
= 1;
3531 ap
->ability_match_cfg
= rx_cfg_reg
;
3534 if (rx_cfg_reg
& ANEG_CFG_ACK
)
3542 ap
->ability_match_cfg
= 0;
3543 ap
->ability_match_count
= 0;
3544 ap
->ability_match
= 0;
3550 ap
->rxconfig
= rx_cfg_reg
;
3553 switch (ap
->state
) {
3554 case ANEG_STATE_UNKNOWN
:
3555 if (ap
->flags
& (MR_AN_ENABLE
| MR_RESTART_AN
))
3556 ap
->state
= ANEG_STATE_AN_ENABLE
;
3559 case ANEG_STATE_AN_ENABLE
:
3560 ap
->flags
&= ~(MR_AN_COMPLETE
| MR_PAGE_RX
);
3561 if (ap
->flags
& MR_AN_ENABLE
) {
3564 ap
->ability_match_cfg
= 0;
3565 ap
->ability_match_count
= 0;
3566 ap
->ability_match
= 0;
3570 ap
->state
= ANEG_STATE_RESTART_INIT
;
3572 ap
->state
= ANEG_STATE_DISABLE_LINK_OK
;
3576 case ANEG_STATE_RESTART_INIT
:
3577 ap
->link_time
= ap
->cur_time
;
3578 ap
->flags
&= ~(MR_NP_LOADED
);
3580 tw32(MAC_TX_AUTO_NEG
, 0);
3581 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3582 tw32_f(MAC_MODE
, tp
->mac_mode
);
3585 ret
= ANEG_TIMER_ENAB
;
3586 ap
->state
= ANEG_STATE_RESTART
;
3589 case ANEG_STATE_RESTART
:
3590 delta
= ap
->cur_time
- ap
->link_time
;
3591 if (delta
> ANEG_STATE_SETTLE_TIME
)
3592 ap
->state
= ANEG_STATE_ABILITY_DETECT_INIT
;
3594 ret
= ANEG_TIMER_ENAB
;
3597 case ANEG_STATE_DISABLE_LINK_OK
:
3601 case ANEG_STATE_ABILITY_DETECT_INIT
:
3602 ap
->flags
&= ~(MR_TOGGLE_TX
);
3603 ap
->txconfig
= ANEG_CFG_FD
;
3604 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3605 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3606 ap
->txconfig
|= ANEG_CFG_PS1
;
3607 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3608 ap
->txconfig
|= ANEG_CFG_PS2
;
3609 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3610 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3611 tw32_f(MAC_MODE
, tp
->mac_mode
);
3614 ap
->state
= ANEG_STATE_ABILITY_DETECT
;
3617 case ANEG_STATE_ABILITY_DETECT
:
3618 if (ap
->ability_match
!= 0 && ap
->rxconfig
!= 0)
3619 ap
->state
= ANEG_STATE_ACK_DETECT_INIT
;
3622 case ANEG_STATE_ACK_DETECT_INIT
:
3623 ap
->txconfig
|= ANEG_CFG_ACK
;
3624 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3625 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3626 tw32_f(MAC_MODE
, tp
->mac_mode
);
3629 ap
->state
= ANEG_STATE_ACK_DETECT
;
3632 case ANEG_STATE_ACK_DETECT
:
3633 if (ap
->ack_match
!= 0) {
3634 if ((ap
->rxconfig
& ~ANEG_CFG_ACK
) ==
3635 (ap
->ability_match_cfg
& ~ANEG_CFG_ACK
)) {
3636 ap
->state
= ANEG_STATE_COMPLETE_ACK_INIT
;
3638 ap
->state
= ANEG_STATE_AN_ENABLE
;
3640 } else if (ap
->ability_match
!= 0 &&
3641 ap
->rxconfig
== 0) {
3642 ap
->state
= ANEG_STATE_AN_ENABLE
;
3646 case ANEG_STATE_COMPLETE_ACK_INIT
:
3647 if (ap
->rxconfig
& ANEG_CFG_INVAL
) {
3651 ap
->flags
&= ~(MR_LP_ADV_FULL_DUPLEX
|
3652 MR_LP_ADV_HALF_DUPLEX
|
3653 MR_LP_ADV_SYM_PAUSE
|
3654 MR_LP_ADV_ASYM_PAUSE
|
3655 MR_LP_ADV_REMOTE_FAULT1
|
3656 MR_LP_ADV_REMOTE_FAULT2
|
3657 MR_LP_ADV_NEXT_PAGE
|
3660 if (ap
->rxconfig
& ANEG_CFG_FD
)
3661 ap
->flags
|= MR_LP_ADV_FULL_DUPLEX
;
3662 if (ap
->rxconfig
& ANEG_CFG_HD
)
3663 ap
->flags
|= MR_LP_ADV_HALF_DUPLEX
;
3664 if (ap
->rxconfig
& ANEG_CFG_PS1
)
3665 ap
->flags
|= MR_LP_ADV_SYM_PAUSE
;
3666 if (ap
->rxconfig
& ANEG_CFG_PS2
)
3667 ap
->flags
|= MR_LP_ADV_ASYM_PAUSE
;
3668 if (ap
->rxconfig
& ANEG_CFG_RF1
)
3669 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT1
;
3670 if (ap
->rxconfig
& ANEG_CFG_RF2
)
3671 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT2
;
3672 if (ap
->rxconfig
& ANEG_CFG_NP
)
3673 ap
->flags
|= MR_LP_ADV_NEXT_PAGE
;
3675 ap
->link_time
= ap
->cur_time
;
3677 ap
->flags
^= (MR_TOGGLE_TX
);
3678 if (ap
->rxconfig
& 0x0008)
3679 ap
->flags
|= MR_TOGGLE_RX
;
3680 if (ap
->rxconfig
& ANEG_CFG_NP
)
3681 ap
->flags
|= MR_NP_RX
;
3682 ap
->flags
|= MR_PAGE_RX
;
3684 ap
->state
= ANEG_STATE_COMPLETE_ACK
;
3685 ret
= ANEG_TIMER_ENAB
;
3688 case ANEG_STATE_COMPLETE_ACK
:
3689 if (ap
->ability_match
!= 0 &&
3690 ap
->rxconfig
== 0) {
3691 ap
->state
= ANEG_STATE_AN_ENABLE
;
3694 delta
= ap
->cur_time
- ap
->link_time
;
3695 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3696 if (!(ap
->flags
& (MR_LP_ADV_NEXT_PAGE
))) {
3697 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3699 if ((ap
->txconfig
& ANEG_CFG_NP
) == 0 &&
3700 !(ap
->flags
& MR_NP_RX
)) {
3701 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3709 case ANEG_STATE_IDLE_DETECT_INIT
:
3710 ap
->link_time
= ap
->cur_time
;
3711 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3712 tw32_f(MAC_MODE
, tp
->mac_mode
);
3715 ap
->state
= ANEG_STATE_IDLE_DETECT
;
3716 ret
= ANEG_TIMER_ENAB
;
3719 case ANEG_STATE_IDLE_DETECT
:
3720 if (ap
->ability_match
!= 0 &&
3721 ap
->rxconfig
== 0) {
3722 ap
->state
= ANEG_STATE_AN_ENABLE
;
3725 delta
= ap
->cur_time
- ap
->link_time
;
3726 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3727 /* XXX another gem from the Broadcom driver :( */
3728 ap
->state
= ANEG_STATE_LINK_OK
;
3732 case ANEG_STATE_LINK_OK
:
3733 ap
->flags
|= (MR_AN_COMPLETE
| MR_LINK_OK
);
3737 case ANEG_STATE_NEXT_PAGE_WAIT_INIT
:
3738 /* ??? unimplemented */
3741 case ANEG_STATE_NEXT_PAGE_WAIT
:
3742 /* ??? unimplemented */
3753 static int fiber_autoneg(struct tg3
*tp
, u32
*txflags
, u32
*rxflags
)
3756 struct tg3_fiber_aneginfo aninfo
;
3757 int status
= ANEG_FAILED
;
3761 tw32_f(MAC_TX_AUTO_NEG
, 0);
3763 tmp
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
3764 tw32_f(MAC_MODE
, tmp
| MAC_MODE_PORT_MODE_GMII
);
3767 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
);
3770 memset(&aninfo
, 0, sizeof(aninfo
));
3771 aninfo
.flags
|= MR_AN_ENABLE
;
3772 aninfo
.state
= ANEG_STATE_UNKNOWN
;
3773 aninfo
.cur_time
= 0;
3775 while (++tick
< 195000) {
3776 status
= tg3_fiber_aneg_smachine(tp
, &aninfo
);
3777 if (status
== ANEG_DONE
|| status
== ANEG_FAILED
)
3783 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3784 tw32_f(MAC_MODE
, tp
->mac_mode
);
3787 *txflags
= aninfo
.txconfig
;
3788 *rxflags
= aninfo
.flags
;
3790 if (status
== ANEG_DONE
&&
3791 (aninfo
.flags
& (MR_AN_COMPLETE
| MR_LINK_OK
|
3792 MR_LP_ADV_FULL_DUPLEX
)))
3798 static void tg3_init_bcm8002(struct tg3
*tp
)
3800 u32 mac_status
= tr32(MAC_STATUS
);
3803 /* Reset when initting first time or we have a link. */
3804 if ((tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) &&
3805 !(mac_status
& MAC_STATUS_PCS_SYNCED
))
3808 /* Set PLL lock range. */
3809 tg3_writephy(tp
, 0x16, 0x8007);
3812 tg3_writephy(tp
, MII_BMCR
, BMCR_RESET
);
3814 /* Wait for reset to complete. */
3815 /* XXX schedule_timeout() ... */
3816 for (i
= 0; i
< 500; i
++)
3819 /* Config mode; select PMA/Ch 1 regs. */
3820 tg3_writephy(tp
, 0x10, 0x8411);
3822 /* Enable auto-lock and comdet, select txclk for tx. */
3823 tg3_writephy(tp
, 0x11, 0x0a10);
3825 tg3_writephy(tp
, 0x18, 0x00a0);
3826 tg3_writephy(tp
, 0x16, 0x41ff);
3828 /* Assert and deassert POR. */
3829 tg3_writephy(tp
, 0x13, 0x0400);
3831 tg3_writephy(tp
, 0x13, 0x0000);
3833 tg3_writephy(tp
, 0x11, 0x0a50);
3835 tg3_writephy(tp
, 0x11, 0x0a10);
3837 /* Wait for signal to stabilize */
3838 /* XXX schedule_timeout() ... */
3839 for (i
= 0; i
< 15000; i
++)
3842 /* Deselect the channel register so we can read the PHYID
3845 tg3_writephy(tp
, 0x10, 0x8011);
3848 static int tg3_setup_fiber_hw_autoneg(struct tg3
*tp
, u32 mac_status
)
3851 u32 sg_dig_ctrl
, sg_dig_status
;
3852 u32 serdes_cfg
, expected_sg_dig_ctrl
;
3853 int workaround
, port_a
;
3854 int current_link_up
;
3857 expected_sg_dig_ctrl
= 0;
3860 current_link_up
= 0;
3862 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A0
&&
3863 tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A1
) {
3865 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
3868 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3869 /* preserve bits 20-23 for voltage regulator */
3870 serdes_cfg
= tr32(MAC_SERDES_CFG
) & 0x00f06fff;
3873 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
3875 if (tp
->link_config
.autoneg
!= AUTONEG_ENABLE
) {
3876 if (sg_dig_ctrl
& SG_DIG_USING_HW_AUTONEG
) {
3878 u32 val
= serdes_cfg
;
3884 tw32_f(MAC_SERDES_CFG
, val
);
3887 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3889 if (mac_status
& MAC_STATUS_PCS_SYNCED
) {
3890 tg3_setup_flow_control(tp
, 0, 0);
3891 current_link_up
= 1;
3896 /* Want auto-negotiation. */
3897 expected_sg_dig_ctrl
= SG_DIG_USING_HW_AUTONEG
| SG_DIG_COMMON_SETUP
;
3899 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3900 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3901 expected_sg_dig_ctrl
|= SG_DIG_PAUSE_CAP
;
3902 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3903 expected_sg_dig_ctrl
|= SG_DIG_ASYM_PAUSE
;
3905 if (sg_dig_ctrl
!= expected_sg_dig_ctrl
) {
3906 if ((tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
) &&
3907 tp
->serdes_counter
&&
3908 ((mac_status
& (MAC_STATUS_PCS_SYNCED
|
3909 MAC_STATUS_RCVD_CFG
)) ==
3910 MAC_STATUS_PCS_SYNCED
)) {
3911 tp
->serdes_counter
--;
3912 current_link_up
= 1;
3917 tw32_f(MAC_SERDES_CFG
, serdes_cfg
| 0xc011000);
3918 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
| SG_DIG_SOFT_RESET
);
3920 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
);
3922 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3923 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
3924 } else if (mac_status
& (MAC_STATUS_PCS_SYNCED
|
3925 MAC_STATUS_SIGNAL_DET
)) {
3926 sg_dig_status
= tr32(SG_DIG_STATUS
);
3927 mac_status
= tr32(MAC_STATUS
);
3929 if ((sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
) &&
3930 (mac_status
& MAC_STATUS_PCS_SYNCED
)) {
3931 u32 local_adv
= 0, remote_adv
= 0;
3933 if (sg_dig_ctrl
& SG_DIG_PAUSE_CAP
)
3934 local_adv
|= ADVERTISE_1000XPAUSE
;
3935 if (sg_dig_ctrl
& SG_DIG_ASYM_PAUSE
)
3936 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
3938 if (sg_dig_status
& SG_DIG_PARTNER_PAUSE_CAPABLE
)
3939 remote_adv
|= LPA_1000XPAUSE
;
3940 if (sg_dig_status
& SG_DIG_PARTNER_ASYM_PAUSE
)
3941 remote_adv
|= LPA_1000XPAUSE_ASYM
;
3943 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3944 current_link_up
= 1;
3945 tp
->serdes_counter
= 0;
3946 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
3947 } else if (!(sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
)) {
3948 if (tp
->serdes_counter
)
3949 tp
->serdes_counter
--;
3952 u32 val
= serdes_cfg
;
3959 tw32_f(MAC_SERDES_CFG
, val
);
3962 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3965 /* Link parallel detection - link is up */
3966 /* only if we have PCS_SYNC and not */
3967 /* receiving config code words */
3968 mac_status
= tr32(MAC_STATUS
);
3969 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) &&
3970 !(mac_status
& MAC_STATUS_RCVD_CFG
)) {
3971 tg3_setup_flow_control(tp
, 0, 0);
3972 current_link_up
= 1;
3974 TG3_PHYFLG_PARALLEL_DETECT
;
3975 tp
->serdes_counter
=
3976 SERDES_PARALLEL_DET_TIMEOUT
;
3978 goto restart_autoneg
;
3982 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3983 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
3987 return current_link_up
;
3990 static int tg3_setup_fiber_by_hand(struct tg3
*tp
, u32 mac_status
)
3992 int current_link_up
= 0;
3994 if (!(mac_status
& MAC_STATUS_PCS_SYNCED
))
3997 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3998 u32 txflags
, rxflags
;
4001 if (fiber_autoneg(tp
, &txflags
, &rxflags
)) {
4002 u32 local_adv
= 0, remote_adv
= 0;
4004 if (txflags
& ANEG_CFG_PS1
)
4005 local_adv
|= ADVERTISE_1000XPAUSE
;
4006 if (txflags
& ANEG_CFG_PS2
)
4007 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
4009 if (rxflags
& MR_LP_ADV_SYM_PAUSE
)
4010 remote_adv
|= LPA_1000XPAUSE
;
4011 if (rxflags
& MR_LP_ADV_ASYM_PAUSE
)
4012 remote_adv
|= LPA_1000XPAUSE_ASYM
;
4014 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
4016 current_link_up
= 1;
4018 for (i
= 0; i
< 30; i
++) {
4021 (MAC_STATUS_SYNC_CHANGED
|
4022 MAC_STATUS_CFG_CHANGED
));
4024 if ((tr32(MAC_STATUS
) &
4025 (MAC_STATUS_SYNC_CHANGED
|
4026 MAC_STATUS_CFG_CHANGED
)) == 0)
4030 mac_status
= tr32(MAC_STATUS
);
4031 if (current_link_up
== 0 &&
4032 (mac_status
& MAC_STATUS_PCS_SYNCED
) &&
4033 !(mac_status
& MAC_STATUS_RCVD_CFG
))
4034 current_link_up
= 1;
4036 tg3_setup_flow_control(tp
, 0, 0);
4038 /* Forcing 1000FD link up. */
4039 current_link_up
= 1;
4041 tw32_f(MAC_MODE
, (tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
));
4044 tw32_f(MAC_MODE
, tp
->mac_mode
);
4049 return current_link_up
;
4052 static int tg3_setup_fiber_phy(struct tg3
*tp
, int force_reset
)
4055 u16 orig_active_speed
;
4056 u8 orig_active_duplex
;
4058 int current_link_up
;
4061 orig_pause_cfg
= tp
->link_config
.active_flowctrl
;
4062 orig_active_speed
= tp
->link_config
.active_speed
;
4063 orig_active_duplex
= tp
->link_config
.active_duplex
;
4065 if (!(tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
) &&
4066 netif_carrier_ok(tp
->dev
) &&
4067 (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)) {
4068 mac_status
= tr32(MAC_STATUS
);
4069 mac_status
&= (MAC_STATUS_PCS_SYNCED
|
4070 MAC_STATUS_SIGNAL_DET
|
4071 MAC_STATUS_CFG_CHANGED
|
4072 MAC_STATUS_RCVD_CFG
);
4073 if (mac_status
== (MAC_STATUS_PCS_SYNCED
|
4074 MAC_STATUS_SIGNAL_DET
)) {
4075 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
4076 MAC_STATUS_CFG_CHANGED
));
4081 tw32_f(MAC_TX_AUTO_NEG
, 0);
4083 tp
->mac_mode
&= ~(MAC_MODE_PORT_MODE_MASK
| MAC_MODE_HALF_DUPLEX
);
4084 tp
->mac_mode
|= MAC_MODE_PORT_MODE_TBI
;
4085 tw32_f(MAC_MODE
, tp
->mac_mode
);
4088 if (tp
->phy_id
== TG3_PHY_ID_BCM8002
)
4089 tg3_init_bcm8002(tp
);
4091 /* Enable link change event even when serdes polling. */
4092 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4095 current_link_up
= 0;
4096 mac_status
= tr32(MAC_STATUS
);
4098 if (tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
)
4099 current_link_up
= tg3_setup_fiber_hw_autoneg(tp
, mac_status
);
4101 current_link_up
= tg3_setup_fiber_by_hand(tp
, mac_status
);
4103 tp
->napi
[0].hw_status
->status
=
4104 (SD_STATUS_UPDATED
|
4105 (tp
->napi
[0].hw_status
->status
& ~SD_STATUS_LINK_CHG
));
4107 for (i
= 0; i
< 100; i
++) {
4108 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
4109 MAC_STATUS_CFG_CHANGED
));
4111 if ((tr32(MAC_STATUS
) & (MAC_STATUS_SYNC_CHANGED
|
4112 MAC_STATUS_CFG_CHANGED
|
4113 MAC_STATUS_LNKSTATE_CHANGED
)) == 0)
4117 mac_status
= tr32(MAC_STATUS
);
4118 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) == 0) {
4119 current_link_up
= 0;
4120 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
&&
4121 tp
->serdes_counter
== 0) {
4122 tw32_f(MAC_MODE
, (tp
->mac_mode
|
4123 MAC_MODE_SEND_CONFIGS
));
4125 tw32_f(MAC_MODE
, tp
->mac_mode
);
4129 if (current_link_up
== 1) {
4130 tp
->link_config
.active_speed
= SPEED_1000
;
4131 tp
->link_config
.active_duplex
= DUPLEX_FULL
;
4132 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
4133 LED_CTRL_LNKLED_OVERRIDE
|
4134 LED_CTRL_1000MBPS_ON
));
4136 tp
->link_config
.active_speed
= SPEED_INVALID
;
4137 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
4138 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
4139 LED_CTRL_LNKLED_OVERRIDE
|
4140 LED_CTRL_TRAFFIC_OVERRIDE
));
4143 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
4144 if (current_link_up
)
4145 netif_carrier_on(tp
->dev
);
4147 netif_carrier_off(tp
->dev
);
4148 tg3_link_report(tp
);
4150 u32 now_pause_cfg
= tp
->link_config
.active_flowctrl
;
4151 if (orig_pause_cfg
!= now_pause_cfg
||
4152 orig_active_speed
!= tp
->link_config
.active_speed
||
4153 orig_active_duplex
!= tp
->link_config
.active_duplex
)
4154 tg3_link_report(tp
);
4160 static int tg3_setup_fiber_mii_phy(struct tg3
*tp
, int force_reset
)
4162 int current_link_up
, err
= 0;
4166 u32 local_adv
, remote_adv
;
4168 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
4169 tw32_f(MAC_MODE
, tp
->mac_mode
);
4175 (MAC_STATUS_SYNC_CHANGED
|
4176 MAC_STATUS_CFG_CHANGED
|
4177 MAC_STATUS_MI_COMPLETION
|
4178 MAC_STATUS_LNKSTATE_CHANGED
));
4184 current_link_up
= 0;
4185 current_speed
= SPEED_INVALID
;
4186 current_duplex
= DUPLEX_INVALID
;
4188 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4189 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4190 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
4191 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
4192 bmsr
|= BMSR_LSTATUS
;
4194 bmsr
&= ~BMSR_LSTATUS
;
4197 err
|= tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4199 if ((tp
->link_config
.autoneg
== AUTONEG_ENABLE
) && !force_reset
&&
4200 (tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
)) {
4201 /* do nothing, just check for link up at the end */
4202 } else if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
4205 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
4206 new_adv
= adv
& ~(ADVERTISE_1000XFULL
| ADVERTISE_1000XHALF
|
4207 ADVERTISE_1000XPAUSE
|
4208 ADVERTISE_1000XPSE_ASYM
|
4211 new_adv
|= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
4213 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
4214 new_adv
|= ADVERTISE_1000XHALF
;
4215 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
4216 new_adv
|= ADVERTISE_1000XFULL
;
4218 if ((new_adv
!= adv
) || !(bmcr
& BMCR_ANENABLE
)) {
4219 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
4220 bmcr
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
4221 tg3_writephy(tp
, MII_BMCR
, bmcr
);
4223 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4224 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5714S
;
4225 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
4232 bmcr
&= ~BMCR_SPEED1000
;
4233 new_bmcr
= bmcr
& ~(BMCR_ANENABLE
| BMCR_FULLDPLX
);
4235 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
4236 new_bmcr
|= BMCR_FULLDPLX
;
4238 if (new_bmcr
!= bmcr
) {
4239 /* BMCR_SPEED1000 is a reserved bit that needs
4240 * to be set on write.
4242 new_bmcr
|= BMCR_SPEED1000
;
4244 /* Force a linkdown */
4245 if (netif_carrier_ok(tp
->dev
)) {
4248 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
4249 adv
&= ~(ADVERTISE_1000XFULL
|
4250 ADVERTISE_1000XHALF
|
4252 tg3_writephy(tp
, MII_ADVERTISE
, adv
);
4253 tg3_writephy(tp
, MII_BMCR
, bmcr
|
4257 netif_carrier_off(tp
->dev
);
4259 tg3_writephy(tp
, MII_BMCR
, new_bmcr
);
4261 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4262 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4263 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
4265 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
4266 bmsr
|= BMSR_LSTATUS
;
4268 bmsr
&= ~BMSR_LSTATUS
;
4270 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
4274 if (bmsr
& BMSR_LSTATUS
) {
4275 current_speed
= SPEED_1000
;
4276 current_link_up
= 1;
4277 if (bmcr
& BMCR_FULLDPLX
)
4278 current_duplex
= DUPLEX_FULL
;
4280 current_duplex
= DUPLEX_HALF
;
4285 if (bmcr
& BMCR_ANENABLE
) {
4288 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &local_adv
);
4289 err
|= tg3_readphy(tp
, MII_LPA
, &remote_adv
);
4290 common
= local_adv
& remote_adv
;
4291 if (common
& (ADVERTISE_1000XHALF
|
4292 ADVERTISE_1000XFULL
)) {
4293 if (common
& ADVERTISE_1000XFULL
)
4294 current_duplex
= DUPLEX_FULL
;
4296 current_duplex
= DUPLEX_HALF
;
4297 } else if (!(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
4298 /* Link is up via parallel detect */
4300 current_link_up
= 0;
4305 if (current_link_up
== 1 && current_duplex
== DUPLEX_FULL
)
4306 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
4308 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
4309 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4310 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
4312 tw32_f(MAC_MODE
, tp
->mac_mode
);
4315 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4317 tp
->link_config
.active_speed
= current_speed
;
4318 tp
->link_config
.active_duplex
= current_duplex
;
4320 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
4321 if (current_link_up
)
4322 netif_carrier_on(tp
->dev
);
4324 netif_carrier_off(tp
->dev
);
4325 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
4327 tg3_link_report(tp
);
4332 static void tg3_serdes_parallel_detect(struct tg3
*tp
)
4334 if (tp
->serdes_counter
) {
4335 /* Give autoneg time to complete. */
4336 tp
->serdes_counter
--;
4340 if (!netif_carrier_ok(tp
->dev
) &&
4341 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
)) {
4344 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4345 if (bmcr
& BMCR_ANENABLE
) {
4348 /* Select shadow register 0x1f */
4349 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x7c00);
4350 tg3_readphy(tp
, MII_TG3_MISC_SHDW
, &phy1
);
4352 /* Select expansion interrupt status register */
4353 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
4354 MII_TG3_DSP_EXP1_INT_STAT
);
4355 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &phy2
);
4356 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &phy2
);
4358 if ((phy1
& 0x10) && !(phy2
& 0x20)) {
4359 /* We have signal detect and not receiving
4360 * config code words, link is up by parallel
4364 bmcr
&= ~BMCR_ANENABLE
;
4365 bmcr
|= BMCR_SPEED1000
| BMCR_FULLDPLX
;
4366 tg3_writephy(tp
, MII_BMCR
, bmcr
);
4367 tp
->phy_flags
|= TG3_PHYFLG_PARALLEL_DETECT
;
4370 } else if (netif_carrier_ok(tp
->dev
) &&
4371 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) &&
4372 (tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
)) {
4375 /* Select expansion interrupt status register */
4376 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
4377 MII_TG3_DSP_EXP1_INT_STAT
);
4378 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &phy2
);
4382 /* Config code words received, turn on autoneg. */
4383 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4384 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANENABLE
);
4386 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
4392 static int tg3_setup_phy(struct tg3
*tp
, int force_reset
)
4397 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
4398 err
= tg3_setup_fiber_phy(tp
, force_reset
);
4399 else if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)
4400 err
= tg3_setup_fiber_mii_phy(tp
, force_reset
);
4402 err
= tg3_setup_copper_phy(tp
, force_reset
);
4404 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
4407 val
= tr32(TG3_CPMU_CLCK_STAT
) & CPMU_CLCK_STAT_MAC_CLCK_MASK
;
4408 if (val
== CPMU_CLCK_STAT_MAC_CLCK_62_5
)
4410 else if (val
== CPMU_CLCK_STAT_MAC_CLCK_6_25
)
4415 val
= tr32(GRC_MISC_CFG
) & ~GRC_MISC_CFG_PRESCALAR_MASK
;
4416 val
|= (scale
<< GRC_MISC_CFG_PRESCALAR_SHIFT
);
4417 tw32(GRC_MISC_CFG
, val
);
4420 val
= (2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
4421 (6 << TX_LENGTHS_IPG_SHIFT
);
4422 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
)
4423 val
|= tr32(MAC_TX_LENGTHS
) &
4424 (TX_LENGTHS_JMB_FRM_LEN_MSK
|
4425 TX_LENGTHS_CNT_DWN_VAL_MSK
);
4427 if (tp
->link_config
.active_speed
== SPEED_1000
&&
4428 tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4429 tw32(MAC_TX_LENGTHS
, val
|
4430 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
));
4432 tw32(MAC_TX_LENGTHS
, val
|
4433 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
));
4435 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
4436 if (netif_carrier_ok(tp
->dev
)) {
4437 tw32(HOSTCC_STAT_COAL_TICKS
,
4438 tp
->coal
.stats_block_coalesce_usecs
);
4440 tw32(HOSTCC_STAT_COAL_TICKS
, 0);
4444 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
) {
4445 val
= tr32(PCIE_PWR_MGMT_THRESH
);
4446 if (!netif_carrier_ok(tp
->dev
))
4447 val
= (val
& ~PCIE_PWR_MGMT_L1_THRESH_MSK
) |
4450 val
|= PCIE_PWR_MGMT_L1_THRESH_MSK
;
4451 tw32(PCIE_PWR_MGMT_THRESH
, val
);
4457 static inline int tg3_irq_sync(struct tg3
*tp
)
4459 return tp
->irq_sync
;
4462 static inline void tg3_rd32_loop(struct tg3
*tp
, u32
*dst
, u32 off
, u32 len
)
4466 dst
= (u32
*)((u8
*)dst
+ off
);
4467 for (i
= 0; i
< len
; i
+= sizeof(u32
))
4468 *dst
++ = tr32(off
+ i
);
4471 static void tg3_dump_legacy_regs(struct tg3
*tp
, u32
*regs
)
4473 tg3_rd32_loop(tp
, regs
, TG3PCI_VENDOR
, 0xb0);
4474 tg3_rd32_loop(tp
, regs
, MAILBOX_INTERRUPT_0
, 0x200);
4475 tg3_rd32_loop(tp
, regs
, MAC_MODE
, 0x4f0);
4476 tg3_rd32_loop(tp
, regs
, SNDDATAI_MODE
, 0xe0);
4477 tg3_rd32_loop(tp
, regs
, SNDDATAC_MODE
, 0x04);
4478 tg3_rd32_loop(tp
, regs
, SNDBDS_MODE
, 0x80);
4479 tg3_rd32_loop(tp
, regs
, SNDBDI_MODE
, 0x48);
4480 tg3_rd32_loop(tp
, regs
, SNDBDC_MODE
, 0x04);
4481 tg3_rd32_loop(tp
, regs
, RCVLPC_MODE
, 0x20);
4482 tg3_rd32_loop(tp
, regs
, RCVLPC_SELLST_BASE
, 0x15c);
4483 tg3_rd32_loop(tp
, regs
, RCVDBDI_MODE
, 0x0c);
4484 tg3_rd32_loop(tp
, regs
, RCVDBDI_JUMBO_BD
, 0x3c);
4485 tg3_rd32_loop(tp
, regs
, RCVDBDI_BD_PROD_IDX_0
, 0x44);
4486 tg3_rd32_loop(tp
, regs
, RCVDCC_MODE
, 0x04);
4487 tg3_rd32_loop(tp
, regs
, RCVBDI_MODE
, 0x20);
4488 tg3_rd32_loop(tp
, regs
, RCVCC_MODE
, 0x14);
4489 tg3_rd32_loop(tp
, regs
, RCVLSC_MODE
, 0x08);
4490 tg3_rd32_loop(tp
, regs
, MBFREE_MODE
, 0x08);
4491 tg3_rd32_loop(tp
, regs
, HOSTCC_MODE
, 0x100);
4493 if (tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
)
4494 tg3_rd32_loop(tp
, regs
, HOSTCC_RXCOL_TICKS_VEC1
, 0x180);
4496 tg3_rd32_loop(tp
, regs
, MEMARB_MODE
, 0x10);
4497 tg3_rd32_loop(tp
, regs
, BUFMGR_MODE
, 0x58);
4498 tg3_rd32_loop(tp
, regs
, RDMAC_MODE
, 0x08);
4499 tg3_rd32_loop(tp
, regs
, WDMAC_MODE
, 0x08);
4500 tg3_rd32_loop(tp
, regs
, RX_CPU_MODE
, 0x04);
4501 tg3_rd32_loop(tp
, regs
, RX_CPU_STATE
, 0x04);
4502 tg3_rd32_loop(tp
, regs
, RX_CPU_PGMCTR
, 0x04);
4503 tg3_rd32_loop(tp
, regs
, RX_CPU_HWBKPT
, 0x04);
4505 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
4506 tg3_rd32_loop(tp
, regs
, TX_CPU_MODE
, 0x04);
4507 tg3_rd32_loop(tp
, regs
, TX_CPU_STATE
, 0x04);
4508 tg3_rd32_loop(tp
, regs
, TX_CPU_PGMCTR
, 0x04);
4511 tg3_rd32_loop(tp
, regs
, GRCMBOX_INTERRUPT_0
, 0x110);
4512 tg3_rd32_loop(tp
, regs
, FTQ_RESET
, 0x120);
4513 tg3_rd32_loop(tp
, regs
, MSGINT_MODE
, 0x0c);
4514 tg3_rd32_loop(tp
, regs
, DMAC_MODE
, 0x04);
4515 tg3_rd32_loop(tp
, regs
, GRC_MODE
, 0x4c);
4517 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
4518 tg3_rd32_loop(tp
, regs
, NVRAM_CMD
, 0x24);
4521 static void tg3_dump_state(struct tg3
*tp
)
4526 regs
= kzalloc(TG3_REG_BLK_SIZE
, GFP_ATOMIC
);
4528 netdev_err(tp
->dev
, "Failed allocating register dump buffer\n");
4532 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
4533 /* Read up to but not including private PCI registers */
4534 for (i
= 0; i
< TG3_PCIE_TLDLPL_PORT
; i
+= sizeof(u32
))
4535 regs
[i
/ sizeof(u32
)] = tr32(i
);
4537 tg3_dump_legacy_regs(tp
, regs
);
4539 for (i
= 0; i
< TG3_REG_BLK_SIZE
/ sizeof(u32
); i
+= 4) {
4540 if (!regs
[i
+ 0] && !regs
[i
+ 1] &&
4541 !regs
[i
+ 2] && !regs
[i
+ 3])
4544 netdev_err(tp
->dev
, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
4546 regs
[i
+ 0], regs
[i
+ 1], regs
[i
+ 2], regs
[i
+ 3]);
4551 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
4552 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
4554 /* SW status block */
4556 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
4558 tnapi
->hw_status
->status
,
4559 tnapi
->hw_status
->status_tag
,
4560 tnapi
->hw_status
->rx_jumbo_consumer
,
4561 tnapi
->hw_status
->rx_consumer
,
4562 tnapi
->hw_status
->rx_mini_consumer
,
4563 tnapi
->hw_status
->idx
[0].rx_producer
,
4564 tnapi
->hw_status
->idx
[0].tx_consumer
);
4567 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
4569 tnapi
->last_tag
, tnapi
->last_irq_tag
,
4570 tnapi
->tx_prod
, tnapi
->tx_cons
, tnapi
->tx_pending
,
4572 tnapi
->prodring
.rx_std_prod_idx
,
4573 tnapi
->prodring
.rx_std_cons_idx
,
4574 tnapi
->prodring
.rx_jmb_prod_idx
,
4575 tnapi
->prodring
.rx_jmb_cons_idx
);
4579 /* This is called whenever we suspect that the system chipset is re-
4580 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4581 * is bogus tx completions. We try to recover by setting the
4582 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4585 static void tg3_tx_recover(struct tg3
*tp
)
4587 BUG_ON((tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) ||
4588 tp
->write32_tx_mbox
== tg3_write_indirect_mbox
);
4590 netdev_warn(tp
->dev
,
4591 "The system may be re-ordering memory-mapped I/O "
4592 "cycles to the network device, attempting to recover. "
4593 "Please report the problem to the driver maintainer "
4594 "and include system chipset information.\n");
4596 spin_lock(&tp
->lock
);
4597 tp
->tg3_flags
|= TG3_FLAG_TX_RECOVERY_PENDING
;
4598 spin_unlock(&tp
->lock
);
4601 static inline u32
tg3_tx_avail(struct tg3_napi
*tnapi
)
4603 /* Tell compiler to fetch tx indices from memory. */
4605 return tnapi
->tx_pending
-
4606 ((tnapi
->tx_prod
- tnapi
->tx_cons
) & (TG3_TX_RING_SIZE
- 1));
4609 /* Tigon3 never reports partial packet sends. So we do not
4610 * need special logic to handle SKBs that have not had all
4611 * of their frags sent yet, like SunGEM does.
4613 static void tg3_tx(struct tg3_napi
*tnapi
)
4615 struct tg3
*tp
= tnapi
->tp
;
4616 u32 hw_idx
= tnapi
->hw_status
->idx
[0].tx_consumer
;
4617 u32 sw_idx
= tnapi
->tx_cons
;
4618 struct netdev_queue
*txq
;
4619 int index
= tnapi
- tp
->napi
;
4621 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
4624 txq
= netdev_get_tx_queue(tp
->dev
, index
);
4626 while (sw_idx
!= hw_idx
) {
4627 struct ring_info
*ri
= &tnapi
->tx_buffers
[sw_idx
];
4628 struct sk_buff
*skb
= ri
->skb
;
4631 if (unlikely(skb
== NULL
)) {
4636 pci_unmap_single(tp
->pdev
,
4637 dma_unmap_addr(ri
, mapping
),
4643 sw_idx
= NEXT_TX(sw_idx
);
4645 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
4646 ri
= &tnapi
->tx_buffers
[sw_idx
];
4647 if (unlikely(ri
->skb
!= NULL
|| sw_idx
== hw_idx
))
4650 pci_unmap_page(tp
->pdev
,
4651 dma_unmap_addr(ri
, mapping
),
4652 skb_shinfo(skb
)->frags
[i
].size
,
4654 sw_idx
= NEXT_TX(sw_idx
);
4659 if (unlikely(tx_bug
)) {
4665 tnapi
->tx_cons
= sw_idx
;
4667 /* Need to make the tx_cons update visible to tg3_start_xmit()
4668 * before checking for netif_queue_stopped(). Without the
4669 * memory barrier, there is a small possibility that tg3_start_xmit()
4670 * will miss it and cause the queue to be stopped forever.
4674 if (unlikely(netif_tx_queue_stopped(txq
) &&
4675 (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
)))) {
4676 __netif_tx_lock(txq
, smp_processor_id());
4677 if (netif_tx_queue_stopped(txq
) &&
4678 (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
)))
4679 netif_tx_wake_queue(txq
);
4680 __netif_tx_unlock(txq
);
4684 static void tg3_rx_skb_free(struct tg3
*tp
, struct ring_info
*ri
, u32 map_sz
)
4689 pci_unmap_single(tp
->pdev
, dma_unmap_addr(ri
, mapping
),
4690 map_sz
, PCI_DMA_FROMDEVICE
);
4691 dev_kfree_skb_any(ri
->skb
);
4695 /* Returns size of skb allocated or < 0 on error.
4697 * We only need to fill in the address because the other members
4698 * of the RX descriptor are invariant, see tg3_init_rings.
4700 * Note the purposeful assymetry of cpu vs. chip accesses. For
4701 * posting buffers we only dirty the first cache line of the RX
4702 * descriptor (containing the address). Whereas for the RX status
4703 * buffers the cpu only reads the last cacheline of the RX descriptor
4704 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4706 static int tg3_alloc_rx_skb(struct tg3
*tp
, struct tg3_rx_prodring_set
*tpr
,
4707 u32 opaque_key
, u32 dest_idx_unmasked
)
4709 struct tg3_rx_buffer_desc
*desc
;
4710 struct ring_info
*map
;
4711 struct sk_buff
*skb
;
4713 int skb_size
, dest_idx
;
4715 switch (opaque_key
) {
4716 case RXD_OPAQUE_RING_STD
:
4717 dest_idx
= dest_idx_unmasked
& tp
->rx_std_ring_mask
;
4718 desc
= &tpr
->rx_std
[dest_idx
];
4719 map
= &tpr
->rx_std_buffers
[dest_idx
];
4720 skb_size
= tp
->rx_pkt_map_sz
;
4723 case RXD_OPAQUE_RING_JUMBO
:
4724 dest_idx
= dest_idx_unmasked
& tp
->rx_jmb_ring_mask
;
4725 desc
= &tpr
->rx_jmb
[dest_idx
].std
;
4726 map
= &tpr
->rx_jmb_buffers
[dest_idx
];
4727 skb_size
= TG3_RX_JMB_MAP_SZ
;
4734 /* Do not overwrite any of the map or rp information
4735 * until we are sure we can commit to a new buffer.
4737 * Callers depend upon this behavior and assume that
4738 * we leave everything unchanged if we fail.
4740 skb
= netdev_alloc_skb(tp
->dev
, skb_size
+ tp
->rx_offset
);
4744 skb_reserve(skb
, tp
->rx_offset
);
4746 mapping
= pci_map_single(tp
->pdev
, skb
->data
, skb_size
,
4747 PCI_DMA_FROMDEVICE
);
4748 if (pci_dma_mapping_error(tp
->pdev
, mapping
)) {
4754 dma_unmap_addr_set(map
, mapping
, mapping
);
4756 desc
->addr_hi
= ((u64
)mapping
>> 32);
4757 desc
->addr_lo
= ((u64
)mapping
& 0xffffffff);
4762 /* We only need to move over in the address because the other
4763 * members of the RX descriptor are invariant. See notes above
4764 * tg3_alloc_rx_skb for full details.
4766 static void tg3_recycle_rx(struct tg3_napi
*tnapi
,
4767 struct tg3_rx_prodring_set
*dpr
,
4768 u32 opaque_key
, int src_idx
,
4769 u32 dest_idx_unmasked
)
4771 struct tg3
*tp
= tnapi
->tp
;
4772 struct tg3_rx_buffer_desc
*src_desc
, *dest_desc
;
4773 struct ring_info
*src_map
, *dest_map
;
4774 struct tg3_rx_prodring_set
*spr
= &tp
->napi
[0].prodring
;
4777 switch (opaque_key
) {
4778 case RXD_OPAQUE_RING_STD
:
4779 dest_idx
= dest_idx_unmasked
& tp
->rx_std_ring_mask
;
4780 dest_desc
= &dpr
->rx_std
[dest_idx
];
4781 dest_map
= &dpr
->rx_std_buffers
[dest_idx
];
4782 src_desc
= &spr
->rx_std
[src_idx
];
4783 src_map
= &spr
->rx_std_buffers
[src_idx
];
4786 case RXD_OPAQUE_RING_JUMBO
:
4787 dest_idx
= dest_idx_unmasked
& tp
->rx_jmb_ring_mask
;
4788 dest_desc
= &dpr
->rx_jmb
[dest_idx
].std
;
4789 dest_map
= &dpr
->rx_jmb_buffers
[dest_idx
];
4790 src_desc
= &spr
->rx_jmb
[src_idx
].std
;
4791 src_map
= &spr
->rx_jmb_buffers
[src_idx
];
4798 dest_map
->skb
= src_map
->skb
;
4799 dma_unmap_addr_set(dest_map
, mapping
,
4800 dma_unmap_addr(src_map
, mapping
));
4801 dest_desc
->addr_hi
= src_desc
->addr_hi
;
4802 dest_desc
->addr_lo
= src_desc
->addr_lo
;
4804 /* Ensure that the update to the skb happens after the physical
4805 * addresses have been transferred to the new BD location.
4809 src_map
->skb
= NULL
;
4812 /* The RX ring scheme is composed of multiple rings which post fresh
4813 * buffers to the chip, and one special ring the chip uses to report
4814 * status back to the host.
4816 * The special ring reports the status of received packets to the
4817 * host. The chip does not write into the original descriptor the
4818 * RX buffer was obtained from. The chip simply takes the original
4819 * descriptor as provided by the host, updates the status and length
4820 * field, then writes this into the next status ring entry.
4822 * Each ring the host uses to post buffers to the chip is described
4823 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4824 * it is first placed into the on-chip ram. When the packet's length
4825 * is known, it walks down the TG3_BDINFO entries to select the ring.
4826 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4827 * which is within the range of the new packet's length is chosen.
4829 * The "separate ring for rx status" scheme may sound queer, but it makes
4830 * sense from a cache coherency perspective. If only the host writes
4831 * to the buffer post rings, and only the chip writes to the rx status
4832 * rings, then cache lines never move beyond shared-modified state.
4833 * If both the host and chip were to write into the same ring, cache line
4834 * eviction could occur since both entities want it in an exclusive state.
4836 static int tg3_rx(struct tg3_napi
*tnapi
, int budget
)
4838 struct tg3
*tp
= tnapi
->tp
;
4839 u32 work_mask
, rx_std_posted
= 0;
4840 u32 std_prod_idx
, jmb_prod_idx
;
4841 u32 sw_idx
= tnapi
->rx_rcb_ptr
;
4844 struct tg3_rx_prodring_set
*tpr
= &tnapi
->prodring
;
4846 hw_idx
= *(tnapi
->rx_rcb_prod_idx
);
4848 * We need to order the read of hw_idx and the read of
4849 * the opaque cookie.
4854 std_prod_idx
= tpr
->rx_std_prod_idx
;
4855 jmb_prod_idx
= tpr
->rx_jmb_prod_idx
;
4856 while (sw_idx
!= hw_idx
&& budget
> 0) {
4857 struct ring_info
*ri
;
4858 struct tg3_rx_buffer_desc
*desc
= &tnapi
->rx_rcb
[sw_idx
];
4860 struct sk_buff
*skb
;
4861 dma_addr_t dma_addr
;
4862 u32 opaque_key
, desc_idx
, *post_ptr
;
4864 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
4865 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
4866 if (opaque_key
== RXD_OPAQUE_RING_STD
) {
4867 ri
= &tp
->napi
[0].prodring
.rx_std_buffers
[desc_idx
];
4868 dma_addr
= dma_unmap_addr(ri
, mapping
);
4870 post_ptr
= &std_prod_idx
;
4872 } else if (opaque_key
== RXD_OPAQUE_RING_JUMBO
) {
4873 ri
= &tp
->napi
[0].prodring
.rx_jmb_buffers
[desc_idx
];
4874 dma_addr
= dma_unmap_addr(ri
, mapping
);
4876 post_ptr
= &jmb_prod_idx
;
4878 goto next_pkt_nopost
;
4880 work_mask
|= opaque_key
;
4882 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
4883 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
)) {
4885 tg3_recycle_rx(tnapi
, tpr
, opaque_key
,
4886 desc_idx
, *post_ptr
);
4888 /* Other statistics kept track of by card. */
4893 len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) -
4896 if (len
> TG3_RX_COPY_THRESH(tp
)) {
4899 skb_size
= tg3_alloc_rx_skb(tp
, tpr
, opaque_key
,
4904 pci_unmap_single(tp
->pdev
, dma_addr
, skb_size
,
4905 PCI_DMA_FROMDEVICE
);
4907 /* Ensure that the update to the skb happens
4908 * after the usage of the old DMA mapping.
4916 struct sk_buff
*copy_skb
;
4918 tg3_recycle_rx(tnapi
, tpr
, opaque_key
,
4919 desc_idx
, *post_ptr
);
4921 copy_skb
= netdev_alloc_skb(tp
->dev
, len
+
4923 if (copy_skb
== NULL
)
4924 goto drop_it_no_recycle
;
4926 skb_reserve(copy_skb
, TG3_RAW_IP_ALIGN
);
4927 skb_put(copy_skb
, len
);
4928 pci_dma_sync_single_for_cpu(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4929 skb_copy_from_linear_data(skb
, copy_skb
->data
, len
);
4930 pci_dma_sync_single_for_device(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4932 /* We'll reuse the original ring buffer. */
4936 if ((tp
->dev
->features
& NETIF_F_RXCSUM
) &&
4937 (desc
->type_flags
& RXD_FLAG_TCPUDP_CSUM
) &&
4938 (((desc
->ip_tcp_csum
& RXD_TCPCSUM_MASK
)
4939 >> RXD_TCPCSUM_SHIFT
) == 0xffff))
4940 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4942 skb_checksum_none_assert(skb
);
4944 skb
->protocol
= eth_type_trans(skb
, tp
->dev
);
4946 if (len
> (tp
->dev
->mtu
+ ETH_HLEN
) &&
4947 skb
->protocol
!= htons(ETH_P_8021Q
)) {
4949 goto drop_it_no_recycle
;
4952 if (desc
->type_flags
& RXD_FLAG_VLAN
&&
4953 !(tp
->rx_mode
& RX_MODE_KEEP_VLAN_TAG
))
4954 __vlan_hwaccel_put_tag(skb
,
4955 desc
->err_vlan
& RXD_VLAN_MASK
);
4957 napi_gro_receive(&tnapi
->napi
, skb
);
4965 if (unlikely(rx_std_posted
>= tp
->rx_std_max_post
)) {
4966 tpr
->rx_std_prod_idx
= std_prod_idx
&
4967 tp
->rx_std_ring_mask
;
4968 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
4969 tpr
->rx_std_prod_idx
);
4970 work_mask
&= ~RXD_OPAQUE_RING_STD
;
4975 sw_idx
&= tp
->rx_ret_ring_mask
;
4977 /* Refresh hw_idx to see if there is new work */
4978 if (sw_idx
== hw_idx
) {
4979 hw_idx
= *(tnapi
->rx_rcb_prod_idx
);
4984 /* ACK the status ring. */
4985 tnapi
->rx_rcb_ptr
= sw_idx
;
4986 tw32_rx_mbox(tnapi
->consmbox
, sw_idx
);
4988 /* Refill RX ring(s). */
4989 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)) {
4990 if (work_mask
& RXD_OPAQUE_RING_STD
) {
4991 tpr
->rx_std_prod_idx
= std_prod_idx
&
4992 tp
->rx_std_ring_mask
;
4993 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
4994 tpr
->rx_std_prod_idx
);
4996 if (work_mask
& RXD_OPAQUE_RING_JUMBO
) {
4997 tpr
->rx_jmb_prod_idx
= jmb_prod_idx
&
4998 tp
->rx_jmb_ring_mask
;
4999 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
,
5000 tpr
->rx_jmb_prod_idx
);
5003 } else if (work_mask
) {
5004 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
5005 * updated before the producer indices can be updated.
5009 tpr
->rx_std_prod_idx
= std_prod_idx
& tp
->rx_std_ring_mask
;
5010 tpr
->rx_jmb_prod_idx
= jmb_prod_idx
& tp
->rx_jmb_ring_mask
;
5012 if (tnapi
!= &tp
->napi
[1])
5013 napi_schedule(&tp
->napi
[1].napi
);
5019 static void tg3_poll_link(struct tg3
*tp
)
5021 /* handle link change and other phy events */
5022 if (!(tp
->tg3_flags
&
5023 (TG3_FLAG_USE_LINKCHG_REG
|
5024 TG3_FLAG_POLL_SERDES
))) {
5025 struct tg3_hw_status
*sblk
= tp
->napi
[0].hw_status
;
5027 if (sblk
->status
& SD_STATUS_LINK_CHG
) {
5028 sblk
->status
= SD_STATUS_UPDATED
|
5029 (sblk
->status
& ~SD_STATUS_LINK_CHG
);
5030 spin_lock(&tp
->lock
);
5031 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
5033 (MAC_STATUS_SYNC_CHANGED
|
5034 MAC_STATUS_CFG_CHANGED
|
5035 MAC_STATUS_MI_COMPLETION
|
5036 MAC_STATUS_LNKSTATE_CHANGED
));
5039 tg3_setup_phy(tp
, 0);
5040 spin_unlock(&tp
->lock
);
5045 static int tg3_rx_prodring_xfer(struct tg3
*tp
,
5046 struct tg3_rx_prodring_set
*dpr
,
5047 struct tg3_rx_prodring_set
*spr
)
5049 u32 si
, di
, cpycnt
, src_prod_idx
;
5053 src_prod_idx
= spr
->rx_std_prod_idx
;
5055 /* Make sure updates to the rx_std_buffers[] entries and the
5056 * standard producer index are seen in the correct order.
5060 if (spr
->rx_std_cons_idx
== src_prod_idx
)
5063 if (spr
->rx_std_cons_idx
< src_prod_idx
)
5064 cpycnt
= src_prod_idx
- spr
->rx_std_cons_idx
;
5066 cpycnt
= tp
->rx_std_ring_mask
+ 1 -
5067 spr
->rx_std_cons_idx
;
5069 cpycnt
= min(cpycnt
,
5070 tp
->rx_std_ring_mask
+ 1 - dpr
->rx_std_prod_idx
);
5072 si
= spr
->rx_std_cons_idx
;
5073 di
= dpr
->rx_std_prod_idx
;
5075 for (i
= di
; i
< di
+ cpycnt
; i
++) {
5076 if (dpr
->rx_std_buffers
[i
].skb
) {
5086 /* Ensure that updates to the rx_std_buffers ring and the
5087 * shadowed hardware producer ring from tg3_recycle_skb() are
5088 * ordered correctly WRT the skb check above.
5092 memcpy(&dpr
->rx_std_buffers
[di
],
5093 &spr
->rx_std_buffers
[si
],
5094 cpycnt
* sizeof(struct ring_info
));
5096 for (i
= 0; i
< cpycnt
; i
++, di
++, si
++) {
5097 struct tg3_rx_buffer_desc
*sbd
, *dbd
;
5098 sbd
= &spr
->rx_std
[si
];
5099 dbd
= &dpr
->rx_std
[di
];
5100 dbd
->addr_hi
= sbd
->addr_hi
;
5101 dbd
->addr_lo
= sbd
->addr_lo
;
5104 spr
->rx_std_cons_idx
= (spr
->rx_std_cons_idx
+ cpycnt
) &
5105 tp
->rx_std_ring_mask
;
5106 dpr
->rx_std_prod_idx
= (dpr
->rx_std_prod_idx
+ cpycnt
) &
5107 tp
->rx_std_ring_mask
;
5111 src_prod_idx
= spr
->rx_jmb_prod_idx
;
5113 /* Make sure updates to the rx_jmb_buffers[] entries and
5114 * the jumbo producer index are seen in the correct order.
5118 if (spr
->rx_jmb_cons_idx
== src_prod_idx
)
5121 if (spr
->rx_jmb_cons_idx
< src_prod_idx
)
5122 cpycnt
= src_prod_idx
- spr
->rx_jmb_cons_idx
;
5124 cpycnt
= tp
->rx_jmb_ring_mask
+ 1 -
5125 spr
->rx_jmb_cons_idx
;
5127 cpycnt
= min(cpycnt
,
5128 tp
->rx_jmb_ring_mask
+ 1 - dpr
->rx_jmb_prod_idx
);
5130 si
= spr
->rx_jmb_cons_idx
;
5131 di
= dpr
->rx_jmb_prod_idx
;
5133 for (i
= di
; i
< di
+ cpycnt
; i
++) {
5134 if (dpr
->rx_jmb_buffers
[i
].skb
) {
5144 /* Ensure that updates to the rx_jmb_buffers ring and the
5145 * shadowed hardware producer ring from tg3_recycle_skb() are
5146 * ordered correctly WRT the skb check above.
5150 memcpy(&dpr
->rx_jmb_buffers
[di
],
5151 &spr
->rx_jmb_buffers
[si
],
5152 cpycnt
* sizeof(struct ring_info
));
5154 for (i
= 0; i
< cpycnt
; i
++, di
++, si
++) {
5155 struct tg3_rx_buffer_desc
*sbd
, *dbd
;
5156 sbd
= &spr
->rx_jmb
[si
].std
;
5157 dbd
= &dpr
->rx_jmb
[di
].std
;
5158 dbd
->addr_hi
= sbd
->addr_hi
;
5159 dbd
->addr_lo
= sbd
->addr_lo
;
5162 spr
->rx_jmb_cons_idx
= (spr
->rx_jmb_cons_idx
+ cpycnt
) &
5163 tp
->rx_jmb_ring_mask
;
5164 dpr
->rx_jmb_prod_idx
= (dpr
->rx_jmb_prod_idx
+ cpycnt
) &
5165 tp
->rx_jmb_ring_mask
;
5171 static int tg3_poll_work(struct tg3_napi
*tnapi
, int work_done
, int budget
)
5173 struct tg3
*tp
= tnapi
->tp
;
5175 /* run TX completion thread */
5176 if (tnapi
->hw_status
->idx
[0].tx_consumer
!= tnapi
->tx_cons
) {
5178 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
5182 /* run RX thread, within the bounds set by NAPI.
5183 * All RX "locking" is done by ensuring outside
5184 * code synchronizes with tg3->napi.poll()
5186 if (*(tnapi
->rx_rcb_prod_idx
) != tnapi
->rx_rcb_ptr
)
5187 work_done
+= tg3_rx(tnapi
, budget
- work_done
);
5189 if ((tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
) && tnapi
== &tp
->napi
[1]) {
5190 struct tg3_rx_prodring_set
*dpr
= &tp
->napi
[0].prodring
;
5192 u32 std_prod_idx
= dpr
->rx_std_prod_idx
;
5193 u32 jmb_prod_idx
= dpr
->rx_jmb_prod_idx
;
5195 for (i
= 1; i
< tp
->irq_cnt
; i
++)
5196 err
|= tg3_rx_prodring_xfer(tp
, dpr
,
5197 &tp
->napi
[i
].prodring
);
5201 if (std_prod_idx
!= dpr
->rx_std_prod_idx
)
5202 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
5203 dpr
->rx_std_prod_idx
);
5205 if (jmb_prod_idx
!= dpr
->rx_jmb_prod_idx
)
5206 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
,
5207 dpr
->rx_jmb_prod_idx
);
5212 tw32_f(HOSTCC_MODE
, tp
->coal_now
);
5218 static int tg3_poll_msix(struct napi_struct
*napi
, int budget
)
5220 struct tg3_napi
*tnapi
= container_of(napi
, struct tg3_napi
, napi
);
5221 struct tg3
*tp
= tnapi
->tp
;
5223 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5226 work_done
= tg3_poll_work(tnapi
, work_done
, budget
);
5228 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
5231 if (unlikely(work_done
>= budget
))
5234 /* tp->last_tag is used in tg3_int_reenable() below
5235 * to tell the hw how much work has been processed,
5236 * so we must read it before checking for more work.
5238 tnapi
->last_tag
= sblk
->status_tag
;
5239 tnapi
->last_irq_tag
= tnapi
->last_tag
;
5242 /* check for RX/TX work to do */
5243 if (likely(sblk
->idx
[0].tx_consumer
== tnapi
->tx_cons
&&
5244 *(tnapi
->rx_rcb_prod_idx
) == tnapi
->rx_rcb_ptr
)) {
5245 napi_complete(napi
);
5246 /* Reenable interrupts. */
5247 tw32_mailbox(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
5256 /* work_done is guaranteed to be less than budget. */
5257 napi_complete(napi
);
5258 schedule_work(&tp
->reset_task
);
5262 static void tg3_process_error(struct tg3
*tp
)
5265 bool real_error
= false;
5267 if (tp
->tg3_flags
& TG3_FLAG_ERROR_PROCESSED
)
5270 /* Check Flow Attention register */
5271 val
= tr32(HOSTCC_FLOW_ATTN
);
5272 if (val
& ~HOSTCC_FLOW_ATTN_MBUF_LWM
) {
5273 netdev_err(tp
->dev
, "FLOW Attention error. Resetting chip.\n");
5277 if (tr32(MSGINT_STATUS
) & ~MSGINT_STATUS_MSI_REQ
) {
5278 netdev_err(tp
->dev
, "MSI Status error. Resetting chip.\n");
5282 if (tr32(RDMAC_STATUS
) || tr32(WDMAC_STATUS
)) {
5283 netdev_err(tp
->dev
, "DMA Status error. Resetting chip.\n");
5292 tp
->tg3_flags
|= TG3_FLAG_ERROR_PROCESSED
;
5293 schedule_work(&tp
->reset_task
);
5296 static int tg3_poll(struct napi_struct
*napi
, int budget
)
5298 struct tg3_napi
*tnapi
= container_of(napi
, struct tg3_napi
, napi
);
5299 struct tg3
*tp
= tnapi
->tp
;
5301 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5304 if (sblk
->status
& SD_STATUS_ERROR
)
5305 tg3_process_error(tp
);
5309 work_done
= tg3_poll_work(tnapi
, work_done
, budget
);
5311 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
5314 if (unlikely(work_done
>= budget
))
5317 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
5318 /* tp->last_tag is used in tg3_int_reenable() below
5319 * to tell the hw how much work has been processed,
5320 * so we must read it before checking for more work.
5322 tnapi
->last_tag
= sblk
->status_tag
;
5323 tnapi
->last_irq_tag
= tnapi
->last_tag
;
5326 sblk
->status
&= ~SD_STATUS_UPDATED
;
5328 if (likely(!tg3_has_work(tnapi
))) {
5329 napi_complete(napi
);
5330 tg3_int_reenable(tnapi
);
5338 /* work_done is guaranteed to be less than budget. */
5339 napi_complete(napi
);
5340 schedule_work(&tp
->reset_task
);
5344 static void tg3_napi_disable(struct tg3
*tp
)
5348 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--)
5349 napi_disable(&tp
->napi
[i
].napi
);
5352 static void tg3_napi_enable(struct tg3
*tp
)
5356 for (i
= 0; i
< tp
->irq_cnt
; i
++)
5357 napi_enable(&tp
->napi
[i
].napi
);
5360 static void tg3_napi_init(struct tg3
*tp
)
5364 netif_napi_add(tp
->dev
, &tp
->napi
[0].napi
, tg3_poll
, 64);
5365 for (i
= 1; i
< tp
->irq_cnt
; i
++)
5366 netif_napi_add(tp
->dev
, &tp
->napi
[i
].napi
, tg3_poll_msix
, 64);
5369 static void tg3_napi_fini(struct tg3
*tp
)
5373 for (i
= 0; i
< tp
->irq_cnt
; i
++)
5374 netif_napi_del(&tp
->napi
[i
].napi
);
5377 static inline void tg3_netif_stop(struct tg3
*tp
)
5379 tp
->dev
->trans_start
= jiffies
; /* prevent tx timeout */
5380 tg3_napi_disable(tp
);
5381 netif_tx_disable(tp
->dev
);
5384 static inline void tg3_netif_start(struct tg3
*tp
)
5386 /* NOTE: unconditional netif_tx_wake_all_queues is only
5387 * appropriate so long as all callers are assured to
5388 * have free tx slots (such as after tg3_init_hw)
5390 netif_tx_wake_all_queues(tp
->dev
);
5392 tg3_napi_enable(tp
);
5393 tp
->napi
[0].hw_status
->status
|= SD_STATUS_UPDATED
;
5394 tg3_enable_ints(tp
);
5397 static void tg3_irq_quiesce(struct tg3
*tp
)
5401 BUG_ON(tp
->irq_sync
);
5406 for (i
= 0; i
< tp
->irq_cnt
; i
++)
5407 synchronize_irq(tp
->napi
[i
].irq_vec
);
5410 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5411 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5412 * with as well. Most of the time, this is not necessary except when
5413 * shutting down the device.
5415 static inline void tg3_full_lock(struct tg3
*tp
, int irq_sync
)
5417 spin_lock_bh(&tp
->lock
);
5419 tg3_irq_quiesce(tp
);
5422 static inline void tg3_full_unlock(struct tg3
*tp
)
5424 spin_unlock_bh(&tp
->lock
);
5427 /* One-shot MSI handler - Chip automatically disables interrupt
5428 * after sending MSI so driver doesn't have to do it.
5430 static irqreturn_t
tg3_msi_1shot(int irq
, void *dev_id
)
5432 struct tg3_napi
*tnapi
= dev_id
;
5433 struct tg3
*tp
= tnapi
->tp
;
5435 prefetch(tnapi
->hw_status
);
5437 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5439 if (likely(!tg3_irq_sync(tp
)))
5440 napi_schedule(&tnapi
->napi
);
5445 /* MSI ISR - No need to check for interrupt sharing and no need to
5446 * flush status block and interrupt mailbox. PCI ordering rules
5447 * guarantee that MSI will arrive after the status block.
5449 static irqreturn_t
tg3_msi(int irq
, void *dev_id
)
5451 struct tg3_napi
*tnapi
= dev_id
;
5452 struct tg3
*tp
= tnapi
->tp
;
5454 prefetch(tnapi
->hw_status
);
5456 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5458 * Writing any value to intr-mbox-0 clears PCI INTA# and
5459 * chip-internal interrupt pending events.
5460 * Writing non-zero to intr-mbox-0 additional tells the
5461 * NIC to stop sending us irqs, engaging "in-intr-handler"
5464 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
5465 if (likely(!tg3_irq_sync(tp
)))
5466 napi_schedule(&tnapi
->napi
);
5468 return IRQ_RETVAL(1);
5471 static irqreturn_t
tg3_interrupt(int irq
, void *dev_id
)
5473 struct tg3_napi
*tnapi
= dev_id
;
5474 struct tg3
*tp
= tnapi
->tp
;
5475 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5476 unsigned int handled
= 1;
5478 /* In INTx mode, it is possible for the interrupt to arrive at
5479 * the CPU before the status block posted prior to the interrupt.
5480 * Reading the PCI State register will confirm whether the
5481 * interrupt is ours and will flush the status block.
5483 if (unlikely(!(sblk
->status
& SD_STATUS_UPDATED
))) {
5484 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
5485 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
5492 * Writing any value to intr-mbox-0 clears PCI INTA# and
5493 * chip-internal interrupt pending events.
5494 * Writing non-zero to intr-mbox-0 additional tells the
5495 * NIC to stop sending us irqs, engaging "in-intr-handler"
5498 * Flush the mailbox to de-assert the IRQ immediately to prevent
5499 * spurious interrupts. The flush impacts performance but
5500 * excessive spurious interrupts can be worse in some cases.
5502 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
5503 if (tg3_irq_sync(tp
))
5505 sblk
->status
&= ~SD_STATUS_UPDATED
;
5506 if (likely(tg3_has_work(tnapi
))) {
5507 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5508 napi_schedule(&tnapi
->napi
);
5510 /* No work, shared interrupt perhaps? re-enable
5511 * interrupts, and flush that PCI write
5513 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
5517 return IRQ_RETVAL(handled
);
5520 static irqreturn_t
tg3_interrupt_tagged(int irq
, void *dev_id
)
5522 struct tg3_napi
*tnapi
= dev_id
;
5523 struct tg3
*tp
= tnapi
->tp
;
5524 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5525 unsigned int handled
= 1;
5527 /* In INTx mode, it is possible for the interrupt to arrive at
5528 * the CPU before the status block posted prior to the interrupt.
5529 * Reading the PCI State register will confirm whether the
5530 * interrupt is ours and will flush the status block.
5532 if (unlikely(sblk
->status_tag
== tnapi
->last_irq_tag
)) {
5533 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
5534 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
5541 * writing any value to intr-mbox-0 clears PCI INTA# and
5542 * chip-internal interrupt pending events.
5543 * writing non-zero to intr-mbox-0 additional tells the
5544 * NIC to stop sending us irqs, engaging "in-intr-handler"
5547 * Flush the mailbox to de-assert the IRQ immediately to prevent
5548 * spurious interrupts. The flush impacts performance but
5549 * excessive spurious interrupts can be worse in some cases.
5551 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
5554 * In a shared interrupt configuration, sometimes other devices'
5555 * interrupts will scream. We record the current status tag here
5556 * so that the above check can report that the screaming interrupts
5557 * are unhandled. Eventually they will be silenced.
5559 tnapi
->last_irq_tag
= sblk
->status_tag
;
5561 if (tg3_irq_sync(tp
))
5564 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5566 napi_schedule(&tnapi
->napi
);
5569 return IRQ_RETVAL(handled
);
5572 /* ISR for interrupt test */
5573 static irqreturn_t
tg3_test_isr(int irq
, void *dev_id
)
5575 struct tg3_napi
*tnapi
= dev_id
;
5576 struct tg3
*tp
= tnapi
->tp
;
5577 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5579 if ((sblk
->status
& SD_STATUS_UPDATED
) ||
5580 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
5581 tg3_disable_ints(tp
);
5582 return IRQ_RETVAL(1);
5584 return IRQ_RETVAL(0);
5587 static int tg3_init_hw(struct tg3
*, int);
5588 static int tg3_halt(struct tg3
*, int, int);
5590 /* Restart hardware after configuration changes, self-test, etc.
5591 * Invoked with tp->lock held.
5593 static int tg3_restart_hw(struct tg3
*tp
, int reset_phy
)
5594 __releases(tp
->lock
)
5595 __acquires(tp
->lock
)
5599 err
= tg3_init_hw(tp
, reset_phy
);
5602 "Failed to re-initialize device, aborting\n");
5603 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
5604 tg3_full_unlock(tp
);
5605 del_timer_sync(&tp
->timer
);
5607 tg3_napi_enable(tp
);
5609 tg3_full_lock(tp
, 0);
5614 #ifdef CONFIG_NET_POLL_CONTROLLER
5615 static void tg3_poll_controller(struct net_device
*dev
)
5618 struct tg3
*tp
= netdev_priv(dev
);
5620 for (i
= 0; i
< tp
->irq_cnt
; i
++)
5621 tg3_interrupt(tp
->napi
[i
].irq_vec
, &tp
->napi
[i
]);
5625 static void tg3_reset_task(struct work_struct
*work
)
5627 struct tg3
*tp
= container_of(work
, struct tg3
, reset_task
);
5629 unsigned int restart_timer
;
5631 tg3_full_lock(tp
, 0);
5633 if (!netif_running(tp
->dev
)) {
5634 tg3_full_unlock(tp
);
5638 tg3_full_unlock(tp
);
5644 tg3_full_lock(tp
, 1);
5646 restart_timer
= tp
->tg3_flags2
& TG3_FLG2_RESTART_TIMER
;
5647 tp
->tg3_flags2
&= ~TG3_FLG2_RESTART_TIMER
;
5649 if (tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
) {
5650 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
5651 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
5652 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
5653 tp
->tg3_flags
&= ~TG3_FLAG_TX_RECOVERY_PENDING
;
5656 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 0);
5657 err
= tg3_init_hw(tp
, 1);
5661 tg3_netif_start(tp
);
5664 mod_timer(&tp
->timer
, jiffies
+ 1);
5667 tg3_full_unlock(tp
);
5673 static void tg3_tx_timeout(struct net_device
*dev
)
5675 struct tg3
*tp
= netdev_priv(dev
);
5677 if (netif_msg_tx_err(tp
)) {
5678 netdev_err(dev
, "transmit timed out, resetting\n");
5682 schedule_work(&tp
->reset_task
);
5685 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5686 static inline int tg3_4g_overflow_test(dma_addr_t mapping
, int len
)
5688 u32 base
= (u32
) mapping
& 0xffffffff;
5690 return (base
> 0xffffdcc0) && (base
+ len
+ 8 < base
);
5693 /* Test for DMA addresses > 40-bit */
5694 static inline int tg3_40bit_overflow_test(struct tg3
*tp
, dma_addr_t mapping
,
5697 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5698 if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
)
5699 return ((u64
) mapping
+ len
) > DMA_BIT_MASK(40);
5706 static void tg3_set_txd(struct tg3_napi
*, int, dma_addr_t
, int, u32
, u32
);
5708 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5709 static int tigon3_dma_hwbug_workaround(struct tg3_napi
*tnapi
,
5710 struct sk_buff
*skb
, u32 last_plus_one
,
5711 u32
*start
, u32 base_flags
, u32 mss
)
5713 struct tg3
*tp
= tnapi
->tp
;
5714 struct sk_buff
*new_skb
;
5715 dma_addr_t new_addr
= 0;
5719 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
5720 new_skb
= skb_copy(skb
, GFP_ATOMIC
);
5722 int more_headroom
= 4 - ((unsigned long)skb
->data
& 3);
5724 new_skb
= skb_copy_expand(skb
,
5725 skb_headroom(skb
) + more_headroom
,
5726 skb_tailroom(skb
), GFP_ATOMIC
);
5732 /* New SKB is guaranteed to be linear. */
5734 new_addr
= pci_map_single(tp
->pdev
, new_skb
->data
, new_skb
->len
,
5736 /* Make sure the mapping succeeded */
5737 if (pci_dma_mapping_error(tp
->pdev
, new_addr
)) {
5739 dev_kfree_skb(new_skb
);
5742 /* Make sure new skb does not cross any 4G boundaries.
5743 * Drop the packet if it does.
5745 } else if ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
5746 tg3_4g_overflow_test(new_addr
, new_skb
->len
)) {
5747 pci_unmap_single(tp
->pdev
, new_addr
, new_skb
->len
,
5750 dev_kfree_skb(new_skb
);
5753 tg3_set_txd(tnapi
, entry
, new_addr
, new_skb
->len
,
5754 base_flags
, 1 | (mss
<< 1));
5755 *start
= NEXT_TX(entry
);
5759 /* Now clean up the sw ring entries. */
5761 while (entry
!= last_plus_one
) {
5765 len
= skb_headlen(skb
);
5767 len
= skb_shinfo(skb
)->frags
[i
-1].size
;
5769 pci_unmap_single(tp
->pdev
,
5770 dma_unmap_addr(&tnapi
->tx_buffers
[entry
],
5772 len
, PCI_DMA_TODEVICE
);
5774 tnapi
->tx_buffers
[entry
].skb
= new_skb
;
5775 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
,
5778 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5780 entry
= NEXT_TX(entry
);
5789 static void tg3_set_txd(struct tg3_napi
*tnapi
, int entry
,
5790 dma_addr_t mapping
, int len
, u32 flags
,
5793 struct tg3_tx_buffer_desc
*txd
= &tnapi
->tx_ring
[entry
];
5794 int is_end
= (mss_and_is_end
& 0x1);
5795 u32 mss
= (mss_and_is_end
>> 1);
5799 flags
|= TXD_FLAG_END
;
5800 if (flags
& TXD_FLAG_VLAN
) {
5801 vlan_tag
= flags
>> 16;
5804 vlan_tag
|= (mss
<< TXD_MSS_SHIFT
);
5806 txd
->addr_hi
= ((u64
) mapping
>> 32);
5807 txd
->addr_lo
= ((u64
) mapping
& 0xffffffff);
5808 txd
->len_flags
= (len
<< TXD_LEN_SHIFT
) | flags
;
5809 txd
->vlan_tag
= vlan_tag
<< TXD_VLAN_TAG_SHIFT
;
5812 /* hard_start_xmit for devices that don't have any bugs and
5813 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5815 static netdev_tx_t
tg3_start_xmit(struct sk_buff
*skb
,
5816 struct net_device
*dev
)
5818 struct tg3
*tp
= netdev_priv(dev
);
5819 u32 len
, entry
, base_flags
, mss
;
5821 struct tg3_napi
*tnapi
;
5822 struct netdev_queue
*txq
;
5823 unsigned int i
, last
;
5825 txq
= netdev_get_tx_queue(dev
, skb_get_queue_mapping(skb
));
5826 tnapi
= &tp
->napi
[skb_get_queue_mapping(skb
)];
5827 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
5830 /* We are running in BH disabled context with netif_tx_lock
5831 * and TX reclaim runs via tp->napi.poll inside of a software
5832 * interrupt. Furthermore, IRQ processing runs lockless so we have
5833 * no IRQ context deadlocks to worry about either. Rejoice!
5835 if (unlikely(tg3_tx_avail(tnapi
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
5836 if (!netif_tx_queue_stopped(txq
)) {
5837 netif_tx_stop_queue(txq
);
5839 /* This is a hard error, log it. */
5841 "BUG! Tx Ring full when queue awake!\n");
5843 return NETDEV_TX_BUSY
;
5846 entry
= tnapi
->tx_prod
;
5848 mss
= skb_shinfo(skb
)->gso_size
;
5850 int tcp_opt_len
, ip_tcp_len
;
5853 if (skb_header_cloned(skb
) &&
5854 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
5859 if (skb_is_gso_v6(skb
)) {
5860 hdrlen
= skb_headlen(skb
) - ETH_HLEN
;
5862 struct iphdr
*iph
= ip_hdr(skb
);
5864 tcp_opt_len
= tcp_optlen(skb
);
5865 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
5868 iph
->tot_len
= htons(mss
+ ip_tcp_len
+ tcp_opt_len
);
5869 hdrlen
= ip_tcp_len
+ tcp_opt_len
;
5872 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) {
5873 mss
|= (hdrlen
& 0xc) << 12;
5875 base_flags
|= 0x00000010;
5876 base_flags
|= (hdrlen
& 0x3e0) << 5;
5880 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
5881 TXD_FLAG_CPU_POST_DMA
);
5883 tcp_hdr(skb
)->check
= 0;
5885 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5886 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
5889 if (vlan_tx_tag_present(skb
))
5890 base_flags
|= (TXD_FLAG_VLAN
|
5891 (vlan_tx_tag_get(skb
) << 16));
5893 len
= skb_headlen(skb
);
5895 /* Queue skb data, a.k.a. the main skb fragment. */
5896 mapping
= pci_map_single(tp
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
5897 if (pci_dma_mapping_error(tp
->pdev
, mapping
)) {
5902 tnapi
->tx_buffers
[entry
].skb
= skb
;
5903 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
, mapping
);
5905 if ((tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
) &&
5906 !mss
&& skb
->len
> VLAN_ETH_FRAME_LEN
)
5907 base_flags
|= TXD_FLAG_JMB_PKT
;
5909 tg3_set_txd(tnapi
, entry
, mapping
, len
, base_flags
,
5910 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
5912 entry
= NEXT_TX(entry
);
5914 /* Now loop through additional data fragments, and queue them. */
5915 if (skb_shinfo(skb
)->nr_frags
> 0) {
5916 last
= skb_shinfo(skb
)->nr_frags
- 1;
5917 for (i
= 0; i
<= last
; i
++) {
5918 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5921 mapping
= pci_map_page(tp
->pdev
,
5924 len
, PCI_DMA_TODEVICE
);
5925 if (pci_dma_mapping_error(tp
->pdev
, mapping
))
5928 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5929 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
,
5932 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5933 base_flags
, (i
== last
) | (mss
<< 1));
5935 entry
= NEXT_TX(entry
);
5939 /* Packets are ready, update Tx producer idx local and on card. */
5940 tw32_tx_mbox(tnapi
->prodmbox
, entry
);
5942 tnapi
->tx_prod
= entry
;
5943 if (unlikely(tg3_tx_avail(tnapi
) <= (MAX_SKB_FRAGS
+ 1))) {
5944 netif_tx_stop_queue(txq
);
5946 /* netif_tx_stop_queue() must be done before checking
5947 * checking tx index in tg3_tx_avail() below, because in
5948 * tg3_tx(), we update tx index before checking for
5949 * netif_tx_queue_stopped().
5952 if (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
))
5953 netif_tx_wake_queue(txq
);
5959 return NETDEV_TX_OK
;
5963 entry
= tnapi
->tx_prod
;
5964 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5965 pci_unmap_single(tp
->pdev
,
5966 dma_unmap_addr(&tnapi
->tx_buffers
[entry
], mapping
),
5969 for (i
= 0; i
<= last
; i
++) {
5970 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5971 entry
= NEXT_TX(entry
);
5973 pci_unmap_page(tp
->pdev
,
5974 dma_unmap_addr(&tnapi
->tx_buffers
[entry
],
5976 frag
->size
, PCI_DMA_TODEVICE
);
5980 return NETDEV_TX_OK
;
5983 static netdev_tx_t
tg3_start_xmit_dma_bug(struct sk_buff
*,
5984 struct net_device
*);
5986 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5987 * TSO header is greater than 80 bytes.
5989 static int tg3_tso_bug(struct tg3
*tp
, struct sk_buff
*skb
)
5991 struct sk_buff
*segs
, *nskb
;
5992 u32 frag_cnt_est
= skb_shinfo(skb
)->gso_segs
* 3;
5994 /* Estimate the number of fragments in the worst case */
5995 if (unlikely(tg3_tx_avail(&tp
->napi
[0]) <= frag_cnt_est
)) {
5996 netif_stop_queue(tp
->dev
);
5998 /* netif_tx_stop_queue() must be done before checking
5999 * checking tx index in tg3_tx_avail() below, because in
6000 * tg3_tx(), we update tx index before checking for
6001 * netif_tx_queue_stopped().
6004 if (tg3_tx_avail(&tp
->napi
[0]) <= frag_cnt_est
)
6005 return NETDEV_TX_BUSY
;
6007 netif_wake_queue(tp
->dev
);
6010 segs
= skb_gso_segment(skb
, tp
->dev
->features
& ~NETIF_F_TSO
);
6012 goto tg3_tso_bug_end
;
6018 tg3_start_xmit_dma_bug(nskb
, tp
->dev
);
6024 return NETDEV_TX_OK
;
6027 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
6028 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
6030 static netdev_tx_t
tg3_start_xmit_dma_bug(struct sk_buff
*skb
,
6031 struct net_device
*dev
)
6033 struct tg3
*tp
= netdev_priv(dev
);
6034 u32 len
, entry
, base_flags
, mss
;
6035 int would_hit_hwbug
;
6037 struct tg3_napi
*tnapi
;
6038 struct netdev_queue
*txq
;
6039 unsigned int i
, last
;
6041 txq
= netdev_get_tx_queue(dev
, skb_get_queue_mapping(skb
));
6042 tnapi
= &tp
->napi
[skb_get_queue_mapping(skb
)];
6043 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
6046 /* We are running in BH disabled context with netif_tx_lock
6047 * and TX reclaim runs via tp->napi.poll inside of a software
6048 * interrupt. Furthermore, IRQ processing runs lockless so we have
6049 * no IRQ context deadlocks to worry about either. Rejoice!
6051 if (unlikely(tg3_tx_avail(tnapi
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
6052 if (!netif_tx_queue_stopped(txq
)) {
6053 netif_tx_stop_queue(txq
);
6055 /* This is a hard error, log it. */
6057 "BUG! Tx Ring full when queue awake!\n");
6059 return NETDEV_TX_BUSY
;
6062 entry
= tnapi
->tx_prod
;
6064 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
6065 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
6067 mss
= skb_shinfo(skb
)->gso_size
;
6070 u32 tcp_opt_len
, hdr_len
;
6072 if (skb_header_cloned(skb
) &&
6073 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
6079 tcp_opt_len
= tcp_optlen(skb
);
6081 if (skb_is_gso_v6(skb
)) {
6082 hdr_len
= skb_headlen(skb
) - ETH_HLEN
;
6086 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
6087 hdr_len
= ip_tcp_len
+ tcp_opt_len
;
6090 iph
->tot_len
= htons(mss
+ hdr_len
);
6093 if (unlikely((ETH_HLEN
+ hdr_len
) > 80) &&
6094 (tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
))
6095 return tg3_tso_bug(tp
, skb
);
6097 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
6098 TXD_FLAG_CPU_POST_DMA
);
6100 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
6101 tcp_hdr(skb
)->check
= 0;
6102 base_flags
&= ~TXD_FLAG_TCPUDP_CSUM
;
6104 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
6109 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) {
6110 mss
|= (hdr_len
& 0xc) << 12;
6112 base_flags
|= 0x00000010;
6113 base_flags
|= (hdr_len
& 0x3e0) << 5;
6114 } else if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
)
6115 mss
|= hdr_len
<< 9;
6116 else if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_1
) ||
6117 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
6118 if (tcp_opt_len
|| iph
->ihl
> 5) {
6121 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
6122 mss
|= (tsflags
<< 11);
6125 if (tcp_opt_len
|| iph
->ihl
> 5) {
6128 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
6129 base_flags
|= tsflags
<< 12;
6134 if (vlan_tx_tag_present(skb
))
6135 base_flags
|= (TXD_FLAG_VLAN
|
6136 (vlan_tx_tag_get(skb
) << 16));
6138 if ((tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
) &&
6139 !mss
&& skb
->len
> VLAN_ETH_FRAME_LEN
)
6140 base_flags
|= TXD_FLAG_JMB_PKT
;
6142 len
= skb_headlen(skb
);
6144 mapping
= pci_map_single(tp
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
6145 if (pci_dma_mapping_error(tp
->pdev
, mapping
)) {
6150 tnapi
->tx_buffers
[entry
].skb
= skb
;
6151 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
, mapping
);
6153 would_hit_hwbug
= 0;
6155 if ((tp
->tg3_flags3
& TG3_FLG3_SHORT_DMA_BUG
) && len
<= 8)
6156 would_hit_hwbug
= 1;
6158 if ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
6159 tg3_4g_overflow_test(mapping
, len
))
6160 would_hit_hwbug
= 1;
6162 if ((tp
->tg3_flags3
& TG3_FLG3_40BIT_DMA_LIMIT_BUG
) &&
6163 tg3_40bit_overflow_test(tp
, mapping
, len
))
6164 would_hit_hwbug
= 1;
6166 if (tp
->tg3_flags3
& TG3_FLG3_5701_DMA_BUG
)
6167 would_hit_hwbug
= 1;
6169 tg3_set_txd(tnapi
, entry
, mapping
, len
, base_flags
,
6170 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
6172 entry
= NEXT_TX(entry
);
6174 /* Now loop through additional data fragments, and queue them. */
6175 if (skb_shinfo(skb
)->nr_frags
> 0) {
6176 last
= skb_shinfo(skb
)->nr_frags
- 1;
6177 for (i
= 0; i
<= last
; i
++) {
6178 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
6181 mapping
= pci_map_page(tp
->pdev
,
6184 len
, PCI_DMA_TODEVICE
);
6186 tnapi
->tx_buffers
[entry
].skb
= NULL
;
6187 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
,
6189 if (pci_dma_mapping_error(tp
->pdev
, mapping
))
6192 if ((tp
->tg3_flags3
& TG3_FLG3_SHORT_DMA_BUG
) &&
6194 would_hit_hwbug
= 1;
6196 if ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
6197 tg3_4g_overflow_test(mapping
, len
))
6198 would_hit_hwbug
= 1;
6200 if ((tp
->tg3_flags3
& TG3_FLG3_40BIT_DMA_LIMIT_BUG
) &&
6201 tg3_40bit_overflow_test(tp
, mapping
, len
))
6202 would_hit_hwbug
= 1;
6204 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
6205 tg3_set_txd(tnapi
, entry
, mapping
, len
,
6206 base_flags
, (i
== last
)|(mss
<< 1));
6208 tg3_set_txd(tnapi
, entry
, mapping
, len
,
6209 base_flags
, (i
== last
));
6211 entry
= NEXT_TX(entry
);
6215 if (would_hit_hwbug
) {
6216 u32 last_plus_one
= entry
;
6219 start
= entry
- 1 - skb_shinfo(skb
)->nr_frags
;
6220 start
&= (TG3_TX_RING_SIZE
- 1);
6222 /* If the workaround fails due to memory/mapping
6223 * failure, silently drop this packet.
6225 if (tigon3_dma_hwbug_workaround(tnapi
, skb
, last_plus_one
,
6226 &start
, base_flags
, mss
))
6232 /* Packets are ready, update Tx producer idx local and on card. */
6233 tw32_tx_mbox(tnapi
->prodmbox
, entry
);
6235 tnapi
->tx_prod
= entry
;
6236 if (unlikely(tg3_tx_avail(tnapi
) <= (MAX_SKB_FRAGS
+ 1))) {
6237 netif_tx_stop_queue(txq
);
6239 /* netif_tx_stop_queue() must be done before checking
6240 * checking tx index in tg3_tx_avail() below, because in
6241 * tg3_tx(), we update tx index before checking for
6242 * netif_tx_queue_stopped().
6245 if (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
))
6246 netif_tx_wake_queue(txq
);
6252 return NETDEV_TX_OK
;
6256 entry
= tnapi
->tx_prod
;
6257 tnapi
->tx_buffers
[entry
].skb
= NULL
;
6258 pci_unmap_single(tp
->pdev
,
6259 dma_unmap_addr(&tnapi
->tx_buffers
[entry
], mapping
),
6262 for (i
= 0; i
<= last
; i
++) {
6263 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
6264 entry
= NEXT_TX(entry
);
6266 pci_unmap_page(tp
->pdev
,
6267 dma_unmap_addr(&tnapi
->tx_buffers
[entry
],
6269 frag
->size
, PCI_DMA_TODEVICE
);
6273 return NETDEV_TX_OK
;
6276 static u32
tg3_fix_features(struct net_device
*dev
, u32 features
)
6278 struct tg3
*tp
= netdev_priv(dev
);
6280 if (dev
->mtu
> ETH_DATA_LEN
&& (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
6281 features
&= ~NETIF_F_ALL_TSO
;
6286 static inline void tg3_set_mtu(struct net_device
*dev
, struct tg3
*tp
,
6291 if (new_mtu
> ETH_DATA_LEN
) {
6292 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
6293 netdev_update_features(dev
);
6294 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
6296 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
6299 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
6300 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
6301 netdev_update_features(dev
);
6303 tp
->tg3_flags
&= ~TG3_FLAG_JUMBO_RING_ENABLE
;
6307 static int tg3_change_mtu(struct net_device
*dev
, int new_mtu
)
6309 struct tg3
*tp
= netdev_priv(dev
);
6312 if (new_mtu
< TG3_MIN_MTU
|| new_mtu
> TG3_MAX_MTU(tp
))
6315 if (!netif_running(dev
)) {
6316 /* We'll just catch it later when the
6319 tg3_set_mtu(dev
, tp
, new_mtu
);
6327 tg3_full_lock(tp
, 1);
6329 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
6331 tg3_set_mtu(dev
, tp
, new_mtu
);
6333 err
= tg3_restart_hw(tp
, 0);
6336 tg3_netif_start(tp
);
6338 tg3_full_unlock(tp
);
6346 static void tg3_rx_prodring_free(struct tg3
*tp
,
6347 struct tg3_rx_prodring_set
*tpr
)
6351 if (tpr
!= &tp
->napi
[0].prodring
) {
6352 for (i
= tpr
->rx_std_cons_idx
; i
!= tpr
->rx_std_prod_idx
;
6353 i
= (i
+ 1) & tp
->rx_std_ring_mask
)
6354 tg3_rx_skb_free(tp
, &tpr
->rx_std_buffers
[i
],
6357 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
6358 for (i
= tpr
->rx_jmb_cons_idx
;
6359 i
!= tpr
->rx_jmb_prod_idx
;
6360 i
= (i
+ 1) & tp
->rx_jmb_ring_mask
) {
6361 tg3_rx_skb_free(tp
, &tpr
->rx_jmb_buffers
[i
],
6369 for (i
= 0; i
<= tp
->rx_std_ring_mask
; i
++)
6370 tg3_rx_skb_free(tp
, &tpr
->rx_std_buffers
[i
],
6373 if ((tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) &&
6374 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
6375 for (i
= 0; i
<= tp
->rx_jmb_ring_mask
; i
++)
6376 tg3_rx_skb_free(tp
, &tpr
->rx_jmb_buffers
[i
],
6381 /* Initialize rx rings for packet processing.
6383 * The chip has been shut down and the driver detached from
6384 * the networking, so no interrupts or new tx packets will
6385 * end up in the driver. tp->{tx,}lock are held and thus
6388 static int tg3_rx_prodring_alloc(struct tg3
*tp
,
6389 struct tg3_rx_prodring_set
*tpr
)
6391 u32 i
, rx_pkt_dma_sz
;
6393 tpr
->rx_std_cons_idx
= 0;
6394 tpr
->rx_std_prod_idx
= 0;
6395 tpr
->rx_jmb_cons_idx
= 0;
6396 tpr
->rx_jmb_prod_idx
= 0;
6398 if (tpr
!= &tp
->napi
[0].prodring
) {
6399 memset(&tpr
->rx_std_buffers
[0], 0,
6400 TG3_RX_STD_BUFF_RING_SIZE(tp
));
6401 if (tpr
->rx_jmb_buffers
)
6402 memset(&tpr
->rx_jmb_buffers
[0], 0,
6403 TG3_RX_JMB_BUFF_RING_SIZE(tp
));
6407 /* Zero out all descriptors. */
6408 memset(tpr
->rx_std
, 0, TG3_RX_STD_RING_BYTES(tp
));
6410 rx_pkt_dma_sz
= TG3_RX_STD_DMA_SZ
;
6411 if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) &&
6412 tp
->dev
->mtu
> ETH_DATA_LEN
)
6413 rx_pkt_dma_sz
= TG3_RX_JMB_DMA_SZ
;
6414 tp
->rx_pkt_map_sz
= TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz
);
6416 /* Initialize invariants of the rings, we only set this
6417 * stuff once. This works because the card does not
6418 * write into the rx buffer posting rings.
6420 for (i
= 0; i
<= tp
->rx_std_ring_mask
; i
++) {
6421 struct tg3_rx_buffer_desc
*rxd
;
6423 rxd
= &tpr
->rx_std
[i
];
6424 rxd
->idx_len
= rx_pkt_dma_sz
<< RXD_LEN_SHIFT
;
6425 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
);
6426 rxd
->opaque
= (RXD_OPAQUE_RING_STD
|
6427 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
6430 /* Now allocate fresh SKBs for each rx ring. */
6431 for (i
= 0; i
< tp
->rx_pending
; i
++) {
6432 if (tg3_alloc_rx_skb(tp
, tpr
, RXD_OPAQUE_RING_STD
, i
) < 0) {
6433 netdev_warn(tp
->dev
,
6434 "Using a smaller RX standard ring. Only "
6435 "%d out of %d buffers were allocated "
6436 "successfully\n", i
, tp
->rx_pending
);
6444 if (!(tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) ||
6445 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
6448 memset(tpr
->rx_jmb
, 0, TG3_RX_JMB_RING_BYTES(tp
));
6450 if (!(tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
))
6453 for (i
= 0; i
<= tp
->rx_jmb_ring_mask
; i
++) {
6454 struct tg3_rx_buffer_desc
*rxd
;
6456 rxd
= &tpr
->rx_jmb
[i
].std
;
6457 rxd
->idx_len
= TG3_RX_JMB_DMA_SZ
<< RXD_LEN_SHIFT
;
6458 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
) |
6460 rxd
->opaque
= (RXD_OPAQUE_RING_JUMBO
|
6461 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
6464 for (i
= 0; i
< tp
->rx_jumbo_pending
; i
++) {
6465 if (tg3_alloc_rx_skb(tp
, tpr
, RXD_OPAQUE_RING_JUMBO
, i
) < 0) {
6466 netdev_warn(tp
->dev
,
6467 "Using a smaller RX jumbo ring. Only %d "
6468 "out of %d buffers were allocated "
6469 "successfully\n", i
, tp
->rx_jumbo_pending
);
6472 tp
->rx_jumbo_pending
= i
;
6481 tg3_rx_prodring_free(tp
, tpr
);
6485 static void tg3_rx_prodring_fini(struct tg3
*tp
,
6486 struct tg3_rx_prodring_set
*tpr
)
6488 kfree(tpr
->rx_std_buffers
);
6489 tpr
->rx_std_buffers
= NULL
;
6490 kfree(tpr
->rx_jmb_buffers
);
6491 tpr
->rx_jmb_buffers
= NULL
;
6493 dma_free_coherent(&tp
->pdev
->dev
, TG3_RX_STD_RING_BYTES(tp
),
6494 tpr
->rx_std
, tpr
->rx_std_mapping
);
6498 dma_free_coherent(&tp
->pdev
->dev
, TG3_RX_JMB_RING_BYTES(tp
),
6499 tpr
->rx_jmb
, tpr
->rx_jmb_mapping
);
6504 static int tg3_rx_prodring_init(struct tg3
*tp
,
6505 struct tg3_rx_prodring_set
*tpr
)
6507 tpr
->rx_std_buffers
= kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp
),
6509 if (!tpr
->rx_std_buffers
)
6512 tpr
->rx_std
= dma_alloc_coherent(&tp
->pdev
->dev
,
6513 TG3_RX_STD_RING_BYTES(tp
),
6514 &tpr
->rx_std_mapping
,
6519 if ((tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) &&
6520 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
6521 tpr
->rx_jmb_buffers
= kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp
),
6523 if (!tpr
->rx_jmb_buffers
)
6526 tpr
->rx_jmb
= dma_alloc_coherent(&tp
->pdev
->dev
,
6527 TG3_RX_JMB_RING_BYTES(tp
),
6528 &tpr
->rx_jmb_mapping
,
6537 tg3_rx_prodring_fini(tp
, tpr
);
6541 /* Free up pending packets in all rx/tx rings.
6543 * The chip has been shut down and the driver detached from
6544 * the networking, so no interrupts or new tx packets will
6545 * end up in the driver. tp->{tx,}lock is not held and we are not
6546 * in an interrupt context and thus may sleep.
6548 static void tg3_free_rings(struct tg3
*tp
)
6552 for (j
= 0; j
< tp
->irq_cnt
; j
++) {
6553 struct tg3_napi
*tnapi
= &tp
->napi
[j
];
6555 tg3_rx_prodring_free(tp
, &tnapi
->prodring
);
6557 if (!tnapi
->tx_buffers
)
6560 for (i
= 0; i
< TG3_TX_RING_SIZE
; ) {
6561 struct ring_info
*txp
;
6562 struct sk_buff
*skb
;
6565 txp
= &tnapi
->tx_buffers
[i
];
6573 pci_unmap_single(tp
->pdev
,
6574 dma_unmap_addr(txp
, mapping
),
6581 for (k
= 0; k
< skb_shinfo(skb
)->nr_frags
; k
++) {
6582 txp
= &tnapi
->tx_buffers
[i
& (TG3_TX_RING_SIZE
- 1)];
6583 pci_unmap_page(tp
->pdev
,
6584 dma_unmap_addr(txp
, mapping
),
6585 skb_shinfo(skb
)->frags
[k
].size
,
6590 dev_kfree_skb_any(skb
);
6595 /* Initialize tx/rx rings for packet processing.
6597 * The chip has been shut down and the driver detached from
6598 * the networking, so no interrupts or new tx packets will
6599 * end up in the driver. tp->{tx,}lock are held and thus
6602 static int tg3_init_rings(struct tg3
*tp
)
6606 /* Free up all the SKBs. */
6609 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6610 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6612 tnapi
->last_tag
= 0;
6613 tnapi
->last_irq_tag
= 0;
6614 tnapi
->hw_status
->status
= 0;
6615 tnapi
->hw_status
->status_tag
= 0;
6616 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6621 memset(tnapi
->tx_ring
, 0, TG3_TX_RING_BYTES
);
6623 tnapi
->rx_rcb_ptr
= 0;
6625 memset(tnapi
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
6627 if (tg3_rx_prodring_alloc(tp
, &tnapi
->prodring
)) {
6637 * Must not be invoked with interrupt sources disabled and
6638 * the hardware shutdown down.
6640 static void tg3_free_consistent(struct tg3
*tp
)
6644 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6645 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6647 if (tnapi
->tx_ring
) {
6648 dma_free_coherent(&tp
->pdev
->dev
, TG3_TX_RING_BYTES
,
6649 tnapi
->tx_ring
, tnapi
->tx_desc_mapping
);
6650 tnapi
->tx_ring
= NULL
;
6653 kfree(tnapi
->tx_buffers
);
6654 tnapi
->tx_buffers
= NULL
;
6656 if (tnapi
->rx_rcb
) {
6657 dma_free_coherent(&tp
->pdev
->dev
,
6658 TG3_RX_RCB_RING_BYTES(tp
),
6660 tnapi
->rx_rcb_mapping
);
6661 tnapi
->rx_rcb
= NULL
;
6664 tg3_rx_prodring_fini(tp
, &tnapi
->prodring
);
6666 if (tnapi
->hw_status
) {
6667 dma_free_coherent(&tp
->pdev
->dev
, TG3_HW_STATUS_SIZE
,
6669 tnapi
->status_mapping
);
6670 tnapi
->hw_status
= NULL
;
6675 dma_free_coherent(&tp
->pdev
->dev
, sizeof(struct tg3_hw_stats
),
6676 tp
->hw_stats
, tp
->stats_mapping
);
6677 tp
->hw_stats
= NULL
;
6682 * Must not be invoked with interrupt sources disabled and
6683 * the hardware shutdown down. Can sleep.
6685 static int tg3_alloc_consistent(struct tg3
*tp
)
6689 tp
->hw_stats
= dma_alloc_coherent(&tp
->pdev
->dev
,
6690 sizeof(struct tg3_hw_stats
),
6696 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
6698 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6699 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6700 struct tg3_hw_status
*sblk
;
6702 tnapi
->hw_status
= dma_alloc_coherent(&tp
->pdev
->dev
,
6704 &tnapi
->status_mapping
,
6706 if (!tnapi
->hw_status
)
6709 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6710 sblk
= tnapi
->hw_status
;
6712 if (tg3_rx_prodring_init(tp
, &tnapi
->prodring
))
6715 /* If multivector TSS is enabled, vector 0 does not handle
6716 * tx interrupts. Don't allocate any resources for it.
6718 if ((!i
&& !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)) ||
6719 (i
&& (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
))) {
6720 tnapi
->tx_buffers
= kzalloc(sizeof(struct ring_info
) *
6723 if (!tnapi
->tx_buffers
)
6726 tnapi
->tx_ring
= dma_alloc_coherent(&tp
->pdev
->dev
,
6728 &tnapi
->tx_desc_mapping
,
6730 if (!tnapi
->tx_ring
)
6735 * When RSS is enabled, the status block format changes
6736 * slightly. The "rx_jumbo_consumer", "reserved",
6737 * and "rx_mini_consumer" members get mapped to the
6738 * other three rx return ring producer indexes.
6742 tnapi
->rx_rcb_prod_idx
= &sblk
->idx
[0].rx_producer
;
6745 tnapi
->rx_rcb_prod_idx
= &sblk
->rx_jumbo_consumer
;
6748 tnapi
->rx_rcb_prod_idx
= &sblk
->reserved
;
6751 tnapi
->rx_rcb_prod_idx
= &sblk
->rx_mini_consumer
;
6756 * If multivector RSS is enabled, vector 0 does not handle
6757 * rx or tx interrupts. Don't allocate any resources for it.
6759 if (!i
&& (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
))
6762 tnapi
->rx_rcb
= dma_alloc_coherent(&tp
->pdev
->dev
,
6763 TG3_RX_RCB_RING_BYTES(tp
),
6764 &tnapi
->rx_rcb_mapping
,
6769 memset(tnapi
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
6775 tg3_free_consistent(tp
);
6779 #define MAX_WAIT_CNT 1000
6781 /* To stop a block, clear the enable bit and poll till it
6782 * clears. tp->lock is held.
6784 static int tg3_stop_block(struct tg3
*tp
, unsigned long ofs
, u32 enable_bit
, int silent
)
6789 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
6796 /* We can't enable/disable these bits of the
6797 * 5705/5750, just say success.
6810 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
6813 if ((val
& enable_bit
) == 0)
6817 if (i
== MAX_WAIT_CNT
&& !silent
) {
6818 dev_err(&tp
->pdev
->dev
,
6819 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6827 /* tp->lock is held. */
6828 static int tg3_abort_hw(struct tg3
*tp
, int silent
)
6832 tg3_disable_ints(tp
);
6834 tp
->rx_mode
&= ~RX_MODE_ENABLE
;
6835 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
6838 err
= tg3_stop_block(tp
, RCVBDI_MODE
, RCVBDI_MODE_ENABLE
, silent
);
6839 err
|= tg3_stop_block(tp
, RCVLPC_MODE
, RCVLPC_MODE_ENABLE
, silent
);
6840 err
|= tg3_stop_block(tp
, RCVLSC_MODE
, RCVLSC_MODE_ENABLE
, silent
);
6841 err
|= tg3_stop_block(tp
, RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
, silent
);
6842 err
|= tg3_stop_block(tp
, RCVDCC_MODE
, RCVDCC_MODE_ENABLE
, silent
);
6843 err
|= tg3_stop_block(tp
, RCVCC_MODE
, RCVCC_MODE_ENABLE
, silent
);
6845 err
|= tg3_stop_block(tp
, SNDBDS_MODE
, SNDBDS_MODE_ENABLE
, silent
);
6846 err
|= tg3_stop_block(tp
, SNDBDI_MODE
, SNDBDI_MODE_ENABLE
, silent
);
6847 err
|= tg3_stop_block(tp
, SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
, silent
);
6848 err
|= tg3_stop_block(tp
, RDMAC_MODE
, RDMAC_MODE_ENABLE
, silent
);
6849 err
|= tg3_stop_block(tp
, SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
, silent
);
6850 err
|= tg3_stop_block(tp
, DMAC_MODE
, DMAC_MODE_ENABLE
, silent
);
6851 err
|= tg3_stop_block(tp
, SNDBDC_MODE
, SNDBDC_MODE_ENABLE
, silent
);
6853 tp
->mac_mode
&= ~MAC_MODE_TDE_ENABLE
;
6854 tw32_f(MAC_MODE
, tp
->mac_mode
);
6857 tp
->tx_mode
&= ~TX_MODE_ENABLE
;
6858 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
6860 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
6862 if (!(tr32(MAC_TX_MODE
) & TX_MODE_ENABLE
))
6865 if (i
>= MAX_WAIT_CNT
) {
6866 dev_err(&tp
->pdev
->dev
,
6867 "%s timed out, TX_MODE_ENABLE will not clear "
6868 "MAC_TX_MODE=%08x\n", __func__
, tr32(MAC_TX_MODE
));
6872 err
|= tg3_stop_block(tp
, HOSTCC_MODE
, HOSTCC_MODE_ENABLE
, silent
);
6873 err
|= tg3_stop_block(tp
, WDMAC_MODE
, WDMAC_MODE_ENABLE
, silent
);
6874 err
|= tg3_stop_block(tp
, MBFREE_MODE
, MBFREE_MODE_ENABLE
, silent
);
6876 tw32(FTQ_RESET
, 0xffffffff);
6877 tw32(FTQ_RESET
, 0x00000000);
6879 err
|= tg3_stop_block(tp
, BUFMGR_MODE
, BUFMGR_MODE_ENABLE
, silent
);
6880 err
|= tg3_stop_block(tp
, MEMARB_MODE
, MEMARB_MODE_ENABLE
, silent
);
6882 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6883 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6884 if (tnapi
->hw_status
)
6885 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6888 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
6893 static void tg3_ape_send_event(struct tg3
*tp
, u32 event
)
6898 /* NCSI does not support APE events */
6899 if (tp
->tg3_flags3
& TG3_FLG3_APE_HAS_NCSI
)
6902 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
6903 if (apedata
!= APE_SEG_SIG_MAGIC
)
6906 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
6907 if (!(apedata
& APE_FW_STATUS_READY
))
6910 /* Wait for up to 1 millisecond for APE to service previous event. */
6911 for (i
= 0; i
< 10; i
++) {
6912 if (tg3_ape_lock(tp
, TG3_APE_LOCK_MEM
))
6915 apedata
= tg3_ape_read32(tp
, TG3_APE_EVENT_STATUS
);
6917 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6918 tg3_ape_write32(tp
, TG3_APE_EVENT_STATUS
,
6919 event
| APE_EVENT_STATUS_EVENT_PENDING
);
6921 tg3_ape_unlock(tp
, TG3_APE_LOCK_MEM
);
6923 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6929 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6930 tg3_ape_write32(tp
, TG3_APE_EVENT
, APE_EVENT_1
);
6933 static void tg3_ape_driver_state_change(struct tg3
*tp
, int kind
)
6938 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
6942 case RESET_KIND_INIT
:
6943 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
,
6944 APE_HOST_SEG_SIG_MAGIC
);
6945 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_LEN
,
6946 APE_HOST_SEG_LEN_MAGIC
);
6947 apedata
= tg3_ape_read32(tp
, TG3_APE_HOST_INIT_COUNT
);
6948 tg3_ape_write32(tp
, TG3_APE_HOST_INIT_COUNT
, ++apedata
);
6949 tg3_ape_write32(tp
, TG3_APE_HOST_DRIVER_ID
,
6950 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM
, TG3_MIN_NUM
));
6951 tg3_ape_write32(tp
, TG3_APE_HOST_BEHAVIOR
,
6952 APE_HOST_BEHAV_NO_PHYLOCK
);
6953 tg3_ape_write32(tp
, TG3_APE_HOST_DRVR_STATE
,
6954 TG3_APE_HOST_DRVR_STATE_START
);
6956 event
= APE_EVENT_STATUS_STATE_START
;
6958 case RESET_KIND_SHUTDOWN
:
6959 /* With the interface we are currently using,
6960 * APE does not track driver state. Wiping
6961 * out the HOST SEGMENT SIGNATURE forces
6962 * the APE to assume OS absent status.
6964 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
, 0x0);
6966 if (device_may_wakeup(&tp
->pdev
->dev
) &&
6967 (tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
)) {
6968 tg3_ape_write32(tp
, TG3_APE_HOST_WOL_SPEED
,
6969 TG3_APE_HOST_WOL_SPEED_AUTO
);
6970 apedata
= TG3_APE_HOST_DRVR_STATE_WOL
;
6972 apedata
= TG3_APE_HOST_DRVR_STATE_UNLOAD
;
6974 tg3_ape_write32(tp
, TG3_APE_HOST_DRVR_STATE
, apedata
);
6976 event
= APE_EVENT_STATUS_STATE_UNLOAD
;
6978 case RESET_KIND_SUSPEND
:
6979 event
= APE_EVENT_STATUS_STATE_SUSPEND
;
6985 event
|= APE_EVENT_STATUS_DRIVER_EVNT
| APE_EVENT_STATUS_STATE_CHNGE
;
6987 tg3_ape_send_event(tp
, event
);
6990 /* tp->lock is held. */
6991 static void tg3_write_sig_pre_reset(struct tg3
*tp
, int kind
)
6993 tg3_write_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
,
6994 NIC_SRAM_FIRMWARE_MBOX_MAGIC1
);
6996 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
6998 case RESET_KIND_INIT
:
6999 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
7003 case RESET_KIND_SHUTDOWN
:
7004 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
7008 case RESET_KIND_SUSPEND
:
7009 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
7018 if (kind
== RESET_KIND_INIT
||
7019 kind
== RESET_KIND_SUSPEND
)
7020 tg3_ape_driver_state_change(tp
, kind
);
7023 /* tp->lock is held. */
7024 static void tg3_write_sig_post_reset(struct tg3
*tp
, int kind
)
7026 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
7028 case RESET_KIND_INIT
:
7029 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
7030 DRV_STATE_START_DONE
);
7033 case RESET_KIND_SHUTDOWN
:
7034 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
7035 DRV_STATE_UNLOAD_DONE
);
7043 if (kind
== RESET_KIND_SHUTDOWN
)
7044 tg3_ape_driver_state_change(tp
, kind
);
7047 /* tp->lock is held. */
7048 static void tg3_write_sig_legacy(struct tg3
*tp
, int kind
)
7050 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
7052 case RESET_KIND_INIT
:
7053 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
7057 case RESET_KIND_SHUTDOWN
:
7058 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
7062 case RESET_KIND_SUSPEND
:
7063 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
7073 static int tg3_poll_fw(struct tg3
*tp
)
7078 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
7079 /* Wait up to 20ms for init done. */
7080 for (i
= 0; i
< 200; i
++) {
7081 if (tr32(VCPU_STATUS
) & VCPU_STATUS_INIT_DONE
)
7088 /* Wait for firmware initialization to complete. */
7089 for (i
= 0; i
< 100000; i
++) {
7090 tg3_read_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
, &val
);
7091 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
7096 /* Chip might not be fitted with firmware. Some Sun onboard
7097 * parts are configured like that. So don't signal the timeout
7098 * of the above loop as an error, but do report the lack of
7099 * running firmware once.
7102 !(tp
->tg3_flags2
& TG3_FLG2_NO_FWARE_REPORTED
)) {
7103 tp
->tg3_flags2
|= TG3_FLG2_NO_FWARE_REPORTED
;
7105 netdev_info(tp
->dev
, "No firmware running\n");
7108 if (tp
->pci_chip_rev_id
== CHIPREV_ID_57765_A0
) {
7109 /* The 57765 A0 needs a little more
7110 * time to do some important work.
7118 /* Save PCI command register before chip reset */
7119 static void tg3_save_pci_state(struct tg3
*tp
)
7121 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &tp
->pci_cmd
);
7124 /* Restore PCI state after chip reset */
7125 static void tg3_restore_pci_state(struct tg3
*tp
)
7129 /* Re-enable indirect register accesses. */
7130 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
7131 tp
->misc_host_ctrl
);
7133 /* Set MAX PCI retry to zero. */
7134 val
= (PCISTATE_ROM_ENABLE
| PCISTATE_ROM_RETRY_ENABLE
);
7135 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
7136 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
))
7137 val
|= PCISTATE_RETRY_SAME_DMA
;
7138 /* Allow reads and writes to the APE register and memory space. */
7139 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
7140 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
7141 PCISTATE_ALLOW_APE_SHMEM_WR
|
7142 PCISTATE_ALLOW_APE_PSPACE_WR
;
7143 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, val
);
7145 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, tp
->pci_cmd
);
7147 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
) {
7148 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
7149 pcie_set_readrq(tp
->pdev
, tp
->pcie_readrq
);
7151 pci_write_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
7152 tp
->pci_cacheline_sz
);
7153 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
7158 /* Make sure PCI-X relaxed ordering bit is clear. */
7159 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
7162 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
7164 pcix_cmd
&= ~PCI_X_CMD_ERO
;
7165 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
7169 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
7171 /* Chip reset on 5780 will reset MSI enable bit,
7172 * so need to restore it.
7174 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
7177 pci_read_config_word(tp
->pdev
,
7178 tp
->msi_cap
+ PCI_MSI_FLAGS
,
7180 pci_write_config_word(tp
->pdev
,
7181 tp
->msi_cap
+ PCI_MSI_FLAGS
,
7182 ctrl
| PCI_MSI_FLAGS_ENABLE
);
7183 val
= tr32(MSGINT_MODE
);
7184 tw32(MSGINT_MODE
, val
| MSGINT_MODE_ENABLE
);
7189 static void tg3_stop_fw(struct tg3
*);
7191 /* tp->lock is held. */
7192 static int tg3_chip_reset(struct tg3
*tp
)
7195 void (*write_op
)(struct tg3
*, u32
, u32
);
7200 tg3_ape_lock(tp
, TG3_APE_LOCK_GRC
);
7202 /* No matching tg3_nvram_unlock() after this because
7203 * chip reset below will undo the nvram lock.
7205 tp
->nvram_lock_cnt
= 0;
7207 /* GRC_MISC_CFG core clock reset will clear the memory
7208 * enable bit in PCI register 4 and the MSI enable bit
7209 * on some chips, so we save relevant registers here.
7211 tg3_save_pci_state(tp
);
7213 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
7214 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
))
7215 tw32(GRC_FASTBOOT_PC
, 0);
7218 * We must avoid the readl() that normally takes place.
7219 * It locks machines, causes machine checks, and other
7220 * fun things. So, temporarily disable the 5701
7221 * hardware workaround, while we do the reset.
7223 write_op
= tp
->write32
;
7224 if (write_op
== tg3_write_flush_reg32
)
7225 tp
->write32
= tg3_write32
;
7227 /* Prevent the irq handler from reading or writing PCI registers
7228 * during chip reset when the memory enable bit in the PCI command
7229 * register may be cleared. The chip does not generate interrupt
7230 * at this time, but the irq handler may still be called due to irq
7231 * sharing or irqpoll.
7233 tp
->tg3_flags
|= TG3_FLAG_CHIP_RESETTING
;
7234 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
7235 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
7236 if (tnapi
->hw_status
) {
7237 tnapi
->hw_status
->status
= 0;
7238 tnapi
->hw_status
->status_tag
= 0;
7240 tnapi
->last_tag
= 0;
7241 tnapi
->last_irq_tag
= 0;
7245 for (i
= 0; i
< tp
->irq_cnt
; i
++)
7246 synchronize_irq(tp
->napi
[i
].irq_vec
);
7248 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
7249 val
= tr32(TG3_PCIE_LNKCTL
) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
7250 tw32(TG3_PCIE_LNKCTL
, val
| TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
);
7254 val
= GRC_MISC_CFG_CORECLK_RESET
;
7256 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
7257 /* Force PCIe 1.0a mode */
7258 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
7259 !(tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
) &&
7260 tr32(TG3_PCIE_PHY_TSTCTL
) ==
7261 (TG3_PCIE_PHY_TSTCTL_PCIE10
| TG3_PCIE_PHY_TSTCTL_PSCRAM
))
7262 tw32(TG3_PCIE_PHY_TSTCTL
, TG3_PCIE_PHY_TSTCTL_PSCRAM
);
7264 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
) {
7265 tw32(GRC_MISC_CFG
, (1 << 29));
7270 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
7271 tw32(VCPU_STATUS
, tr32(VCPU_STATUS
) | VCPU_STATUS_DRV_RESET
);
7272 tw32(GRC_VCPU_EXT_CTRL
,
7273 tr32(GRC_VCPU_EXT_CTRL
) & ~GRC_VCPU_EXT_CTRL_HALT_CPU
);
7276 /* Manage gphy power for all CPMU absent PCIe devices. */
7277 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
7278 !(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
))
7279 val
|= GRC_MISC_CFG_KEEP_GPHY_POWER
;
7281 tw32(GRC_MISC_CFG
, val
);
7283 /* restore 5701 hardware bug workaround write method */
7284 tp
->write32
= write_op
;
7286 /* Unfortunately, we have to delay before the PCI read back.
7287 * Some 575X chips even will not respond to a PCI cfg access
7288 * when the reset command is given to the chip.
7290 * How do these hardware designers expect things to work
7291 * properly if the PCI write is posted for a long period
7292 * of time? It is always necessary to have some method by
7293 * which a register read back can occur to push the write
7294 * out which does the reset.
7296 * For most tg3 variants the trick below was working.
7301 /* Flush PCI posted writes. The normal MMIO registers
7302 * are inaccessible at this time so this is the only
7303 * way to make this reliably (actually, this is no longer
7304 * the case, see above). I tried to use indirect
7305 * register read/write but this upset some 5701 variants.
7307 pci_read_config_dword(tp
->pdev
, PCI_COMMAND
, &val
);
7311 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) && tp
->pcie_cap
) {
7314 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
) {
7318 /* Wait for link training to complete. */
7319 for (i
= 0; i
< 5000; i
++)
7322 pci_read_config_dword(tp
->pdev
, 0xc4, &cfg_val
);
7323 pci_write_config_dword(tp
->pdev
, 0xc4,
7324 cfg_val
| (1 << 15));
7327 /* Clear the "no snoop" and "relaxed ordering" bits. */
7328 pci_read_config_word(tp
->pdev
,
7329 tp
->pcie_cap
+ PCI_EXP_DEVCTL
,
7331 val16
&= ~(PCI_EXP_DEVCTL_RELAX_EN
|
7332 PCI_EXP_DEVCTL_NOSNOOP_EN
);
7334 * Older PCIe devices only support the 128 byte
7335 * MPS setting. Enforce the restriction.
7337 if (!(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
))
7338 val16
&= ~PCI_EXP_DEVCTL_PAYLOAD
;
7339 pci_write_config_word(tp
->pdev
,
7340 tp
->pcie_cap
+ PCI_EXP_DEVCTL
,
7343 pcie_set_readrq(tp
->pdev
, tp
->pcie_readrq
);
7345 /* Clear error status */
7346 pci_write_config_word(tp
->pdev
,
7347 tp
->pcie_cap
+ PCI_EXP_DEVSTA
,
7348 PCI_EXP_DEVSTA_CED
|
7349 PCI_EXP_DEVSTA_NFED
|
7350 PCI_EXP_DEVSTA_FED
|
7351 PCI_EXP_DEVSTA_URD
);
7354 tg3_restore_pci_state(tp
);
7356 tp
->tg3_flags
&= ~(TG3_FLAG_CHIP_RESETTING
|
7357 TG3_FLAG_ERROR_PROCESSED
);
7360 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
7361 val
= tr32(MEMARB_MODE
);
7362 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
7364 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A3
) {
7366 tw32(0x5000, 0x400);
7369 tw32(GRC_MODE
, tp
->grc_mode
);
7371 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
) {
7374 tw32(0xc4, val
| (1 << 15));
7377 if ((tp
->nic_sram_data_cfg
& NIC_SRAM_DATA_CFG_MINI_PCI
) != 0 &&
7378 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
7379 tp
->pci_clock_ctrl
|= CLOCK_CTRL_CLKRUN_OENABLE
;
7380 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
)
7381 tp
->pci_clock_ctrl
|= CLOCK_CTRL_FORCE_CLKRUN
;
7382 tw32(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
7385 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
7386 tp
->mac_mode
= MAC_MODE_APE_TX_EN
|
7387 MAC_MODE_APE_RX_EN
|
7388 MAC_MODE_TDE_ENABLE
;
7390 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
7391 tp
->mac_mode
|= MAC_MODE_PORT_MODE_TBI
;
7393 } else if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) {
7394 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
7399 tw32_f(MAC_MODE
, val
);
7402 tg3_ape_unlock(tp
, TG3_APE_LOCK_GRC
);
7404 err
= tg3_poll_fw(tp
);
7410 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
7411 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
&&
7412 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
7413 !(tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
)) {
7416 tw32(0x7c00, val
| (1 << 25));
7419 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
) {
7420 val
= tr32(TG3_CPMU_CLCK_ORIDE
);
7421 tw32(TG3_CPMU_CLCK_ORIDE
, val
& ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN
);
7424 /* Reprobe ASF enable state. */
7425 tp
->tg3_flags
&= ~TG3_FLAG_ENABLE_ASF
;
7426 tp
->tg3_flags2
&= ~TG3_FLG2_ASF_NEW_HANDSHAKE
;
7427 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
7428 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
7431 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
7432 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
7433 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
7434 tp
->last_event_jiffies
= jiffies
;
7435 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
7436 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
7443 /* tp->lock is held. */
7444 static void tg3_stop_fw(struct tg3
*tp
)
7446 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
7447 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
7448 /* Wait for RX cpu to ACK the previous event. */
7449 tg3_wait_for_event_ack(tp
);
7451 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_PAUSE_FW
);
7453 tg3_generate_fw_event(tp
);
7455 /* Wait for RX cpu to ACK this event. */
7456 tg3_wait_for_event_ack(tp
);
7460 /* tp->lock is held. */
7461 static int tg3_halt(struct tg3
*tp
, int kind
, int silent
)
7467 tg3_write_sig_pre_reset(tp
, kind
);
7469 tg3_abort_hw(tp
, silent
);
7470 err
= tg3_chip_reset(tp
);
7472 __tg3_set_mac_addr(tp
, 0);
7474 tg3_write_sig_legacy(tp
, kind
);
7475 tg3_write_sig_post_reset(tp
, kind
);
7483 #define RX_CPU_SCRATCH_BASE 0x30000
7484 #define RX_CPU_SCRATCH_SIZE 0x04000
7485 #define TX_CPU_SCRATCH_BASE 0x34000
7486 #define TX_CPU_SCRATCH_SIZE 0x04000
7488 /* tp->lock is held. */
7489 static int tg3_halt_cpu(struct tg3
*tp
, u32 offset
)
7493 BUG_ON(offset
== TX_CPU_BASE
&&
7494 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
));
7496 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
7497 u32 val
= tr32(GRC_VCPU_EXT_CTRL
);
7499 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_HALT_CPU
);
7502 if (offset
== RX_CPU_BASE
) {
7503 for (i
= 0; i
< 10000; i
++) {
7504 tw32(offset
+ CPU_STATE
, 0xffffffff);
7505 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
7506 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
7510 tw32(offset
+ CPU_STATE
, 0xffffffff);
7511 tw32_f(offset
+ CPU_MODE
, CPU_MODE_HALT
);
7514 for (i
= 0; i
< 10000; i
++) {
7515 tw32(offset
+ CPU_STATE
, 0xffffffff);
7516 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
7517 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
7523 netdev_err(tp
->dev
, "%s timed out, %s CPU\n",
7524 __func__
, offset
== RX_CPU_BASE
? "RX" : "TX");
7528 /* Clear firmware's nvram arbitration. */
7529 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
7530 tw32(NVRAM_SWARB
, SWARB_REQ_CLR0
);
7535 unsigned int fw_base
;
7536 unsigned int fw_len
;
7537 const __be32
*fw_data
;
7540 /* tp->lock is held. */
7541 static int tg3_load_firmware_cpu(struct tg3
*tp
, u32 cpu_base
, u32 cpu_scratch_base
,
7542 int cpu_scratch_size
, struct fw_info
*info
)
7544 int err
, lock_err
, i
;
7545 void (*write_op
)(struct tg3
*, u32
, u32
);
7547 if (cpu_base
== TX_CPU_BASE
&&
7548 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7550 "%s: Trying to load TX cpu firmware which is 5705\n",
7555 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
7556 write_op
= tg3_write_mem
;
7558 write_op
= tg3_write_indirect_reg32
;
7560 /* It is possible that bootcode is still loading at this point.
7561 * Get the nvram lock first before halting the cpu.
7563 lock_err
= tg3_nvram_lock(tp
);
7564 err
= tg3_halt_cpu(tp
, cpu_base
);
7566 tg3_nvram_unlock(tp
);
7570 for (i
= 0; i
< cpu_scratch_size
; i
+= sizeof(u32
))
7571 write_op(tp
, cpu_scratch_base
+ i
, 0);
7572 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7573 tw32(cpu_base
+ CPU_MODE
, tr32(cpu_base
+CPU_MODE
)|CPU_MODE_HALT
);
7574 for (i
= 0; i
< (info
->fw_len
/ sizeof(u32
)); i
++)
7575 write_op(tp
, (cpu_scratch_base
+
7576 (info
->fw_base
& 0xffff) +
7578 be32_to_cpu(info
->fw_data
[i
]));
7586 /* tp->lock is held. */
7587 static int tg3_load_5701_a0_firmware_fix(struct tg3
*tp
)
7589 struct fw_info info
;
7590 const __be32
*fw_data
;
7593 fw_data
= (void *)tp
->fw
->data
;
7595 /* Firmware blob starts with version numbers, followed by
7596 start address and length. We are setting complete length.
7597 length = end_address_of_bss - start_address_of_text.
7598 Remainder is the blob to be loaded contiguously
7599 from start address. */
7601 info
.fw_base
= be32_to_cpu(fw_data
[1]);
7602 info
.fw_len
= tp
->fw
->size
- 12;
7603 info
.fw_data
= &fw_data
[3];
7605 err
= tg3_load_firmware_cpu(tp
, RX_CPU_BASE
,
7606 RX_CPU_SCRATCH_BASE
, RX_CPU_SCRATCH_SIZE
,
7611 err
= tg3_load_firmware_cpu(tp
, TX_CPU_BASE
,
7612 TX_CPU_SCRATCH_BASE
, TX_CPU_SCRATCH_SIZE
,
7617 /* Now startup only the RX cpu. */
7618 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
7619 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
7621 for (i
= 0; i
< 5; i
++) {
7622 if (tr32(RX_CPU_BASE
+ CPU_PC
) == info
.fw_base
)
7624 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
7625 tw32(RX_CPU_BASE
+ CPU_MODE
, CPU_MODE_HALT
);
7626 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
7630 netdev_err(tp
->dev
, "%s fails to set RX CPU PC, is %08x "
7631 "should be %08x\n", __func__
,
7632 tr32(RX_CPU_BASE
+ CPU_PC
), info
.fw_base
);
7635 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
7636 tw32_f(RX_CPU_BASE
+ CPU_MODE
, 0x00000000);
7641 /* 5705 needs a special version of the TSO firmware. */
7643 /* tp->lock is held. */
7644 static int tg3_load_tso_firmware(struct tg3
*tp
)
7646 struct fw_info info
;
7647 const __be32
*fw_data
;
7648 unsigned long cpu_base
, cpu_scratch_base
, cpu_scratch_size
;
7651 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
7654 fw_data
= (void *)tp
->fw
->data
;
7656 /* Firmware blob starts with version numbers, followed by
7657 start address and length. We are setting complete length.
7658 length = end_address_of_bss - start_address_of_text.
7659 Remainder is the blob to be loaded contiguously
7660 from start address. */
7662 info
.fw_base
= be32_to_cpu(fw_data
[1]);
7663 cpu_scratch_size
= tp
->fw_len
;
7664 info
.fw_len
= tp
->fw
->size
- 12;
7665 info
.fw_data
= &fw_data
[3];
7667 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
7668 cpu_base
= RX_CPU_BASE
;
7669 cpu_scratch_base
= NIC_SRAM_MBUF_POOL_BASE5705
;
7671 cpu_base
= TX_CPU_BASE
;
7672 cpu_scratch_base
= TX_CPU_SCRATCH_BASE
;
7673 cpu_scratch_size
= TX_CPU_SCRATCH_SIZE
;
7676 err
= tg3_load_firmware_cpu(tp
, cpu_base
,
7677 cpu_scratch_base
, cpu_scratch_size
,
7682 /* Now startup the cpu. */
7683 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7684 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
7686 for (i
= 0; i
< 5; i
++) {
7687 if (tr32(cpu_base
+ CPU_PC
) == info
.fw_base
)
7689 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7690 tw32(cpu_base
+ CPU_MODE
, CPU_MODE_HALT
);
7691 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
7696 "%s fails to set CPU PC, is %08x should be %08x\n",
7697 __func__
, tr32(cpu_base
+ CPU_PC
), info
.fw_base
);
7700 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7701 tw32_f(cpu_base
+ CPU_MODE
, 0x00000000);
7706 static int tg3_set_mac_addr(struct net_device
*dev
, void *p
)
7708 struct tg3
*tp
= netdev_priv(dev
);
7709 struct sockaddr
*addr
= p
;
7710 int err
= 0, skip_mac_1
= 0;
7712 if (!is_valid_ether_addr(addr
->sa_data
))
7715 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
7717 if (!netif_running(dev
))
7720 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
7721 u32 addr0_high
, addr0_low
, addr1_high
, addr1_low
;
7723 addr0_high
= tr32(MAC_ADDR_0_HIGH
);
7724 addr0_low
= tr32(MAC_ADDR_0_LOW
);
7725 addr1_high
= tr32(MAC_ADDR_1_HIGH
);
7726 addr1_low
= tr32(MAC_ADDR_1_LOW
);
7728 /* Skip MAC addr 1 if ASF is using it. */
7729 if ((addr0_high
!= addr1_high
|| addr0_low
!= addr1_low
) &&
7730 !(addr1_high
== 0 && addr1_low
== 0))
7733 spin_lock_bh(&tp
->lock
);
7734 __tg3_set_mac_addr(tp
, skip_mac_1
);
7735 spin_unlock_bh(&tp
->lock
);
7740 /* tp->lock is held. */
7741 static void tg3_set_bdinfo(struct tg3
*tp
, u32 bdinfo_addr
,
7742 dma_addr_t mapping
, u32 maxlen_flags
,
7746 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
7747 ((u64
) mapping
>> 32));
7749 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
),
7750 ((u64
) mapping
& 0xffffffff));
7752 (bdinfo_addr
+ TG3_BDINFO_MAXLEN_FLAGS
),
7755 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7757 (bdinfo_addr
+ TG3_BDINFO_NIC_ADDR
),
7761 static void __tg3_set_rx_mode(struct net_device
*);
7762 static void __tg3_set_coalesce(struct tg3
*tp
, struct ethtool_coalesce
*ec
)
7766 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)) {
7767 tw32(HOSTCC_TXCOL_TICKS
, ec
->tx_coalesce_usecs
);
7768 tw32(HOSTCC_TXMAX_FRAMES
, ec
->tx_max_coalesced_frames
);
7769 tw32(HOSTCC_TXCOAL_MAXF_INT
, ec
->tx_max_coalesced_frames_irq
);
7771 tw32(HOSTCC_TXCOL_TICKS
, 0);
7772 tw32(HOSTCC_TXMAX_FRAMES
, 0);
7773 tw32(HOSTCC_TXCOAL_MAXF_INT
, 0);
7776 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)) {
7777 tw32(HOSTCC_RXCOL_TICKS
, ec
->rx_coalesce_usecs
);
7778 tw32(HOSTCC_RXMAX_FRAMES
, ec
->rx_max_coalesced_frames
);
7779 tw32(HOSTCC_RXCOAL_MAXF_INT
, ec
->rx_max_coalesced_frames_irq
);
7781 tw32(HOSTCC_RXCOL_TICKS
, 0);
7782 tw32(HOSTCC_RXMAX_FRAMES
, 0);
7783 tw32(HOSTCC_RXCOAL_MAXF_INT
, 0);
7786 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7787 u32 val
= ec
->stats_block_coalesce_usecs
;
7789 tw32(HOSTCC_RXCOAL_TICK_INT
, ec
->rx_coalesce_usecs_irq
);
7790 tw32(HOSTCC_TXCOAL_TICK_INT
, ec
->tx_coalesce_usecs_irq
);
7792 if (!netif_carrier_ok(tp
->dev
))
7795 tw32(HOSTCC_STAT_COAL_TICKS
, val
);
7798 for (i
= 0; i
< tp
->irq_cnt
- 1; i
++) {
7801 reg
= HOSTCC_RXCOL_TICKS_VEC1
+ i
* 0x18;
7802 tw32(reg
, ec
->rx_coalesce_usecs
);
7803 reg
= HOSTCC_RXMAX_FRAMES_VEC1
+ i
* 0x18;
7804 tw32(reg
, ec
->rx_max_coalesced_frames
);
7805 reg
= HOSTCC_RXCOAL_MAXF_INT_VEC1
+ i
* 0x18;
7806 tw32(reg
, ec
->rx_max_coalesced_frames_irq
);
7808 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
) {
7809 reg
= HOSTCC_TXCOL_TICKS_VEC1
+ i
* 0x18;
7810 tw32(reg
, ec
->tx_coalesce_usecs
);
7811 reg
= HOSTCC_TXMAX_FRAMES_VEC1
+ i
* 0x18;
7812 tw32(reg
, ec
->tx_max_coalesced_frames
);
7813 reg
= HOSTCC_TXCOAL_MAXF_INT_VEC1
+ i
* 0x18;
7814 tw32(reg
, ec
->tx_max_coalesced_frames_irq
);
7818 for (; i
< tp
->irq_max
- 1; i
++) {
7819 tw32(HOSTCC_RXCOL_TICKS_VEC1
+ i
* 0x18, 0);
7820 tw32(HOSTCC_RXMAX_FRAMES_VEC1
+ i
* 0x18, 0);
7821 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1
+ i
* 0x18, 0);
7823 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
) {
7824 tw32(HOSTCC_TXCOL_TICKS_VEC1
+ i
* 0x18, 0);
7825 tw32(HOSTCC_TXMAX_FRAMES_VEC1
+ i
* 0x18, 0);
7826 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1
+ i
* 0x18, 0);
7831 /* tp->lock is held. */
7832 static void tg3_rings_reset(struct tg3
*tp
)
7835 u32 stblk
, txrcb
, rxrcb
, limit
;
7836 struct tg3_napi
*tnapi
= &tp
->napi
[0];
7838 /* Disable all transmit rings but the first. */
7839 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7840 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 16;
7841 else if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)
7842 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 4;
7843 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
7844 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 2;
7846 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
;
7848 for (txrcb
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
;
7849 txrcb
< limit
; txrcb
+= TG3_BDINFO_SIZE
)
7850 tg3_write_mem(tp
, txrcb
+ TG3_BDINFO_MAXLEN_FLAGS
,
7851 BDINFO_FLAGS_DISABLED
);
7854 /* Disable all receive return rings but the first. */
7855 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)
7856 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 17;
7857 else if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7858 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 16;
7859 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
7860 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
7861 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 4;
7863 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
;
7865 for (rxrcb
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
;
7866 rxrcb
< limit
; rxrcb
+= TG3_BDINFO_SIZE
)
7867 tg3_write_mem(tp
, rxrcb
+ TG3_BDINFO_MAXLEN_FLAGS
,
7868 BDINFO_FLAGS_DISABLED
);
7870 /* Disable interrupts */
7871 tw32_mailbox_f(tp
->napi
[0].int_mbox
, 1);
7873 /* Zero mailbox registers. */
7874 if (tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
) {
7875 for (i
= 1; i
< tp
->irq_max
; i
++) {
7876 tp
->napi
[i
].tx_prod
= 0;
7877 tp
->napi
[i
].tx_cons
= 0;
7878 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
7879 tw32_mailbox(tp
->napi
[i
].prodmbox
, 0);
7880 tw32_rx_mbox(tp
->napi
[i
].consmbox
, 0);
7881 tw32_mailbox_f(tp
->napi
[i
].int_mbox
, 1);
7883 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
))
7884 tw32_mailbox(tp
->napi
[0].prodmbox
, 0);
7886 tp
->napi
[0].tx_prod
= 0;
7887 tp
->napi
[0].tx_cons
= 0;
7888 tw32_mailbox(tp
->napi
[0].prodmbox
, 0);
7889 tw32_rx_mbox(tp
->napi
[0].consmbox
, 0);
7892 /* Make sure the NIC-based send BD rings are disabled. */
7893 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7894 u32 mbox
= MAILBOX_SNDNIC_PROD_IDX_0
+ TG3_64BIT_REG_LOW
;
7895 for (i
= 0; i
< 16; i
++)
7896 tw32_tx_mbox(mbox
+ i
* 8, 0);
7899 txrcb
= NIC_SRAM_SEND_RCB
;
7900 rxrcb
= NIC_SRAM_RCV_RET_RCB
;
7902 /* Clear status block in ram. */
7903 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
7905 /* Set status block DMA address */
7906 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7907 ((u64
) tnapi
->status_mapping
>> 32));
7908 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7909 ((u64
) tnapi
->status_mapping
& 0xffffffff));
7911 if (tnapi
->tx_ring
) {
7912 tg3_set_bdinfo(tp
, txrcb
, tnapi
->tx_desc_mapping
,
7913 (TG3_TX_RING_SIZE
<<
7914 BDINFO_FLAGS_MAXLEN_SHIFT
),
7915 NIC_SRAM_TX_BUFFER_DESC
);
7916 txrcb
+= TG3_BDINFO_SIZE
;
7919 if (tnapi
->rx_rcb
) {
7920 tg3_set_bdinfo(tp
, rxrcb
, tnapi
->rx_rcb_mapping
,
7921 (tp
->rx_ret_ring_mask
+ 1) <<
7922 BDINFO_FLAGS_MAXLEN_SHIFT
, 0);
7923 rxrcb
+= TG3_BDINFO_SIZE
;
7926 stblk
= HOSTCC_STATBLCK_RING1
;
7928 for (i
= 1, tnapi
++; i
< tp
->irq_cnt
; i
++, tnapi
++) {
7929 u64 mapping
= (u64
)tnapi
->status_mapping
;
7930 tw32(stblk
+ TG3_64BIT_REG_HIGH
, mapping
>> 32);
7931 tw32(stblk
+ TG3_64BIT_REG_LOW
, mapping
& 0xffffffff);
7933 /* Clear status block in ram. */
7934 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
7936 if (tnapi
->tx_ring
) {
7937 tg3_set_bdinfo(tp
, txrcb
, tnapi
->tx_desc_mapping
,
7938 (TG3_TX_RING_SIZE
<<
7939 BDINFO_FLAGS_MAXLEN_SHIFT
),
7940 NIC_SRAM_TX_BUFFER_DESC
);
7941 txrcb
+= TG3_BDINFO_SIZE
;
7944 tg3_set_bdinfo(tp
, rxrcb
, tnapi
->rx_rcb_mapping
,
7945 ((tp
->rx_ret_ring_mask
+ 1) <<
7946 BDINFO_FLAGS_MAXLEN_SHIFT
), 0);
7949 rxrcb
+= TG3_BDINFO_SIZE
;
7953 /* tp->lock is held. */
7954 static int tg3_reset_hw(struct tg3
*tp
, int reset_phy
)
7956 u32 val
, rdmac_mode
;
7958 struct tg3_rx_prodring_set
*tpr
= &tp
->napi
[0].prodring
;
7960 tg3_disable_ints(tp
);
7964 tg3_write_sig_pre_reset(tp
, RESET_KIND_INIT
);
7966 if (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)
7967 tg3_abort_hw(tp
, 1);
7969 /* Enable MAC control of LPI */
7970 if (tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
) {
7971 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL
,
7972 TG3_CPMU_EEE_LNKIDL_PCIE_NL0
|
7973 TG3_CPMU_EEE_LNKIDL_UART_IDL
);
7975 tw32_f(TG3_CPMU_EEE_CTRL
,
7976 TG3_CPMU_EEE_CTRL_EXIT_20_1_US
);
7978 val
= TG3_CPMU_EEEMD_ERLY_L1_XIT_DET
|
7979 TG3_CPMU_EEEMD_LPI_IN_TX
|
7980 TG3_CPMU_EEEMD_LPI_IN_RX
|
7981 TG3_CPMU_EEEMD_EEE_ENABLE
;
7983 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
)
7984 val
|= TG3_CPMU_EEEMD_SND_IDX_DET_EN
;
7986 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
7987 val
|= TG3_CPMU_EEEMD_APE_TX_DET_EN
;
7989 tw32_f(TG3_CPMU_EEE_MODE
, val
);
7991 tw32_f(TG3_CPMU_EEE_DBTMR1
,
7992 TG3_CPMU_DBTMR1_PCIEXIT_2047US
|
7993 TG3_CPMU_DBTMR1_LNKIDLE_2047US
);
7995 tw32_f(TG3_CPMU_EEE_DBTMR2
,
7996 TG3_CPMU_DBTMR2_APE_TX_2047US
|
7997 TG3_CPMU_DBTMR2_TXIDXEQ_2047US
);
8003 err
= tg3_chip_reset(tp
);
8007 tg3_write_sig_legacy(tp
, RESET_KIND_INIT
);
8009 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
8010 val
= tr32(TG3_CPMU_CTRL
);
8011 val
&= ~(CPMU_CTRL_LINK_AWARE_MODE
| CPMU_CTRL_LINK_IDLE_MODE
);
8012 tw32(TG3_CPMU_CTRL
, val
);
8014 val
= tr32(TG3_CPMU_LSPD_10MB_CLK
);
8015 val
&= ~CPMU_LSPD_10MB_MACCLK_MASK
;
8016 val
|= CPMU_LSPD_10MB_MACCLK_6_25
;
8017 tw32(TG3_CPMU_LSPD_10MB_CLK
, val
);
8019 val
= tr32(TG3_CPMU_LNK_AWARE_PWRMD
);
8020 val
&= ~CPMU_LNK_AWARE_MACCLK_MASK
;
8021 val
|= CPMU_LNK_AWARE_MACCLK_6_25
;
8022 tw32(TG3_CPMU_LNK_AWARE_PWRMD
, val
);
8024 val
= tr32(TG3_CPMU_HST_ACC
);
8025 val
&= ~CPMU_HST_ACC_MACCLK_MASK
;
8026 val
|= CPMU_HST_ACC_MACCLK_6_25
;
8027 tw32(TG3_CPMU_HST_ACC
, val
);
8030 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
8031 val
= tr32(PCIE_PWR_MGMT_THRESH
) & ~PCIE_PWR_MGMT_L1_THRESH_MSK
;
8032 val
|= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN
|
8033 PCIE_PWR_MGMT_L1_THRESH_4MS
;
8034 tw32(PCIE_PWR_MGMT_THRESH
, val
);
8036 val
= tr32(TG3_PCIE_EIDLE_DELAY
) & ~TG3_PCIE_EIDLE_DELAY_MASK
;
8037 tw32(TG3_PCIE_EIDLE_DELAY
, val
| TG3_PCIE_EIDLE_DELAY_13_CLKS
);
8039 tw32(TG3_CORR_ERR_STAT
, TG3_CORR_ERR_STAT_CLEAR
);
8041 val
= tr32(TG3_PCIE_LNKCTL
) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
8042 tw32(TG3_PCIE_LNKCTL
, val
| TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
);
8045 if (tp
->tg3_flags3
& TG3_FLG3_L1PLLPD_EN
) {
8046 u32 grc_mode
= tr32(GRC_MODE
);
8048 /* Access the lower 1K of PL PCIE block registers. */
8049 val
= grc_mode
& ~GRC_MODE_PCIE_PORT_MASK
;
8050 tw32(GRC_MODE
, val
| GRC_MODE_PCIE_PL_SEL
);
8052 val
= tr32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL1
);
8053 tw32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL1
,
8054 val
| TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN
);
8056 tw32(GRC_MODE
, grc_mode
);
8059 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) {
8060 if (tp
->pci_chip_rev_id
== CHIPREV_ID_57765_A0
) {
8061 u32 grc_mode
= tr32(GRC_MODE
);
8063 /* Access the lower 1K of PL PCIE block registers. */
8064 val
= grc_mode
& ~GRC_MODE_PCIE_PORT_MASK
;
8065 tw32(GRC_MODE
, val
| GRC_MODE_PCIE_PL_SEL
);
8067 val
= tr32(TG3_PCIE_TLDLPL_PORT
+
8068 TG3_PCIE_PL_LO_PHYCTL5
);
8069 tw32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL5
,
8070 val
| TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ
);
8072 tw32(GRC_MODE
, grc_mode
);
8075 val
= tr32(TG3_CPMU_LSPD_10MB_CLK
);
8076 val
&= ~CPMU_LSPD_10MB_MACCLK_MASK
;
8077 val
|= CPMU_LSPD_10MB_MACCLK_6_25
;
8078 tw32(TG3_CPMU_LSPD_10MB_CLK
, val
);
8081 /* This works around an issue with Athlon chipsets on
8082 * B3 tigon3 silicon. This bit has no effect on any
8083 * other revision. But do not set this on PCI Express
8084 * chips and don't even touch the clocks if the CPMU is present.
8086 if (!(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)) {
8087 if (!(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
8088 tp
->pci_clock_ctrl
|= CLOCK_CTRL_DELAY_PCI_GRANT
;
8089 tw32_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
8092 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
8093 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
8094 val
= tr32(TG3PCI_PCISTATE
);
8095 val
|= PCISTATE_RETRY_SAME_DMA
;
8096 tw32(TG3PCI_PCISTATE
, val
);
8099 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
8100 /* Allow reads and writes to the
8101 * APE register and memory space.
8103 val
= tr32(TG3PCI_PCISTATE
);
8104 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
8105 PCISTATE_ALLOW_APE_SHMEM_WR
|
8106 PCISTATE_ALLOW_APE_PSPACE_WR
;
8107 tw32(TG3PCI_PCISTATE
, val
);
8110 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_BX
) {
8111 /* Enable some hw fixes. */
8112 val
= tr32(TG3PCI_MSI_DATA
);
8113 val
|= (1 << 26) | (1 << 28) | (1 << 29);
8114 tw32(TG3PCI_MSI_DATA
, val
);
8117 /* Descriptor ring init may make accesses to the
8118 * NIC SRAM area to setup the TX descriptors, so we
8119 * can only do this after the hardware has been
8120 * successfully reset.
8122 err
= tg3_init_rings(tp
);
8126 if (tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
) {
8127 val
= tr32(TG3PCI_DMA_RW_CTRL
) &
8128 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT
;
8129 if (tp
->pci_chip_rev_id
== CHIPREV_ID_57765_A0
)
8130 val
&= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK
;
8131 tw32(TG3PCI_DMA_RW_CTRL
, val
| tp
->dma_rwctrl
);
8132 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
&&
8133 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5761
) {
8134 /* This value is determined during the probe time DMA
8135 * engine test, tg3_test_dma.
8137 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
8140 tp
->grc_mode
&= ~(GRC_MODE_HOST_SENDBDS
|
8141 GRC_MODE_4X_NIC_SEND_RINGS
|
8142 GRC_MODE_NO_TX_PHDR_CSUM
|
8143 GRC_MODE_NO_RX_PHDR_CSUM
);
8144 tp
->grc_mode
|= GRC_MODE_HOST_SENDBDS
;
8146 /* Pseudo-header checksum is done by hardware logic and not
8147 * the offload processers, so make the chip do the pseudo-
8148 * header checksums on receive. For transmit it is more
8149 * convenient to do the pseudo-header checksum in software
8150 * as Linux does that on transmit for us in all cases.
8152 tp
->grc_mode
|= GRC_MODE_NO_TX_PHDR_CSUM
;
8156 (GRC_MODE_IRQ_ON_MAC_ATTN
| GRC_MODE_HOST_STACKUP
));
8158 /* Setup the timer prescalar register. Clock is always 66Mhz. */
8159 val
= tr32(GRC_MISC_CFG
);
8161 val
|= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT
);
8162 tw32(GRC_MISC_CFG
, val
);
8164 /* Initialize MBUF/DESC pool. */
8165 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
8167 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5705
) {
8168 tw32(BUFMGR_MB_POOL_ADDR
, NIC_SRAM_MBUF_POOL_BASE
);
8169 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
8170 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE64
);
8172 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE96
);
8173 tw32(BUFMGR_DMA_DESC_POOL_ADDR
, NIC_SRAM_DMA_DESC_POOL_BASE
);
8174 tw32(BUFMGR_DMA_DESC_POOL_SIZE
, NIC_SRAM_DMA_DESC_POOL_SIZE
);
8175 } else if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
8178 fw_len
= tp
->fw_len
;
8179 fw_len
= (fw_len
+ (0x80 - 1)) & ~(0x80 - 1);
8180 tw32(BUFMGR_MB_POOL_ADDR
,
8181 NIC_SRAM_MBUF_POOL_BASE5705
+ fw_len
);
8182 tw32(BUFMGR_MB_POOL_SIZE
,
8183 NIC_SRAM_MBUF_POOL_SIZE5705
- fw_len
- 0xa00);
8186 if (tp
->dev
->mtu
<= ETH_DATA_LEN
) {
8187 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
8188 tp
->bufmgr_config
.mbuf_read_dma_low_water
);
8189 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
8190 tp
->bufmgr_config
.mbuf_mac_rx_low_water
);
8191 tw32(BUFMGR_MB_HIGH_WATER
,
8192 tp
->bufmgr_config
.mbuf_high_water
);
8194 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
8195 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
);
8196 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
8197 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
);
8198 tw32(BUFMGR_MB_HIGH_WATER
,
8199 tp
->bufmgr_config
.mbuf_high_water_jumbo
);
8201 tw32(BUFMGR_DMA_LOW_WATER
,
8202 tp
->bufmgr_config
.dma_low_water
);
8203 tw32(BUFMGR_DMA_HIGH_WATER
,
8204 tp
->bufmgr_config
.dma_high_water
);
8206 val
= BUFMGR_MODE_ENABLE
| BUFMGR_MODE_ATTN_ENABLE
;
8207 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
)
8208 val
|= BUFMGR_MODE_NO_TX_UNDERRUN
;
8209 tw32(BUFMGR_MODE
, val
);
8210 for (i
= 0; i
< 2000; i
++) {
8211 if (tr32(BUFMGR_MODE
) & BUFMGR_MODE_ENABLE
)
8216 netdev_err(tp
->dev
, "%s cannot enable BUFMGR\n", __func__
);
8220 /* Setup replenish threshold. */
8221 val
= tp
->rx_pending
/ 8;
8224 else if (val
> tp
->rx_std_max_post
)
8225 val
= tp
->rx_std_max_post
;
8226 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
8227 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5906_A1
)
8228 tw32(ISO_PKT_TX
, (tr32(ISO_PKT_TX
) & ~0x3) | 0x2);
8230 if (val
> (TG3_RX_INTERNAL_RING_SZ_5906
/ 2))
8231 val
= TG3_RX_INTERNAL_RING_SZ_5906
/ 2;
8234 tw32(RCVBDI_STD_THRESH
, val
);
8236 /* Initialize TG3_BDINFO's at:
8237 * RCVDBDI_STD_BD: standard eth size rx ring
8238 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
8239 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
8242 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
8243 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
8244 * ring attribute flags
8245 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
8247 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8248 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8250 * The size of each ring is fixed in the firmware, but the location is
8253 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
8254 ((u64
) tpr
->rx_std_mapping
>> 32));
8255 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
8256 ((u64
) tpr
->rx_std_mapping
& 0xffffffff));
8257 if (!(tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
))
8258 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_NIC_ADDR
,
8259 NIC_SRAM_RX_BUFFER_DESC
);
8261 /* Disable the mini ring */
8262 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
8263 tw32(RCVDBDI_MINI_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
8264 BDINFO_FLAGS_DISABLED
);
8266 /* Program the jumbo buffer descriptor ring control
8267 * blocks on those devices that have them.
8269 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
8270 ((tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) &&
8271 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))) {
8272 /* Setup replenish threshold. */
8273 tw32(RCVBDI_JUMBO_THRESH
, tp
->rx_jumbo_pending
/ 8);
8275 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) {
8276 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
8277 ((u64
) tpr
->rx_jmb_mapping
>> 32));
8278 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
8279 ((u64
) tpr
->rx_jmb_mapping
& 0xffffffff));
8280 val
= TG3_RX_JMB_RING_SIZE(tp
) <<
8281 BDINFO_FLAGS_MAXLEN_SHIFT
;
8282 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
8283 val
| BDINFO_FLAGS_USE_EXT_RECV
);
8284 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
) ||
8285 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
8286 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_NIC_ADDR
,
8287 NIC_SRAM_RX_JUMBO_BUFFER_DESC
);
8289 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
8290 BDINFO_FLAGS_DISABLED
);
8293 if (tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
) {
8294 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
8295 val
= TG3_RX_STD_MAX_SIZE_5700
;
8297 val
= TG3_RX_STD_MAX_SIZE_5717
;
8298 val
<<= BDINFO_FLAGS_MAXLEN_SHIFT
;
8299 val
|= (TG3_RX_STD_DMA_SZ
<< 2);
8301 val
= TG3_RX_STD_DMA_SZ
<< BDINFO_FLAGS_MAXLEN_SHIFT
;
8303 val
= TG3_RX_STD_MAX_SIZE_5700
<< BDINFO_FLAGS_MAXLEN_SHIFT
;
8305 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_MAXLEN_FLAGS
, val
);
8307 tpr
->rx_std_prod_idx
= tp
->rx_pending
;
8308 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
, tpr
->rx_std_prod_idx
);
8310 tpr
->rx_jmb_prod_idx
= (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) ?
8311 tp
->rx_jumbo_pending
: 0;
8312 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
, tpr
->rx_jmb_prod_idx
);
8314 if (tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
) {
8315 tw32(STD_REPLENISH_LWM
, 32);
8316 tw32(JMB_REPLENISH_LWM
, 16);
8319 tg3_rings_reset(tp
);
8321 /* Initialize MAC address and backoff seed. */
8322 __tg3_set_mac_addr(tp
, 0);
8324 /* MTU + ethernet header + FCS + optional VLAN tag */
8325 tw32(MAC_RX_MTU_SIZE
,
8326 tp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
);
8328 /* The slot time is changed by tg3_setup_phy if we
8329 * run at gigabit with half duplex.
8331 val
= (2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
8332 (6 << TX_LENGTHS_IPG_SHIFT
) |
8333 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
);
8335 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
)
8336 val
|= tr32(MAC_TX_LENGTHS
) &
8337 (TX_LENGTHS_JMB_FRM_LEN_MSK
|
8338 TX_LENGTHS_CNT_DWN_VAL_MSK
);
8340 tw32(MAC_TX_LENGTHS
, val
);
8342 /* Receive rules. */
8343 tw32(MAC_RCV_RULE_CFG
, RCV_RULE_CFG_DEFAULT_CLASS
);
8344 tw32(RCVLPC_CONFIG
, 0x0181);
8346 /* Calculate RDMAC_MODE setting early, we need it to determine
8347 * the RCVLPC_STATE_ENABLE mask.
8349 rdmac_mode
= (RDMAC_MODE_ENABLE
| RDMAC_MODE_TGTABORT_ENAB
|
8350 RDMAC_MODE_MSTABORT_ENAB
| RDMAC_MODE_PARITYERR_ENAB
|
8351 RDMAC_MODE_ADDROFLOW_ENAB
| RDMAC_MODE_FIFOOFLOW_ENAB
|
8352 RDMAC_MODE_FIFOURUN_ENAB
| RDMAC_MODE_FIFOOREAD_ENAB
|
8353 RDMAC_MODE_LNGREAD_ENAB
);
8355 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
8356 rdmac_mode
|= RDMAC_MODE_MULT_DMA_RD_DIS
;
8358 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
8359 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
8360 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
8361 rdmac_mode
|= RDMAC_MODE_BD_SBD_CRPT_ENAB
|
8362 RDMAC_MODE_MBUF_RBD_CRPT_ENAB
|
8363 RDMAC_MODE_MBUF_SBD_CRPT_ENAB
;
8365 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
8366 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) {
8367 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
&&
8368 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
8369 rdmac_mode
|= RDMAC_MODE_FIFO_SIZE_128
;
8370 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
8371 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
)) {
8372 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
8376 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
8377 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
8379 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
8380 rdmac_mode
|= RDMAC_MODE_IPV4_LSO_EN
;
8382 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) ||
8383 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
8384 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
8385 rdmac_mode
|= RDMAC_MODE_IPV6_LSO_EN
;
8387 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
)
8388 rdmac_mode
|= tr32(RDMAC_MODE
) & RDMAC_MODE_H2BNC_VLAN_DET
;
8390 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
8391 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
8392 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
8393 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
8394 (tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
)) {
8395 val
= tr32(TG3_RDMA_RSRVCTRL_REG
);
8396 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
8397 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
) {
8398 val
&= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK
|
8399 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK
|
8400 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK
);
8401 val
|= TG3_RDMA_RSRVCTRL_TXMRGN_320B
|
8402 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K
|
8403 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K
;
8405 tw32(TG3_RDMA_RSRVCTRL_REG
,
8406 val
| TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX
);
8409 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
8410 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
) {
8411 val
= tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL
);
8412 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL
, val
|
8413 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K
|
8414 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K
);
8417 /* Receive/send statistics. */
8418 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
8419 val
= tr32(RCVLPC_STATS_ENABLE
);
8420 val
&= ~RCVLPC_STATSENAB_DACK_FIX
;
8421 tw32(RCVLPC_STATS_ENABLE
, val
);
8422 } else if ((rdmac_mode
& RDMAC_MODE_FIFO_SIZE_128
) &&
8423 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
8424 val
= tr32(RCVLPC_STATS_ENABLE
);
8425 val
&= ~RCVLPC_STATSENAB_LNGBRST_RFIX
;
8426 tw32(RCVLPC_STATS_ENABLE
, val
);
8428 tw32(RCVLPC_STATS_ENABLE
, 0xffffff);
8430 tw32(RCVLPC_STATSCTRL
, RCVLPC_STATSCTRL_ENABLE
);
8431 tw32(SNDDATAI_STATSENAB
, 0xffffff);
8432 tw32(SNDDATAI_STATSCTRL
,
8433 (SNDDATAI_SCTRL_ENABLE
|
8434 SNDDATAI_SCTRL_FASTUPD
));
8436 /* Setup host coalescing engine. */
8437 tw32(HOSTCC_MODE
, 0);
8438 for (i
= 0; i
< 2000; i
++) {
8439 if (!(tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
))
8444 __tg3_set_coalesce(tp
, &tp
->coal
);
8446 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
8447 /* Status/statistics block address. See tg3_timer,
8448 * the tg3_periodic_fetch_stats call there, and
8449 * tg3_get_stats to see how this works for 5705/5750 chips.
8451 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
8452 ((u64
) tp
->stats_mapping
>> 32));
8453 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
8454 ((u64
) tp
->stats_mapping
& 0xffffffff));
8455 tw32(HOSTCC_STATS_BLK_NIC_ADDR
, NIC_SRAM_STATS_BLK
);
8457 tw32(HOSTCC_STATUS_BLK_NIC_ADDR
, NIC_SRAM_STATUS_BLK
);
8459 /* Clear statistics and status block memory areas */
8460 for (i
= NIC_SRAM_STATS_BLK
;
8461 i
< NIC_SRAM_STATUS_BLK
+ TG3_HW_STATUS_SIZE
;
8463 tg3_write_mem(tp
, i
, 0);
8468 tw32(HOSTCC_MODE
, HOSTCC_MODE_ENABLE
| tp
->coalesce_mode
);
8470 tw32(RCVCC_MODE
, RCVCC_MODE_ENABLE
| RCVCC_MODE_ATTN_ENABLE
);
8471 tw32(RCVLPC_MODE
, RCVLPC_MODE_ENABLE
);
8472 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
8473 tw32(RCVLSC_MODE
, RCVLSC_MODE_ENABLE
| RCVLSC_MODE_ATTN_ENABLE
);
8475 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) {
8476 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
8477 /* reset to prevent losing 1st rx packet intermittently */
8478 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
8482 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
8483 tp
->mac_mode
= MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
8486 tp
->mac_mode
|= MAC_MODE_TXSTAT_ENABLE
| MAC_MODE_RXSTAT_ENABLE
|
8487 MAC_MODE_TDE_ENABLE
| MAC_MODE_RDE_ENABLE
| MAC_MODE_FHDE_ENABLE
;
8488 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
8489 !(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
8490 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
)
8491 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
8492 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_RXSTAT_CLEAR
| MAC_MODE_TXSTAT_CLEAR
);
8495 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8496 * If TG3_FLG2_IS_NIC is zero, we should read the
8497 * register to preserve the GPIO settings for LOMs. The GPIOs,
8498 * whether used as inputs or outputs, are set by boot code after
8501 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)) {
8504 gpio_mask
= GRC_LCLCTRL_GPIO_OE0
| GRC_LCLCTRL_GPIO_OE1
|
8505 GRC_LCLCTRL_GPIO_OE2
| GRC_LCLCTRL_GPIO_OUTPUT0
|
8506 GRC_LCLCTRL_GPIO_OUTPUT1
| GRC_LCLCTRL_GPIO_OUTPUT2
;
8508 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
8509 gpio_mask
|= GRC_LCLCTRL_GPIO_OE3
|
8510 GRC_LCLCTRL_GPIO_OUTPUT3
;
8512 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
8513 gpio_mask
|= GRC_LCLCTRL_GPIO_UART_SEL
;
8515 tp
->grc_local_ctrl
&= ~gpio_mask
;
8516 tp
->grc_local_ctrl
|= tr32(GRC_LOCAL_CTRL
) & gpio_mask
;
8518 /* GPIO1 must be driven high for eeprom write protect */
8519 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
)
8520 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
8521 GRC_LCLCTRL_GPIO_OUTPUT1
);
8523 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
8526 if ((tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
) &&
8528 val
= tr32(MSGINT_MODE
);
8529 val
|= MSGINT_MODE_MULTIVEC_EN
| MSGINT_MODE_ENABLE
;
8530 tw32(MSGINT_MODE
, val
);
8533 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
8534 tw32_f(DMAC_MODE
, DMAC_MODE_ENABLE
);
8538 val
= (WDMAC_MODE_ENABLE
| WDMAC_MODE_TGTABORT_ENAB
|
8539 WDMAC_MODE_MSTABORT_ENAB
| WDMAC_MODE_PARITYERR_ENAB
|
8540 WDMAC_MODE_ADDROFLOW_ENAB
| WDMAC_MODE_FIFOOFLOW_ENAB
|
8541 WDMAC_MODE_FIFOURUN_ENAB
| WDMAC_MODE_FIFOOREAD_ENAB
|
8542 WDMAC_MODE_LNGREAD_ENAB
);
8544 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
8545 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) {
8546 if ((tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
8547 (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
||
8548 tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A2
)) {
8550 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
8551 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
)) {
8552 val
|= WDMAC_MODE_RX_ACCEL
;
8556 /* Enable host coalescing bug fix */
8557 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
8558 val
|= WDMAC_MODE_STATUS_TAG_FIX
;
8560 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
8561 val
|= WDMAC_MODE_BURST_ALL_DATA
;
8563 tw32_f(WDMAC_MODE
, val
);
8566 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
8569 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
8571 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
) {
8572 pcix_cmd
&= ~PCI_X_CMD_MAX_READ
;
8573 pcix_cmd
|= PCI_X_CMD_READ_2K
;
8574 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
8575 pcix_cmd
&= ~(PCI_X_CMD_MAX_SPLIT
| PCI_X_CMD_MAX_READ
);
8576 pcix_cmd
|= PCI_X_CMD_READ_2K
;
8578 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
8582 tw32_f(RDMAC_MODE
, rdmac_mode
);
8585 tw32(RCVDCC_MODE
, RCVDCC_MODE_ENABLE
| RCVDCC_MODE_ATTN_ENABLE
);
8586 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
8587 tw32(MBFREE_MODE
, MBFREE_MODE_ENABLE
);
8589 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
8591 SNDDATAC_MODE_ENABLE
| SNDDATAC_MODE_CDELAY
);
8593 tw32(SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
);
8595 tw32(SNDBDC_MODE
, SNDBDC_MODE_ENABLE
| SNDBDC_MODE_ATTN_ENABLE
);
8596 tw32(RCVBDI_MODE
, RCVBDI_MODE_ENABLE
| RCVBDI_MODE_RCB_ATTN_ENAB
);
8597 val
= RCVDBDI_MODE_ENABLE
| RCVDBDI_MODE_INV_RING_SZ
;
8598 if (tp
->tg3_flags3
& TG3_FLG3_LRG_PROD_RING_CAP
)
8599 val
|= RCVDBDI_MODE_LRG_RING_SZ
;
8600 tw32(RCVDBDI_MODE
, val
);
8601 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
);
8602 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
8603 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
| 0x8);
8604 val
= SNDBDI_MODE_ENABLE
| SNDBDI_MODE_ATTN_ENABLE
;
8605 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
8606 val
|= SNDBDI_MODE_MULTI_TXQ_EN
;
8607 tw32(SNDBDI_MODE
, val
);
8608 tw32(SNDBDS_MODE
, SNDBDS_MODE_ENABLE
| SNDBDS_MODE_ATTN_ENABLE
);
8610 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
8611 err
= tg3_load_5701_a0_firmware_fix(tp
);
8616 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
8617 err
= tg3_load_tso_firmware(tp
);
8622 tp
->tx_mode
= TX_MODE_ENABLE
;
8624 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
8625 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
8626 tp
->tx_mode
|= TX_MODE_MBUF_LOCKUP_FIX
;
8628 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
) {
8629 val
= TX_MODE_JMB_FRM_LEN
| TX_MODE_CNT_DN_MODE
;
8630 tp
->tx_mode
&= ~val
;
8631 tp
->tx_mode
|= tr32(MAC_TX_MODE
) & val
;
8634 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
8637 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
) {
8638 u32 reg
= MAC_RSS_INDIR_TBL_0
;
8639 u8
*ent
= (u8
*)&val
;
8641 /* Setup the indirection table */
8642 for (i
= 0; i
< TG3_RSS_INDIR_TBL_SIZE
; i
++) {
8643 int idx
= i
% sizeof(val
);
8645 ent
[idx
] = i
% (tp
->irq_cnt
- 1);
8646 if (idx
== sizeof(val
) - 1) {
8652 /* Setup the "secret" hash key. */
8653 tw32(MAC_RSS_HASH_KEY_0
, 0x5f865437);
8654 tw32(MAC_RSS_HASH_KEY_1
, 0xe4ac62cc);
8655 tw32(MAC_RSS_HASH_KEY_2
, 0x50103a45);
8656 tw32(MAC_RSS_HASH_KEY_3
, 0x36621985);
8657 tw32(MAC_RSS_HASH_KEY_4
, 0xbf14c0e8);
8658 tw32(MAC_RSS_HASH_KEY_5
, 0x1bc27a1e);
8659 tw32(MAC_RSS_HASH_KEY_6
, 0x84f4b556);
8660 tw32(MAC_RSS_HASH_KEY_7
, 0x094ea6fe);
8661 tw32(MAC_RSS_HASH_KEY_8
, 0x7dda01e7);
8662 tw32(MAC_RSS_HASH_KEY_9
, 0xc04d7481);
8665 tp
->rx_mode
= RX_MODE_ENABLE
;
8666 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
8667 tp
->rx_mode
|= RX_MODE_IPV6_CSUM_ENABLE
;
8669 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)
8670 tp
->rx_mode
|= RX_MODE_RSS_ENABLE
|
8671 RX_MODE_RSS_ITBL_HASH_BITS_7
|
8672 RX_MODE_RSS_IPV6_HASH_EN
|
8673 RX_MODE_RSS_TCP_IPV6_HASH_EN
|
8674 RX_MODE_RSS_IPV4_HASH_EN
|
8675 RX_MODE_RSS_TCP_IPV4_HASH_EN
;
8677 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
8680 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
8682 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
8683 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
8684 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
8687 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
8690 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
8691 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) &&
8692 !(tp
->phy_flags
& TG3_PHYFLG_SERDES_PREEMPHASIS
)) {
8693 /* Set drive transmission level to 1.2V */
8694 /* only if the signal pre-emphasis bit is not set */
8695 val
= tr32(MAC_SERDES_CFG
);
8698 tw32(MAC_SERDES_CFG
, val
);
8700 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
)
8701 tw32(MAC_SERDES_CFG
, 0x616000);
8704 /* Prevent chip from dropping frames when flow control
8707 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
8711 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME
, val
);
8713 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
&&
8714 (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)) {
8715 /* Use hardware link auto-negotiation */
8716 tp
->tg3_flags2
|= TG3_FLG2_HW_AUTONEG
;
8719 if ((tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) &&
8720 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
)) {
8723 tmp
= tr32(SERDES_RX_CTRL
);
8724 tw32(SERDES_RX_CTRL
, tmp
| SERDES_RX_SIG_DETECT
);
8725 tp
->grc_local_ctrl
&= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT
;
8726 tp
->grc_local_ctrl
|= GRC_LCLCTRL_USE_SIG_DETECT
;
8727 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
8730 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
8731 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
) {
8732 tp
->phy_flags
&= ~TG3_PHYFLG_IS_LOW_POWER
;
8733 tp
->link_config
.speed
= tp
->link_config
.orig_speed
;
8734 tp
->link_config
.duplex
= tp
->link_config
.orig_duplex
;
8735 tp
->link_config
.autoneg
= tp
->link_config
.orig_autoneg
;
8738 err
= tg3_setup_phy(tp
, 0);
8742 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
8743 !(tp
->phy_flags
& TG3_PHYFLG_IS_FET
)) {
8746 /* Clear CRC stats. */
8747 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &tmp
)) {
8748 tg3_writephy(tp
, MII_TG3_TEST1
,
8749 tmp
| MII_TG3_TEST1_CRC_EN
);
8750 tg3_readphy(tp
, MII_TG3_RXR_COUNTERS
, &tmp
);
8755 __tg3_set_rx_mode(tp
->dev
);
8757 /* Initialize receive rules. */
8758 tw32(MAC_RCV_RULE_0
, 0xc2000000 & RCV_RULE_DISABLE_MASK
);
8759 tw32(MAC_RCV_VALUE_0
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
8760 tw32(MAC_RCV_RULE_1
, 0x86000004 & RCV_RULE_DISABLE_MASK
);
8761 tw32(MAC_RCV_VALUE_1
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
8763 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
8764 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
8768 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
8772 tw32(MAC_RCV_RULE_15
, 0); tw32(MAC_RCV_VALUE_15
, 0);
8774 tw32(MAC_RCV_RULE_14
, 0); tw32(MAC_RCV_VALUE_14
, 0);
8776 tw32(MAC_RCV_RULE_13
, 0); tw32(MAC_RCV_VALUE_13
, 0);
8778 tw32(MAC_RCV_RULE_12
, 0); tw32(MAC_RCV_VALUE_12
, 0);
8780 tw32(MAC_RCV_RULE_11
, 0); tw32(MAC_RCV_VALUE_11
, 0);
8782 tw32(MAC_RCV_RULE_10
, 0); tw32(MAC_RCV_VALUE_10
, 0);
8784 tw32(MAC_RCV_RULE_9
, 0); tw32(MAC_RCV_VALUE_9
, 0);
8786 tw32(MAC_RCV_RULE_8
, 0); tw32(MAC_RCV_VALUE_8
, 0);
8788 tw32(MAC_RCV_RULE_7
, 0); tw32(MAC_RCV_VALUE_7
, 0);
8790 tw32(MAC_RCV_RULE_6
, 0); tw32(MAC_RCV_VALUE_6
, 0);
8792 tw32(MAC_RCV_RULE_5
, 0); tw32(MAC_RCV_VALUE_5
, 0);
8794 tw32(MAC_RCV_RULE_4
, 0); tw32(MAC_RCV_VALUE_4
, 0);
8796 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8798 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8806 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
8807 /* Write our heartbeat update interval to APE. */
8808 tg3_ape_write32(tp
, TG3_APE_HOST_HEARTBEAT_INT_MS
,
8809 APE_HOST_HEARTBEAT_INT_DISABLE
);
8811 tg3_write_sig_post_reset(tp
, RESET_KIND_INIT
);
8816 /* Called at device open time to get the chip ready for
8817 * packet processing. Invoked with tp->lock held.
8819 static int tg3_init_hw(struct tg3
*tp
, int reset_phy
)
8821 tg3_switch_clocks(tp
);
8823 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
8825 return tg3_reset_hw(tp
, reset_phy
);
8828 #define TG3_STAT_ADD32(PSTAT, REG) \
8829 do { u32 __val = tr32(REG); \
8830 (PSTAT)->low += __val; \
8831 if ((PSTAT)->low < __val) \
8832 (PSTAT)->high += 1; \
8835 static void tg3_periodic_fetch_stats(struct tg3
*tp
)
8837 struct tg3_hw_stats
*sp
= tp
->hw_stats
;
8839 if (!netif_carrier_ok(tp
->dev
))
8842 TG3_STAT_ADD32(&sp
->tx_octets
, MAC_TX_STATS_OCTETS
);
8843 TG3_STAT_ADD32(&sp
->tx_collisions
, MAC_TX_STATS_COLLISIONS
);
8844 TG3_STAT_ADD32(&sp
->tx_xon_sent
, MAC_TX_STATS_XON_SENT
);
8845 TG3_STAT_ADD32(&sp
->tx_xoff_sent
, MAC_TX_STATS_XOFF_SENT
);
8846 TG3_STAT_ADD32(&sp
->tx_mac_errors
, MAC_TX_STATS_MAC_ERRORS
);
8847 TG3_STAT_ADD32(&sp
->tx_single_collisions
, MAC_TX_STATS_SINGLE_COLLISIONS
);
8848 TG3_STAT_ADD32(&sp
->tx_mult_collisions
, MAC_TX_STATS_MULT_COLLISIONS
);
8849 TG3_STAT_ADD32(&sp
->tx_deferred
, MAC_TX_STATS_DEFERRED
);
8850 TG3_STAT_ADD32(&sp
->tx_excessive_collisions
, MAC_TX_STATS_EXCESSIVE_COL
);
8851 TG3_STAT_ADD32(&sp
->tx_late_collisions
, MAC_TX_STATS_LATE_COL
);
8852 TG3_STAT_ADD32(&sp
->tx_ucast_packets
, MAC_TX_STATS_UCAST
);
8853 TG3_STAT_ADD32(&sp
->tx_mcast_packets
, MAC_TX_STATS_MCAST
);
8854 TG3_STAT_ADD32(&sp
->tx_bcast_packets
, MAC_TX_STATS_BCAST
);
8856 TG3_STAT_ADD32(&sp
->rx_octets
, MAC_RX_STATS_OCTETS
);
8857 TG3_STAT_ADD32(&sp
->rx_fragments
, MAC_RX_STATS_FRAGMENTS
);
8858 TG3_STAT_ADD32(&sp
->rx_ucast_packets
, MAC_RX_STATS_UCAST
);
8859 TG3_STAT_ADD32(&sp
->rx_mcast_packets
, MAC_RX_STATS_MCAST
);
8860 TG3_STAT_ADD32(&sp
->rx_bcast_packets
, MAC_RX_STATS_BCAST
);
8861 TG3_STAT_ADD32(&sp
->rx_fcs_errors
, MAC_RX_STATS_FCS_ERRORS
);
8862 TG3_STAT_ADD32(&sp
->rx_align_errors
, MAC_RX_STATS_ALIGN_ERRORS
);
8863 TG3_STAT_ADD32(&sp
->rx_xon_pause_rcvd
, MAC_RX_STATS_XON_PAUSE_RECVD
);
8864 TG3_STAT_ADD32(&sp
->rx_xoff_pause_rcvd
, MAC_RX_STATS_XOFF_PAUSE_RECVD
);
8865 TG3_STAT_ADD32(&sp
->rx_mac_ctrl_rcvd
, MAC_RX_STATS_MAC_CTRL_RECVD
);
8866 TG3_STAT_ADD32(&sp
->rx_xoff_entered
, MAC_RX_STATS_XOFF_ENTERED
);
8867 TG3_STAT_ADD32(&sp
->rx_frame_too_long_errors
, MAC_RX_STATS_FRAME_TOO_LONG
);
8868 TG3_STAT_ADD32(&sp
->rx_jabbers
, MAC_RX_STATS_JABBERS
);
8869 TG3_STAT_ADD32(&sp
->rx_undersize_packets
, MAC_RX_STATS_UNDERSIZE
);
8871 TG3_STAT_ADD32(&sp
->rxbds_empty
, RCVLPC_NO_RCV_BD_CNT
);
8872 TG3_STAT_ADD32(&sp
->rx_discards
, RCVLPC_IN_DISCARDS_CNT
);
8873 TG3_STAT_ADD32(&sp
->rx_errors
, RCVLPC_IN_ERRORS_CNT
);
8876 static void tg3_timer(unsigned long __opaque
)
8878 struct tg3
*tp
= (struct tg3
*) __opaque
;
8883 spin_lock(&tp
->lock
);
8885 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
8886 /* All of this garbage is because when using non-tagged
8887 * IRQ status the mailbox/status_block protocol the chip
8888 * uses with the cpu is race prone.
8890 if (tp
->napi
[0].hw_status
->status
& SD_STATUS_UPDATED
) {
8891 tw32(GRC_LOCAL_CTRL
,
8892 tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
8894 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
8895 HOSTCC_MODE_ENABLE
| HOSTCC_MODE_NOW
);
8898 if (!(tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
8899 tp
->tg3_flags2
|= TG3_FLG2_RESTART_TIMER
;
8900 spin_unlock(&tp
->lock
);
8901 schedule_work(&tp
->reset_task
);
8906 /* This part only runs once per second. */
8907 if (!--tp
->timer_counter
) {
8908 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
8909 tg3_periodic_fetch_stats(tp
);
8911 if (tp
->setlpicnt
&& !--tp
->setlpicnt
) {
8912 u32 val
= tr32(TG3_CPMU_EEE_MODE
);
8913 tw32(TG3_CPMU_EEE_MODE
,
8914 val
| TG3_CPMU_EEEMD_LPI_ENABLE
);
8917 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
8921 mac_stat
= tr32(MAC_STATUS
);
8924 if (tp
->phy_flags
& TG3_PHYFLG_USE_MI_INTERRUPT
) {
8925 if (mac_stat
& MAC_STATUS_MI_INTERRUPT
)
8927 } else if (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)
8931 tg3_setup_phy(tp
, 0);
8932 } else if (tp
->tg3_flags
& TG3_FLAG_POLL_SERDES
) {
8933 u32 mac_stat
= tr32(MAC_STATUS
);
8936 if (netif_carrier_ok(tp
->dev
) &&
8937 (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)) {
8940 if (!netif_carrier_ok(tp
->dev
) &&
8941 (mac_stat
& (MAC_STATUS_PCS_SYNCED
|
8942 MAC_STATUS_SIGNAL_DET
))) {
8946 if (!tp
->serdes_counter
) {
8949 ~MAC_MODE_PORT_MODE_MASK
));
8951 tw32_f(MAC_MODE
, tp
->mac_mode
);
8954 tg3_setup_phy(tp
, 0);
8956 } else if ((tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) &&
8957 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
8958 tg3_serdes_parallel_detect(tp
);
8961 tp
->timer_counter
= tp
->timer_multiplier
;
8964 /* Heartbeat is only sent once every 2 seconds.
8966 * The heartbeat is to tell the ASF firmware that the host
8967 * driver is still alive. In the event that the OS crashes,
8968 * ASF needs to reset the hardware to free up the FIFO space
8969 * that may be filled with rx packets destined for the host.
8970 * If the FIFO is full, ASF will no longer function properly.
8972 * Unintended resets have been reported on real time kernels
8973 * where the timer doesn't run on time. Netpoll will also have
8976 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8977 * to check the ring condition when the heartbeat is expiring
8978 * before doing the reset. This will prevent most unintended
8981 if (!--tp
->asf_counter
) {
8982 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
8983 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
8984 tg3_wait_for_event_ack(tp
);
8986 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
,
8987 FWCMD_NICDRV_ALIVE3
);
8988 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 4);
8989 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
,
8990 TG3_FW_UPDATE_TIMEOUT_SEC
);
8992 tg3_generate_fw_event(tp
);
8994 tp
->asf_counter
= tp
->asf_multiplier
;
8997 spin_unlock(&tp
->lock
);
9000 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
9001 add_timer(&tp
->timer
);
9004 static int tg3_request_irq(struct tg3
*tp
, int irq_num
)
9007 unsigned long flags
;
9009 struct tg3_napi
*tnapi
= &tp
->napi
[irq_num
];
9011 if (tp
->irq_cnt
== 1)
9012 name
= tp
->dev
->name
;
9014 name
= &tnapi
->irq_lbl
[0];
9015 snprintf(name
, IFNAMSIZ
, "%s-%d", tp
->dev
->name
, irq_num
);
9016 name
[IFNAMSIZ
-1] = 0;
9019 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI_OR_MSIX
) {
9021 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
9026 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
9027 fn
= tg3_interrupt_tagged
;
9028 flags
= IRQF_SHARED
;
9031 return request_irq(tnapi
->irq_vec
, fn
, flags
, name
, tnapi
);
9034 static int tg3_test_interrupt(struct tg3
*tp
)
9036 struct tg3_napi
*tnapi
= &tp
->napi
[0];
9037 struct net_device
*dev
= tp
->dev
;
9038 int err
, i
, intr_ok
= 0;
9041 if (!netif_running(dev
))
9044 tg3_disable_ints(tp
);
9046 free_irq(tnapi
->irq_vec
, tnapi
);
9049 * Turn off MSI one shot mode. Otherwise this test has no
9050 * observable way to know whether the interrupt was delivered.
9052 if ((tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
) &&
9053 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)) {
9054 val
= tr32(MSGINT_MODE
) | MSGINT_MODE_ONE_SHOT_DISABLE
;
9055 tw32(MSGINT_MODE
, val
);
9058 err
= request_irq(tnapi
->irq_vec
, tg3_test_isr
,
9059 IRQF_SHARED
| IRQF_SAMPLE_RANDOM
, dev
->name
, tnapi
);
9063 tnapi
->hw_status
->status
&= ~SD_STATUS_UPDATED
;
9064 tg3_enable_ints(tp
);
9066 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
9069 for (i
= 0; i
< 5; i
++) {
9070 u32 int_mbox
, misc_host_ctrl
;
9072 int_mbox
= tr32_mailbox(tnapi
->int_mbox
);
9073 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
9075 if ((int_mbox
!= 0) ||
9076 (misc_host_ctrl
& MISC_HOST_CTRL_MASK_PCI_INT
)) {
9084 tg3_disable_ints(tp
);
9086 free_irq(tnapi
->irq_vec
, tnapi
);
9088 err
= tg3_request_irq(tp
, 0);
9094 /* Reenable MSI one shot mode. */
9095 if ((tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
) &&
9096 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)) {
9097 val
= tr32(MSGINT_MODE
) & ~MSGINT_MODE_ONE_SHOT_DISABLE
;
9098 tw32(MSGINT_MODE
, val
);
9106 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
9107 * successfully restored
9109 static int tg3_test_msi(struct tg3
*tp
)
9114 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSI
))
9117 /* Turn off SERR reporting in case MSI terminates with Master
9120 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
9121 pci_write_config_word(tp
->pdev
, PCI_COMMAND
,
9122 pci_cmd
& ~PCI_COMMAND_SERR
);
9124 err
= tg3_test_interrupt(tp
);
9126 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
9131 /* other failures */
9135 /* MSI test failed, go back to INTx mode */
9136 netdev_warn(tp
->dev
, "No interrupt was generated using MSI. Switching "
9137 "to INTx mode. Please report this failure to the PCI "
9138 "maintainer and include system chipset information\n");
9140 free_irq(tp
->napi
[0].irq_vec
, &tp
->napi
[0]);
9142 pci_disable_msi(tp
->pdev
);
9144 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
9145 tp
->napi
[0].irq_vec
= tp
->pdev
->irq
;
9147 err
= tg3_request_irq(tp
, 0);
9151 /* Need to reset the chip because the MSI cycle may have terminated
9152 * with Master Abort.
9154 tg3_full_lock(tp
, 1);
9156 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9157 err
= tg3_init_hw(tp
, 1);
9159 tg3_full_unlock(tp
);
9162 free_irq(tp
->napi
[0].irq_vec
, &tp
->napi
[0]);
9167 static int tg3_request_firmware(struct tg3
*tp
)
9169 const __be32
*fw_data
;
9171 if (request_firmware(&tp
->fw
, tp
->fw_needed
, &tp
->pdev
->dev
)) {
9172 netdev_err(tp
->dev
, "Failed to load firmware \"%s\"\n",
9177 fw_data
= (void *)tp
->fw
->data
;
9179 /* Firmware blob starts with version numbers, followed by
9180 * start address and _full_ length including BSS sections
9181 * (which must be longer than the actual data, of course
9184 tp
->fw_len
= be32_to_cpu(fw_data
[2]); /* includes bss */
9185 if (tp
->fw_len
< (tp
->fw
->size
- 12)) {
9186 netdev_err(tp
->dev
, "bogus length %d in \"%s\"\n",
9187 tp
->fw_len
, tp
->fw_needed
);
9188 release_firmware(tp
->fw
);
9193 /* We no longer need firmware; we have it. */
9194 tp
->fw_needed
= NULL
;
9198 static bool tg3_enable_msix(struct tg3
*tp
)
9200 int i
, rc
, cpus
= num_online_cpus();
9201 struct msix_entry msix_ent
[tp
->irq_max
];
9204 /* Just fallback to the simpler MSI mode. */
9208 * We want as many rx rings enabled as there are cpus.
9209 * The first MSIX vector only deals with link interrupts, etc,
9210 * so we add one to the number of vectors we are requesting.
9212 tp
->irq_cnt
= min_t(unsigned, cpus
+ 1, tp
->irq_max
);
9214 for (i
= 0; i
< tp
->irq_max
; i
++) {
9215 msix_ent
[i
].entry
= i
;
9216 msix_ent
[i
].vector
= 0;
9219 rc
= pci_enable_msix(tp
->pdev
, msix_ent
, tp
->irq_cnt
);
9222 } else if (rc
!= 0) {
9223 if (pci_enable_msix(tp
->pdev
, msix_ent
, rc
))
9225 netdev_notice(tp
->dev
, "Requested %d MSI-X vectors, received %d\n",
9230 for (i
= 0; i
< tp
->irq_max
; i
++)
9231 tp
->napi
[i
].irq_vec
= msix_ent
[i
].vector
;
9233 netif_set_real_num_tx_queues(tp
->dev
, 1);
9234 rc
= tp
->irq_cnt
> 1 ? tp
->irq_cnt
- 1 : 1;
9235 if (netif_set_real_num_rx_queues(tp
->dev
, rc
)) {
9236 pci_disable_msix(tp
->pdev
);
9240 if (tp
->irq_cnt
> 1) {
9241 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_RSS
;
9243 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
9244 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
) {
9245 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_TSS
;
9246 netif_set_real_num_tx_queues(tp
->dev
, tp
->irq_cnt
- 1);
9253 static void tg3_ints_init(struct tg3
*tp
)
9255 if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSI_OR_MSIX
) &&
9256 !(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
9257 /* All MSI supporting chips should support tagged
9258 * status. Assert that this is the case.
9260 netdev_warn(tp
->dev
,
9261 "MSI without TAGGED_STATUS? Not using MSI\n");
9265 if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
) && tg3_enable_msix(tp
))
9266 tp
->tg3_flags2
|= TG3_FLG2_USING_MSIX
;
9267 else if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSI
) &&
9268 pci_enable_msi(tp
->pdev
) == 0)
9269 tp
->tg3_flags2
|= TG3_FLG2_USING_MSI
;
9271 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI_OR_MSIX
) {
9272 u32 msi_mode
= tr32(MSGINT_MODE
);
9273 if ((tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
) &&
9275 msi_mode
|= MSGINT_MODE_MULTIVEC_EN
;
9276 tw32(MSGINT_MODE
, msi_mode
| MSGINT_MODE_ENABLE
);
9279 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)) {
9281 tp
->napi
[0].irq_vec
= tp
->pdev
->irq
;
9282 netif_set_real_num_tx_queues(tp
->dev
, 1);
9283 netif_set_real_num_rx_queues(tp
->dev
, 1);
9287 static void tg3_ints_fini(struct tg3
*tp
)
9289 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)
9290 pci_disable_msix(tp
->pdev
);
9291 else if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)
9292 pci_disable_msi(tp
->pdev
);
9293 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI_OR_MSIX
;
9294 tp
->tg3_flags3
&= ~(TG3_FLG3_ENABLE_RSS
| TG3_FLG3_ENABLE_TSS
);
9297 static int tg3_open(struct net_device
*dev
)
9299 struct tg3
*tp
= netdev_priv(dev
);
9302 if (tp
->fw_needed
) {
9303 err
= tg3_request_firmware(tp
);
9304 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
9308 netdev_warn(tp
->dev
, "TSO capability disabled\n");
9309 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
9310 } else if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
9311 netdev_notice(tp
->dev
, "TSO capability restored\n");
9312 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
9316 netif_carrier_off(tp
->dev
);
9318 err
= tg3_power_up(tp
);
9322 tg3_full_lock(tp
, 0);
9324 tg3_disable_ints(tp
);
9325 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
9327 tg3_full_unlock(tp
);
9330 * Setup interrupts first so we know how
9331 * many NAPI resources to allocate
9335 /* The placement of this call is tied
9336 * to the setup and use of Host TX descriptors.
9338 err
= tg3_alloc_consistent(tp
);
9344 tg3_napi_enable(tp
);
9346 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
9347 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
9348 err
= tg3_request_irq(tp
, i
);
9350 for (i
--; i
>= 0; i
--)
9351 free_irq(tnapi
->irq_vec
, tnapi
);
9359 tg3_full_lock(tp
, 0);
9361 err
= tg3_init_hw(tp
, 1);
9363 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9366 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
9367 tp
->timer_offset
= HZ
;
9369 tp
->timer_offset
= HZ
/ 10;
9371 BUG_ON(tp
->timer_offset
> HZ
);
9372 tp
->timer_counter
= tp
->timer_multiplier
=
9373 (HZ
/ tp
->timer_offset
);
9374 tp
->asf_counter
= tp
->asf_multiplier
=
9375 ((HZ
/ tp
->timer_offset
) * 2);
9377 init_timer(&tp
->timer
);
9378 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
9379 tp
->timer
.data
= (unsigned long) tp
;
9380 tp
->timer
.function
= tg3_timer
;
9383 tg3_full_unlock(tp
);
9388 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
9389 err
= tg3_test_msi(tp
);
9392 tg3_full_lock(tp
, 0);
9393 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9395 tg3_full_unlock(tp
);
9400 if (!(tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
) &&
9401 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)) {
9402 u32 val
= tr32(PCIE_TRANSACTION_CFG
);
9404 tw32(PCIE_TRANSACTION_CFG
,
9405 val
| PCIE_TRANS_CFG_1SHOT_MSI
);
9411 tg3_full_lock(tp
, 0);
9413 add_timer(&tp
->timer
);
9414 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
9415 tg3_enable_ints(tp
);
9417 tg3_full_unlock(tp
);
9419 netif_tx_start_all_queues(dev
);
9424 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--) {
9425 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
9426 free_irq(tnapi
->irq_vec
, tnapi
);
9430 tg3_napi_disable(tp
);
9432 tg3_free_consistent(tp
);
9439 static struct rtnl_link_stats64
*tg3_get_stats64(struct net_device
*,
9440 struct rtnl_link_stats64
*);
9441 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*);
9443 static int tg3_close(struct net_device
*dev
)
9446 struct tg3
*tp
= netdev_priv(dev
);
9448 tg3_napi_disable(tp
);
9449 cancel_work_sync(&tp
->reset_task
);
9451 netif_tx_stop_all_queues(dev
);
9453 del_timer_sync(&tp
->timer
);
9457 tg3_full_lock(tp
, 1);
9459 tg3_disable_ints(tp
);
9461 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9463 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
9465 tg3_full_unlock(tp
);
9467 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--) {
9468 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
9469 free_irq(tnapi
->irq_vec
, tnapi
);
9474 tg3_get_stats64(tp
->dev
, &tp
->net_stats_prev
);
9476 memcpy(&tp
->estats_prev
, tg3_get_estats(tp
),
9477 sizeof(tp
->estats_prev
));
9481 tg3_free_consistent(tp
);
9485 netif_carrier_off(tp
->dev
);
9490 static inline u64
get_stat64(tg3_stat64_t
*val
)
9492 return ((u64
)val
->high
<< 32) | ((u64
)val
->low
);
9495 static u64
calc_crc_errors(struct tg3
*tp
)
9497 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
9499 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
9500 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
9501 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
9504 spin_lock_bh(&tp
->lock
);
9505 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &val
)) {
9506 tg3_writephy(tp
, MII_TG3_TEST1
,
9507 val
| MII_TG3_TEST1_CRC_EN
);
9508 tg3_readphy(tp
, MII_TG3_RXR_COUNTERS
, &val
);
9511 spin_unlock_bh(&tp
->lock
);
9513 tp
->phy_crc_errors
+= val
;
9515 return tp
->phy_crc_errors
;
9518 return get_stat64(&hw_stats
->rx_fcs_errors
);
9521 #define ESTAT_ADD(member) \
9522 estats->member = old_estats->member + \
9523 get_stat64(&hw_stats->member)
9525 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*tp
)
9527 struct tg3_ethtool_stats
*estats
= &tp
->estats
;
9528 struct tg3_ethtool_stats
*old_estats
= &tp
->estats_prev
;
9529 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
9534 ESTAT_ADD(rx_octets
);
9535 ESTAT_ADD(rx_fragments
);
9536 ESTAT_ADD(rx_ucast_packets
);
9537 ESTAT_ADD(rx_mcast_packets
);
9538 ESTAT_ADD(rx_bcast_packets
);
9539 ESTAT_ADD(rx_fcs_errors
);
9540 ESTAT_ADD(rx_align_errors
);
9541 ESTAT_ADD(rx_xon_pause_rcvd
);
9542 ESTAT_ADD(rx_xoff_pause_rcvd
);
9543 ESTAT_ADD(rx_mac_ctrl_rcvd
);
9544 ESTAT_ADD(rx_xoff_entered
);
9545 ESTAT_ADD(rx_frame_too_long_errors
);
9546 ESTAT_ADD(rx_jabbers
);
9547 ESTAT_ADD(rx_undersize_packets
);
9548 ESTAT_ADD(rx_in_length_errors
);
9549 ESTAT_ADD(rx_out_length_errors
);
9550 ESTAT_ADD(rx_64_or_less_octet_packets
);
9551 ESTAT_ADD(rx_65_to_127_octet_packets
);
9552 ESTAT_ADD(rx_128_to_255_octet_packets
);
9553 ESTAT_ADD(rx_256_to_511_octet_packets
);
9554 ESTAT_ADD(rx_512_to_1023_octet_packets
);
9555 ESTAT_ADD(rx_1024_to_1522_octet_packets
);
9556 ESTAT_ADD(rx_1523_to_2047_octet_packets
);
9557 ESTAT_ADD(rx_2048_to_4095_octet_packets
);
9558 ESTAT_ADD(rx_4096_to_8191_octet_packets
);
9559 ESTAT_ADD(rx_8192_to_9022_octet_packets
);
9561 ESTAT_ADD(tx_octets
);
9562 ESTAT_ADD(tx_collisions
);
9563 ESTAT_ADD(tx_xon_sent
);
9564 ESTAT_ADD(tx_xoff_sent
);
9565 ESTAT_ADD(tx_flow_control
);
9566 ESTAT_ADD(tx_mac_errors
);
9567 ESTAT_ADD(tx_single_collisions
);
9568 ESTAT_ADD(tx_mult_collisions
);
9569 ESTAT_ADD(tx_deferred
);
9570 ESTAT_ADD(tx_excessive_collisions
);
9571 ESTAT_ADD(tx_late_collisions
);
9572 ESTAT_ADD(tx_collide_2times
);
9573 ESTAT_ADD(tx_collide_3times
);
9574 ESTAT_ADD(tx_collide_4times
);
9575 ESTAT_ADD(tx_collide_5times
);
9576 ESTAT_ADD(tx_collide_6times
);
9577 ESTAT_ADD(tx_collide_7times
);
9578 ESTAT_ADD(tx_collide_8times
);
9579 ESTAT_ADD(tx_collide_9times
);
9580 ESTAT_ADD(tx_collide_10times
);
9581 ESTAT_ADD(tx_collide_11times
);
9582 ESTAT_ADD(tx_collide_12times
);
9583 ESTAT_ADD(tx_collide_13times
);
9584 ESTAT_ADD(tx_collide_14times
);
9585 ESTAT_ADD(tx_collide_15times
);
9586 ESTAT_ADD(tx_ucast_packets
);
9587 ESTAT_ADD(tx_mcast_packets
);
9588 ESTAT_ADD(tx_bcast_packets
);
9589 ESTAT_ADD(tx_carrier_sense_errors
);
9590 ESTAT_ADD(tx_discards
);
9591 ESTAT_ADD(tx_errors
);
9593 ESTAT_ADD(dma_writeq_full
);
9594 ESTAT_ADD(dma_write_prioq_full
);
9595 ESTAT_ADD(rxbds_empty
);
9596 ESTAT_ADD(rx_discards
);
9597 ESTAT_ADD(rx_errors
);
9598 ESTAT_ADD(rx_threshold_hit
);
9600 ESTAT_ADD(dma_readq_full
);
9601 ESTAT_ADD(dma_read_prioq_full
);
9602 ESTAT_ADD(tx_comp_queue_full
);
9604 ESTAT_ADD(ring_set_send_prod_index
);
9605 ESTAT_ADD(ring_status_update
);
9606 ESTAT_ADD(nic_irqs
);
9607 ESTAT_ADD(nic_avoided_irqs
);
9608 ESTAT_ADD(nic_tx_threshold_hit
);
9613 static struct rtnl_link_stats64
*tg3_get_stats64(struct net_device
*dev
,
9614 struct rtnl_link_stats64
*stats
)
9616 struct tg3
*tp
= netdev_priv(dev
);
9617 struct rtnl_link_stats64
*old_stats
= &tp
->net_stats_prev
;
9618 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
9623 stats
->rx_packets
= old_stats
->rx_packets
+
9624 get_stat64(&hw_stats
->rx_ucast_packets
) +
9625 get_stat64(&hw_stats
->rx_mcast_packets
) +
9626 get_stat64(&hw_stats
->rx_bcast_packets
);
9628 stats
->tx_packets
= old_stats
->tx_packets
+
9629 get_stat64(&hw_stats
->tx_ucast_packets
) +
9630 get_stat64(&hw_stats
->tx_mcast_packets
) +
9631 get_stat64(&hw_stats
->tx_bcast_packets
);
9633 stats
->rx_bytes
= old_stats
->rx_bytes
+
9634 get_stat64(&hw_stats
->rx_octets
);
9635 stats
->tx_bytes
= old_stats
->tx_bytes
+
9636 get_stat64(&hw_stats
->tx_octets
);
9638 stats
->rx_errors
= old_stats
->rx_errors
+
9639 get_stat64(&hw_stats
->rx_errors
);
9640 stats
->tx_errors
= old_stats
->tx_errors
+
9641 get_stat64(&hw_stats
->tx_errors
) +
9642 get_stat64(&hw_stats
->tx_mac_errors
) +
9643 get_stat64(&hw_stats
->tx_carrier_sense_errors
) +
9644 get_stat64(&hw_stats
->tx_discards
);
9646 stats
->multicast
= old_stats
->multicast
+
9647 get_stat64(&hw_stats
->rx_mcast_packets
);
9648 stats
->collisions
= old_stats
->collisions
+
9649 get_stat64(&hw_stats
->tx_collisions
);
9651 stats
->rx_length_errors
= old_stats
->rx_length_errors
+
9652 get_stat64(&hw_stats
->rx_frame_too_long_errors
) +
9653 get_stat64(&hw_stats
->rx_undersize_packets
);
9655 stats
->rx_over_errors
= old_stats
->rx_over_errors
+
9656 get_stat64(&hw_stats
->rxbds_empty
);
9657 stats
->rx_frame_errors
= old_stats
->rx_frame_errors
+
9658 get_stat64(&hw_stats
->rx_align_errors
);
9659 stats
->tx_aborted_errors
= old_stats
->tx_aborted_errors
+
9660 get_stat64(&hw_stats
->tx_discards
);
9661 stats
->tx_carrier_errors
= old_stats
->tx_carrier_errors
+
9662 get_stat64(&hw_stats
->tx_carrier_sense_errors
);
9664 stats
->rx_crc_errors
= old_stats
->rx_crc_errors
+
9665 calc_crc_errors(tp
);
9667 stats
->rx_missed_errors
= old_stats
->rx_missed_errors
+
9668 get_stat64(&hw_stats
->rx_discards
);
9670 stats
->rx_dropped
= tp
->rx_dropped
;
9675 static inline u32
calc_crc(unsigned char *buf
, int len
)
9683 for (j
= 0; j
< len
; j
++) {
9686 for (k
= 0; k
< 8; k
++) {
9699 static void tg3_set_multi(struct tg3
*tp
, unsigned int accept_all
)
9701 /* accept or reject all multicast frames */
9702 tw32(MAC_HASH_REG_0
, accept_all
? 0xffffffff : 0);
9703 tw32(MAC_HASH_REG_1
, accept_all
? 0xffffffff : 0);
9704 tw32(MAC_HASH_REG_2
, accept_all
? 0xffffffff : 0);
9705 tw32(MAC_HASH_REG_3
, accept_all
? 0xffffffff : 0);
9708 static void __tg3_set_rx_mode(struct net_device
*dev
)
9710 struct tg3
*tp
= netdev_priv(dev
);
9713 rx_mode
= tp
->rx_mode
& ~(RX_MODE_PROMISC
|
9714 RX_MODE_KEEP_VLAN_TAG
);
9716 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9717 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9720 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
9721 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
9724 if (dev
->flags
& IFF_PROMISC
) {
9725 /* Promiscuous mode. */
9726 rx_mode
|= RX_MODE_PROMISC
;
9727 } else if (dev
->flags
& IFF_ALLMULTI
) {
9728 /* Accept all multicast. */
9729 tg3_set_multi(tp
, 1);
9730 } else if (netdev_mc_empty(dev
)) {
9731 /* Reject all multicast. */
9732 tg3_set_multi(tp
, 0);
9734 /* Accept one or more multicast(s). */
9735 struct netdev_hw_addr
*ha
;
9736 u32 mc_filter
[4] = { 0, };
9741 netdev_for_each_mc_addr(ha
, dev
) {
9742 crc
= calc_crc(ha
->addr
, ETH_ALEN
);
9744 regidx
= (bit
& 0x60) >> 5;
9746 mc_filter
[regidx
] |= (1 << bit
);
9749 tw32(MAC_HASH_REG_0
, mc_filter
[0]);
9750 tw32(MAC_HASH_REG_1
, mc_filter
[1]);
9751 tw32(MAC_HASH_REG_2
, mc_filter
[2]);
9752 tw32(MAC_HASH_REG_3
, mc_filter
[3]);
9755 if (rx_mode
!= tp
->rx_mode
) {
9756 tp
->rx_mode
= rx_mode
;
9757 tw32_f(MAC_RX_MODE
, rx_mode
);
9762 static void tg3_set_rx_mode(struct net_device
*dev
)
9764 struct tg3
*tp
= netdev_priv(dev
);
9766 if (!netif_running(dev
))
9769 tg3_full_lock(tp
, 0);
9770 __tg3_set_rx_mode(dev
);
9771 tg3_full_unlock(tp
);
9774 static int tg3_get_regs_len(struct net_device
*dev
)
9776 return TG3_REG_BLK_SIZE
;
9779 static void tg3_get_regs(struct net_device
*dev
,
9780 struct ethtool_regs
*regs
, void *_p
)
9782 struct tg3
*tp
= netdev_priv(dev
);
9786 memset(_p
, 0, TG3_REG_BLK_SIZE
);
9788 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
9791 tg3_full_lock(tp
, 0);
9793 tg3_dump_legacy_regs(tp
, (u32
*)_p
);
9795 tg3_full_unlock(tp
);
9798 static int tg3_get_eeprom_len(struct net_device
*dev
)
9800 struct tg3
*tp
= netdev_priv(dev
);
9802 return tp
->nvram_size
;
9805 static int tg3_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
9807 struct tg3
*tp
= netdev_priv(dev
);
9810 u32 i
, offset
, len
, b_offset
, b_count
;
9813 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
)
9816 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
9819 offset
= eeprom
->offset
;
9823 eeprom
->magic
= TG3_EEPROM_MAGIC
;
9826 /* adjustments to start on required 4 byte boundary */
9827 b_offset
= offset
& 3;
9828 b_count
= 4 - b_offset
;
9829 if (b_count
> len
) {
9830 /* i.e. offset=1 len=2 */
9833 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &val
);
9836 memcpy(data
, ((char *)&val
) + b_offset
, b_count
);
9839 eeprom
->len
+= b_count
;
9842 /* read bytes up to the last 4 byte boundary */
9843 pd
= &data
[eeprom
->len
];
9844 for (i
= 0; i
< (len
- (len
& 3)); i
+= 4) {
9845 ret
= tg3_nvram_read_be32(tp
, offset
+ i
, &val
);
9850 memcpy(pd
+ i
, &val
, 4);
9855 /* read last bytes not ending on 4 byte boundary */
9856 pd
= &data
[eeprom
->len
];
9858 b_offset
= offset
+ len
- b_count
;
9859 ret
= tg3_nvram_read_be32(tp
, b_offset
, &val
);
9862 memcpy(pd
, &val
, b_count
);
9863 eeprom
->len
+= b_count
;
9868 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
);
9870 static int tg3_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
9872 struct tg3
*tp
= netdev_priv(dev
);
9874 u32 offset
, len
, b_offset
, odd_len
;
9878 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
9881 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
9882 eeprom
->magic
!= TG3_EEPROM_MAGIC
)
9885 offset
= eeprom
->offset
;
9888 if ((b_offset
= (offset
& 3))) {
9889 /* adjustments to start on required 4 byte boundary */
9890 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &start
);
9901 /* adjustments to end on required 4 byte boundary */
9903 len
= (len
+ 3) & ~3;
9904 ret
= tg3_nvram_read_be32(tp
, offset
+len
-4, &end
);
9910 if (b_offset
|| odd_len
) {
9911 buf
= kmalloc(len
, GFP_KERNEL
);
9915 memcpy(buf
, &start
, 4);
9917 memcpy(buf
+len
-4, &end
, 4);
9918 memcpy(buf
+ b_offset
, data
, eeprom
->len
);
9921 ret
= tg3_nvram_write_block(tp
, offset
, len
, buf
);
9929 static int tg3_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
9931 struct tg3
*tp
= netdev_priv(dev
);
9933 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9934 struct phy_device
*phydev
;
9935 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
9937 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
9938 return phy_ethtool_gset(phydev
, cmd
);
9941 cmd
->supported
= (SUPPORTED_Autoneg
);
9943 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
9944 cmd
->supported
|= (SUPPORTED_1000baseT_Half
|
9945 SUPPORTED_1000baseT_Full
);
9947 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)) {
9948 cmd
->supported
|= (SUPPORTED_100baseT_Half
|
9949 SUPPORTED_100baseT_Full
|
9950 SUPPORTED_10baseT_Half
|
9951 SUPPORTED_10baseT_Full
|
9953 cmd
->port
= PORT_TP
;
9955 cmd
->supported
|= SUPPORTED_FIBRE
;
9956 cmd
->port
= PORT_FIBRE
;
9959 cmd
->advertising
= tp
->link_config
.advertising
;
9960 if (netif_running(dev
)) {
9961 cmd
->speed
= tp
->link_config
.active_speed
;
9962 cmd
->duplex
= tp
->link_config
.active_duplex
;
9964 cmd
->speed
= SPEED_INVALID
;
9965 cmd
->duplex
= DUPLEX_INVALID
;
9967 cmd
->phy_address
= tp
->phy_addr
;
9968 cmd
->transceiver
= XCVR_INTERNAL
;
9969 cmd
->autoneg
= tp
->link_config
.autoneg
;
9975 static int tg3_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
9977 struct tg3
*tp
= netdev_priv(dev
);
9979 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9980 struct phy_device
*phydev
;
9981 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
9983 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
9984 return phy_ethtool_sset(phydev
, cmd
);
9987 if (cmd
->autoneg
!= AUTONEG_ENABLE
&&
9988 cmd
->autoneg
!= AUTONEG_DISABLE
)
9991 if (cmd
->autoneg
== AUTONEG_DISABLE
&&
9992 cmd
->duplex
!= DUPLEX_FULL
&&
9993 cmd
->duplex
!= DUPLEX_HALF
)
9996 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
9997 u32 mask
= ADVERTISED_Autoneg
|
9999 ADVERTISED_Asym_Pause
;
10001 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
10002 mask
|= ADVERTISED_1000baseT_Half
|
10003 ADVERTISED_1000baseT_Full
;
10005 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
10006 mask
|= ADVERTISED_100baseT_Half
|
10007 ADVERTISED_100baseT_Full
|
10008 ADVERTISED_10baseT_Half
|
10009 ADVERTISED_10baseT_Full
|
10012 mask
|= ADVERTISED_FIBRE
;
10014 if (cmd
->advertising
& ~mask
)
10017 mask
&= (ADVERTISED_1000baseT_Half
|
10018 ADVERTISED_1000baseT_Full
|
10019 ADVERTISED_100baseT_Half
|
10020 ADVERTISED_100baseT_Full
|
10021 ADVERTISED_10baseT_Half
|
10022 ADVERTISED_10baseT_Full
);
10024 cmd
->advertising
&= mask
;
10026 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
) {
10027 if (cmd
->speed
!= SPEED_1000
)
10030 if (cmd
->duplex
!= DUPLEX_FULL
)
10033 if (cmd
->speed
!= SPEED_100
&&
10034 cmd
->speed
!= SPEED_10
)
10039 tg3_full_lock(tp
, 0);
10041 tp
->link_config
.autoneg
= cmd
->autoneg
;
10042 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
10043 tp
->link_config
.advertising
= (cmd
->advertising
|
10044 ADVERTISED_Autoneg
);
10045 tp
->link_config
.speed
= SPEED_INVALID
;
10046 tp
->link_config
.duplex
= DUPLEX_INVALID
;
10048 tp
->link_config
.advertising
= 0;
10049 tp
->link_config
.speed
= cmd
->speed
;
10050 tp
->link_config
.duplex
= cmd
->duplex
;
10053 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
10054 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
10055 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
10057 if (netif_running(dev
))
10058 tg3_setup_phy(tp
, 1);
10060 tg3_full_unlock(tp
);
10065 static void tg3_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
10067 struct tg3
*tp
= netdev_priv(dev
);
10069 strcpy(info
->driver
, DRV_MODULE_NAME
);
10070 strcpy(info
->version
, DRV_MODULE_VERSION
);
10071 strcpy(info
->fw_version
, tp
->fw_ver
);
10072 strcpy(info
->bus_info
, pci_name(tp
->pdev
));
10075 static void tg3_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
10077 struct tg3
*tp
= netdev_priv(dev
);
10079 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
10080 device_can_wakeup(&tp
->pdev
->dev
))
10081 wol
->supported
= WAKE_MAGIC
;
10083 wol
->supported
= 0;
10085 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) &&
10086 device_can_wakeup(&tp
->pdev
->dev
))
10087 wol
->wolopts
= WAKE_MAGIC
;
10088 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
10091 static int tg3_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
10093 struct tg3
*tp
= netdev_priv(dev
);
10094 struct device
*dp
= &tp
->pdev
->dev
;
10096 if (wol
->wolopts
& ~WAKE_MAGIC
)
10098 if ((wol
->wolopts
& WAKE_MAGIC
) &&
10099 !((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) && device_can_wakeup(dp
)))
10102 device_set_wakeup_enable(dp
, wol
->wolopts
& WAKE_MAGIC
);
10104 spin_lock_bh(&tp
->lock
);
10105 if (device_may_wakeup(dp
))
10106 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
10108 tp
->tg3_flags
&= ~TG3_FLAG_WOL_ENABLE
;
10109 spin_unlock_bh(&tp
->lock
);
10115 static u32
tg3_get_msglevel(struct net_device
*dev
)
10117 struct tg3
*tp
= netdev_priv(dev
);
10118 return tp
->msg_enable
;
10121 static void tg3_set_msglevel(struct net_device
*dev
, u32 value
)
10123 struct tg3
*tp
= netdev_priv(dev
);
10124 tp
->msg_enable
= value
;
10127 static int tg3_nway_reset(struct net_device
*dev
)
10129 struct tg3
*tp
= netdev_priv(dev
);
10132 if (!netif_running(dev
))
10135 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
10138 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
10139 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
10141 r
= phy_start_aneg(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
10145 spin_lock_bh(&tp
->lock
);
10147 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
10148 if (!tg3_readphy(tp
, MII_BMCR
, &bmcr
) &&
10149 ((bmcr
& BMCR_ANENABLE
) ||
10150 (tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
))) {
10151 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANRESTART
|
10155 spin_unlock_bh(&tp
->lock
);
10161 static void tg3_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
10163 struct tg3
*tp
= netdev_priv(dev
);
10165 ering
->rx_max_pending
= tp
->rx_std_ring_mask
;
10166 ering
->rx_mini_max_pending
= 0;
10167 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
10168 ering
->rx_jumbo_max_pending
= tp
->rx_jmb_ring_mask
;
10170 ering
->rx_jumbo_max_pending
= 0;
10172 ering
->tx_max_pending
= TG3_TX_RING_SIZE
- 1;
10174 ering
->rx_pending
= tp
->rx_pending
;
10175 ering
->rx_mini_pending
= 0;
10176 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
10177 ering
->rx_jumbo_pending
= tp
->rx_jumbo_pending
;
10179 ering
->rx_jumbo_pending
= 0;
10181 ering
->tx_pending
= tp
->napi
[0].tx_pending
;
10184 static int tg3_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
10186 struct tg3
*tp
= netdev_priv(dev
);
10187 int i
, irq_sync
= 0, err
= 0;
10189 if ((ering
->rx_pending
> tp
->rx_std_ring_mask
) ||
10190 (ering
->rx_jumbo_pending
> tp
->rx_jmb_ring_mask
) ||
10191 (ering
->tx_pending
> TG3_TX_RING_SIZE
- 1) ||
10192 (ering
->tx_pending
<= MAX_SKB_FRAGS
) ||
10193 ((tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
) &&
10194 (ering
->tx_pending
<= (MAX_SKB_FRAGS
* 3))))
10197 if (netif_running(dev
)) {
10199 tg3_netif_stop(tp
);
10203 tg3_full_lock(tp
, irq_sync
);
10205 tp
->rx_pending
= ering
->rx_pending
;
10207 if ((tp
->tg3_flags2
& TG3_FLG2_MAX_RXPEND_64
) &&
10208 tp
->rx_pending
> 63)
10209 tp
->rx_pending
= 63;
10210 tp
->rx_jumbo_pending
= ering
->rx_jumbo_pending
;
10212 for (i
= 0; i
< tp
->irq_max
; i
++)
10213 tp
->napi
[i
].tx_pending
= ering
->tx_pending
;
10215 if (netif_running(dev
)) {
10216 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
10217 err
= tg3_restart_hw(tp
, 1);
10219 tg3_netif_start(tp
);
10222 tg3_full_unlock(tp
);
10224 if (irq_sync
&& !err
)
10230 static void tg3_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
10232 struct tg3
*tp
= netdev_priv(dev
);
10234 epause
->autoneg
= (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
) != 0;
10236 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
)
10237 epause
->rx_pause
= 1;
10239 epause
->rx_pause
= 0;
10241 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
)
10242 epause
->tx_pause
= 1;
10244 epause
->tx_pause
= 0;
10247 static int tg3_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
10249 struct tg3
*tp
= netdev_priv(dev
);
10252 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
10254 struct phy_device
*phydev
;
10256 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
10258 if (!(phydev
->supported
& SUPPORTED_Pause
) ||
10259 (!(phydev
->supported
& SUPPORTED_Asym_Pause
) &&
10260 (epause
->rx_pause
!= epause
->tx_pause
)))
10263 tp
->link_config
.flowctrl
= 0;
10264 if (epause
->rx_pause
) {
10265 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
10267 if (epause
->tx_pause
) {
10268 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
10269 newadv
= ADVERTISED_Pause
;
10271 newadv
= ADVERTISED_Pause
|
10272 ADVERTISED_Asym_Pause
;
10273 } else if (epause
->tx_pause
) {
10274 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
10275 newadv
= ADVERTISED_Asym_Pause
;
10279 if (epause
->autoneg
)
10280 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
10282 tp
->tg3_flags
&= ~TG3_FLAG_PAUSE_AUTONEG
;
10284 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) {
10285 u32 oldadv
= phydev
->advertising
&
10286 (ADVERTISED_Pause
| ADVERTISED_Asym_Pause
);
10287 if (oldadv
!= newadv
) {
10288 phydev
->advertising
&=
10289 ~(ADVERTISED_Pause
|
10290 ADVERTISED_Asym_Pause
);
10291 phydev
->advertising
|= newadv
;
10292 if (phydev
->autoneg
) {
10294 * Always renegotiate the link to
10295 * inform our link partner of our
10296 * flow control settings, even if the
10297 * flow control is forced. Let
10298 * tg3_adjust_link() do the final
10299 * flow control setup.
10301 return phy_start_aneg(phydev
);
10305 if (!epause
->autoneg
)
10306 tg3_setup_flow_control(tp
, 0, 0);
10308 tp
->link_config
.orig_advertising
&=
10309 ~(ADVERTISED_Pause
|
10310 ADVERTISED_Asym_Pause
);
10311 tp
->link_config
.orig_advertising
|= newadv
;
10316 if (netif_running(dev
)) {
10317 tg3_netif_stop(tp
);
10321 tg3_full_lock(tp
, irq_sync
);
10323 if (epause
->autoneg
)
10324 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
10326 tp
->tg3_flags
&= ~TG3_FLAG_PAUSE_AUTONEG
;
10327 if (epause
->rx_pause
)
10328 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
10330 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_RX
;
10331 if (epause
->tx_pause
)
10332 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
10334 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_TX
;
10336 if (netif_running(dev
)) {
10337 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
10338 err
= tg3_restart_hw(tp
, 1);
10340 tg3_netif_start(tp
);
10343 tg3_full_unlock(tp
);
10349 static int tg3_get_sset_count(struct net_device
*dev
, int sset
)
10353 return TG3_NUM_TEST
;
10355 return TG3_NUM_STATS
;
10357 return -EOPNOTSUPP
;
10361 static void tg3_get_strings(struct net_device
*dev
, u32 stringset
, u8
*buf
)
10363 switch (stringset
) {
10365 memcpy(buf
, ðtool_stats_keys
, sizeof(ethtool_stats_keys
));
10368 memcpy(buf
, ðtool_test_keys
, sizeof(ethtool_test_keys
));
10371 WARN_ON(1); /* we need a WARN() */
10376 static int tg3_set_phys_id(struct net_device
*dev
,
10377 enum ethtool_phys_id_state state
)
10379 struct tg3
*tp
= netdev_priv(dev
);
10381 if (!netif_running(tp
->dev
))
10385 case ETHTOOL_ID_ACTIVE
:
10388 case ETHTOOL_ID_ON
:
10389 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
10390 LED_CTRL_1000MBPS_ON
|
10391 LED_CTRL_100MBPS_ON
|
10392 LED_CTRL_10MBPS_ON
|
10393 LED_CTRL_TRAFFIC_OVERRIDE
|
10394 LED_CTRL_TRAFFIC_BLINK
|
10395 LED_CTRL_TRAFFIC_LED
);
10398 case ETHTOOL_ID_OFF
:
10399 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
10400 LED_CTRL_TRAFFIC_OVERRIDE
);
10403 case ETHTOOL_ID_INACTIVE
:
10404 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
10411 static void tg3_get_ethtool_stats(struct net_device
*dev
,
10412 struct ethtool_stats
*estats
, u64
*tmp_stats
)
10414 struct tg3
*tp
= netdev_priv(dev
);
10415 memcpy(tmp_stats
, tg3_get_estats(tp
), sizeof(tp
->estats
));
10418 #define NVRAM_TEST_SIZE 0x100
10419 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10420 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10421 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10422 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10423 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10425 static int tg3_test_nvram(struct tg3
*tp
)
10429 int i
, j
, k
, err
= 0, size
;
10431 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
)
10434 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
10437 if (magic
== TG3_EEPROM_MAGIC
)
10438 size
= NVRAM_TEST_SIZE
;
10439 else if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
) {
10440 if ((magic
& TG3_EEPROM_SB_FORMAT_MASK
) ==
10441 TG3_EEPROM_SB_FORMAT_1
) {
10442 switch (magic
& TG3_EEPROM_SB_REVISION_MASK
) {
10443 case TG3_EEPROM_SB_REVISION_0
:
10444 size
= NVRAM_SELFBOOT_FORMAT1_0_SIZE
;
10446 case TG3_EEPROM_SB_REVISION_2
:
10447 size
= NVRAM_SELFBOOT_FORMAT1_2_SIZE
;
10449 case TG3_EEPROM_SB_REVISION_3
:
10450 size
= NVRAM_SELFBOOT_FORMAT1_3_SIZE
;
10457 } else if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
10458 size
= NVRAM_SELFBOOT_HW_SIZE
;
10462 buf
= kmalloc(size
, GFP_KERNEL
);
10467 for (i
= 0, j
= 0; i
< size
; i
+= 4, j
++) {
10468 err
= tg3_nvram_read_be32(tp
, i
, &buf
[j
]);
10475 /* Selfboot format */
10476 magic
= be32_to_cpu(buf
[0]);
10477 if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) ==
10478 TG3_EEPROM_MAGIC_FW
) {
10479 u8
*buf8
= (u8
*) buf
, csum8
= 0;
10481 if ((magic
& TG3_EEPROM_SB_REVISION_MASK
) ==
10482 TG3_EEPROM_SB_REVISION_2
) {
10483 /* For rev 2, the csum doesn't include the MBA. */
10484 for (i
= 0; i
< TG3_EEPROM_SB_F1R2_MBA_OFF
; i
++)
10486 for (i
= TG3_EEPROM_SB_F1R2_MBA_OFF
+ 4; i
< size
; i
++)
10489 for (i
= 0; i
< size
; i
++)
10502 if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) ==
10503 TG3_EEPROM_MAGIC_HW
) {
10504 u8 data
[NVRAM_SELFBOOT_DATA_SIZE
];
10505 u8 parity
[NVRAM_SELFBOOT_DATA_SIZE
];
10506 u8
*buf8
= (u8
*) buf
;
10508 /* Separate the parity bits and the data bytes. */
10509 for (i
= 0, j
= 0, k
= 0; i
< NVRAM_SELFBOOT_HW_SIZE
; i
++) {
10510 if ((i
== 0) || (i
== 8)) {
10514 for (l
= 0, msk
= 0x80; l
< 7; l
++, msk
>>= 1)
10515 parity
[k
++] = buf8
[i
] & msk
;
10517 } else if (i
== 16) {
10521 for (l
= 0, msk
= 0x20; l
< 6; l
++, msk
>>= 1)
10522 parity
[k
++] = buf8
[i
] & msk
;
10525 for (l
= 0, msk
= 0x80; l
< 8; l
++, msk
>>= 1)
10526 parity
[k
++] = buf8
[i
] & msk
;
10529 data
[j
++] = buf8
[i
];
10533 for (i
= 0; i
< NVRAM_SELFBOOT_DATA_SIZE
; i
++) {
10534 u8 hw8
= hweight8(data
[i
]);
10536 if ((hw8
& 0x1) && parity
[i
])
10538 else if (!(hw8
& 0x1) && !parity
[i
])
10547 /* Bootstrap checksum at offset 0x10 */
10548 csum
= calc_crc((unsigned char *) buf
, 0x10);
10549 if (csum
!= le32_to_cpu(buf
[0x10/4]))
10552 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10553 csum
= calc_crc((unsigned char *) &buf
[0x74/4], 0x88);
10554 if (csum
!= le32_to_cpu(buf
[0xfc/4]))
10557 for (i
= 0; i
< TG3_NVM_VPD_LEN
; i
+= 4) {
10558 /* The data is in little-endian format in NVRAM.
10559 * Use the big-endian read routines to preserve
10560 * the byte order as it exists in NVRAM.
10562 if (tg3_nvram_read_be32(tp
, TG3_NVM_VPD_OFF
+ i
, &buf
[i
/4]))
10566 i
= pci_vpd_find_tag((u8
*)buf
, 0, TG3_NVM_VPD_LEN
,
10567 PCI_VPD_LRDT_RO_DATA
);
10569 j
= pci_vpd_lrdt_size(&((u8
*)buf
)[i
]);
10573 if (i
+ PCI_VPD_LRDT_TAG_SIZE
+ j
> TG3_NVM_VPD_LEN
)
10576 i
+= PCI_VPD_LRDT_TAG_SIZE
;
10577 j
= pci_vpd_find_info_keyword((u8
*)buf
, i
, j
,
10578 PCI_VPD_RO_KEYWORD_CHKSUM
);
10582 j
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
10584 for (i
= 0; i
<= j
; i
++)
10585 csum8
+= ((u8
*)buf
)[i
];
10599 #define TG3_SERDES_TIMEOUT_SEC 2
10600 #define TG3_COPPER_TIMEOUT_SEC 6
10602 static int tg3_test_link(struct tg3
*tp
)
10606 if (!netif_running(tp
->dev
))
10609 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
10610 max
= TG3_SERDES_TIMEOUT_SEC
;
10612 max
= TG3_COPPER_TIMEOUT_SEC
;
10614 for (i
= 0; i
< max
; i
++) {
10615 if (netif_carrier_ok(tp
->dev
))
10618 if (msleep_interruptible(1000))
10625 /* Only test the commonly used registers */
10626 static int tg3_test_registers(struct tg3
*tp
)
10628 int i
, is_5705
, is_5750
;
10629 u32 offset
, read_mask
, write_mask
, val
, save_val
, read_val
;
10633 #define TG3_FL_5705 0x1
10634 #define TG3_FL_NOT_5705 0x2
10635 #define TG3_FL_NOT_5788 0x4
10636 #define TG3_FL_NOT_5750 0x8
10640 /* MAC Control Registers */
10641 { MAC_MODE
, TG3_FL_NOT_5705
,
10642 0x00000000, 0x00ef6f8c },
10643 { MAC_MODE
, TG3_FL_5705
,
10644 0x00000000, 0x01ef6b8c },
10645 { MAC_STATUS
, TG3_FL_NOT_5705
,
10646 0x03800107, 0x00000000 },
10647 { MAC_STATUS
, TG3_FL_5705
,
10648 0x03800100, 0x00000000 },
10649 { MAC_ADDR_0_HIGH
, 0x0000,
10650 0x00000000, 0x0000ffff },
10651 { MAC_ADDR_0_LOW
, 0x0000,
10652 0x00000000, 0xffffffff },
10653 { MAC_RX_MTU_SIZE
, 0x0000,
10654 0x00000000, 0x0000ffff },
10655 { MAC_TX_MODE
, 0x0000,
10656 0x00000000, 0x00000070 },
10657 { MAC_TX_LENGTHS
, 0x0000,
10658 0x00000000, 0x00003fff },
10659 { MAC_RX_MODE
, TG3_FL_NOT_5705
,
10660 0x00000000, 0x000007fc },
10661 { MAC_RX_MODE
, TG3_FL_5705
,
10662 0x00000000, 0x000007dc },
10663 { MAC_HASH_REG_0
, 0x0000,
10664 0x00000000, 0xffffffff },
10665 { MAC_HASH_REG_1
, 0x0000,
10666 0x00000000, 0xffffffff },
10667 { MAC_HASH_REG_2
, 0x0000,
10668 0x00000000, 0xffffffff },
10669 { MAC_HASH_REG_3
, 0x0000,
10670 0x00000000, 0xffffffff },
10672 /* Receive Data and Receive BD Initiator Control Registers. */
10673 { RCVDBDI_JUMBO_BD
+0, TG3_FL_NOT_5705
,
10674 0x00000000, 0xffffffff },
10675 { RCVDBDI_JUMBO_BD
+4, TG3_FL_NOT_5705
,
10676 0x00000000, 0xffffffff },
10677 { RCVDBDI_JUMBO_BD
+8, TG3_FL_NOT_5705
,
10678 0x00000000, 0x00000003 },
10679 { RCVDBDI_JUMBO_BD
+0xc, TG3_FL_NOT_5705
,
10680 0x00000000, 0xffffffff },
10681 { RCVDBDI_STD_BD
+0, 0x0000,
10682 0x00000000, 0xffffffff },
10683 { RCVDBDI_STD_BD
+4, 0x0000,
10684 0x00000000, 0xffffffff },
10685 { RCVDBDI_STD_BD
+8, 0x0000,
10686 0x00000000, 0xffff0002 },
10687 { RCVDBDI_STD_BD
+0xc, 0x0000,
10688 0x00000000, 0xffffffff },
10690 /* Receive BD Initiator Control Registers. */
10691 { RCVBDI_STD_THRESH
, TG3_FL_NOT_5705
,
10692 0x00000000, 0xffffffff },
10693 { RCVBDI_STD_THRESH
, TG3_FL_5705
,
10694 0x00000000, 0x000003ff },
10695 { RCVBDI_JUMBO_THRESH
, TG3_FL_NOT_5705
,
10696 0x00000000, 0xffffffff },
10698 /* Host Coalescing Control Registers. */
10699 { HOSTCC_MODE
, TG3_FL_NOT_5705
,
10700 0x00000000, 0x00000004 },
10701 { HOSTCC_MODE
, TG3_FL_5705
,
10702 0x00000000, 0x000000f6 },
10703 { HOSTCC_RXCOL_TICKS
, TG3_FL_NOT_5705
,
10704 0x00000000, 0xffffffff },
10705 { HOSTCC_RXCOL_TICKS
, TG3_FL_5705
,
10706 0x00000000, 0x000003ff },
10707 { HOSTCC_TXCOL_TICKS
, TG3_FL_NOT_5705
,
10708 0x00000000, 0xffffffff },
10709 { HOSTCC_TXCOL_TICKS
, TG3_FL_5705
,
10710 0x00000000, 0x000003ff },
10711 { HOSTCC_RXMAX_FRAMES
, TG3_FL_NOT_5705
,
10712 0x00000000, 0xffffffff },
10713 { HOSTCC_RXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10714 0x00000000, 0x000000ff },
10715 { HOSTCC_TXMAX_FRAMES
, TG3_FL_NOT_5705
,
10716 0x00000000, 0xffffffff },
10717 { HOSTCC_TXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10718 0x00000000, 0x000000ff },
10719 { HOSTCC_RXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
10720 0x00000000, 0xffffffff },
10721 { HOSTCC_TXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
10722 0x00000000, 0xffffffff },
10723 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
10724 0x00000000, 0xffffffff },
10725 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10726 0x00000000, 0x000000ff },
10727 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
10728 0x00000000, 0xffffffff },
10729 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10730 0x00000000, 0x000000ff },
10731 { HOSTCC_STAT_COAL_TICKS
, TG3_FL_NOT_5705
,
10732 0x00000000, 0xffffffff },
10733 { HOSTCC_STATS_BLK_HOST_ADDR
, TG3_FL_NOT_5705
,
10734 0x00000000, 0xffffffff },
10735 { HOSTCC_STATS_BLK_HOST_ADDR
+4, TG3_FL_NOT_5705
,
10736 0x00000000, 0xffffffff },
10737 { HOSTCC_STATUS_BLK_HOST_ADDR
, 0x0000,
10738 0x00000000, 0xffffffff },
10739 { HOSTCC_STATUS_BLK_HOST_ADDR
+4, 0x0000,
10740 0x00000000, 0xffffffff },
10741 { HOSTCC_STATS_BLK_NIC_ADDR
, 0x0000,
10742 0xffffffff, 0x00000000 },
10743 { HOSTCC_STATUS_BLK_NIC_ADDR
, 0x0000,
10744 0xffffffff, 0x00000000 },
10746 /* Buffer Manager Control Registers. */
10747 { BUFMGR_MB_POOL_ADDR
, TG3_FL_NOT_5750
,
10748 0x00000000, 0x007fff80 },
10749 { BUFMGR_MB_POOL_SIZE
, TG3_FL_NOT_5750
,
10750 0x00000000, 0x007fffff },
10751 { BUFMGR_MB_RDMA_LOW_WATER
, 0x0000,
10752 0x00000000, 0x0000003f },
10753 { BUFMGR_MB_MACRX_LOW_WATER
, 0x0000,
10754 0x00000000, 0x000001ff },
10755 { BUFMGR_MB_HIGH_WATER
, 0x0000,
10756 0x00000000, 0x000001ff },
10757 { BUFMGR_DMA_DESC_POOL_ADDR
, TG3_FL_NOT_5705
,
10758 0xffffffff, 0x00000000 },
10759 { BUFMGR_DMA_DESC_POOL_SIZE
, TG3_FL_NOT_5705
,
10760 0xffffffff, 0x00000000 },
10762 /* Mailbox Registers */
10763 { GRCMBOX_RCVSTD_PROD_IDX
+4, 0x0000,
10764 0x00000000, 0x000001ff },
10765 { GRCMBOX_RCVJUMBO_PROD_IDX
+4, TG3_FL_NOT_5705
,
10766 0x00000000, 0x000001ff },
10767 { GRCMBOX_RCVRET_CON_IDX_0
+4, 0x0000,
10768 0x00000000, 0x000007ff },
10769 { GRCMBOX_SNDHOST_PROD_IDX_0
+4, 0x0000,
10770 0x00000000, 0x000001ff },
10772 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10775 is_5705
= is_5750
= 0;
10776 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
10778 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
10782 for (i
= 0; reg_tbl
[i
].offset
!= 0xffff; i
++) {
10783 if (is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5705
))
10786 if (!is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_5705
))
10789 if ((tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
10790 (reg_tbl
[i
].flags
& TG3_FL_NOT_5788
))
10793 if (is_5750
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5750
))
10796 offset
= (u32
) reg_tbl
[i
].offset
;
10797 read_mask
= reg_tbl
[i
].read_mask
;
10798 write_mask
= reg_tbl
[i
].write_mask
;
10800 /* Save the original register content */
10801 save_val
= tr32(offset
);
10803 /* Determine the read-only value. */
10804 read_val
= save_val
& read_mask
;
10806 /* Write zero to the register, then make sure the read-only bits
10807 * are not changed and the read/write bits are all zeros.
10811 val
= tr32(offset
);
10813 /* Test the read-only and read/write bits. */
10814 if (((val
& read_mask
) != read_val
) || (val
& write_mask
))
10817 /* Write ones to all the bits defined by RdMask and WrMask, then
10818 * make sure the read-only bits are not changed and the
10819 * read/write bits are all ones.
10821 tw32(offset
, read_mask
| write_mask
);
10823 val
= tr32(offset
);
10825 /* Test the read-only bits. */
10826 if ((val
& read_mask
) != read_val
)
10829 /* Test the read/write bits. */
10830 if ((val
& write_mask
) != write_mask
)
10833 tw32(offset
, save_val
);
10839 if (netif_msg_hw(tp
))
10840 netdev_err(tp
->dev
,
10841 "Register test failed at offset %x\n", offset
);
10842 tw32(offset
, save_val
);
10846 static int tg3_do_mem_test(struct tg3
*tp
, u32 offset
, u32 len
)
10848 static const u32 test_pattern
[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10852 for (i
= 0; i
< ARRAY_SIZE(test_pattern
); i
++) {
10853 for (j
= 0; j
< len
; j
+= 4) {
10856 tg3_write_mem(tp
, offset
+ j
, test_pattern
[i
]);
10857 tg3_read_mem(tp
, offset
+ j
, &val
);
10858 if (val
!= test_pattern
[i
])
10865 static int tg3_test_memory(struct tg3
*tp
)
10867 static struct mem_entry
{
10870 } mem_tbl_570x
[] = {
10871 { 0x00000000, 0x00b50},
10872 { 0x00002000, 0x1c000},
10873 { 0xffffffff, 0x00000}
10874 }, mem_tbl_5705
[] = {
10875 { 0x00000100, 0x0000c},
10876 { 0x00000200, 0x00008},
10877 { 0x00004000, 0x00800},
10878 { 0x00006000, 0x01000},
10879 { 0x00008000, 0x02000},
10880 { 0x00010000, 0x0e000},
10881 { 0xffffffff, 0x00000}
10882 }, mem_tbl_5755
[] = {
10883 { 0x00000200, 0x00008},
10884 { 0x00004000, 0x00800},
10885 { 0x00006000, 0x00800},
10886 { 0x00008000, 0x02000},
10887 { 0x00010000, 0x0c000},
10888 { 0xffffffff, 0x00000}
10889 }, mem_tbl_5906
[] = {
10890 { 0x00000200, 0x00008},
10891 { 0x00004000, 0x00400},
10892 { 0x00006000, 0x00400},
10893 { 0x00008000, 0x01000},
10894 { 0x00010000, 0x01000},
10895 { 0xffffffff, 0x00000}
10896 }, mem_tbl_5717
[] = {
10897 { 0x00000200, 0x00008},
10898 { 0x00010000, 0x0a000},
10899 { 0x00020000, 0x13c00},
10900 { 0xffffffff, 0x00000}
10901 }, mem_tbl_57765
[] = {
10902 { 0x00000200, 0x00008},
10903 { 0x00004000, 0x00800},
10904 { 0x00006000, 0x09800},
10905 { 0x00010000, 0x0a000},
10906 { 0xffffffff, 0x00000}
10908 struct mem_entry
*mem_tbl
;
10912 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)
10913 mem_tbl
= mem_tbl_5717
;
10914 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
10915 mem_tbl
= mem_tbl_57765
;
10916 else if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
10917 mem_tbl
= mem_tbl_5755
;
10918 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
10919 mem_tbl
= mem_tbl_5906
;
10920 else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
10921 mem_tbl
= mem_tbl_5705
;
10923 mem_tbl
= mem_tbl_570x
;
10925 for (i
= 0; mem_tbl
[i
].offset
!= 0xffffffff; i
++) {
10926 err
= tg3_do_mem_test(tp
, mem_tbl
[i
].offset
, mem_tbl
[i
].len
);
10934 #define TG3_MAC_LOOPBACK 0
10935 #define TG3_PHY_LOOPBACK 1
10937 static int tg3_run_loopback(struct tg3
*tp
, int loopback_mode
)
10939 u32 mac_mode
, rx_start_idx
, rx_idx
, tx_idx
, opaque_key
;
10940 u32 desc_idx
, coal_now
;
10941 struct sk_buff
*skb
, *rx_skb
;
10944 int num_pkts
, tx_len
, rx_len
, i
, err
;
10945 struct tg3_rx_buffer_desc
*desc
;
10946 struct tg3_napi
*tnapi
, *rnapi
;
10947 struct tg3_rx_prodring_set
*tpr
= &tp
->napi
[0].prodring
;
10949 tnapi
= &tp
->napi
[0];
10950 rnapi
= &tp
->napi
[0];
10951 if (tp
->irq_cnt
> 1) {
10952 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)
10953 rnapi
= &tp
->napi
[1];
10954 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
10955 tnapi
= &tp
->napi
[1];
10957 coal_now
= tnapi
->coal_now
| rnapi
->coal_now
;
10959 if (loopback_mode
== TG3_MAC_LOOPBACK
) {
10960 /* HW errata - mac loopback fails in some cases on 5780.
10961 * Normal traffic and PHY loopback are not affected by
10962 * errata. Also, the MAC loopback test is deprecated for
10963 * all newer ASIC revisions.
10965 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
||
10966 (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
))
10969 mac_mode
= tp
->mac_mode
&
10970 ~(MAC_MODE_PORT_MODE_MASK
| MAC_MODE_HALF_DUPLEX
);
10971 mac_mode
|= MAC_MODE_PORT_INT_LPBACK
;
10972 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
10973 mac_mode
|= MAC_MODE_LINK_POLARITY
;
10974 if (tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)
10975 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
10977 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
10978 tw32(MAC_MODE
, mac_mode
);
10979 } else if (loopback_mode
== TG3_PHY_LOOPBACK
) {
10982 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
10983 tg3_phy_fet_toggle_apd(tp
, false);
10984 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED100
;
10986 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED1000
;
10988 tg3_phy_toggle_automdix(tp
, 0);
10990 tg3_writephy(tp
, MII_BMCR
, val
);
10993 mac_mode
= tp
->mac_mode
&
10994 ~(MAC_MODE_PORT_MODE_MASK
| MAC_MODE_HALF_DUPLEX
);
10995 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
10996 tg3_writephy(tp
, MII_TG3_FET_PTEST
,
10997 MII_TG3_FET_PTEST_FRC_TX_LINK
|
10998 MII_TG3_FET_PTEST_FRC_TX_LOCK
);
10999 /* The write needs to be flushed for the AC131 */
11000 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
11001 tg3_readphy(tp
, MII_TG3_FET_PTEST
, &val
);
11002 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
11004 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
11006 /* reset to prevent losing 1st rx packet intermittently */
11007 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) {
11008 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
11010 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
11012 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
11013 u32 masked_phy_id
= tp
->phy_id
& TG3_PHY_ID_MASK
;
11014 if (masked_phy_id
== TG3_PHY_ID_BCM5401
)
11015 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
11016 else if (masked_phy_id
== TG3_PHY_ID_BCM5411
)
11017 mac_mode
|= MAC_MODE_LINK_POLARITY
;
11018 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
11019 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
11021 tw32(MAC_MODE
, mac_mode
);
11023 /* Wait for link */
11024 for (i
= 0; i
< 100; i
++) {
11025 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
11036 skb
= netdev_alloc_skb(tp
->dev
, tx_len
);
11040 tx_data
= skb_put(skb
, tx_len
);
11041 memcpy(tx_data
, tp
->dev
->dev_addr
, 6);
11042 memset(tx_data
+ 6, 0x0, 8);
11044 tw32(MAC_RX_MTU_SIZE
, tx_len
+ 4);
11046 for (i
= 14; i
< tx_len
; i
++)
11047 tx_data
[i
] = (u8
) (i
& 0xff);
11049 map
= pci_map_single(tp
->pdev
, skb
->data
, tx_len
, PCI_DMA_TODEVICE
);
11050 if (pci_dma_mapping_error(tp
->pdev
, map
)) {
11051 dev_kfree_skb(skb
);
11055 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
11060 rx_start_idx
= rnapi
->hw_status
->idx
[0].rx_producer
;
11064 tg3_set_txd(tnapi
, tnapi
->tx_prod
, map
, tx_len
, 0, 1);
11069 tw32_tx_mbox(tnapi
->prodmbox
, tnapi
->tx_prod
);
11070 tr32_mailbox(tnapi
->prodmbox
);
11074 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
11075 for (i
= 0; i
< 35; i
++) {
11076 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
11081 tx_idx
= tnapi
->hw_status
->idx
[0].tx_consumer
;
11082 rx_idx
= rnapi
->hw_status
->idx
[0].rx_producer
;
11083 if ((tx_idx
== tnapi
->tx_prod
) &&
11084 (rx_idx
== (rx_start_idx
+ num_pkts
)))
11088 pci_unmap_single(tp
->pdev
, map
, tx_len
, PCI_DMA_TODEVICE
);
11089 dev_kfree_skb(skb
);
11091 if (tx_idx
!= tnapi
->tx_prod
)
11094 if (rx_idx
!= rx_start_idx
+ num_pkts
)
11097 desc
= &rnapi
->rx_rcb
[rx_start_idx
];
11098 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
11099 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
11100 if (opaque_key
!= RXD_OPAQUE_RING_STD
)
11103 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
11104 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
))
11107 rx_len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) - 4;
11108 if (rx_len
!= tx_len
)
11111 rx_skb
= tpr
->rx_std_buffers
[desc_idx
].skb
;
11113 map
= dma_unmap_addr(&tpr
->rx_std_buffers
[desc_idx
], mapping
);
11114 pci_dma_sync_single_for_cpu(tp
->pdev
, map
, rx_len
, PCI_DMA_FROMDEVICE
);
11116 for (i
= 14; i
< tx_len
; i
++) {
11117 if (*(rx_skb
->data
+ i
) != (u8
) (i
& 0xff))
11122 /* tg3_free_rings will unmap and free the rx_skb */
11127 #define TG3_MAC_LOOPBACK_FAILED 1
11128 #define TG3_PHY_LOOPBACK_FAILED 2
11129 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
11130 TG3_PHY_LOOPBACK_FAILED)
11132 static int tg3_test_loopback(struct tg3
*tp
)
11135 u32 eee_cap
, cpmuctrl
= 0;
11137 if (!netif_running(tp
->dev
))
11138 return TG3_LOOPBACK_FAILED
;
11140 eee_cap
= tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
;
11141 tp
->phy_flags
&= ~TG3_PHYFLG_EEE_CAP
;
11143 err
= tg3_reset_hw(tp
, 1);
11145 err
= TG3_LOOPBACK_FAILED
;
11149 /* Turn off gphy autopowerdown. */
11150 if (tp
->phy_flags
& TG3_PHYFLG_ENABLE_APD
)
11151 tg3_phy_toggle_apd(tp
, false);
11153 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
11157 tw32(TG3_CPMU_MUTEX_REQ
, CPMU_MUTEX_REQ_DRIVER
);
11159 /* Wait for up to 40 microseconds to acquire lock. */
11160 for (i
= 0; i
< 4; i
++) {
11161 status
= tr32(TG3_CPMU_MUTEX_GNT
);
11162 if (status
== CPMU_MUTEX_GNT_DRIVER
)
11167 if (status
!= CPMU_MUTEX_GNT_DRIVER
) {
11168 err
= TG3_LOOPBACK_FAILED
;
11172 /* Turn off link-based power management. */
11173 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
11174 tw32(TG3_CPMU_CTRL
,
11175 cpmuctrl
& ~(CPMU_CTRL_LINK_SPEED_MODE
|
11176 CPMU_CTRL_LINK_AWARE_MODE
));
11179 if (tg3_run_loopback(tp
, TG3_MAC_LOOPBACK
))
11180 err
|= TG3_MAC_LOOPBACK_FAILED
;
11182 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
11183 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
11185 /* Release the mutex */
11186 tw32(TG3_CPMU_MUTEX_GNT
, CPMU_MUTEX_GNT_DRIVER
);
11189 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
11190 !(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
11191 if (tg3_run_loopback(tp
, TG3_PHY_LOOPBACK
))
11192 err
|= TG3_PHY_LOOPBACK_FAILED
;
11195 /* Re-enable gphy autopowerdown. */
11196 if (tp
->phy_flags
& TG3_PHYFLG_ENABLE_APD
)
11197 tg3_phy_toggle_apd(tp
, true);
11200 tp
->phy_flags
|= eee_cap
;
11205 static void tg3_self_test(struct net_device
*dev
, struct ethtool_test
*etest
,
11208 struct tg3
*tp
= netdev_priv(dev
);
11210 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
11213 memset(data
, 0, sizeof(u64
) * TG3_NUM_TEST
);
11215 if (tg3_test_nvram(tp
) != 0) {
11216 etest
->flags
|= ETH_TEST_FL_FAILED
;
11219 if (tg3_test_link(tp
) != 0) {
11220 etest
->flags
|= ETH_TEST_FL_FAILED
;
11223 if (etest
->flags
& ETH_TEST_FL_OFFLINE
) {
11224 int err
, err2
= 0, irq_sync
= 0;
11226 if (netif_running(dev
)) {
11228 tg3_netif_stop(tp
);
11232 tg3_full_lock(tp
, irq_sync
);
11234 tg3_halt(tp
, RESET_KIND_SUSPEND
, 1);
11235 err
= tg3_nvram_lock(tp
);
11236 tg3_halt_cpu(tp
, RX_CPU_BASE
);
11237 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
11238 tg3_halt_cpu(tp
, TX_CPU_BASE
);
11240 tg3_nvram_unlock(tp
);
11242 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)
11245 if (tg3_test_registers(tp
) != 0) {
11246 etest
->flags
|= ETH_TEST_FL_FAILED
;
11249 if (tg3_test_memory(tp
) != 0) {
11250 etest
->flags
|= ETH_TEST_FL_FAILED
;
11253 if ((data
[4] = tg3_test_loopback(tp
)) != 0)
11254 etest
->flags
|= ETH_TEST_FL_FAILED
;
11256 tg3_full_unlock(tp
);
11258 if (tg3_test_interrupt(tp
) != 0) {
11259 etest
->flags
|= ETH_TEST_FL_FAILED
;
11263 tg3_full_lock(tp
, 0);
11265 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
11266 if (netif_running(dev
)) {
11267 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
11268 err2
= tg3_restart_hw(tp
, 1);
11270 tg3_netif_start(tp
);
11273 tg3_full_unlock(tp
);
11275 if (irq_sync
&& !err2
)
11278 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
11279 tg3_power_down(tp
);
11283 static int tg3_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
11285 struct mii_ioctl_data
*data
= if_mii(ifr
);
11286 struct tg3
*tp
= netdev_priv(dev
);
11289 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
11290 struct phy_device
*phydev
;
11291 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
11293 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
11294 return phy_mii_ioctl(phydev
, ifr
, cmd
);
11299 data
->phy_id
= tp
->phy_addr
;
11302 case SIOCGMIIREG
: {
11305 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
11306 break; /* We have no PHY */
11308 if ((tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
) ||
11309 ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
11310 !netif_running(dev
)))
11313 spin_lock_bh(&tp
->lock
);
11314 err
= tg3_readphy(tp
, data
->reg_num
& 0x1f, &mii_regval
);
11315 spin_unlock_bh(&tp
->lock
);
11317 data
->val_out
= mii_regval
;
11323 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
11324 break; /* We have no PHY */
11326 if ((tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
) ||
11327 ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
11328 !netif_running(dev
)))
11331 spin_lock_bh(&tp
->lock
);
11332 err
= tg3_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
11333 spin_unlock_bh(&tp
->lock
);
11341 return -EOPNOTSUPP
;
11344 static int tg3_get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
11346 struct tg3
*tp
= netdev_priv(dev
);
11348 memcpy(ec
, &tp
->coal
, sizeof(*ec
));
11352 static int tg3_set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
11354 struct tg3
*tp
= netdev_priv(dev
);
11355 u32 max_rxcoal_tick_int
= 0, max_txcoal_tick_int
= 0;
11356 u32 max_stat_coal_ticks
= 0, min_stat_coal_ticks
= 0;
11358 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
11359 max_rxcoal_tick_int
= MAX_RXCOAL_TICK_INT
;
11360 max_txcoal_tick_int
= MAX_TXCOAL_TICK_INT
;
11361 max_stat_coal_ticks
= MAX_STAT_COAL_TICKS
;
11362 min_stat_coal_ticks
= MIN_STAT_COAL_TICKS
;
11365 if ((ec
->rx_coalesce_usecs
> MAX_RXCOL_TICKS
) ||
11366 (ec
->tx_coalesce_usecs
> MAX_TXCOL_TICKS
) ||
11367 (ec
->rx_max_coalesced_frames
> MAX_RXMAX_FRAMES
) ||
11368 (ec
->tx_max_coalesced_frames
> MAX_TXMAX_FRAMES
) ||
11369 (ec
->rx_coalesce_usecs_irq
> max_rxcoal_tick_int
) ||
11370 (ec
->tx_coalesce_usecs_irq
> max_txcoal_tick_int
) ||
11371 (ec
->rx_max_coalesced_frames_irq
> MAX_RXCOAL_MAXF_INT
) ||
11372 (ec
->tx_max_coalesced_frames_irq
> MAX_TXCOAL_MAXF_INT
) ||
11373 (ec
->stats_block_coalesce_usecs
> max_stat_coal_ticks
) ||
11374 (ec
->stats_block_coalesce_usecs
< min_stat_coal_ticks
))
11377 /* No rx interrupts will be generated if both are zero */
11378 if ((ec
->rx_coalesce_usecs
== 0) &&
11379 (ec
->rx_max_coalesced_frames
== 0))
11382 /* No tx interrupts will be generated if both are zero */
11383 if ((ec
->tx_coalesce_usecs
== 0) &&
11384 (ec
->tx_max_coalesced_frames
== 0))
11387 /* Only copy relevant parameters, ignore all others. */
11388 tp
->coal
.rx_coalesce_usecs
= ec
->rx_coalesce_usecs
;
11389 tp
->coal
.tx_coalesce_usecs
= ec
->tx_coalesce_usecs
;
11390 tp
->coal
.rx_max_coalesced_frames
= ec
->rx_max_coalesced_frames
;
11391 tp
->coal
.tx_max_coalesced_frames
= ec
->tx_max_coalesced_frames
;
11392 tp
->coal
.rx_coalesce_usecs_irq
= ec
->rx_coalesce_usecs_irq
;
11393 tp
->coal
.tx_coalesce_usecs_irq
= ec
->tx_coalesce_usecs_irq
;
11394 tp
->coal
.rx_max_coalesced_frames_irq
= ec
->rx_max_coalesced_frames_irq
;
11395 tp
->coal
.tx_max_coalesced_frames_irq
= ec
->tx_max_coalesced_frames_irq
;
11396 tp
->coal
.stats_block_coalesce_usecs
= ec
->stats_block_coalesce_usecs
;
11398 if (netif_running(dev
)) {
11399 tg3_full_lock(tp
, 0);
11400 __tg3_set_coalesce(tp
, &tp
->coal
);
11401 tg3_full_unlock(tp
);
11406 static const struct ethtool_ops tg3_ethtool_ops
= {
11407 .get_settings
= tg3_get_settings
,
11408 .set_settings
= tg3_set_settings
,
11409 .get_drvinfo
= tg3_get_drvinfo
,
11410 .get_regs_len
= tg3_get_regs_len
,
11411 .get_regs
= tg3_get_regs
,
11412 .get_wol
= tg3_get_wol
,
11413 .set_wol
= tg3_set_wol
,
11414 .get_msglevel
= tg3_get_msglevel
,
11415 .set_msglevel
= tg3_set_msglevel
,
11416 .nway_reset
= tg3_nway_reset
,
11417 .get_link
= ethtool_op_get_link
,
11418 .get_eeprom_len
= tg3_get_eeprom_len
,
11419 .get_eeprom
= tg3_get_eeprom
,
11420 .set_eeprom
= tg3_set_eeprom
,
11421 .get_ringparam
= tg3_get_ringparam
,
11422 .set_ringparam
= tg3_set_ringparam
,
11423 .get_pauseparam
= tg3_get_pauseparam
,
11424 .set_pauseparam
= tg3_set_pauseparam
,
11425 .self_test
= tg3_self_test
,
11426 .get_strings
= tg3_get_strings
,
11427 .set_phys_id
= tg3_set_phys_id
,
11428 .get_ethtool_stats
= tg3_get_ethtool_stats
,
11429 .get_coalesce
= tg3_get_coalesce
,
11430 .set_coalesce
= tg3_set_coalesce
,
11431 .get_sset_count
= tg3_get_sset_count
,
11434 static void __devinit
tg3_get_eeprom_size(struct tg3
*tp
)
11436 u32 cursize
, val
, magic
;
11438 tp
->nvram_size
= EEPROM_CHIP_SIZE
;
11440 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
11443 if ((magic
!= TG3_EEPROM_MAGIC
) &&
11444 ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) != TG3_EEPROM_MAGIC_FW
) &&
11445 ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) != TG3_EEPROM_MAGIC_HW
))
11449 * Size the chip by reading offsets at increasing powers of two.
11450 * When we encounter our validation signature, we know the addressing
11451 * has wrapped around, and thus have our chip size.
11455 while (cursize
< tp
->nvram_size
) {
11456 if (tg3_nvram_read(tp
, cursize
, &val
) != 0)
11465 tp
->nvram_size
= cursize
;
11468 static void __devinit
tg3_get_nvram_size(struct tg3
*tp
)
11472 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
11473 tg3_nvram_read(tp
, 0, &val
) != 0)
11476 /* Selfboot format */
11477 if (val
!= TG3_EEPROM_MAGIC
) {
11478 tg3_get_eeprom_size(tp
);
11482 if (tg3_nvram_read(tp
, 0xf0, &val
) == 0) {
11484 /* This is confusing. We want to operate on the
11485 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11486 * call will read from NVRAM and byteswap the data
11487 * according to the byteswapping settings for all
11488 * other register accesses. This ensures the data we
11489 * want will always reside in the lower 16-bits.
11490 * However, the data in NVRAM is in LE format, which
11491 * means the data from the NVRAM read will always be
11492 * opposite the endianness of the CPU. The 16-bit
11493 * byteswap then brings the data to CPU endianness.
11495 tp
->nvram_size
= swab16((u16
)(val
& 0x0000ffff)) * 1024;
11499 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11502 static void __devinit
tg3_get_nvram_info(struct tg3
*tp
)
11506 nvcfg1
= tr32(NVRAM_CFG1
);
11507 if (nvcfg1
& NVRAM_CFG1_FLASHIF_ENAB
) {
11508 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11510 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11511 tw32(NVRAM_CFG1
, nvcfg1
);
11514 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) ||
11515 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
11516 switch (nvcfg1
& NVRAM_CFG1_VENDOR_MASK
) {
11517 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED
:
11518 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11519 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
11520 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11522 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED
:
11523 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11524 tp
->nvram_pagesize
= ATMEL_AT25F512_PAGE_SIZE
;
11526 case FLASH_VENDOR_ATMEL_EEPROM
:
11527 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11528 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11529 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11531 case FLASH_VENDOR_ST
:
11532 tp
->nvram_jedecnum
= JEDEC_ST
;
11533 tp
->nvram_pagesize
= ST_M45PEX0_PAGE_SIZE
;
11534 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11536 case FLASH_VENDOR_SAIFUN
:
11537 tp
->nvram_jedecnum
= JEDEC_SAIFUN
;
11538 tp
->nvram_pagesize
= SAIFUN_SA25F0XX_PAGE_SIZE
;
11540 case FLASH_VENDOR_SST_SMALL
:
11541 case FLASH_VENDOR_SST_LARGE
:
11542 tp
->nvram_jedecnum
= JEDEC_SST
;
11543 tp
->nvram_pagesize
= SST_25VF0X0_PAGE_SIZE
;
11547 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11548 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
11549 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11553 static void __devinit
tg3_nvram_get_pagesize(struct tg3
*tp
, u32 nvmcfg1
)
11555 switch (nvmcfg1
& NVRAM_CFG1_5752PAGE_SIZE_MASK
) {
11556 case FLASH_5752PAGE_SIZE_256
:
11557 tp
->nvram_pagesize
= 256;
11559 case FLASH_5752PAGE_SIZE_512
:
11560 tp
->nvram_pagesize
= 512;
11562 case FLASH_5752PAGE_SIZE_1K
:
11563 tp
->nvram_pagesize
= 1024;
11565 case FLASH_5752PAGE_SIZE_2K
:
11566 tp
->nvram_pagesize
= 2048;
11568 case FLASH_5752PAGE_SIZE_4K
:
11569 tp
->nvram_pagesize
= 4096;
11571 case FLASH_5752PAGE_SIZE_264
:
11572 tp
->nvram_pagesize
= 264;
11574 case FLASH_5752PAGE_SIZE_528
:
11575 tp
->nvram_pagesize
= 528;
11580 static void __devinit
tg3_get_5752_nvram_info(struct tg3
*tp
)
11584 nvcfg1
= tr32(NVRAM_CFG1
);
11586 /* NVRAM protection for TPM */
11587 if (nvcfg1
& (1 << 27))
11588 tp
->tg3_flags3
|= TG3_FLG3_PROTECTED_NVRAM
;
11590 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11591 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ
:
11592 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ
:
11593 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11594 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11596 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11597 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11598 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11599 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11601 case FLASH_5752VENDOR_ST_M45PE10
:
11602 case FLASH_5752VENDOR_ST_M45PE20
:
11603 case FLASH_5752VENDOR_ST_M45PE40
:
11604 tp
->nvram_jedecnum
= JEDEC_ST
;
11605 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11606 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11610 if (tp
->tg3_flags2
& TG3_FLG2_FLASH
) {
11611 tg3_nvram_get_pagesize(tp
, nvcfg1
);
11613 /* For eeprom, set pagesize to maximum eeprom size */
11614 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11616 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11617 tw32(NVRAM_CFG1
, nvcfg1
);
11621 static void __devinit
tg3_get_5755_nvram_info(struct tg3
*tp
)
11623 u32 nvcfg1
, protect
= 0;
11625 nvcfg1
= tr32(NVRAM_CFG1
);
11627 /* NVRAM protection for TPM */
11628 if (nvcfg1
& (1 << 27)) {
11629 tp
->tg3_flags3
|= TG3_FLG3_PROTECTED_NVRAM
;
11633 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
11635 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
11636 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
11637 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
11638 case FLASH_5755VENDOR_ATMEL_FLASH_5
:
11639 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11640 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11641 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11642 tp
->nvram_pagesize
= 264;
11643 if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_1
||
11644 nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_5
)
11645 tp
->nvram_size
= (protect
? 0x3e200 :
11646 TG3_NVRAM_SIZE_512KB
);
11647 else if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_2
)
11648 tp
->nvram_size
= (protect
? 0x1f200 :
11649 TG3_NVRAM_SIZE_256KB
);
11651 tp
->nvram_size
= (protect
? 0x1f200 :
11652 TG3_NVRAM_SIZE_128KB
);
11654 case FLASH_5752VENDOR_ST_M45PE10
:
11655 case FLASH_5752VENDOR_ST_M45PE20
:
11656 case FLASH_5752VENDOR_ST_M45PE40
:
11657 tp
->nvram_jedecnum
= JEDEC_ST
;
11658 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11659 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11660 tp
->nvram_pagesize
= 256;
11661 if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE10
)
11662 tp
->nvram_size
= (protect
?
11663 TG3_NVRAM_SIZE_64KB
:
11664 TG3_NVRAM_SIZE_128KB
);
11665 else if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE20
)
11666 tp
->nvram_size
= (protect
?
11667 TG3_NVRAM_SIZE_64KB
:
11668 TG3_NVRAM_SIZE_256KB
);
11670 tp
->nvram_size
= (protect
?
11671 TG3_NVRAM_SIZE_128KB
:
11672 TG3_NVRAM_SIZE_512KB
);
11677 static void __devinit
tg3_get_5787_nvram_info(struct tg3
*tp
)
11681 nvcfg1
= tr32(NVRAM_CFG1
);
11683 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11684 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ
:
11685 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
11686 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ
:
11687 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
11688 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11689 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11690 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11692 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11693 tw32(NVRAM_CFG1
, nvcfg1
);
11695 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11696 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
11697 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
11698 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
11699 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11700 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11701 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11702 tp
->nvram_pagesize
= 264;
11704 case FLASH_5752VENDOR_ST_M45PE10
:
11705 case FLASH_5752VENDOR_ST_M45PE20
:
11706 case FLASH_5752VENDOR_ST_M45PE40
:
11707 tp
->nvram_jedecnum
= JEDEC_ST
;
11708 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11709 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11710 tp
->nvram_pagesize
= 256;
11715 static void __devinit
tg3_get_5761_nvram_info(struct tg3
*tp
)
11717 u32 nvcfg1
, protect
= 0;
11719 nvcfg1
= tr32(NVRAM_CFG1
);
11721 /* NVRAM protection for TPM */
11722 if (nvcfg1
& (1 << 27)) {
11723 tp
->tg3_flags3
|= TG3_FLG3_PROTECTED_NVRAM
;
11727 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
11729 case FLASH_5761VENDOR_ATMEL_ADB021D
:
11730 case FLASH_5761VENDOR_ATMEL_ADB041D
:
11731 case FLASH_5761VENDOR_ATMEL_ADB081D
:
11732 case FLASH_5761VENDOR_ATMEL_ADB161D
:
11733 case FLASH_5761VENDOR_ATMEL_MDB021D
:
11734 case FLASH_5761VENDOR_ATMEL_MDB041D
:
11735 case FLASH_5761VENDOR_ATMEL_MDB081D
:
11736 case FLASH_5761VENDOR_ATMEL_MDB161D
:
11737 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11738 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11739 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11740 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
11741 tp
->nvram_pagesize
= 256;
11743 case FLASH_5761VENDOR_ST_A_M45PE20
:
11744 case FLASH_5761VENDOR_ST_A_M45PE40
:
11745 case FLASH_5761VENDOR_ST_A_M45PE80
:
11746 case FLASH_5761VENDOR_ST_A_M45PE16
:
11747 case FLASH_5761VENDOR_ST_M_M45PE20
:
11748 case FLASH_5761VENDOR_ST_M_M45PE40
:
11749 case FLASH_5761VENDOR_ST_M_M45PE80
:
11750 case FLASH_5761VENDOR_ST_M_M45PE16
:
11751 tp
->nvram_jedecnum
= JEDEC_ST
;
11752 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11753 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11754 tp
->nvram_pagesize
= 256;
11759 tp
->nvram_size
= tr32(NVRAM_ADDR_LOCKOUT
);
11762 case FLASH_5761VENDOR_ATMEL_ADB161D
:
11763 case FLASH_5761VENDOR_ATMEL_MDB161D
:
11764 case FLASH_5761VENDOR_ST_A_M45PE16
:
11765 case FLASH_5761VENDOR_ST_M_M45PE16
:
11766 tp
->nvram_size
= TG3_NVRAM_SIZE_2MB
;
11768 case FLASH_5761VENDOR_ATMEL_ADB081D
:
11769 case FLASH_5761VENDOR_ATMEL_MDB081D
:
11770 case FLASH_5761VENDOR_ST_A_M45PE80
:
11771 case FLASH_5761VENDOR_ST_M_M45PE80
:
11772 tp
->nvram_size
= TG3_NVRAM_SIZE_1MB
;
11774 case FLASH_5761VENDOR_ATMEL_ADB041D
:
11775 case FLASH_5761VENDOR_ATMEL_MDB041D
:
11776 case FLASH_5761VENDOR_ST_A_M45PE40
:
11777 case FLASH_5761VENDOR_ST_M_M45PE40
:
11778 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11780 case FLASH_5761VENDOR_ATMEL_ADB021D
:
11781 case FLASH_5761VENDOR_ATMEL_MDB021D
:
11782 case FLASH_5761VENDOR_ST_A_M45PE20
:
11783 case FLASH_5761VENDOR_ST_M_M45PE20
:
11784 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11790 static void __devinit
tg3_get_5906_nvram_info(struct tg3
*tp
)
11792 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11793 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11794 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11797 static void __devinit
tg3_get_57780_nvram_info(struct tg3
*tp
)
11801 nvcfg1
= tr32(NVRAM_CFG1
);
11803 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11804 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
11805 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
11806 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11807 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11808 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11810 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11811 tw32(NVRAM_CFG1
, nvcfg1
);
11813 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11814 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
11815 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
11816 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
11817 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
11818 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
11819 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
11820 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11821 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11822 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11824 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11825 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11826 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
11827 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
11828 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11830 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
11831 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
11832 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11834 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
11835 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
11836 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11840 case FLASH_5752VENDOR_ST_M45PE10
:
11841 case FLASH_5752VENDOR_ST_M45PE20
:
11842 case FLASH_5752VENDOR_ST_M45PE40
:
11843 tp
->nvram_jedecnum
= JEDEC_ST
;
11844 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11845 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11847 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11848 case FLASH_5752VENDOR_ST_M45PE10
:
11849 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11851 case FLASH_5752VENDOR_ST_M45PE20
:
11852 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11854 case FLASH_5752VENDOR_ST_M45PE40
:
11855 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11860 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM
;
11864 tg3_nvram_get_pagesize(tp
, nvcfg1
);
11865 if (tp
->nvram_pagesize
!= 264 && tp
->nvram_pagesize
!= 528)
11866 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
11870 static void __devinit
tg3_get_5717_nvram_info(struct tg3
*tp
)
11874 nvcfg1
= tr32(NVRAM_CFG1
);
11876 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11877 case FLASH_5717VENDOR_ATMEL_EEPROM
:
11878 case FLASH_5717VENDOR_MICRO_EEPROM
:
11879 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11880 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11881 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11883 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11884 tw32(NVRAM_CFG1
, nvcfg1
);
11886 case FLASH_5717VENDOR_ATMEL_MDB011D
:
11887 case FLASH_5717VENDOR_ATMEL_ADB011B
:
11888 case FLASH_5717VENDOR_ATMEL_ADB011D
:
11889 case FLASH_5717VENDOR_ATMEL_MDB021D
:
11890 case FLASH_5717VENDOR_ATMEL_ADB021B
:
11891 case FLASH_5717VENDOR_ATMEL_ADB021D
:
11892 case FLASH_5717VENDOR_ATMEL_45USPT
:
11893 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11894 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11895 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11897 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11898 case FLASH_5717VENDOR_ATMEL_MDB021D
:
11899 /* Detect size with tg3_nvram_get_size() */
11901 case FLASH_5717VENDOR_ATMEL_ADB021B
:
11902 case FLASH_5717VENDOR_ATMEL_ADB021D
:
11903 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11906 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11910 case FLASH_5717VENDOR_ST_M_M25PE10
:
11911 case FLASH_5717VENDOR_ST_A_M25PE10
:
11912 case FLASH_5717VENDOR_ST_M_M45PE10
:
11913 case FLASH_5717VENDOR_ST_A_M45PE10
:
11914 case FLASH_5717VENDOR_ST_M_M25PE20
:
11915 case FLASH_5717VENDOR_ST_A_M25PE20
:
11916 case FLASH_5717VENDOR_ST_M_M45PE20
:
11917 case FLASH_5717VENDOR_ST_A_M45PE20
:
11918 case FLASH_5717VENDOR_ST_25USPT
:
11919 case FLASH_5717VENDOR_ST_45USPT
:
11920 tp
->nvram_jedecnum
= JEDEC_ST
;
11921 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11922 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11924 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11925 case FLASH_5717VENDOR_ST_M_M25PE20
:
11926 case FLASH_5717VENDOR_ST_M_M45PE20
:
11927 /* Detect size with tg3_nvram_get_size() */
11929 case FLASH_5717VENDOR_ST_A_M25PE20
:
11930 case FLASH_5717VENDOR_ST_A_M45PE20
:
11931 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11934 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11939 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM
;
11943 tg3_nvram_get_pagesize(tp
, nvcfg1
);
11944 if (tp
->nvram_pagesize
!= 264 && tp
->nvram_pagesize
!= 528)
11945 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
11948 static void __devinit
tg3_get_5720_nvram_info(struct tg3
*tp
)
11950 u32 nvcfg1
, nvmpinstrp
;
11952 nvcfg1
= tr32(NVRAM_CFG1
);
11953 nvmpinstrp
= nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
;
11955 switch (nvmpinstrp
) {
11956 case FLASH_5720_EEPROM_HD
:
11957 case FLASH_5720_EEPROM_LD
:
11958 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11959 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11961 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11962 tw32(NVRAM_CFG1
, nvcfg1
);
11963 if (nvmpinstrp
== FLASH_5720_EEPROM_HD
)
11964 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11966 tp
->nvram_pagesize
= ATMEL_AT24C02_CHIP_SIZE
;
11968 case FLASH_5720VENDOR_M_ATMEL_DB011D
:
11969 case FLASH_5720VENDOR_A_ATMEL_DB011B
:
11970 case FLASH_5720VENDOR_A_ATMEL_DB011D
:
11971 case FLASH_5720VENDOR_M_ATMEL_DB021D
:
11972 case FLASH_5720VENDOR_A_ATMEL_DB021B
:
11973 case FLASH_5720VENDOR_A_ATMEL_DB021D
:
11974 case FLASH_5720VENDOR_M_ATMEL_DB041D
:
11975 case FLASH_5720VENDOR_A_ATMEL_DB041B
:
11976 case FLASH_5720VENDOR_A_ATMEL_DB041D
:
11977 case FLASH_5720VENDOR_M_ATMEL_DB081D
:
11978 case FLASH_5720VENDOR_A_ATMEL_DB081D
:
11979 case FLASH_5720VENDOR_ATMEL_45USPT
:
11980 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11981 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11982 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11984 switch (nvmpinstrp
) {
11985 case FLASH_5720VENDOR_M_ATMEL_DB021D
:
11986 case FLASH_5720VENDOR_A_ATMEL_DB021B
:
11987 case FLASH_5720VENDOR_A_ATMEL_DB021D
:
11988 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11990 case FLASH_5720VENDOR_M_ATMEL_DB041D
:
11991 case FLASH_5720VENDOR_A_ATMEL_DB041B
:
11992 case FLASH_5720VENDOR_A_ATMEL_DB041D
:
11993 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11995 case FLASH_5720VENDOR_M_ATMEL_DB081D
:
11996 case FLASH_5720VENDOR_A_ATMEL_DB081D
:
11997 tp
->nvram_size
= TG3_NVRAM_SIZE_1MB
;
12000 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
12004 case FLASH_5720VENDOR_M_ST_M25PE10
:
12005 case FLASH_5720VENDOR_M_ST_M45PE10
:
12006 case FLASH_5720VENDOR_A_ST_M25PE10
:
12007 case FLASH_5720VENDOR_A_ST_M45PE10
:
12008 case FLASH_5720VENDOR_M_ST_M25PE20
:
12009 case FLASH_5720VENDOR_M_ST_M45PE20
:
12010 case FLASH_5720VENDOR_A_ST_M25PE20
:
12011 case FLASH_5720VENDOR_A_ST_M45PE20
:
12012 case FLASH_5720VENDOR_M_ST_M25PE40
:
12013 case FLASH_5720VENDOR_M_ST_M45PE40
:
12014 case FLASH_5720VENDOR_A_ST_M25PE40
:
12015 case FLASH_5720VENDOR_A_ST_M45PE40
:
12016 case FLASH_5720VENDOR_M_ST_M25PE80
:
12017 case FLASH_5720VENDOR_M_ST_M45PE80
:
12018 case FLASH_5720VENDOR_A_ST_M25PE80
:
12019 case FLASH_5720VENDOR_A_ST_M45PE80
:
12020 case FLASH_5720VENDOR_ST_25USPT
:
12021 case FLASH_5720VENDOR_ST_45USPT
:
12022 tp
->nvram_jedecnum
= JEDEC_ST
;
12023 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
12024 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
12026 switch (nvmpinstrp
) {
12027 case FLASH_5720VENDOR_M_ST_M25PE20
:
12028 case FLASH_5720VENDOR_M_ST_M45PE20
:
12029 case FLASH_5720VENDOR_A_ST_M25PE20
:
12030 case FLASH_5720VENDOR_A_ST_M45PE20
:
12031 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
12033 case FLASH_5720VENDOR_M_ST_M25PE40
:
12034 case FLASH_5720VENDOR_M_ST_M45PE40
:
12035 case FLASH_5720VENDOR_A_ST_M25PE40
:
12036 case FLASH_5720VENDOR_A_ST_M45PE40
:
12037 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
12039 case FLASH_5720VENDOR_M_ST_M25PE80
:
12040 case FLASH_5720VENDOR_M_ST_M45PE80
:
12041 case FLASH_5720VENDOR_A_ST_M25PE80
:
12042 case FLASH_5720VENDOR_A_ST_M45PE80
:
12043 tp
->nvram_size
= TG3_NVRAM_SIZE_1MB
;
12046 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
12051 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM
;
12055 tg3_nvram_get_pagesize(tp
, nvcfg1
);
12056 if (tp
->nvram_pagesize
!= 264 && tp
->nvram_pagesize
!= 528)
12057 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
12060 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
12061 static void __devinit
tg3_nvram_init(struct tg3
*tp
)
12063 tw32_f(GRC_EEPROM_ADDR
,
12064 (EEPROM_ADDR_FSM_RESET
|
12065 (EEPROM_DEFAULT_CLOCK_PERIOD
<<
12066 EEPROM_ADDR_CLKPERD_SHIFT
)));
12070 /* Enable seeprom accesses. */
12071 tw32_f(GRC_LOCAL_CTRL
,
12072 tr32(GRC_LOCAL_CTRL
) | GRC_LCLCTRL_AUTO_SEEPROM
);
12075 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
12076 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
12077 tp
->tg3_flags
|= TG3_FLAG_NVRAM
;
12079 if (tg3_nvram_lock(tp
)) {
12080 netdev_warn(tp
->dev
,
12081 "Cannot get nvram lock, %s failed\n",
12085 tg3_enable_nvram_access(tp
);
12087 tp
->nvram_size
= 0;
12089 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
12090 tg3_get_5752_nvram_info(tp
);
12091 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
12092 tg3_get_5755_nvram_info(tp
);
12093 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
12094 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
12095 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
12096 tg3_get_5787_nvram_info(tp
);
12097 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
12098 tg3_get_5761_nvram_info(tp
);
12099 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
12100 tg3_get_5906_nvram_info(tp
);
12101 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
12102 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
12103 tg3_get_57780_nvram_info(tp
);
12104 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
12105 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
)
12106 tg3_get_5717_nvram_info(tp
);
12107 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
)
12108 tg3_get_5720_nvram_info(tp
);
12110 tg3_get_nvram_info(tp
);
12112 if (tp
->nvram_size
== 0)
12113 tg3_get_nvram_size(tp
);
12115 tg3_disable_nvram_access(tp
);
12116 tg3_nvram_unlock(tp
);
12119 tp
->tg3_flags
&= ~(TG3_FLAG_NVRAM
| TG3_FLAG_NVRAM_BUFFERED
);
12121 tg3_get_eeprom_size(tp
);
12125 static int tg3_nvram_write_block_using_eeprom(struct tg3
*tp
,
12126 u32 offset
, u32 len
, u8
*buf
)
12131 for (i
= 0; i
< len
; i
+= 4) {
12137 memcpy(&data
, buf
+ i
, 4);
12140 * The SEEPROM interface expects the data to always be opposite
12141 * the native endian format. We accomplish this by reversing
12142 * all the operations that would have been performed on the
12143 * data from a call to tg3_nvram_read_be32().
12145 tw32(GRC_EEPROM_DATA
, swab32(be32_to_cpu(data
)));
12147 val
= tr32(GRC_EEPROM_ADDR
);
12148 tw32(GRC_EEPROM_ADDR
, val
| EEPROM_ADDR_COMPLETE
);
12150 val
&= ~(EEPROM_ADDR_ADDR_MASK
| EEPROM_ADDR_DEVID_MASK
|
12152 tw32(GRC_EEPROM_ADDR
, val
|
12153 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
12154 (addr
& EEPROM_ADDR_ADDR_MASK
) |
12155 EEPROM_ADDR_START
|
12156 EEPROM_ADDR_WRITE
);
12158 for (j
= 0; j
< 1000; j
++) {
12159 val
= tr32(GRC_EEPROM_ADDR
);
12161 if (val
& EEPROM_ADDR_COMPLETE
)
12165 if (!(val
& EEPROM_ADDR_COMPLETE
)) {
12174 /* offset and length are dword aligned */
12175 static int tg3_nvram_write_block_unbuffered(struct tg3
*tp
, u32 offset
, u32 len
,
12179 u32 pagesize
= tp
->nvram_pagesize
;
12180 u32 pagemask
= pagesize
- 1;
12184 tmp
= kmalloc(pagesize
, GFP_KERNEL
);
12190 u32 phy_addr
, page_off
, size
;
12192 phy_addr
= offset
& ~pagemask
;
12194 for (j
= 0; j
< pagesize
; j
+= 4) {
12195 ret
= tg3_nvram_read_be32(tp
, phy_addr
+ j
,
12196 (__be32
*) (tmp
+ j
));
12203 page_off
= offset
& pagemask
;
12210 memcpy(tmp
+ page_off
, buf
, size
);
12212 offset
= offset
+ (pagesize
- page_off
);
12214 tg3_enable_nvram_access(tp
);
12217 * Before we can erase the flash page, we need
12218 * to issue a special "write enable" command.
12220 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
12222 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
12225 /* Erase the target page */
12226 tw32(NVRAM_ADDR
, phy_addr
);
12228 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
|
12229 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_ERASE
;
12231 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
12234 /* Issue another write enable to start the write. */
12235 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
12237 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
12240 for (j
= 0; j
< pagesize
; j
+= 4) {
12243 data
= *((__be32
*) (tmp
+ j
));
12245 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
12247 tw32(NVRAM_ADDR
, phy_addr
+ j
);
12249 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
|
12253 nvram_cmd
|= NVRAM_CMD_FIRST
;
12254 else if (j
== (pagesize
- 4))
12255 nvram_cmd
|= NVRAM_CMD_LAST
;
12257 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
12264 nvram_cmd
= NVRAM_CMD_WRDI
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
12265 tg3_nvram_exec_cmd(tp
, nvram_cmd
);
12272 /* offset and length are dword aligned */
12273 static int tg3_nvram_write_block_buffered(struct tg3
*tp
, u32 offset
, u32 len
,
12278 for (i
= 0; i
< len
; i
+= 4, offset
+= 4) {
12279 u32 page_off
, phy_addr
, nvram_cmd
;
12282 memcpy(&data
, buf
+ i
, 4);
12283 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
12285 page_off
= offset
% tp
->nvram_pagesize
;
12287 phy_addr
= tg3_nvram_phys_addr(tp
, offset
);
12289 tw32(NVRAM_ADDR
, phy_addr
);
12291 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
;
12293 if (page_off
== 0 || i
== 0)
12294 nvram_cmd
|= NVRAM_CMD_FIRST
;
12295 if (page_off
== (tp
->nvram_pagesize
- 4))
12296 nvram_cmd
|= NVRAM_CMD_LAST
;
12298 if (i
== (len
- 4))
12299 nvram_cmd
|= NVRAM_CMD_LAST
;
12301 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5752
&&
12302 !(tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) &&
12303 (tp
->nvram_jedecnum
== JEDEC_ST
) &&
12304 (nvram_cmd
& NVRAM_CMD_FIRST
)) {
12306 if ((ret
= tg3_nvram_exec_cmd(tp
,
12307 NVRAM_CMD_WREN
| NVRAM_CMD_GO
|
12312 if (!(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
12313 /* We always do complete word writes to eeprom. */
12314 nvram_cmd
|= (NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
);
12317 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
12323 /* offset and length are dword aligned */
12324 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
)
12328 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
12329 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
&
12330 ~GRC_LCLCTRL_GPIO_OUTPUT1
);
12334 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
)) {
12335 ret
= tg3_nvram_write_block_using_eeprom(tp
, offset
, len
, buf
);
12339 ret
= tg3_nvram_lock(tp
);
12343 tg3_enable_nvram_access(tp
);
12344 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
12345 !(tp
->tg3_flags3
& TG3_FLG3_PROTECTED_NVRAM
))
12346 tw32(NVRAM_WRITE1
, 0x406);
12348 grc_mode
= tr32(GRC_MODE
);
12349 tw32(GRC_MODE
, grc_mode
| GRC_MODE_NVRAM_WR_ENABLE
);
12351 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) ||
12352 !(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
12354 ret
= tg3_nvram_write_block_buffered(tp
, offset
, len
,
12357 ret
= tg3_nvram_write_block_unbuffered(tp
, offset
, len
,
12361 grc_mode
= tr32(GRC_MODE
);
12362 tw32(GRC_MODE
, grc_mode
& ~GRC_MODE_NVRAM_WR_ENABLE
);
12364 tg3_disable_nvram_access(tp
);
12365 tg3_nvram_unlock(tp
);
12368 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
12369 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
12376 struct subsys_tbl_ent
{
12377 u16 subsys_vendor
, subsys_devid
;
12381 static struct subsys_tbl_ent subsys_id_to_phy_id
[] __devinitdata
= {
12382 /* Broadcom boards. */
12383 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
12384 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6
, TG3_PHY_ID_BCM5401
},
12385 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
12386 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5
, TG3_PHY_ID_BCM5701
},
12387 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
12388 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6
, TG3_PHY_ID_BCM8002
},
12389 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
12390 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9
, 0 },
12391 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
12392 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1
, TG3_PHY_ID_BCM5701
},
12393 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
12394 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8
, TG3_PHY_ID_BCM5701
},
12395 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
12396 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7
, 0 },
12397 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
12398 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10
, TG3_PHY_ID_BCM5701
},
12399 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
12400 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12
, TG3_PHY_ID_BCM5701
},
12401 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
12402 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1
, TG3_PHY_ID_BCM5703
},
12403 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
12404 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2
, TG3_PHY_ID_BCM5703
},
12407 { TG3PCI_SUBVENDOR_ID_3COM
,
12408 TG3PCI_SUBDEVICE_ID_3COM_3C996T
, TG3_PHY_ID_BCM5401
},
12409 { TG3PCI_SUBVENDOR_ID_3COM
,
12410 TG3PCI_SUBDEVICE_ID_3COM_3C996BT
, TG3_PHY_ID_BCM5701
},
12411 { TG3PCI_SUBVENDOR_ID_3COM
,
12412 TG3PCI_SUBDEVICE_ID_3COM_3C996SX
, 0 },
12413 { TG3PCI_SUBVENDOR_ID_3COM
,
12414 TG3PCI_SUBDEVICE_ID_3COM_3C1000T
, TG3_PHY_ID_BCM5701
},
12415 { TG3PCI_SUBVENDOR_ID_3COM
,
12416 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01
, TG3_PHY_ID_BCM5701
},
12419 { TG3PCI_SUBVENDOR_ID_DELL
,
12420 TG3PCI_SUBDEVICE_ID_DELL_VIPER
, TG3_PHY_ID_BCM5401
},
12421 { TG3PCI_SUBVENDOR_ID_DELL
,
12422 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR
, TG3_PHY_ID_BCM5401
},
12423 { TG3PCI_SUBVENDOR_ID_DELL
,
12424 TG3PCI_SUBDEVICE_ID_DELL_MERLOT
, TG3_PHY_ID_BCM5411
},
12425 { TG3PCI_SUBVENDOR_ID_DELL
,
12426 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT
, TG3_PHY_ID_BCM5411
},
12428 /* Compaq boards. */
12429 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
12430 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE
, TG3_PHY_ID_BCM5701
},
12431 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
12432 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2
, TG3_PHY_ID_BCM5701
},
12433 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
12434 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING
, 0 },
12435 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
12436 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780
, TG3_PHY_ID_BCM5701
},
12437 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
12438 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2
, TG3_PHY_ID_BCM5701
},
12441 { TG3PCI_SUBVENDOR_ID_IBM
,
12442 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2
, 0 }
12445 static struct subsys_tbl_ent
* __devinit
tg3_lookup_by_subsys(struct tg3
*tp
)
12449 for (i
= 0; i
< ARRAY_SIZE(subsys_id_to_phy_id
); i
++) {
12450 if ((subsys_id_to_phy_id
[i
].subsys_vendor
==
12451 tp
->pdev
->subsystem_vendor
) &&
12452 (subsys_id_to_phy_id
[i
].subsys_devid
==
12453 tp
->pdev
->subsystem_device
))
12454 return &subsys_id_to_phy_id
[i
];
12459 static void __devinit
tg3_get_eeprom_hw_cfg(struct tg3
*tp
)
12464 /* On some early chips the SRAM cannot be accessed in D3hot state,
12465 * so need make sure we're in D0.
12467 pci_read_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
12468 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
12469 pci_write_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
12472 /* Make sure register accesses (indirect or otherwise)
12473 * will function correctly.
12475 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12476 tp
->misc_host_ctrl
);
12478 /* The memory arbiter has to be enabled in order for SRAM accesses
12479 * to succeed. Normally on powerup the tg3 chip firmware will make
12480 * sure it is enabled, but other entities such as system netboot
12481 * code might disable it.
12483 val
= tr32(MEMARB_MODE
);
12484 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
12486 tp
->phy_id
= TG3_PHY_ID_INVALID
;
12487 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12489 /* Assume an onboard device and WOL capable by default. */
12490 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
| TG3_FLAG_WOL_CAP
;
12492 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
12493 if (!(tr32(PCIE_TRANSACTION_CFG
) & PCIE_TRANS_CFG_LOM
)) {
12494 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
12495 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
12497 val
= tr32(VCPU_CFGSHDW
);
12498 if (val
& VCPU_CFGSHDW_ASPM_DBNC
)
12499 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
12500 if ((val
& VCPU_CFGSHDW_WOL_ENABLE
) &&
12501 (val
& VCPU_CFGSHDW_WOL_MAGPKT
))
12502 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
12506 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
12507 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
12508 u32 nic_cfg
, led_cfg
;
12509 u32 nic_phy_id
, ver
, cfg2
= 0, cfg4
= 0, eeprom_phy_id
;
12510 int eeprom_phy_serdes
= 0;
12512 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
12513 tp
->nic_sram_data_cfg
= nic_cfg
;
12515 tg3_read_mem(tp
, NIC_SRAM_DATA_VER
, &ver
);
12516 ver
>>= NIC_SRAM_DATA_VER_SHIFT
;
12517 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
) &&
12518 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) &&
12519 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5703
) &&
12520 (ver
> 0) && (ver
< 0x100))
12521 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_2
, &cfg2
);
12523 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
12524 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_4
, &cfg4
);
12526 if ((nic_cfg
& NIC_SRAM_DATA_CFG_PHY_TYPE_MASK
) ==
12527 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER
)
12528 eeprom_phy_serdes
= 1;
12530 tg3_read_mem(tp
, NIC_SRAM_DATA_PHY_ID
, &nic_phy_id
);
12531 if (nic_phy_id
!= 0) {
12532 u32 id1
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID1_MASK
;
12533 u32 id2
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID2_MASK
;
12535 eeprom_phy_id
= (id1
>> 16) << 10;
12536 eeprom_phy_id
|= (id2
& 0xfc00) << 16;
12537 eeprom_phy_id
|= (id2
& 0x03ff) << 0;
12541 tp
->phy_id
= eeprom_phy_id
;
12542 if (eeprom_phy_serdes
) {
12543 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
12544 tp
->phy_flags
|= TG3_PHYFLG_PHY_SERDES
;
12546 tp
->phy_flags
|= TG3_PHYFLG_MII_SERDES
;
12549 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
12550 led_cfg
= cfg2
& (NIC_SRAM_DATA_CFG_LED_MODE_MASK
|
12551 SHASTA_EXT_LED_MODE_MASK
);
12553 led_cfg
= nic_cfg
& NIC_SRAM_DATA_CFG_LED_MODE_MASK
;
12557 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1
:
12558 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12561 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2
:
12562 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
12565 case NIC_SRAM_DATA_CFG_LED_MODE_MAC
:
12566 tp
->led_ctrl
= LED_CTRL_MODE_MAC
;
12568 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12569 * read on some older 5700/5701 bootcode.
12571 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
12573 GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
12575 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12579 case SHASTA_EXT_LED_SHARED
:
12580 tp
->led_ctrl
= LED_CTRL_MODE_SHARED
;
12581 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
&&
12582 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A1
)
12583 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
12584 LED_CTRL_MODE_PHY_2
);
12587 case SHASTA_EXT_LED_MAC
:
12588 tp
->led_ctrl
= LED_CTRL_MODE_SHASTA_MAC
;
12591 case SHASTA_EXT_LED_COMBO
:
12592 tp
->led_ctrl
= LED_CTRL_MODE_COMBO
;
12593 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
)
12594 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
12595 LED_CTRL_MODE_PHY_2
);
12600 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
12601 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) &&
12602 tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
)
12603 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
12605 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
)
12606 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12608 if (nic_cfg
& NIC_SRAM_DATA_CFG_EEPROM_WP
) {
12609 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
;
12610 if ((tp
->pdev
->subsystem_vendor
==
12611 PCI_VENDOR_ID_ARIMA
) &&
12612 (tp
->pdev
->subsystem_device
== 0x205a ||
12613 tp
->pdev
->subsystem_device
== 0x2063))
12614 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
12616 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
12617 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
12620 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
12621 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
12622 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
12623 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
12626 if ((nic_cfg
& NIC_SRAM_DATA_CFG_APE_ENABLE
) &&
12627 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
12628 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_APE
;
12630 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
&&
12631 !(nic_cfg
& NIC_SRAM_DATA_CFG_FIBER_WOL
))
12632 tp
->tg3_flags
&= ~TG3_FLAG_WOL_CAP
;
12634 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
12635 (nic_cfg
& NIC_SRAM_DATA_CFG_WOL_ENABLE
))
12636 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
12638 if (cfg2
& (1 << 17))
12639 tp
->phy_flags
|= TG3_PHYFLG_CAPACITIVE_COUPLING
;
12641 /* serdes signal pre-emphasis in register 0x590 set by */
12642 /* bootcode if bit 18 is set */
12643 if (cfg2
& (1 << 18))
12644 tp
->phy_flags
|= TG3_PHYFLG_SERDES_PREEMPHASIS
;
12646 if (((tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
) ||
12647 ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
12648 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
))) &&
12649 (cfg2
& NIC_SRAM_DATA_CFG_2_APD_EN
))
12650 tp
->phy_flags
|= TG3_PHYFLG_ENABLE_APD
;
12652 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
12653 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
12654 !(tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
)) {
12657 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_3
, &cfg3
);
12658 if (cfg3
& NIC_SRAM_ASPM_DEBOUNCE
)
12659 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
12662 if (cfg4
& NIC_SRAM_RGMII_INBAND_DISABLE
)
12663 tp
->tg3_flags3
|= TG3_FLG3_RGMII_INBAND_DISABLE
;
12664 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_RX_EN
)
12665 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_RX_EN
;
12666 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_TX_EN
)
12667 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_TX_EN
;
12670 if (tp
->tg3_flags
& TG3_FLAG_WOL_CAP
)
12671 device_set_wakeup_enable(&tp
->pdev
->dev
,
12672 tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
12674 device_set_wakeup_capable(&tp
->pdev
->dev
, false);
12677 static int __devinit
tg3_issue_otp_command(struct tg3
*tp
, u32 cmd
)
12682 tw32(OTP_CTRL
, cmd
| OTP_CTRL_OTP_CMD_START
);
12683 tw32(OTP_CTRL
, cmd
);
12685 /* Wait for up to 1 ms for command to execute. */
12686 for (i
= 0; i
< 100; i
++) {
12687 val
= tr32(OTP_STATUS
);
12688 if (val
& OTP_STATUS_CMD_DONE
)
12693 return (val
& OTP_STATUS_CMD_DONE
) ? 0 : -EBUSY
;
12696 /* Read the gphy configuration from the OTP region of the chip. The gphy
12697 * configuration is a 32-bit value that straddles the alignment boundary.
12698 * We do two 32-bit reads and then shift and merge the results.
12700 static u32 __devinit
tg3_read_otp_phycfg(struct tg3
*tp
)
12702 u32 bhalf_otp
, thalf_otp
;
12704 tw32(OTP_MODE
, OTP_MODE_OTP_THRU_GRC
);
12706 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_INIT
))
12709 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC1
);
12711 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
12714 thalf_otp
= tr32(OTP_READ_DATA
);
12716 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC2
);
12718 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
12721 bhalf_otp
= tr32(OTP_READ_DATA
);
12723 return ((thalf_otp
& 0x0000ffff) << 16) | (bhalf_otp
>> 16);
12726 static void __devinit
tg3_phy_init_link_config(struct tg3
*tp
)
12728 u32 adv
= ADVERTISED_Autoneg
|
12731 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
12732 adv
|= ADVERTISED_1000baseT_Half
|
12733 ADVERTISED_1000baseT_Full
;
12735 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
12736 adv
|= ADVERTISED_100baseT_Half
|
12737 ADVERTISED_100baseT_Full
|
12738 ADVERTISED_10baseT_Half
|
12739 ADVERTISED_10baseT_Full
|
12742 adv
|= ADVERTISED_FIBRE
;
12744 tp
->link_config
.advertising
= adv
;
12745 tp
->link_config
.speed
= SPEED_INVALID
;
12746 tp
->link_config
.duplex
= DUPLEX_INVALID
;
12747 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
12748 tp
->link_config
.active_speed
= SPEED_INVALID
;
12749 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
12750 tp
->link_config
.orig_speed
= SPEED_INVALID
;
12751 tp
->link_config
.orig_duplex
= DUPLEX_INVALID
;
12752 tp
->link_config
.orig_autoneg
= AUTONEG_INVALID
;
12755 static int __devinit
tg3_phy_probe(struct tg3
*tp
)
12757 u32 hw_phy_id_1
, hw_phy_id_2
;
12758 u32 hw_phy_id
, hw_phy_id_masked
;
12761 /* flow control autonegotiation is default behavior */
12762 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
12763 tp
->link_config
.flowctrl
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
12765 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
12766 return tg3_phy_init(tp
);
12768 /* Reading the PHY ID register can conflict with ASF
12769 * firmware access to the PHY hardware.
12772 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
12773 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
12774 hw_phy_id
= hw_phy_id_masked
= TG3_PHY_ID_INVALID
;
12776 /* Now read the physical PHY_ID from the chip and verify
12777 * that it is sane. If it doesn't look good, we fall back
12778 * to either the hard-coded table based PHY_ID and failing
12779 * that the value found in the eeprom area.
12781 err
|= tg3_readphy(tp
, MII_PHYSID1
, &hw_phy_id_1
);
12782 err
|= tg3_readphy(tp
, MII_PHYSID2
, &hw_phy_id_2
);
12784 hw_phy_id
= (hw_phy_id_1
& 0xffff) << 10;
12785 hw_phy_id
|= (hw_phy_id_2
& 0xfc00) << 16;
12786 hw_phy_id
|= (hw_phy_id_2
& 0x03ff) << 0;
12788 hw_phy_id_masked
= hw_phy_id
& TG3_PHY_ID_MASK
;
12791 if (!err
&& TG3_KNOWN_PHY_ID(hw_phy_id_masked
)) {
12792 tp
->phy_id
= hw_phy_id
;
12793 if (hw_phy_id_masked
== TG3_PHY_ID_BCM8002
)
12794 tp
->phy_flags
|= TG3_PHYFLG_PHY_SERDES
;
12796 tp
->phy_flags
&= ~TG3_PHYFLG_PHY_SERDES
;
12798 if (tp
->phy_id
!= TG3_PHY_ID_INVALID
) {
12799 /* Do nothing, phy ID already set up in
12800 * tg3_get_eeprom_hw_cfg().
12803 struct subsys_tbl_ent
*p
;
12805 /* No eeprom signature? Try the hardcoded
12806 * subsys device table.
12808 p
= tg3_lookup_by_subsys(tp
);
12812 tp
->phy_id
= p
->phy_id
;
12814 tp
->phy_id
== TG3_PHY_ID_BCM8002
)
12815 tp
->phy_flags
|= TG3_PHYFLG_PHY_SERDES
;
12819 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
) &&
12820 ((tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5718
&&
12821 tp
->pci_chip_rev_id
!= CHIPREV_ID_5717_A0
) ||
12822 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
&&
12823 tp
->pci_chip_rev_id
!= CHIPREV_ID_57765_A0
)))
12824 tp
->phy_flags
|= TG3_PHYFLG_EEE_CAP
;
12826 tg3_phy_init_link_config(tp
);
12828 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
) &&
12829 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) &&
12830 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
12831 u32 bmsr
, adv_reg
, tg3_ctrl
, mask
;
12833 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
12834 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
12835 (bmsr
& BMSR_LSTATUS
))
12836 goto skip_phy_reset
;
12838 err
= tg3_phy_reset(tp
);
12842 adv_reg
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
12843 ADVERTISE_100HALF
| ADVERTISE_100FULL
|
12844 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
12846 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
12847 tg3_ctrl
= (MII_TG3_CTRL_ADV_1000_HALF
|
12848 MII_TG3_CTRL_ADV_1000_FULL
);
12849 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
12850 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
12851 tg3_ctrl
|= (MII_TG3_CTRL_AS_MASTER
|
12852 MII_TG3_CTRL_ENABLE_AS_MASTER
);
12855 mask
= (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
12856 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
12857 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
);
12858 if (!tg3_copper_is_advertising_all(tp
, mask
)) {
12859 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
12861 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
12862 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
12864 tg3_writephy(tp
, MII_BMCR
,
12865 BMCR_ANENABLE
| BMCR_ANRESTART
);
12867 tg3_phy_set_wirespeed(tp
);
12869 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
12870 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
12871 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
12875 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
12876 err
= tg3_init_5401phy_dsp(tp
);
12880 err
= tg3_init_5401phy_dsp(tp
);
12886 static void __devinit
tg3_read_vpd(struct tg3
*tp
)
12889 unsigned int block_end
, rosize
, len
;
12893 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
12894 tg3_nvram_read(tp
, 0x0, &magic
))
12897 vpd_data
= kmalloc(TG3_NVM_VPD_LEN
, GFP_KERNEL
);
12901 if (magic
== TG3_EEPROM_MAGIC
) {
12902 for (i
= 0; i
< TG3_NVM_VPD_LEN
; i
+= 4) {
12905 /* The data is in little-endian format in NVRAM.
12906 * Use the big-endian read routines to preserve
12907 * the byte order as it exists in NVRAM.
12909 if (tg3_nvram_read_be32(tp
, TG3_NVM_VPD_OFF
+ i
, &tmp
))
12910 goto out_not_found
;
12912 memcpy(&vpd_data
[i
], &tmp
, sizeof(tmp
));
12916 unsigned int pos
= 0;
12918 for (; pos
< TG3_NVM_VPD_LEN
&& i
< 3; i
++, pos
+= cnt
) {
12919 cnt
= pci_read_vpd(tp
->pdev
, pos
,
12920 TG3_NVM_VPD_LEN
- pos
,
12922 if (cnt
== -ETIMEDOUT
|| cnt
== -EINTR
)
12925 goto out_not_found
;
12927 if (pos
!= TG3_NVM_VPD_LEN
)
12928 goto out_not_found
;
12931 i
= pci_vpd_find_tag(vpd_data
, 0, TG3_NVM_VPD_LEN
,
12932 PCI_VPD_LRDT_RO_DATA
);
12934 goto out_not_found
;
12936 rosize
= pci_vpd_lrdt_size(&vpd_data
[i
]);
12937 block_end
= i
+ PCI_VPD_LRDT_TAG_SIZE
+ rosize
;
12938 i
+= PCI_VPD_LRDT_TAG_SIZE
;
12940 if (block_end
> TG3_NVM_VPD_LEN
)
12941 goto out_not_found
;
12943 j
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
12944 PCI_VPD_RO_KEYWORD_MFR_ID
);
12946 len
= pci_vpd_info_field_size(&vpd_data
[j
]);
12948 j
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12949 if (j
+ len
> block_end
|| len
!= 4 ||
12950 memcmp(&vpd_data
[j
], "1028", 4))
12953 j
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
12954 PCI_VPD_RO_KEYWORD_VENDOR0
);
12958 len
= pci_vpd_info_field_size(&vpd_data
[j
]);
12960 j
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12961 if (j
+ len
> block_end
)
12964 memcpy(tp
->fw_ver
, &vpd_data
[j
], len
);
12965 strncat(tp
->fw_ver
, " bc ", TG3_NVM_VPD_LEN
- len
- 1);
12969 i
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
12970 PCI_VPD_RO_KEYWORD_PARTNO
);
12972 goto out_not_found
;
12974 len
= pci_vpd_info_field_size(&vpd_data
[i
]);
12976 i
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12977 if (len
> TG3_BPN_SIZE
||
12978 (len
+ i
) > TG3_NVM_VPD_LEN
)
12979 goto out_not_found
;
12981 memcpy(tp
->board_part_number
, &vpd_data
[i
], len
);
12985 if (tp
->board_part_number
[0])
12989 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
) {
12990 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5717
)
12991 strcpy(tp
->board_part_number
, "BCM5717");
12992 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5718
)
12993 strcpy(tp
->board_part_number
, "BCM5718");
12996 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
12997 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57780
)
12998 strcpy(tp
->board_part_number
, "BCM57780");
12999 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57760
)
13000 strcpy(tp
->board_part_number
, "BCM57760");
13001 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
)
13002 strcpy(tp
->board_part_number
, "BCM57790");
13003 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57788
)
13004 strcpy(tp
->board_part_number
, "BCM57788");
13007 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) {
13008 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57761
)
13009 strcpy(tp
->board_part_number
, "BCM57761");
13010 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57765
)
13011 strcpy(tp
->board_part_number
, "BCM57765");
13012 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57781
)
13013 strcpy(tp
->board_part_number
, "BCM57781");
13014 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57785
)
13015 strcpy(tp
->board_part_number
, "BCM57785");
13016 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
)
13017 strcpy(tp
->board_part_number
, "BCM57791");
13018 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
)
13019 strcpy(tp
->board_part_number
, "BCM57795");
13022 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
13023 strcpy(tp
->board_part_number
, "BCM95906");
13026 strcpy(tp
->board_part_number
, "none");
13030 static int __devinit
tg3_fw_img_is_valid(struct tg3
*tp
, u32 offset
)
13034 if (tg3_nvram_read(tp
, offset
, &val
) ||
13035 (val
& 0xfc000000) != 0x0c000000 ||
13036 tg3_nvram_read(tp
, offset
+ 4, &val
) ||
13043 static void __devinit
tg3_read_bc_ver(struct tg3
*tp
)
13045 u32 val
, offset
, start
, ver_offset
;
13047 bool newver
= false;
13049 if (tg3_nvram_read(tp
, 0xc, &offset
) ||
13050 tg3_nvram_read(tp
, 0x4, &start
))
13053 offset
= tg3_nvram_logical_addr(tp
, offset
);
13055 if (tg3_nvram_read(tp
, offset
, &val
))
13058 if ((val
& 0xfc000000) == 0x0c000000) {
13059 if (tg3_nvram_read(tp
, offset
+ 4, &val
))
13066 dst_off
= strlen(tp
->fw_ver
);
13069 if (TG3_VER_SIZE
- dst_off
< 16 ||
13070 tg3_nvram_read(tp
, offset
+ 8, &ver_offset
))
13073 offset
= offset
+ ver_offset
- start
;
13074 for (i
= 0; i
< 16; i
+= 4) {
13076 if (tg3_nvram_read_be32(tp
, offset
+ i
, &v
))
13079 memcpy(tp
->fw_ver
+ dst_off
+ i
, &v
, sizeof(v
));
13084 if (tg3_nvram_read(tp
, TG3_NVM_PTREV_BCVER
, &ver_offset
))
13087 major
= (ver_offset
& TG3_NVM_BCVER_MAJMSK
) >>
13088 TG3_NVM_BCVER_MAJSFT
;
13089 minor
= ver_offset
& TG3_NVM_BCVER_MINMSK
;
13090 snprintf(&tp
->fw_ver
[dst_off
], TG3_VER_SIZE
- dst_off
,
13091 "v%d.%02d", major
, minor
);
13095 static void __devinit
tg3_read_hwsb_ver(struct tg3
*tp
)
13097 u32 val
, major
, minor
;
13099 /* Use native endian representation */
13100 if (tg3_nvram_read(tp
, TG3_NVM_HWSB_CFG1
, &val
))
13103 major
= (val
& TG3_NVM_HWSB_CFG1_MAJMSK
) >>
13104 TG3_NVM_HWSB_CFG1_MAJSFT
;
13105 minor
= (val
& TG3_NVM_HWSB_CFG1_MINMSK
) >>
13106 TG3_NVM_HWSB_CFG1_MINSFT
;
13108 snprintf(&tp
->fw_ver
[0], 32, "sb v%d.%02d", major
, minor
);
13111 static void __devinit
tg3_read_sb_ver(struct tg3
*tp
, u32 val
)
13113 u32 offset
, major
, minor
, build
;
13115 strncat(tp
->fw_ver
, "sb", TG3_VER_SIZE
- strlen(tp
->fw_ver
) - 1);
13117 if ((val
& TG3_EEPROM_SB_FORMAT_MASK
) != TG3_EEPROM_SB_FORMAT_1
)
13120 switch (val
& TG3_EEPROM_SB_REVISION_MASK
) {
13121 case TG3_EEPROM_SB_REVISION_0
:
13122 offset
= TG3_EEPROM_SB_F1R0_EDH_OFF
;
13124 case TG3_EEPROM_SB_REVISION_2
:
13125 offset
= TG3_EEPROM_SB_F1R2_EDH_OFF
;
13127 case TG3_EEPROM_SB_REVISION_3
:
13128 offset
= TG3_EEPROM_SB_F1R3_EDH_OFF
;
13130 case TG3_EEPROM_SB_REVISION_4
:
13131 offset
= TG3_EEPROM_SB_F1R4_EDH_OFF
;
13133 case TG3_EEPROM_SB_REVISION_5
:
13134 offset
= TG3_EEPROM_SB_F1R5_EDH_OFF
;
13136 case TG3_EEPROM_SB_REVISION_6
:
13137 offset
= TG3_EEPROM_SB_F1R6_EDH_OFF
;
13143 if (tg3_nvram_read(tp
, offset
, &val
))
13146 build
= (val
& TG3_EEPROM_SB_EDH_BLD_MASK
) >>
13147 TG3_EEPROM_SB_EDH_BLD_SHFT
;
13148 major
= (val
& TG3_EEPROM_SB_EDH_MAJ_MASK
) >>
13149 TG3_EEPROM_SB_EDH_MAJ_SHFT
;
13150 minor
= val
& TG3_EEPROM_SB_EDH_MIN_MASK
;
13152 if (minor
> 99 || build
> 26)
13155 offset
= strlen(tp
->fw_ver
);
13156 snprintf(&tp
->fw_ver
[offset
], TG3_VER_SIZE
- offset
,
13157 " v%d.%02d", major
, minor
);
13160 offset
= strlen(tp
->fw_ver
);
13161 if (offset
< TG3_VER_SIZE
- 1)
13162 tp
->fw_ver
[offset
] = 'a' + build
- 1;
13166 static void __devinit
tg3_read_mgmtfw_ver(struct tg3
*tp
)
13168 u32 val
, offset
, start
;
13171 for (offset
= TG3_NVM_DIR_START
;
13172 offset
< TG3_NVM_DIR_END
;
13173 offset
+= TG3_NVM_DIRENT_SIZE
) {
13174 if (tg3_nvram_read(tp
, offset
, &val
))
13177 if ((val
>> TG3_NVM_DIRTYPE_SHIFT
) == TG3_NVM_DIRTYPE_ASFINI
)
13181 if (offset
== TG3_NVM_DIR_END
)
13184 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
13185 start
= 0x08000000;
13186 else if (tg3_nvram_read(tp
, offset
- 4, &start
))
13189 if (tg3_nvram_read(tp
, offset
+ 4, &offset
) ||
13190 !tg3_fw_img_is_valid(tp
, offset
) ||
13191 tg3_nvram_read(tp
, offset
+ 8, &val
))
13194 offset
+= val
- start
;
13196 vlen
= strlen(tp
->fw_ver
);
13198 tp
->fw_ver
[vlen
++] = ',';
13199 tp
->fw_ver
[vlen
++] = ' ';
13201 for (i
= 0; i
< 4; i
++) {
13203 if (tg3_nvram_read_be32(tp
, offset
, &v
))
13206 offset
+= sizeof(v
);
13208 if (vlen
> TG3_VER_SIZE
- sizeof(v
)) {
13209 memcpy(&tp
->fw_ver
[vlen
], &v
, TG3_VER_SIZE
- vlen
);
13213 memcpy(&tp
->fw_ver
[vlen
], &v
, sizeof(v
));
13218 static void __devinit
tg3_read_dash_ver(struct tg3
*tp
)
13224 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) ||
13225 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
13228 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
13229 if (apedata
!= APE_SEG_SIG_MAGIC
)
13232 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
13233 if (!(apedata
& APE_FW_STATUS_READY
))
13236 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_VERSION
);
13238 if (tg3_ape_read32(tp
, TG3_APE_FW_FEATURES
) & TG3_APE_FW_FEATURE_NCSI
) {
13239 tp
->tg3_flags3
|= TG3_FLG3_APE_HAS_NCSI
;
13245 vlen
= strlen(tp
->fw_ver
);
13247 snprintf(&tp
->fw_ver
[vlen
], TG3_VER_SIZE
- vlen
, " %s v%d.%d.%d.%d",
13249 (apedata
& APE_FW_VERSION_MAJMSK
) >> APE_FW_VERSION_MAJSFT
,
13250 (apedata
& APE_FW_VERSION_MINMSK
) >> APE_FW_VERSION_MINSFT
,
13251 (apedata
& APE_FW_VERSION_REVMSK
) >> APE_FW_VERSION_REVSFT
,
13252 (apedata
& APE_FW_VERSION_BLDMSK
));
13255 static void __devinit
tg3_read_fw_ver(struct tg3
*tp
)
13258 bool vpd_vers
= false;
13260 if (tp
->fw_ver
[0] != 0)
13263 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) {
13264 strcat(tp
->fw_ver
, "sb");
13268 if (tg3_nvram_read(tp
, 0, &val
))
13271 if (val
== TG3_EEPROM_MAGIC
)
13272 tg3_read_bc_ver(tp
);
13273 else if ((val
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
)
13274 tg3_read_sb_ver(tp
, val
);
13275 else if ((val
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
13276 tg3_read_hwsb_ver(tp
);
13280 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
13281 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) || vpd_vers
)
13284 tg3_read_mgmtfw_ver(tp
);
13287 tp
->fw_ver
[TG3_VER_SIZE
- 1] = 0;
13290 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*);
13292 static inline u32
tg3_rx_ret_ring_size(struct tg3
*tp
)
13294 if (tp
->tg3_flags3
& TG3_FLG3_LRG_PROD_RING_CAP
)
13295 return TG3_RX_RET_MAX_SIZE_5717
;
13296 else if ((tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) &&
13297 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
13298 return TG3_RX_RET_MAX_SIZE_5700
;
13300 return TG3_RX_RET_MAX_SIZE_5705
;
13303 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets
) = {
13304 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
) },
13305 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
) },
13306 { PCI_DEVICE(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8385_0
) },
13310 static int __devinit
tg3_get_invariants(struct tg3
*tp
)
13313 u32 pci_state_reg
, grc_misc_cfg
;
13318 /* Force memory write invalidate off. If we leave it on,
13319 * then on 5700_BX chips we have to enable a workaround.
13320 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13321 * to match the cacheline size. The Broadcom driver have this
13322 * workaround but turns MWI off all the times so never uses
13323 * it. This seems to suggest that the workaround is insufficient.
13325 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
13326 pci_cmd
&= ~PCI_COMMAND_INVALIDATE
;
13327 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
13329 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
13330 * has the register indirect write enable bit set before
13331 * we try to access any of the MMIO registers. It is also
13332 * critical that the PCI-X hw workaround situation is decided
13333 * before that as well.
13335 pci_read_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
13338 tp
->pci_chip_rev_id
= (misc_ctrl_reg
>>
13339 MISC_HOST_CTRL_CHIPREV_SHIFT
);
13340 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_USE_PROD_ID_REG
) {
13341 u32 prod_id_asic_rev
;
13343 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5717
||
13344 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5718
||
13345 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5719
||
13346 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5720
)
13347 pci_read_config_dword(tp
->pdev
,
13348 TG3PCI_GEN2_PRODID_ASICREV
,
13349 &prod_id_asic_rev
);
13350 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57781
||
13351 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57785
||
13352 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57761
||
13353 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57765
||
13354 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
||
13355 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
)
13356 pci_read_config_dword(tp
->pdev
,
13357 TG3PCI_GEN15_PRODID_ASICREV
,
13358 &prod_id_asic_rev
);
13360 pci_read_config_dword(tp
->pdev
, TG3PCI_PRODID_ASICREV
,
13361 &prod_id_asic_rev
);
13363 tp
->pci_chip_rev_id
= prod_id_asic_rev
;
13366 /* Wrong chip ID in 5752 A0. This code can be removed later
13367 * as A0 is not in production.
13369 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5752_A0_HW
)
13370 tp
->pci_chip_rev_id
= CHIPREV_ID_5752_A0
;
13372 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13373 * we need to disable memory and use config. cycles
13374 * only to access all registers. The 5702/03 chips
13375 * can mistakenly decode the special cycles from the
13376 * ICH chipsets as memory write cycles, causing corruption
13377 * of register and memory space. Only certain ICH bridges
13378 * will drive special cycles with non-zero data during the
13379 * address phase which can fall within the 5703's address
13380 * range. This is not an ICH bug as the PCI spec allows
13381 * non-zero address during special cycles. However, only
13382 * these ICH bridges are known to drive non-zero addresses
13383 * during special cycles.
13385 * Since special cycles do not cross PCI bridges, we only
13386 * enable this workaround if the 5703 is on the secondary
13387 * bus of these ICH bridges.
13389 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
) ||
13390 (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A2
)) {
13391 static struct tg3_dev_id
{
13395 } ich_chipsets
[] = {
13396 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_8
,
13398 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_8
,
13400 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_11
,
13402 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_6
,
13406 struct tg3_dev_id
*pci_id
= &ich_chipsets
[0];
13407 struct pci_dev
*bridge
= NULL
;
13409 while (pci_id
->vendor
!= 0) {
13410 bridge
= pci_get_device(pci_id
->vendor
, pci_id
->device
,
13416 if (pci_id
->rev
!= PCI_ANY_ID
) {
13417 if (bridge
->revision
> pci_id
->rev
)
13420 if (bridge
->subordinate
&&
13421 (bridge
->subordinate
->number
==
13422 tp
->pdev
->bus
->number
)) {
13424 tp
->tg3_flags2
|= TG3_FLG2_ICH_WORKAROUND
;
13425 pci_dev_put(bridge
);
13431 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
13432 static struct tg3_dev_id
{
13435 } bridge_chipsets
[] = {
13436 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
},
13437 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
},
13440 struct tg3_dev_id
*pci_id
= &bridge_chipsets
[0];
13441 struct pci_dev
*bridge
= NULL
;
13443 while (pci_id
->vendor
!= 0) {
13444 bridge
= pci_get_device(pci_id
->vendor
,
13451 if (bridge
->subordinate
&&
13452 (bridge
->subordinate
->number
<=
13453 tp
->pdev
->bus
->number
) &&
13454 (bridge
->subordinate
->subordinate
>=
13455 tp
->pdev
->bus
->number
)) {
13456 tp
->tg3_flags3
|= TG3_FLG3_5701_DMA_BUG
;
13457 pci_dev_put(bridge
);
13463 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13464 * DMA addresses > 40-bit. This bridge may have other additional
13465 * 57xx devices behind it in some 4-port NIC designs for example.
13466 * Any tg3 device found behind the bridge will also need the 40-bit
13469 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
||
13470 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
13471 tp
->tg3_flags2
|= TG3_FLG2_5780_CLASS
;
13472 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
13473 tp
->msi_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_MSI
);
13475 struct pci_dev
*bridge
= NULL
;
13478 bridge
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
13479 PCI_DEVICE_ID_SERVERWORKS_EPB
,
13481 if (bridge
&& bridge
->subordinate
&&
13482 (bridge
->subordinate
->number
<=
13483 tp
->pdev
->bus
->number
) &&
13484 (bridge
->subordinate
->subordinate
>=
13485 tp
->pdev
->bus
->number
)) {
13486 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
13487 pci_dev_put(bridge
);
13493 /* Initialize misc host control in PCI block. */
13494 tp
->misc_host_ctrl
|= (misc_ctrl_reg
&
13495 MISC_HOST_CTRL_CHIPREV
);
13496 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
13497 tp
->misc_host_ctrl
);
13499 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
13500 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
||
13501 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13502 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
)
13503 tp
->pdev_peer
= tg3_find_peer(tp
);
13505 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13506 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
13507 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
)
13508 tp
->tg3_flags3
|= TG3_FLG3_5717_PLUS
;
13510 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
||
13511 (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
))
13512 tp
->tg3_flags3
|= TG3_FLG3_57765_PLUS
;
13514 /* Intentionally exclude ASIC_REV_5906 */
13515 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
13516 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
13517 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13518 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
13519 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
13520 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
13521 (tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
))
13522 tp
->tg3_flags3
|= TG3_FLG3_5755_PLUS
;
13524 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
13525 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
13526 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
||
13527 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13528 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
13529 tp
->tg3_flags2
|= TG3_FLG2_5750_PLUS
;
13531 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) ||
13532 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
13533 tp
->tg3_flags2
|= TG3_FLG2_5705_PLUS
;
13535 /* 5700 B0 chips do not support checksumming correctly due
13536 * to hardware bugs.
13538 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5700_B0
) {
13539 u32 features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_RXCSUM
;
13541 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
13542 features
|= NETIF_F_IPV6_CSUM
;
13543 tp
->dev
->features
|= features
;
13544 tp
->dev
->hw_features
|= features
;
13545 tp
->dev
->vlan_features
|= features
;
13548 /* Determine TSO capabilities */
13549 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
)
13550 ; /* Do nothing. HW bug. */
13551 else if (tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
)
13552 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_3
;
13553 else if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13554 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13555 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_2
;
13556 else if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
13557 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_1
| TG3_FLG2_TSO_BUG
;
13558 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
&&
13559 tp
->pci_chip_rev_id
>= CHIPREV_ID_5750_C2
)
13560 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_BUG
;
13561 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
13562 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
&&
13563 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) {
13564 tp
->tg3_flags2
|= TG3_FLG2_TSO_BUG
;
13565 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
)
13566 tp
->fw_needed
= FIRMWARE_TG3TSO5
;
13568 tp
->fw_needed
= FIRMWARE_TG3TSO
;
13573 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
13574 tp
->tg3_flags
|= TG3_FLAG_SUPPORT_MSI
;
13575 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
||
13576 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
||
13577 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
&&
13578 tp
->pci_chip_rev_id
<= CHIPREV_ID_5714_A2
&&
13579 tp
->pdev_peer
== tp
->pdev
))
13580 tp
->tg3_flags
&= ~TG3_FLAG_SUPPORT_MSI
;
13582 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13583 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
13584 tp
->tg3_flags2
|= TG3_FLG2_1SHOT_MSI
;
13587 if (tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
) {
13588 tp
->tg3_flags
|= TG3_FLAG_SUPPORT_MSIX
;
13589 tp
->irq_max
= TG3_IRQ_MAX_VECS
;
13593 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13594 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
13595 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13596 tp
->tg3_flags3
|= TG3_FLG3_SHORT_DMA_BUG
;
13597 else if (!(tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)) {
13598 tp
->tg3_flags3
|= TG3_FLG3_4G_DMA_BNDRY_BUG
;
13599 tp
->tg3_flags3
|= TG3_FLG3_40BIT_DMA_LIMIT_BUG
;
13602 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)
13603 tp
->tg3_flags3
|= TG3_FLG3_LRG_PROD_RING_CAP
;
13605 if ((tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
) &&
13606 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5719
)
13607 tp
->tg3_flags3
|= TG3_FLG3_USE_JUMBO_BDFLAG
;
13609 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
13610 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
13611 (tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
))
13612 tp
->tg3_flags
|= TG3_FLAG_JUMBO_CAPABLE
;
13614 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
13617 tp
->pcie_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_EXP
);
13618 if (tp
->pcie_cap
!= 0) {
13621 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
13623 tp
->pcie_readrq
= 4096;
13624 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
13625 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
)
13626 tp
->pcie_readrq
= 2048;
13628 pcie_set_readrq(tp
->pdev
, tp
->pcie_readrq
);
13630 pci_read_config_word(tp
->pdev
,
13631 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
13633 if (lnkctl
& PCI_EXP_LNKCTL_CLKREQ_EN
) {
13634 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13635 tp
->tg3_flags2
&= ~TG3_FLG2_HW_TSO_2
;
13636 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13637 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
13638 tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A0
||
13639 tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A1
)
13640 tp
->tg3_flags3
|= TG3_FLG3_CLKREQ_BUG
;
13641 } else if (tp
->pci_chip_rev_id
== CHIPREV_ID_5717_A0
) {
13642 tp
->tg3_flags3
|= TG3_FLG3_L1PLLPD_EN
;
13644 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
13645 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
13646 } else if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
13647 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
13648 tp
->pcix_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_PCIX
);
13649 if (!tp
->pcix_cap
) {
13650 dev_err(&tp
->pdev
->dev
,
13651 "Cannot find PCI-X capability, aborting\n");
13655 if (!(pci_state_reg
& PCISTATE_CONV_PCI_MODE
))
13656 tp
->tg3_flags
|= TG3_FLAG_PCIX_MODE
;
13659 /* If we have an AMD 762 or VIA K8T800 chipset, write
13660 * reordering to the mailbox registers done by the host
13661 * controller can cause major troubles. We read back from
13662 * every mailbox register write to force the writes to be
13663 * posted to the chip in order.
13665 if (pci_dev_present(tg3_write_reorder_chipsets
) &&
13666 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
13667 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
13669 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
13670 &tp
->pci_cacheline_sz
);
13671 pci_read_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
13672 &tp
->pci_lat_timer
);
13673 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
13674 tp
->pci_lat_timer
< 64) {
13675 tp
->pci_lat_timer
= 64;
13676 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
13677 tp
->pci_lat_timer
);
13680 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5700_BX
) {
13681 /* 5700 BX chips need to have their TX producer index
13682 * mailboxes written twice to workaround a bug.
13684 tp
->tg3_flags
|= TG3_FLAG_TXD_MBOX_HWBUG
;
13686 /* If we are in PCI-X mode, enable register write workaround.
13688 * The workaround is to use indirect register accesses
13689 * for all chip writes not to mailbox registers.
13691 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
13694 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
13696 /* The chip can have it's power management PCI config
13697 * space registers clobbered due to this bug.
13698 * So explicitly force the chip into D0 here.
13700 pci_read_config_dword(tp
->pdev
,
13701 tp
->pm_cap
+ PCI_PM_CTRL
,
13703 pm_reg
&= ~PCI_PM_CTRL_STATE_MASK
;
13704 pm_reg
|= PCI_PM_CTRL_PME_ENABLE
| 0 /* D0 */;
13705 pci_write_config_dword(tp
->pdev
,
13706 tp
->pm_cap
+ PCI_PM_CTRL
,
13709 /* Also, force SERR#/PERR# in PCI command. */
13710 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
13711 pci_cmd
|= PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
;
13712 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
13716 if ((pci_state_reg
& PCISTATE_BUS_SPEED_HIGH
) != 0)
13717 tp
->tg3_flags
|= TG3_FLAG_PCI_HIGH_SPEED
;
13718 if ((pci_state_reg
& PCISTATE_BUS_32BIT
) != 0)
13719 tp
->tg3_flags
|= TG3_FLAG_PCI_32BIT
;
13721 /* Chip-specific fixup from Broadcom driver */
13722 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
) &&
13723 (!(pci_state_reg
& PCISTATE_RETRY_SAME_DMA
))) {
13724 pci_state_reg
|= PCISTATE_RETRY_SAME_DMA
;
13725 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, pci_state_reg
);
13728 /* Default fast path register access methods */
13729 tp
->read32
= tg3_read32
;
13730 tp
->write32
= tg3_write32
;
13731 tp
->read32_mbox
= tg3_read32
;
13732 tp
->write32_mbox
= tg3_write32
;
13733 tp
->write32_tx_mbox
= tg3_write32
;
13734 tp
->write32_rx_mbox
= tg3_write32
;
13736 /* Various workaround register access methods */
13737 if (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
)
13738 tp
->write32
= tg3_write_indirect_reg32
;
13739 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
||
13740 ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
13741 tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
)) {
13743 * Back to back register writes can cause problems on these
13744 * chips, the workaround is to read back all reg writes
13745 * except those to mailbox regs.
13747 * See tg3_write_indirect_reg32().
13749 tp
->write32
= tg3_write_flush_reg32
;
13752 if ((tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
) ||
13753 (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)) {
13754 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
13755 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
13756 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
13759 if (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
) {
13760 tp
->read32
= tg3_read_indirect_reg32
;
13761 tp
->write32
= tg3_write_indirect_reg32
;
13762 tp
->read32_mbox
= tg3_read_indirect_mbox
;
13763 tp
->write32_mbox
= tg3_write_indirect_mbox
;
13764 tp
->write32_tx_mbox
= tg3_write_indirect_mbox
;
13765 tp
->write32_rx_mbox
= tg3_write_indirect_mbox
;
13770 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
13771 pci_cmd
&= ~PCI_COMMAND_MEMORY
;
13772 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
13774 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
13775 tp
->read32_mbox
= tg3_read32_mbox_5906
;
13776 tp
->write32_mbox
= tg3_write32_mbox_5906
;
13777 tp
->write32_tx_mbox
= tg3_write32_mbox_5906
;
13778 tp
->write32_rx_mbox
= tg3_write32_mbox_5906
;
13781 if (tp
->write32
== tg3_write_indirect_reg32
||
13782 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
13783 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13784 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)))
13785 tp
->tg3_flags
|= TG3_FLAG_SRAM_USE_CONFIG
;
13787 /* Get eeprom hw config before calling tg3_set_power_state().
13788 * In particular, the TG3_FLG2_IS_NIC flag must be
13789 * determined before calling tg3_set_power_state() so that
13790 * we know whether or not to switch out of Vaux power.
13791 * When the flag is set, it means that GPIO1 is used for eeprom
13792 * write protect and also implies that it is a LOM where GPIOs
13793 * are not used to switch power.
13795 tg3_get_eeprom_hw_cfg(tp
);
13797 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
13798 /* Allow reads and writes to the
13799 * APE register and memory space.
13801 pci_state_reg
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
13802 PCISTATE_ALLOW_APE_SHMEM_WR
|
13803 PCISTATE_ALLOW_APE_PSPACE_WR
;
13804 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
13808 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13809 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
13810 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
13811 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
13812 (tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
))
13813 tp
->tg3_flags
|= TG3_FLAG_CPMU_PRESENT
;
13815 /* Set up tp->grc_local_ctrl before calling tg_power_up().
13816 * GPIO1 driven high will bring 5700's external PHY out of reset.
13817 * It is also used as eeprom write protect on LOMs.
13819 tp
->grc_local_ctrl
= GRC_LCLCTRL_INT_ON_ATTN
| GRC_LCLCTRL_AUTO_SEEPROM
;
13820 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
13821 (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
))
13822 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
13823 GRC_LCLCTRL_GPIO_OUTPUT1
);
13824 /* Unused GPIO3 must be driven as output on 5752 because there
13825 * are no pull-up resistors on unused GPIO pins.
13827 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
13828 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
13830 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
13831 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
13832 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
13833 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
13835 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
13836 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
13837 /* Turn off the debug UART. */
13838 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
13839 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
13840 /* Keep VMain power. */
13841 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
13842 GRC_LCLCTRL_GPIO_OUTPUT0
;
13845 /* Force the chip into D0. */
13846 err
= tg3_power_up(tp
);
13848 dev_err(&tp
->pdev
->dev
, "Transition to D0 failed\n");
13852 /* Derive initial jumbo mode from MTU assigned in
13853 * ether_setup() via the alloc_etherdev() call
13855 if (tp
->dev
->mtu
> ETH_DATA_LEN
&&
13856 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
13857 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
13859 /* Determine WakeOnLan speed to use. */
13860 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13861 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
13862 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
||
13863 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B2
) {
13864 tp
->tg3_flags
&= ~(TG3_FLAG_WOL_SPEED_100MB
);
13866 tp
->tg3_flags
|= TG3_FLAG_WOL_SPEED_100MB
;
13869 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13870 tp
->phy_flags
|= TG3_PHYFLG_IS_FET
;
13872 /* A few boards don't want Ethernet@WireSpeed phy feature */
13873 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
13874 ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
13875 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) &&
13876 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A1
)) ||
13877 (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) ||
13878 (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
13879 tp
->phy_flags
|= TG3_PHYFLG_NO_ETH_WIRE_SPEED
;
13881 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5703_AX
||
13882 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_AX
)
13883 tp
->phy_flags
|= TG3_PHYFLG_ADC_BUG
;
13884 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
)
13885 tp
->phy_flags
|= TG3_PHYFLG_5704_A0_BUG
;
13887 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
13888 !(tp
->phy_flags
& TG3_PHYFLG_IS_FET
) &&
13889 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
13890 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_57780
&&
13891 !(tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
)) {
13892 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
13893 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
13894 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13895 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
) {
13896 if (tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5756
&&
13897 tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5722
)
13898 tp
->phy_flags
|= TG3_PHYFLG_JITTER_BUG
;
13899 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5755M
)
13900 tp
->phy_flags
|= TG3_PHYFLG_ADJUST_TRIM
;
13902 tp
->phy_flags
|= TG3_PHYFLG_BER_BUG
;
13905 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
13906 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
13907 tp
->phy_otp
= tg3_read_otp_phycfg(tp
);
13908 if (tp
->phy_otp
== 0)
13909 tp
->phy_otp
= TG3_OTP_DEFAULT
;
13912 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)
13913 tp
->mi_mode
= MAC_MI_MODE_500KHZ_CONST
;
13915 tp
->mi_mode
= MAC_MI_MODE_BASE
;
13917 tp
->coalesce_mode
= 0;
13918 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_AX
&&
13919 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_BX
)
13920 tp
->coalesce_mode
|= HOSTCC_MODE_32BYTE
;
13922 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
13923 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
13924 tp
->tg3_flags3
|= TG3_FLG3_USE_PHYLIB
;
13926 err
= tg3_mdio_init(tp
);
13930 /* Initialize data/descriptor byte/word swapping. */
13931 val
= tr32(GRC_MODE
);
13932 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
)
13933 val
&= (GRC_MODE_BYTE_SWAP_B2HRX_DATA
|
13934 GRC_MODE_WORD_SWAP_B2HRX_DATA
|
13935 GRC_MODE_B2HRX_ENABLE
|
13936 GRC_MODE_HTX2B_ENABLE
|
13937 GRC_MODE_HOST_STACKUP
);
13939 val
&= GRC_MODE_HOST_STACKUP
;
13941 tw32(GRC_MODE
, val
| tp
->grc_mode
);
13943 tg3_switch_clocks(tp
);
13945 /* Clear this out for sanity. */
13946 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
13948 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
13950 if ((pci_state_reg
& PCISTATE_CONV_PCI_MODE
) == 0 &&
13951 (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) == 0) {
13952 u32 chiprevid
= GET_CHIP_REV_ID(tp
->misc_host_ctrl
);
13954 if (chiprevid
== CHIPREV_ID_5701_A0
||
13955 chiprevid
== CHIPREV_ID_5701_B0
||
13956 chiprevid
== CHIPREV_ID_5701_B2
||
13957 chiprevid
== CHIPREV_ID_5701_B5
) {
13958 void __iomem
*sram_base
;
13960 /* Write some dummy words into the SRAM status block
13961 * area, see if it reads back correctly. If the return
13962 * value is bad, force enable the PCIX workaround.
13964 sram_base
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_STATS_BLK
;
13966 writel(0x00000000, sram_base
);
13967 writel(0x00000000, sram_base
+ 4);
13968 writel(0xffffffff, sram_base
+ 4);
13969 if (readl(sram_base
) != 0x00000000)
13970 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
13975 tg3_nvram_init(tp
);
13977 grc_misc_cfg
= tr32(GRC_MISC_CFG
);
13978 grc_misc_cfg
&= GRC_MISC_CFG_BOARD_ID_MASK
;
13980 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
13981 (grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788
||
13982 grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788M
))
13983 tp
->tg3_flags2
|= TG3_FLG2_IS_5788
;
13985 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
13986 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
))
13987 tp
->tg3_flags
|= TG3_FLAG_TAGGED_STATUS
;
13988 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
13989 tp
->coalesce_mode
|= (HOSTCC_MODE_CLRTICK_RXBD
|
13990 HOSTCC_MODE_CLRTICK_TXBD
);
13992 tp
->misc_host_ctrl
|= MISC_HOST_CTRL_TAGGED_STATUS
;
13993 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
13994 tp
->misc_host_ctrl
);
13997 /* Preserve the APE MAC_MODE bits */
13998 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
13999 tp
->mac_mode
= MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
14001 tp
->mac_mode
= TG3_DEF_MAC_MODE
;
14003 /* these are limited to 10/100 only */
14004 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
14005 (grc_misc_cfg
== 0x8000 || grc_misc_cfg
== 0x4000)) ||
14006 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
14007 tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
14008 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901
||
14009 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901_2
||
14010 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5705F
)) ||
14011 (tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
14012 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5751F
||
14013 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5753F
||
14014 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5787F
)) ||
14015 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
||
14016 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
||
14017 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
||
14018 (tp
->phy_flags
& TG3_PHYFLG_IS_FET
))
14019 tp
->phy_flags
|= TG3_PHYFLG_10_100_ONLY
;
14021 err
= tg3_phy_probe(tp
);
14023 dev_err(&tp
->pdev
->dev
, "phy probe failed, err %d\n", err
);
14024 /* ... but do not return immediately ... */
14029 tg3_read_fw_ver(tp
);
14031 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
14032 tp
->phy_flags
&= ~TG3_PHYFLG_USE_MI_INTERRUPT
;
14034 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
14035 tp
->phy_flags
|= TG3_PHYFLG_USE_MI_INTERRUPT
;
14037 tp
->phy_flags
&= ~TG3_PHYFLG_USE_MI_INTERRUPT
;
14040 /* 5700 {AX,BX} chips have a broken status block link
14041 * change bit implementation, so we must use the
14042 * status register in those cases.
14044 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
14045 tp
->tg3_flags
|= TG3_FLAG_USE_LINKCHG_REG
;
14047 tp
->tg3_flags
&= ~TG3_FLAG_USE_LINKCHG_REG
;
14049 /* The led_ctrl is set during tg3_phy_probe, here we might
14050 * have to force the link status polling mechanism based
14051 * upon subsystem IDs.
14053 if (tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
&&
14054 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
14055 !(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)) {
14056 tp
->phy_flags
|= TG3_PHYFLG_USE_MI_INTERRUPT
;
14057 tp
->tg3_flags
|= TG3_FLAG_USE_LINKCHG_REG
;
14060 /* For all SERDES we poll the MAC status register. */
14061 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
14062 tp
->tg3_flags
|= TG3_FLAG_POLL_SERDES
;
14064 tp
->tg3_flags
&= ~TG3_FLAG_POLL_SERDES
;
14066 tp
->rx_offset
= NET_IP_ALIGN
;
14067 tp
->rx_copy_thresh
= TG3_RX_COPY_THRESHOLD
;
14068 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
14069 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) != 0) {
14071 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
14072 tp
->rx_copy_thresh
= ~(u16
)0;
14076 tp
->rx_std_ring_mask
= TG3_RX_STD_RING_SIZE(tp
) - 1;
14077 tp
->rx_jmb_ring_mask
= TG3_RX_JMB_RING_SIZE(tp
) - 1;
14078 tp
->rx_ret_ring_mask
= tg3_rx_ret_ring_size(tp
) - 1;
14080 tp
->rx_std_max_post
= tp
->rx_std_ring_mask
+ 1;
14082 /* Increment the rx prod index on the rx std ring by at most
14083 * 8 for these chips to workaround hw errata.
14085 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
14086 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
14087 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
14088 tp
->rx_std_max_post
= 8;
14090 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
)
14091 tp
->pwrmgmt_thresh
= tr32(PCIE_PWR_MGMT_THRESH
) &
14092 PCIE_PWR_MGMT_L1_THRESH_MSK
;
14097 #ifdef CONFIG_SPARC
14098 static int __devinit
tg3_get_macaddr_sparc(struct tg3
*tp
)
14100 struct net_device
*dev
= tp
->dev
;
14101 struct pci_dev
*pdev
= tp
->pdev
;
14102 struct device_node
*dp
= pci_device_to_OF_node(pdev
);
14103 const unsigned char *addr
;
14106 addr
= of_get_property(dp
, "local-mac-address", &len
);
14107 if (addr
&& len
== 6) {
14108 memcpy(dev
->dev_addr
, addr
, 6);
14109 memcpy(dev
->perm_addr
, dev
->dev_addr
, 6);
14115 static int __devinit
tg3_get_default_macaddr_sparc(struct tg3
*tp
)
14117 struct net_device
*dev
= tp
->dev
;
14119 memcpy(dev
->dev_addr
, idprom
->id_ethaddr
, 6);
14120 memcpy(dev
->perm_addr
, idprom
->id_ethaddr
, 6);
14125 static int __devinit
tg3_get_device_address(struct tg3
*tp
)
14127 struct net_device
*dev
= tp
->dev
;
14128 u32 hi
, lo
, mac_offset
;
14131 #ifdef CONFIG_SPARC
14132 if (!tg3_get_macaddr_sparc(tp
))
14137 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) ||
14138 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
14139 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
14141 if (tg3_nvram_lock(tp
))
14142 tw32_f(NVRAM_CMD
, NVRAM_CMD_RESET
);
14144 tg3_nvram_unlock(tp
);
14145 } else if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) {
14146 if (PCI_FUNC(tp
->pdev
->devfn
) & 1)
14148 if (PCI_FUNC(tp
->pdev
->devfn
) > 1)
14149 mac_offset
+= 0x18c;
14150 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
14153 /* First try to get it from MAC address mailbox. */
14154 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_HIGH_MBOX
, &hi
);
14155 if ((hi
>> 16) == 0x484b) {
14156 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
14157 dev
->dev_addr
[1] = (hi
>> 0) & 0xff;
14159 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_LOW_MBOX
, &lo
);
14160 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
14161 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
14162 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
14163 dev
->dev_addr
[5] = (lo
>> 0) & 0xff;
14165 /* Some old bootcode may report a 0 MAC address in SRAM */
14166 addr_ok
= is_valid_ether_addr(&dev
->dev_addr
[0]);
14169 /* Next, try NVRAM. */
14170 if (!(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) &&
14171 !tg3_nvram_read_be32(tp
, mac_offset
+ 0, &hi
) &&
14172 !tg3_nvram_read_be32(tp
, mac_offset
+ 4, &lo
)) {
14173 memcpy(&dev
->dev_addr
[0], ((char *)&hi
) + 2, 2);
14174 memcpy(&dev
->dev_addr
[2], (char *)&lo
, sizeof(lo
));
14176 /* Finally just fetch it out of the MAC control regs. */
14178 hi
= tr32(MAC_ADDR_0_HIGH
);
14179 lo
= tr32(MAC_ADDR_0_LOW
);
14181 dev
->dev_addr
[5] = lo
& 0xff;
14182 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
14183 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
14184 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
14185 dev
->dev_addr
[1] = hi
& 0xff;
14186 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
14190 if (!is_valid_ether_addr(&dev
->dev_addr
[0])) {
14191 #ifdef CONFIG_SPARC
14192 if (!tg3_get_default_macaddr_sparc(tp
))
14197 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
14201 #define BOUNDARY_SINGLE_CACHELINE 1
14202 #define BOUNDARY_MULTI_CACHELINE 2
14204 static u32 __devinit
tg3_calc_dma_bndry(struct tg3
*tp
, u32 val
)
14206 int cacheline_size
;
14210 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
, &byte
);
14212 cacheline_size
= 1024;
14214 cacheline_size
= (int) byte
* 4;
14216 /* On 5703 and later chips, the boundary bits have no
14219 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
14220 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
&&
14221 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
14224 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
14225 goal
= BOUNDARY_MULTI_CACHELINE
;
14227 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
14228 goal
= BOUNDARY_SINGLE_CACHELINE
;
14234 if (tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
) {
14235 val
= goal
? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT
;
14242 /* PCI controllers on most RISC systems tend to disconnect
14243 * when a device tries to burst across a cache-line boundary.
14244 * Therefore, letting tg3 do so just wastes PCI bandwidth.
14246 * Unfortunately, for PCI-E there are only limited
14247 * write-side controls for this, and thus for reads
14248 * we will still get the disconnects. We'll also waste
14249 * these PCI cycles for both read and write for chips
14250 * other than 5700 and 5701 which do not implement the
14253 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
14254 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
14255 switch (cacheline_size
) {
14260 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
14261 val
|= (DMA_RWCTRL_READ_BNDRY_128_PCIX
|
14262 DMA_RWCTRL_WRITE_BNDRY_128_PCIX
);
14264 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
14265 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
14270 val
|= (DMA_RWCTRL_READ_BNDRY_256_PCIX
|
14271 DMA_RWCTRL_WRITE_BNDRY_256_PCIX
);
14275 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
14276 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
14279 } else if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
14280 switch (cacheline_size
) {
14284 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
14285 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
14286 val
|= DMA_RWCTRL_WRITE_BNDRY_64_PCIE
;
14292 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
14293 val
|= DMA_RWCTRL_WRITE_BNDRY_128_PCIE
;
14297 switch (cacheline_size
) {
14299 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
14300 val
|= (DMA_RWCTRL_READ_BNDRY_16
|
14301 DMA_RWCTRL_WRITE_BNDRY_16
);
14306 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
14307 val
|= (DMA_RWCTRL_READ_BNDRY_32
|
14308 DMA_RWCTRL_WRITE_BNDRY_32
);
14313 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
14314 val
|= (DMA_RWCTRL_READ_BNDRY_64
|
14315 DMA_RWCTRL_WRITE_BNDRY_64
);
14320 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
14321 val
|= (DMA_RWCTRL_READ_BNDRY_128
|
14322 DMA_RWCTRL_WRITE_BNDRY_128
);
14327 val
|= (DMA_RWCTRL_READ_BNDRY_256
|
14328 DMA_RWCTRL_WRITE_BNDRY_256
);
14331 val
|= (DMA_RWCTRL_READ_BNDRY_512
|
14332 DMA_RWCTRL_WRITE_BNDRY_512
);
14336 val
|= (DMA_RWCTRL_READ_BNDRY_1024
|
14337 DMA_RWCTRL_WRITE_BNDRY_1024
);
14346 static int __devinit
tg3_do_test_dma(struct tg3
*tp
, u32
*buf
, dma_addr_t buf_dma
, int size
, int to_device
)
14348 struct tg3_internal_buffer_desc test_desc
;
14349 u32 sram_dma_descs
;
14352 sram_dma_descs
= NIC_SRAM_DMA_DESC_POOL_BASE
;
14354 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
, 0);
14355 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
, 0);
14356 tw32(RDMAC_STATUS
, 0);
14357 tw32(WDMAC_STATUS
, 0);
14359 tw32(BUFMGR_MODE
, 0);
14360 tw32(FTQ_RESET
, 0);
14362 test_desc
.addr_hi
= ((u64
) buf_dma
) >> 32;
14363 test_desc
.addr_lo
= buf_dma
& 0xffffffff;
14364 test_desc
.nic_mbuf
= 0x00002100;
14365 test_desc
.len
= size
;
14368 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14369 * the *second* time the tg3 driver was getting loaded after an
14372 * Broadcom tells me:
14373 * ...the DMA engine is connected to the GRC block and a DMA
14374 * reset may affect the GRC block in some unpredictable way...
14375 * The behavior of resets to individual blocks has not been tested.
14377 * Broadcom noted the GRC reset will also reset all sub-components.
14380 test_desc
.cqid_sqid
= (13 << 8) | 2;
14382 tw32_f(RDMAC_MODE
, RDMAC_MODE_ENABLE
);
14385 test_desc
.cqid_sqid
= (16 << 8) | 7;
14387 tw32_f(WDMAC_MODE
, WDMAC_MODE_ENABLE
);
14390 test_desc
.flags
= 0x00000005;
14392 for (i
= 0; i
< (sizeof(test_desc
) / sizeof(u32
)); i
++) {
14395 val
= *(((u32
*)&test_desc
) + i
);
14396 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
,
14397 sram_dma_descs
+ (i
* sizeof(u32
)));
14398 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
14400 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
14403 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ
, sram_dma_descs
);
14405 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ
, sram_dma_descs
);
14408 for (i
= 0; i
< 40; i
++) {
14412 val
= tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
);
14414 val
= tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
);
14415 if ((val
& 0xffff) == sram_dma_descs
) {
14426 #define TEST_BUFFER_SIZE 0x2000
14428 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets
) = {
14429 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_UNI_N_PCI15
) },
14433 static int __devinit
tg3_test_dma(struct tg3
*tp
)
14435 dma_addr_t buf_dma
;
14436 u32
*buf
, saved_dma_rwctrl
;
14439 buf
= dma_alloc_coherent(&tp
->pdev
->dev
, TEST_BUFFER_SIZE
,
14440 &buf_dma
, GFP_KERNEL
);
14446 tp
->dma_rwctrl
= ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT
) |
14447 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT
));
14449 tp
->dma_rwctrl
= tg3_calc_dma_bndry(tp
, tp
->dma_rwctrl
);
14451 if (tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
)
14454 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
14455 /* DMA read watermark not used on PCIE */
14456 tp
->dma_rwctrl
|= 0x00180000;
14457 } else if (!(tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
14458 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
||
14459 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)
14460 tp
->dma_rwctrl
|= 0x003f0000;
14462 tp
->dma_rwctrl
|= 0x003f000f;
14464 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
14465 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
14466 u32 ccval
= (tr32(TG3PCI_CLOCK_CTRL
) & 0x1f);
14467 u32 read_water
= 0x7;
14469 /* If the 5704 is behind the EPB bridge, we can
14470 * do the less restrictive ONE_DMA workaround for
14471 * better performance.
14473 if ((tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) &&
14474 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
14475 tp
->dma_rwctrl
|= 0x8000;
14476 else if (ccval
== 0x6 || ccval
== 0x7)
14477 tp
->dma_rwctrl
|= DMA_RWCTRL_ONE_DMA
;
14479 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
)
14481 /* Set bit 23 to enable PCIX hw bug fix */
14483 (read_water
<< DMA_RWCTRL_READ_WATER_SHIFT
) |
14484 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT
) |
14486 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
) {
14487 /* 5780 always in PCIX mode */
14488 tp
->dma_rwctrl
|= 0x00144000;
14489 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
14490 /* 5714 always in PCIX mode */
14491 tp
->dma_rwctrl
|= 0x00148000;
14493 tp
->dma_rwctrl
|= 0x001b000f;
14497 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
14498 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
14499 tp
->dma_rwctrl
&= 0xfffffff0;
14501 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
14502 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
14503 /* Remove this if it causes problems for some boards. */
14504 tp
->dma_rwctrl
|= DMA_RWCTRL_USE_MEM_READ_MULT
;
14506 /* On 5700/5701 chips, we need to set this bit.
14507 * Otherwise the chip will issue cacheline transactions
14508 * to streamable DMA memory with not all the byte
14509 * enables turned on. This is an error on several
14510 * RISC PCI controllers, in particular sparc64.
14512 * On 5703/5704 chips, this bit has been reassigned
14513 * a different meaning. In particular, it is used
14514 * on those chips to enable a PCI-X workaround.
14516 tp
->dma_rwctrl
|= DMA_RWCTRL_ASSERT_ALL_BE
;
14519 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
14522 /* Unneeded, already done by tg3_get_invariants. */
14523 tg3_switch_clocks(tp
);
14526 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
14527 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
14530 /* It is best to perform DMA test with maximum write burst size
14531 * to expose the 5700/5701 write DMA bug.
14533 saved_dma_rwctrl
= tp
->dma_rwctrl
;
14534 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
14535 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
14540 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++)
14543 /* Send the buffer to the chip. */
14544 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 1);
14546 dev_err(&tp
->pdev
->dev
,
14547 "%s: Buffer write failed. err = %d\n",
14553 /* validate data reached card RAM correctly. */
14554 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
14556 tg3_read_mem(tp
, 0x2100 + (i
*4), &val
);
14557 if (le32_to_cpu(val
) != p
[i
]) {
14558 dev_err(&tp
->pdev
->dev
,
14559 "%s: Buffer corrupted on device! "
14560 "(%d != %d)\n", __func__
, val
, i
);
14561 /* ret = -ENODEV here? */
14566 /* Now read it back. */
14567 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 0);
14569 dev_err(&tp
->pdev
->dev
, "%s: Buffer read failed. "
14570 "err = %d\n", __func__
, ret
);
14575 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
14579 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
14580 DMA_RWCTRL_WRITE_BNDRY_16
) {
14581 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
14582 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
14583 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
14586 dev_err(&tp
->pdev
->dev
,
14587 "%s: Buffer corrupted on read back! "
14588 "(%d != %d)\n", __func__
, p
[i
], i
);
14594 if (i
== (TEST_BUFFER_SIZE
/ sizeof(u32
))) {
14600 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
14601 DMA_RWCTRL_WRITE_BNDRY_16
) {
14603 /* DMA test passed without adjusting DMA boundary,
14604 * now look for chipsets that are known to expose the
14605 * DMA bug without failing the test.
14607 if (pci_dev_present(tg3_dma_wait_state_chipsets
)) {
14608 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
14609 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
14611 /* Safe to use the calculated DMA boundary. */
14612 tp
->dma_rwctrl
= saved_dma_rwctrl
;
14615 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
14619 dma_free_coherent(&tp
->pdev
->dev
, TEST_BUFFER_SIZE
, buf
, buf_dma
);
14624 static void __devinit
tg3_init_bufmgr_config(struct tg3
*tp
)
14626 if (tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
) {
14627 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
14628 DEFAULT_MB_RDMA_LOW_WATER_5705
;
14629 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14630 DEFAULT_MB_MACRX_LOW_WATER_57765
;
14631 tp
->bufmgr_config
.mbuf_high_water
=
14632 DEFAULT_MB_HIGH_WATER_57765
;
14634 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
14635 DEFAULT_MB_RDMA_LOW_WATER_5705
;
14636 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
14637 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765
;
14638 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
14639 DEFAULT_MB_HIGH_WATER_JUMBO_57765
;
14640 } else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
14641 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
14642 DEFAULT_MB_RDMA_LOW_WATER_5705
;
14643 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14644 DEFAULT_MB_MACRX_LOW_WATER_5705
;
14645 tp
->bufmgr_config
.mbuf_high_water
=
14646 DEFAULT_MB_HIGH_WATER_5705
;
14647 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
14648 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14649 DEFAULT_MB_MACRX_LOW_WATER_5906
;
14650 tp
->bufmgr_config
.mbuf_high_water
=
14651 DEFAULT_MB_HIGH_WATER_5906
;
14654 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
14655 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780
;
14656 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
14657 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780
;
14658 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
14659 DEFAULT_MB_HIGH_WATER_JUMBO_5780
;
14661 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
14662 DEFAULT_MB_RDMA_LOW_WATER
;
14663 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14664 DEFAULT_MB_MACRX_LOW_WATER
;
14665 tp
->bufmgr_config
.mbuf_high_water
=
14666 DEFAULT_MB_HIGH_WATER
;
14668 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
14669 DEFAULT_MB_RDMA_LOW_WATER_JUMBO
;
14670 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
14671 DEFAULT_MB_MACRX_LOW_WATER_JUMBO
;
14672 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
14673 DEFAULT_MB_HIGH_WATER_JUMBO
;
14676 tp
->bufmgr_config
.dma_low_water
= DEFAULT_DMA_LOW_WATER
;
14677 tp
->bufmgr_config
.dma_high_water
= DEFAULT_DMA_HIGH_WATER
;
14680 static char * __devinit
tg3_phy_string(struct tg3
*tp
)
14682 switch (tp
->phy_id
& TG3_PHY_ID_MASK
) {
14683 case TG3_PHY_ID_BCM5400
: return "5400";
14684 case TG3_PHY_ID_BCM5401
: return "5401";
14685 case TG3_PHY_ID_BCM5411
: return "5411";
14686 case TG3_PHY_ID_BCM5701
: return "5701";
14687 case TG3_PHY_ID_BCM5703
: return "5703";
14688 case TG3_PHY_ID_BCM5704
: return "5704";
14689 case TG3_PHY_ID_BCM5705
: return "5705";
14690 case TG3_PHY_ID_BCM5750
: return "5750";
14691 case TG3_PHY_ID_BCM5752
: return "5752";
14692 case TG3_PHY_ID_BCM5714
: return "5714";
14693 case TG3_PHY_ID_BCM5780
: return "5780";
14694 case TG3_PHY_ID_BCM5755
: return "5755";
14695 case TG3_PHY_ID_BCM5787
: return "5787";
14696 case TG3_PHY_ID_BCM5784
: return "5784";
14697 case TG3_PHY_ID_BCM5756
: return "5722/5756";
14698 case TG3_PHY_ID_BCM5906
: return "5906";
14699 case TG3_PHY_ID_BCM5761
: return "5761";
14700 case TG3_PHY_ID_BCM5718C
: return "5718C";
14701 case TG3_PHY_ID_BCM5718S
: return "5718S";
14702 case TG3_PHY_ID_BCM57765
: return "57765";
14703 case TG3_PHY_ID_BCM5719C
: return "5719C";
14704 case TG3_PHY_ID_BCM5720C
: return "5720C";
14705 case TG3_PHY_ID_BCM8002
: return "8002/serdes";
14706 case 0: return "serdes";
14707 default: return "unknown";
14711 static char * __devinit
tg3_bus_string(struct tg3
*tp
, char *str
)
14713 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
14714 strcpy(str
, "PCI Express");
14716 } else if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
14717 u32 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
) & 0x1f;
14719 strcpy(str
, "PCIX:");
14721 if ((clock_ctrl
== 7) ||
14722 ((tr32(GRC_MISC_CFG
) & GRC_MISC_CFG_BOARD_ID_MASK
) ==
14723 GRC_MISC_CFG_BOARD_ID_5704CIOBE
))
14724 strcat(str
, "133MHz");
14725 else if (clock_ctrl
== 0)
14726 strcat(str
, "33MHz");
14727 else if (clock_ctrl
== 2)
14728 strcat(str
, "50MHz");
14729 else if (clock_ctrl
== 4)
14730 strcat(str
, "66MHz");
14731 else if (clock_ctrl
== 6)
14732 strcat(str
, "100MHz");
14734 strcpy(str
, "PCI:");
14735 if (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
)
14736 strcat(str
, "66MHz");
14738 strcat(str
, "33MHz");
14740 if (tp
->tg3_flags
& TG3_FLAG_PCI_32BIT
)
14741 strcat(str
, ":32-bit");
14743 strcat(str
, ":64-bit");
14747 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*tp
)
14749 struct pci_dev
*peer
;
14750 unsigned int func
, devnr
= tp
->pdev
->devfn
& ~7;
14752 for (func
= 0; func
< 8; func
++) {
14753 peer
= pci_get_slot(tp
->pdev
->bus
, devnr
| func
);
14754 if (peer
&& peer
!= tp
->pdev
)
14758 /* 5704 can be configured in single-port mode, set peer to
14759 * tp->pdev in that case.
14767 * We don't need to keep the refcount elevated; there's no way
14768 * to remove one half of this device without removing the other
14775 static void __devinit
tg3_init_coal(struct tg3
*tp
)
14777 struct ethtool_coalesce
*ec
= &tp
->coal
;
14779 memset(ec
, 0, sizeof(*ec
));
14780 ec
->cmd
= ETHTOOL_GCOALESCE
;
14781 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS
;
14782 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS
;
14783 ec
->rx_max_coalesced_frames
= LOW_RXMAX_FRAMES
;
14784 ec
->tx_max_coalesced_frames
= LOW_TXMAX_FRAMES
;
14785 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT
;
14786 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT
;
14787 ec
->rx_max_coalesced_frames_irq
= DEFAULT_RXCOAL_MAXF_INT
;
14788 ec
->tx_max_coalesced_frames_irq
= DEFAULT_TXCOAL_MAXF_INT
;
14789 ec
->stats_block_coalesce_usecs
= DEFAULT_STAT_COAL_TICKS
;
14791 if (tp
->coalesce_mode
& (HOSTCC_MODE_CLRTICK_RXBD
|
14792 HOSTCC_MODE_CLRTICK_TXBD
)) {
14793 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS_CLRTCKS
;
14794 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT_CLRTCKS
;
14795 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS_CLRTCKS
;
14796 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT_CLRTCKS
;
14799 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
14800 ec
->rx_coalesce_usecs_irq
= 0;
14801 ec
->tx_coalesce_usecs_irq
= 0;
14802 ec
->stats_block_coalesce_usecs
= 0;
14806 static const struct net_device_ops tg3_netdev_ops
= {
14807 .ndo_open
= tg3_open
,
14808 .ndo_stop
= tg3_close
,
14809 .ndo_start_xmit
= tg3_start_xmit
,
14810 .ndo_get_stats64
= tg3_get_stats64
,
14811 .ndo_validate_addr
= eth_validate_addr
,
14812 .ndo_set_multicast_list
= tg3_set_rx_mode
,
14813 .ndo_set_mac_address
= tg3_set_mac_addr
,
14814 .ndo_do_ioctl
= tg3_ioctl
,
14815 .ndo_tx_timeout
= tg3_tx_timeout
,
14816 .ndo_change_mtu
= tg3_change_mtu
,
14817 .ndo_fix_features
= tg3_fix_features
,
14818 #ifdef CONFIG_NET_POLL_CONTROLLER
14819 .ndo_poll_controller
= tg3_poll_controller
,
14823 static const struct net_device_ops tg3_netdev_ops_dma_bug
= {
14824 .ndo_open
= tg3_open
,
14825 .ndo_stop
= tg3_close
,
14826 .ndo_start_xmit
= tg3_start_xmit_dma_bug
,
14827 .ndo_get_stats64
= tg3_get_stats64
,
14828 .ndo_validate_addr
= eth_validate_addr
,
14829 .ndo_set_multicast_list
= tg3_set_rx_mode
,
14830 .ndo_set_mac_address
= tg3_set_mac_addr
,
14831 .ndo_do_ioctl
= tg3_ioctl
,
14832 .ndo_tx_timeout
= tg3_tx_timeout
,
14833 .ndo_change_mtu
= tg3_change_mtu
,
14834 #ifdef CONFIG_NET_POLL_CONTROLLER
14835 .ndo_poll_controller
= tg3_poll_controller
,
14839 static int __devinit
tg3_init_one(struct pci_dev
*pdev
,
14840 const struct pci_device_id
*ent
)
14842 struct net_device
*dev
;
14844 int i
, err
, pm_cap
;
14845 u32 sndmbx
, rcvmbx
, intmbx
;
14847 u64 dma_mask
, persist_dma_mask
;
14848 u32 hw_features
= 0;
14850 printk_once(KERN_INFO
"%s\n", version
);
14852 err
= pci_enable_device(pdev
);
14854 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
14858 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
14860 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
14861 goto err_out_disable_pdev
;
14864 pci_set_master(pdev
);
14866 /* Find power-management capability. */
14867 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
14869 dev_err(&pdev
->dev
,
14870 "Cannot find Power Management capability, aborting\n");
14872 goto err_out_free_res
;
14875 dev
= alloc_etherdev_mq(sizeof(*tp
), TG3_IRQ_MAX_VECS
);
14877 dev_err(&pdev
->dev
, "Etherdev alloc failed, aborting\n");
14879 goto err_out_free_res
;
14882 SET_NETDEV_DEV(dev
, &pdev
->dev
);
14884 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
14886 tp
= netdev_priv(dev
);
14889 tp
->pm_cap
= pm_cap
;
14890 tp
->rx_mode
= TG3_DEF_RX_MODE
;
14891 tp
->tx_mode
= TG3_DEF_TX_MODE
;
14894 tp
->msg_enable
= tg3_debug
;
14896 tp
->msg_enable
= TG3_DEF_MSG_ENABLE
;
14898 /* The word/byte swap controls here control register access byte
14899 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14902 tp
->misc_host_ctrl
=
14903 MISC_HOST_CTRL_MASK_PCI_INT
|
14904 MISC_HOST_CTRL_WORD_SWAP
|
14905 MISC_HOST_CTRL_INDIR_ACCESS
|
14906 MISC_HOST_CTRL_PCISTATE_RW
;
14908 /* The NONFRM (non-frame) byte/word swap controls take effect
14909 * on descriptor entries, anything which isn't packet data.
14911 * The StrongARM chips on the board (one for tx, one for rx)
14912 * are running in big-endian mode.
14914 tp
->grc_mode
= (GRC_MODE_WSWAP_DATA
| GRC_MODE_BSWAP_DATA
|
14915 GRC_MODE_WSWAP_NONFRM_DATA
);
14916 #ifdef __BIG_ENDIAN
14917 tp
->grc_mode
|= GRC_MODE_BSWAP_NONFRM_DATA
;
14919 spin_lock_init(&tp
->lock
);
14920 spin_lock_init(&tp
->indirect_lock
);
14921 INIT_WORK(&tp
->reset_task
, tg3_reset_task
);
14923 tp
->regs
= pci_ioremap_bar(pdev
, BAR_0
);
14925 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
14927 goto err_out_free_dev
;
14930 tp
->rx_pending
= TG3_DEF_RX_RING_PENDING
;
14931 tp
->rx_jumbo_pending
= TG3_DEF_RX_JUMBO_RING_PENDING
;
14933 dev
->ethtool_ops
= &tg3_ethtool_ops
;
14934 dev
->watchdog_timeo
= TG3_TX_TIMEOUT
;
14935 dev
->irq
= pdev
->irq
;
14937 err
= tg3_get_invariants(tp
);
14939 dev_err(&pdev
->dev
,
14940 "Problem fetching invariants of chip, aborting\n");
14941 goto err_out_iounmap
;
14944 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) &&
14945 !(tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
))
14946 dev
->netdev_ops
= &tg3_netdev_ops
;
14948 dev
->netdev_ops
= &tg3_netdev_ops_dma_bug
;
14951 /* The EPB bridge inside 5714, 5715, and 5780 and any
14952 * device behind the EPB cannot support DMA addresses > 40-bit.
14953 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14954 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14955 * do DMA address check in tg3_start_xmit().
14957 if (tp
->tg3_flags2
& TG3_FLG2_IS_5788
)
14958 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(32);
14959 else if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) {
14960 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(40);
14961 #ifdef CONFIG_HIGHMEM
14962 dma_mask
= DMA_BIT_MASK(64);
14965 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(64);
14967 /* Configure DMA attributes. */
14968 if (dma_mask
> DMA_BIT_MASK(32)) {
14969 err
= pci_set_dma_mask(pdev
, dma_mask
);
14971 dev
->features
|= NETIF_F_HIGHDMA
;
14972 err
= pci_set_consistent_dma_mask(pdev
,
14975 dev_err(&pdev
->dev
, "Unable to obtain 64 bit "
14976 "DMA for consistent allocations\n");
14977 goto err_out_iounmap
;
14981 if (err
|| dma_mask
== DMA_BIT_MASK(32)) {
14982 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
14984 dev_err(&pdev
->dev
,
14985 "No usable DMA configuration, aborting\n");
14986 goto err_out_iounmap
;
14990 tg3_init_bufmgr_config(tp
);
14992 /* Selectively allow TSO based on operating conditions */
14993 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) ||
14994 (tp
->fw_needed
&& !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)))
14995 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
14997 tp
->tg3_flags2
&= ~(TG3_FLG2_TSO_CAPABLE
| TG3_FLG2_TSO_BUG
);
14998 tp
->fw_needed
= NULL
;
15001 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
)
15002 tp
->fw_needed
= FIRMWARE_TG3
;
15004 /* TSO is on by default on chips that support hardware TSO.
15005 * Firmware TSO on older chips gives lower performance, so it
15006 * is off by default, but can be enabled using ethtool.
15008 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) &&
15009 (dev
->features
& NETIF_F_IP_CSUM
))
15010 hw_features
|= NETIF_F_TSO
;
15011 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
) ||
15012 (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
)) {
15013 if (dev
->features
& NETIF_F_IPV6_CSUM
)
15014 hw_features
|= NETIF_F_TSO6
;
15015 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) ||
15016 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
15017 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
15018 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) ||
15019 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
15020 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
15021 hw_features
|= NETIF_F_TSO_ECN
;
15024 dev
->hw_features
|= hw_features
;
15025 dev
->features
|= hw_features
;
15026 dev
->vlan_features
|= hw_features
;
15028 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
&&
15029 !(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
15030 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
)) {
15031 tp
->tg3_flags2
|= TG3_FLG2_MAX_RXPEND_64
;
15032 tp
->rx_pending
= 63;
15035 err
= tg3_get_device_address(tp
);
15037 dev_err(&pdev
->dev
,
15038 "Could not obtain valid ethernet address, aborting\n");
15039 goto err_out_iounmap
;
15042 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
15043 tp
->aperegs
= pci_ioremap_bar(pdev
, BAR_2
);
15044 if (!tp
->aperegs
) {
15045 dev_err(&pdev
->dev
,
15046 "Cannot map APE registers, aborting\n");
15048 goto err_out_iounmap
;
15051 tg3_ape_lock_init(tp
);
15053 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
15054 tg3_read_dash_ver(tp
);
15058 * Reset chip in case UNDI or EFI driver did not shutdown
15059 * DMA self test will enable WDMAC and we'll see (spurious)
15060 * pending DMA on the PCI bus at that point.
15062 if ((tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
) ||
15063 (tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
15064 tw32(MEMARB_MODE
, MEMARB_MODE_ENABLE
);
15065 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
15068 err
= tg3_test_dma(tp
);
15070 dev_err(&pdev
->dev
, "DMA engine test failed, aborting\n");
15071 goto err_out_apeunmap
;
15074 intmbx
= MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
;
15075 rcvmbx
= MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
;
15076 sndmbx
= MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
;
15077 for (i
= 0; i
< tp
->irq_max
; i
++) {
15078 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
15081 tnapi
->tx_pending
= TG3_DEF_TX_RING_PENDING
;
15083 tnapi
->int_mbox
= intmbx
;
15089 tnapi
->consmbox
= rcvmbx
;
15090 tnapi
->prodmbox
= sndmbx
;
15093 tnapi
->coal_now
= HOSTCC_MODE_COAL_VEC1_NOW
<< (i
- 1);
15095 tnapi
->coal_now
= HOSTCC_MODE_NOW
;
15097 if (!(tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
))
15101 * If we support MSIX, we'll be using RSS. If we're using
15102 * RSS, the first vector only handles link interrupts and the
15103 * remaining vectors handle rx and tx interrupts. Reuse the
15104 * mailbox values for the next iteration. The values we setup
15105 * above are still useful for the single vectored mode.
15120 pci_set_drvdata(pdev
, dev
);
15122 err
= register_netdev(dev
);
15124 dev_err(&pdev
->dev
, "Cannot register net device, aborting\n");
15125 goto err_out_apeunmap
;
15128 netdev_info(dev
, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
15129 tp
->board_part_number
,
15130 tp
->pci_chip_rev_id
,
15131 tg3_bus_string(tp
, str
),
15134 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) {
15135 struct phy_device
*phydev
;
15136 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
15138 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
15139 phydev
->drv
->name
, dev_name(&phydev
->dev
));
15143 if (tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)
15144 ethtype
= "10/100Base-TX";
15145 else if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
15146 ethtype
= "1000Base-SX";
15148 ethtype
= "10/100/1000Base-T";
15150 netdev_info(dev
, "attached PHY is %s (%s Ethernet) "
15151 "(WireSpeed[%d])\n", tg3_phy_string(tp
), ethtype
,
15152 (tp
->phy_flags
& TG3_PHYFLG_NO_ETH_WIRE_SPEED
) == 0);
15155 netdev_info(dev
, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
15156 (dev
->features
& NETIF_F_RXCSUM
) != 0,
15157 (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) != 0,
15158 (tp
->phy_flags
& TG3_PHYFLG_USE_MI_INTERRUPT
) != 0,
15159 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0,
15160 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) != 0);
15161 netdev_info(dev
, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
15163 pdev
->dma_mask
== DMA_BIT_MASK(32) ? 32 :
15164 ((u64
)pdev
->dma_mask
) == DMA_BIT_MASK(40) ? 40 : 64);
15170 iounmap(tp
->aperegs
);
15171 tp
->aperegs
= NULL
;
15184 pci_release_regions(pdev
);
15186 err_out_disable_pdev
:
15187 pci_disable_device(pdev
);
15188 pci_set_drvdata(pdev
, NULL
);
15192 static void __devexit
tg3_remove_one(struct pci_dev
*pdev
)
15194 struct net_device
*dev
= pci_get_drvdata(pdev
);
15197 struct tg3
*tp
= netdev_priv(dev
);
15200 release_firmware(tp
->fw
);
15202 cancel_work_sync(&tp
->reset_task
);
15204 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
15209 unregister_netdev(dev
);
15211 iounmap(tp
->aperegs
);
15212 tp
->aperegs
= NULL
;
15219 pci_release_regions(pdev
);
15220 pci_disable_device(pdev
);
15221 pci_set_drvdata(pdev
, NULL
);
15225 #ifdef CONFIG_PM_SLEEP
15226 static int tg3_suspend(struct device
*device
)
15228 struct pci_dev
*pdev
= to_pci_dev(device
);
15229 struct net_device
*dev
= pci_get_drvdata(pdev
);
15230 struct tg3
*tp
= netdev_priv(dev
);
15233 if (!netif_running(dev
))
15236 flush_work_sync(&tp
->reset_task
);
15238 tg3_netif_stop(tp
);
15240 del_timer_sync(&tp
->timer
);
15242 tg3_full_lock(tp
, 1);
15243 tg3_disable_ints(tp
);
15244 tg3_full_unlock(tp
);
15246 netif_device_detach(dev
);
15248 tg3_full_lock(tp
, 0);
15249 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
15250 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
15251 tg3_full_unlock(tp
);
15253 err
= tg3_power_down_prepare(tp
);
15257 tg3_full_lock(tp
, 0);
15259 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
15260 err2
= tg3_restart_hw(tp
, 1);
15264 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
15265 add_timer(&tp
->timer
);
15267 netif_device_attach(dev
);
15268 tg3_netif_start(tp
);
15271 tg3_full_unlock(tp
);
15280 static int tg3_resume(struct device
*device
)
15282 struct pci_dev
*pdev
= to_pci_dev(device
);
15283 struct net_device
*dev
= pci_get_drvdata(pdev
);
15284 struct tg3
*tp
= netdev_priv(dev
);
15287 if (!netif_running(dev
))
15290 netif_device_attach(dev
);
15292 tg3_full_lock(tp
, 0);
15294 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
15295 err
= tg3_restart_hw(tp
, 1);
15299 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
15300 add_timer(&tp
->timer
);
15302 tg3_netif_start(tp
);
15305 tg3_full_unlock(tp
);
15313 static SIMPLE_DEV_PM_OPS(tg3_pm_ops
, tg3_suspend
, tg3_resume
);
15314 #define TG3_PM_OPS (&tg3_pm_ops)
15318 #define TG3_PM_OPS NULL
15320 #endif /* CONFIG_PM_SLEEP */
15322 static struct pci_driver tg3_driver
= {
15323 .name
= DRV_MODULE_NAME
,
15324 .id_table
= tg3_pci_tbl
,
15325 .probe
= tg3_init_one
,
15326 .remove
= __devexit_p(tg3_remove_one
),
15327 .driver
.pm
= TG3_PM_OPS
,
15330 static int __init
tg3_init(void)
15332 return pci_register_driver(&tg3_driver
);
15335 static void __exit
tg3_cleanup(void)
15337 pci_unregister_driver(&tg3_driver
);
15340 module_init(tg3_init
);
15341 module_exit(tg3_cleanup
);