2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/eeprom_93cx6.h>
37 #include "rt2x00pci.h"
41 * Allow hardware encryption to be disabled.
43 static int modparam_nohwcrypt
= 0;
44 module_param_named(nohwcrypt
, modparam_nohwcrypt
, bool, S_IRUGO
);
45 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
49 * BBP and RF register require indirect register access,
50 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
51 * These indirect registers work with busy bits,
52 * and we will try maximal REGISTER_BUSY_COUNT times to access
53 * the register while taking a REGISTER_BUSY_DELAY us delay
54 * between each attempt. When the busy bit is still set at that time,
55 * the access attempt is considered to have failed,
56 * and we will print an error.
58 #define WAIT_FOR_BBP(__dev, __reg) \
59 rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
60 #define WAIT_FOR_RF(__dev, __reg) \
61 rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
62 #define WAIT_FOR_MCU(__dev, __reg) \
63 rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
64 H2M_MAILBOX_CSR_OWNER, (__reg))
66 static void rt61pci_bbp_write(struct rt2x00_dev
*rt2x00dev
,
67 const unsigned int word
, const u8 value
)
71 mutex_lock(&rt2x00dev
->csr_mutex
);
74 * Wait until the BBP becomes available, afterwards we
75 * can safely write the new data into the register.
77 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
79 rt2x00_set_field32(®
, PHY_CSR3_VALUE
, value
);
80 rt2x00_set_field32(®
, PHY_CSR3_REGNUM
, word
);
81 rt2x00_set_field32(®
, PHY_CSR3_BUSY
, 1);
82 rt2x00_set_field32(®
, PHY_CSR3_READ_CONTROL
, 0);
84 rt2x00pci_register_write(rt2x00dev
, PHY_CSR3
, reg
);
87 mutex_unlock(&rt2x00dev
->csr_mutex
);
90 static void rt61pci_bbp_read(struct rt2x00_dev
*rt2x00dev
,
91 const unsigned int word
, u8
*value
)
95 mutex_lock(&rt2x00dev
->csr_mutex
);
98 * Wait until the BBP becomes available, afterwards we
99 * can safely write the read request into the register.
100 * After the data has been written, we wait until hardware
101 * returns the correct value, if at any time the register
102 * doesn't become available in time, reg will be 0xffffffff
103 * which means we return 0xff to the caller.
105 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
107 rt2x00_set_field32(®
, PHY_CSR3_REGNUM
, word
);
108 rt2x00_set_field32(®
, PHY_CSR3_BUSY
, 1);
109 rt2x00_set_field32(®
, PHY_CSR3_READ_CONTROL
, 1);
111 rt2x00pci_register_write(rt2x00dev
, PHY_CSR3
, reg
);
113 WAIT_FOR_BBP(rt2x00dev
, ®
);
116 *value
= rt2x00_get_field32(reg
, PHY_CSR3_VALUE
);
118 mutex_unlock(&rt2x00dev
->csr_mutex
);
121 static void rt61pci_rf_write(struct rt2x00_dev
*rt2x00dev
,
122 const unsigned int word
, const u32 value
)
126 mutex_lock(&rt2x00dev
->csr_mutex
);
129 * Wait until the RF becomes available, afterwards we
130 * can safely write the new data into the register.
132 if (WAIT_FOR_RF(rt2x00dev
, ®
)) {
134 rt2x00_set_field32(®
, PHY_CSR4_VALUE
, value
);
135 rt2x00_set_field32(®
, PHY_CSR4_NUMBER_OF_BITS
, 21);
136 rt2x00_set_field32(®
, PHY_CSR4_IF_SELECT
, 0);
137 rt2x00_set_field32(®
, PHY_CSR4_BUSY
, 1);
139 rt2x00pci_register_write(rt2x00dev
, PHY_CSR4
, reg
);
140 rt2x00_rf_write(rt2x00dev
, word
, value
);
143 mutex_unlock(&rt2x00dev
->csr_mutex
);
146 static void rt61pci_mcu_request(struct rt2x00_dev
*rt2x00dev
,
147 const u8 command
, const u8 token
,
148 const u8 arg0
, const u8 arg1
)
152 mutex_lock(&rt2x00dev
->csr_mutex
);
155 * Wait until the MCU becomes available, afterwards we
156 * can safely write the new data into the register.
158 if (WAIT_FOR_MCU(rt2x00dev
, ®
)) {
159 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_OWNER
, 1);
160 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_CMD_TOKEN
, token
);
161 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG0
, arg0
);
162 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG1
, arg1
);
163 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, reg
);
165 rt2x00pci_register_read(rt2x00dev
, HOST_CMD_CSR
, ®
);
166 rt2x00_set_field32(®
, HOST_CMD_CSR_HOST_COMMAND
, command
);
167 rt2x00_set_field32(®
, HOST_CMD_CSR_INTERRUPT_MCU
, 1);
168 rt2x00pci_register_write(rt2x00dev
, HOST_CMD_CSR
, reg
);
171 mutex_unlock(&rt2x00dev
->csr_mutex
);
175 static void rt61pci_eepromregister_read(struct eeprom_93cx6
*eeprom
)
177 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
180 rt2x00pci_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
182 eeprom
->reg_data_in
= !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_IN
);
183 eeprom
->reg_data_out
= !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_OUT
);
184 eeprom
->reg_data_clock
=
185 !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_CLOCK
);
186 eeprom
->reg_chip_select
=
187 !!rt2x00_get_field32(reg
, E2PROM_CSR_CHIP_SELECT
);
190 static void rt61pci_eepromregister_write(struct eeprom_93cx6
*eeprom
)
192 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
195 rt2x00_set_field32(®
, E2PROM_CSR_DATA_IN
, !!eeprom
->reg_data_in
);
196 rt2x00_set_field32(®
, E2PROM_CSR_DATA_OUT
, !!eeprom
->reg_data_out
);
197 rt2x00_set_field32(®
, E2PROM_CSR_DATA_CLOCK
,
198 !!eeprom
->reg_data_clock
);
199 rt2x00_set_field32(®
, E2PROM_CSR_CHIP_SELECT
,
200 !!eeprom
->reg_chip_select
);
202 rt2x00pci_register_write(rt2x00dev
, E2PROM_CSR
, reg
);
205 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
206 static const struct rt2x00debug rt61pci_rt2x00debug
= {
207 .owner
= THIS_MODULE
,
209 .read
= rt2x00pci_register_read
,
210 .write
= rt2x00pci_register_write
,
211 .flags
= RT2X00DEBUGFS_OFFSET
,
212 .word_base
= CSR_REG_BASE
,
213 .word_size
= sizeof(u32
),
214 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
217 .read
= rt2x00_eeprom_read
,
218 .write
= rt2x00_eeprom_write
,
219 .word_base
= EEPROM_BASE
,
220 .word_size
= sizeof(u16
),
221 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
224 .read
= rt61pci_bbp_read
,
225 .write
= rt61pci_bbp_write
,
226 .word_base
= BBP_BASE
,
227 .word_size
= sizeof(u8
),
228 .word_count
= BBP_SIZE
/ sizeof(u8
),
231 .read
= rt2x00_rf_read
,
232 .write
= rt61pci_rf_write
,
233 .word_base
= RF_BASE
,
234 .word_size
= sizeof(u32
),
235 .word_count
= RF_SIZE
/ sizeof(u32
),
238 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
240 static int rt61pci_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
244 rt2x00pci_register_read(rt2x00dev
, MAC_CSR13
, ®
);
245 return rt2x00_get_field32(reg
, MAC_CSR13_BIT5
);
248 #ifdef CONFIG_RT2X00_LIB_LEDS
249 static void rt61pci_brightness_set(struct led_classdev
*led_cdev
,
250 enum led_brightness brightness
)
252 struct rt2x00_led
*led
=
253 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
254 unsigned int enabled
= brightness
!= LED_OFF
;
255 unsigned int a_mode
=
256 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
257 unsigned int bg_mode
=
258 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
260 if (led
->type
== LED_TYPE_RADIO
) {
261 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
262 MCU_LEDCS_RADIO_STATUS
, enabled
);
264 rt61pci_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff,
265 (led
->rt2x00dev
->led_mcu_reg
& 0xff),
266 ((led
->rt2x00dev
->led_mcu_reg
>> 8)));
267 } else if (led
->type
== LED_TYPE_ASSOC
) {
268 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
269 MCU_LEDCS_LINK_BG_STATUS
, bg_mode
);
270 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
271 MCU_LEDCS_LINK_A_STATUS
, a_mode
);
273 rt61pci_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff,
274 (led
->rt2x00dev
->led_mcu_reg
& 0xff),
275 ((led
->rt2x00dev
->led_mcu_reg
>> 8)));
276 } else if (led
->type
== LED_TYPE_QUALITY
) {
278 * The brightness is divided into 6 levels (0 - 5),
279 * this means we need to convert the brightness
280 * argument into the matching level within that range.
282 rt61pci_mcu_request(led
->rt2x00dev
, MCU_LED_STRENGTH
, 0xff,
283 brightness
/ (LED_FULL
/ 6), 0);
287 static int rt61pci_blink_set(struct led_classdev
*led_cdev
,
288 unsigned long *delay_on
,
289 unsigned long *delay_off
)
291 struct rt2x00_led
*led
=
292 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
295 rt2x00pci_register_read(led
->rt2x00dev
, MAC_CSR14
, ®
);
296 rt2x00_set_field32(®
, MAC_CSR14_ON_PERIOD
, *delay_on
);
297 rt2x00_set_field32(®
, MAC_CSR14_OFF_PERIOD
, *delay_off
);
298 rt2x00pci_register_write(led
->rt2x00dev
, MAC_CSR14
, reg
);
303 static void rt61pci_init_led(struct rt2x00_dev
*rt2x00dev
,
304 struct rt2x00_led
*led
,
307 led
->rt2x00dev
= rt2x00dev
;
309 led
->led_dev
.brightness_set
= rt61pci_brightness_set
;
310 led
->led_dev
.blink_set
= rt61pci_blink_set
;
311 led
->flags
= LED_INITIALIZED
;
313 #endif /* CONFIG_RT2X00_LIB_LEDS */
316 * Configuration handlers.
318 static int rt61pci_config_shared_key(struct rt2x00_dev
*rt2x00dev
,
319 struct rt2x00lib_crypto
*crypto
,
320 struct ieee80211_key_conf
*key
)
322 struct hw_key_entry key_entry
;
323 struct rt2x00_field32 field
;
327 if (crypto
->cmd
== SET_KEY
) {
329 * rt2x00lib can't determine the correct free
330 * key_idx for shared keys. We have 1 register
331 * with key valid bits. The goal is simple, read
332 * the register, if that is full we have no slots
334 * Note that each BSS is allowed to have up to 4
335 * shared keys, so put a mask over the allowed
338 mask
= (0xf << crypto
->bssidx
);
340 rt2x00pci_register_read(rt2x00dev
, SEC_CSR0
, ®
);
343 if (reg
&& reg
== mask
)
346 key
->hw_key_idx
+= reg
? ffz(reg
) : 0;
349 * Upload key to hardware
351 memcpy(key_entry
.key
, crypto
->key
,
352 sizeof(key_entry
.key
));
353 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
354 sizeof(key_entry
.tx_mic
));
355 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
356 sizeof(key_entry
.rx_mic
));
358 reg
= SHARED_KEY_ENTRY(key
->hw_key_idx
);
359 rt2x00pci_register_multiwrite(rt2x00dev
, reg
,
360 &key_entry
, sizeof(key_entry
));
363 * The cipher types are stored over 2 registers.
364 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
365 * bssidx 1 and 2 keys are stored in SEC_CSR5.
366 * Using the correct defines correctly will cause overhead,
367 * so just calculate the correct offset.
369 if (key
->hw_key_idx
< 8) {
370 field
.bit_offset
= (3 * key
->hw_key_idx
);
371 field
.bit_mask
= 0x7 << field
.bit_offset
;
373 rt2x00pci_register_read(rt2x00dev
, SEC_CSR1
, ®
);
374 rt2x00_set_field32(®
, field
, crypto
->cipher
);
375 rt2x00pci_register_write(rt2x00dev
, SEC_CSR1
, reg
);
377 field
.bit_offset
= (3 * (key
->hw_key_idx
- 8));
378 field
.bit_mask
= 0x7 << field
.bit_offset
;
380 rt2x00pci_register_read(rt2x00dev
, SEC_CSR5
, ®
);
381 rt2x00_set_field32(®
, field
, crypto
->cipher
);
382 rt2x00pci_register_write(rt2x00dev
, SEC_CSR5
, reg
);
386 * The driver does not support the IV/EIV generation
387 * in hardware. However it doesn't support the IV/EIV
388 * inside the ieee80211 frame either, but requires it
389 * to be provided separately for the descriptor.
390 * rt2x00lib will cut the IV/EIV data out of all frames
391 * given to us by mac80211, but we must tell mac80211
392 * to generate the IV/EIV data.
394 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
398 * SEC_CSR0 contains only single-bit fields to indicate
399 * a particular key is valid. Because using the FIELD32()
400 * defines directly will cause a lot of overhead, we use
401 * a calculation to determine the correct bit directly.
403 mask
= 1 << key
->hw_key_idx
;
405 rt2x00pci_register_read(rt2x00dev
, SEC_CSR0
, ®
);
406 if (crypto
->cmd
== SET_KEY
)
408 else if (crypto
->cmd
== DISABLE_KEY
)
410 rt2x00pci_register_write(rt2x00dev
, SEC_CSR0
, reg
);
415 static int rt61pci_config_pairwise_key(struct rt2x00_dev
*rt2x00dev
,
416 struct rt2x00lib_crypto
*crypto
,
417 struct ieee80211_key_conf
*key
)
419 struct hw_pairwise_ta_entry addr_entry
;
420 struct hw_key_entry key_entry
;
424 if (crypto
->cmd
== SET_KEY
) {
426 * rt2x00lib can't determine the correct free
427 * key_idx for pairwise keys. We have 2 registers
428 * with key valid bits. The goal is simple: read
429 * the first register. If that is full, move to
431 * When both registers are full, we drop the key.
432 * Otherwise, we use the first invalid entry.
434 rt2x00pci_register_read(rt2x00dev
, SEC_CSR2
, ®
);
435 if (reg
&& reg
== ~0) {
436 key
->hw_key_idx
= 32;
437 rt2x00pci_register_read(rt2x00dev
, SEC_CSR3
, ®
);
438 if (reg
&& reg
== ~0)
442 key
->hw_key_idx
+= reg
? ffz(reg
) : 0;
445 * Upload key to hardware
447 memcpy(key_entry
.key
, crypto
->key
,
448 sizeof(key_entry
.key
));
449 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
450 sizeof(key_entry
.tx_mic
));
451 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
452 sizeof(key_entry
.rx_mic
));
454 memset(&addr_entry
, 0, sizeof(addr_entry
));
455 memcpy(&addr_entry
, crypto
->address
, ETH_ALEN
);
456 addr_entry
.cipher
= crypto
->cipher
;
458 reg
= PAIRWISE_KEY_ENTRY(key
->hw_key_idx
);
459 rt2x00pci_register_multiwrite(rt2x00dev
, reg
,
460 &key_entry
, sizeof(key_entry
));
462 reg
= PAIRWISE_TA_ENTRY(key
->hw_key_idx
);
463 rt2x00pci_register_multiwrite(rt2x00dev
, reg
,
464 &addr_entry
, sizeof(addr_entry
));
467 * Enable pairwise lookup table for given BSS idx.
468 * Without this, received frames will not be decrypted
471 rt2x00pci_register_read(rt2x00dev
, SEC_CSR4
, ®
);
472 reg
|= (1 << crypto
->bssidx
);
473 rt2x00pci_register_write(rt2x00dev
, SEC_CSR4
, reg
);
476 * The driver does not support the IV/EIV generation
477 * in hardware. However it doesn't support the IV/EIV
478 * inside the ieee80211 frame either, but requires it
479 * to be provided seperately for the descriptor.
480 * rt2x00lib will cut the IV/EIV data out of all frames
481 * given to us by mac80211, but we must tell mac80211
482 * to generate the IV/EIV data.
484 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
488 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
489 * a particular key is valid. Because using the FIELD32()
490 * defines directly will cause a lot of overhead, we use
491 * a calculation to determine the correct bit directly.
493 if (key
->hw_key_idx
< 32) {
494 mask
= 1 << key
->hw_key_idx
;
496 rt2x00pci_register_read(rt2x00dev
, SEC_CSR2
, ®
);
497 if (crypto
->cmd
== SET_KEY
)
499 else if (crypto
->cmd
== DISABLE_KEY
)
501 rt2x00pci_register_write(rt2x00dev
, SEC_CSR2
, reg
);
503 mask
= 1 << (key
->hw_key_idx
- 32);
505 rt2x00pci_register_read(rt2x00dev
, SEC_CSR3
, ®
);
506 if (crypto
->cmd
== SET_KEY
)
508 else if (crypto
->cmd
== DISABLE_KEY
)
510 rt2x00pci_register_write(rt2x00dev
, SEC_CSR3
, reg
);
516 static void rt61pci_config_filter(struct rt2x00_dev
*rt2x00dev
,
517 const unsigned int filter_flags
)
522 * Start configuration steps.
523 * Note that the version error will always be dropped
524 * and broadcast frames will always be accepted since
525 * there is no filter for it at this time.
527 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
528 rt2x00_set_field32(®
, TXRX_CSR0_DROP_CRC
,
529 !(filter_flags
& FIF_FCSFAIL
));
530 rt2x00_set_field32(®
, TXRX_CSR0_DROP_PHYSICAL
,
531 !(filter_flags
& FIF_PLCPFAIL
));
532 rt2x00_set_field32(®
, TXRX_CSR0_DROP_CONTROL
,
533 !(filter_flags
& (FIF_CONTROL
| FIF_PSPOLL
)));
534 rt2x00_set_field32(®
, TXRX_CSR0_DROP_NOT_TO_ME
,
535 !(filter_flags
& FIF_PROMISC_IN_BSS
));
536 rt2x00_set_field32(®
, TXRX_CSR0_DROP_TO_DS
,
537 !(filter_flags
& FIF_PROMISC_IN_BSS
) &&
538 !rt2x00dev
->intf_ap_count
);
539 rt2x00_set_field32(®
, TXRX_CSR0_DROP_VERSION_ERROR
, 1);
540 rt2x00_set_field32(®
, TXRX_CSR0_DROP_MULTICAST
,
541 !(filter_flags
& FIF_ALLMULTI
));
542 rt2x00_set_field32(®
, TXRX_CSR0_DROP_BROADCAST
, 0);
543 rt2x00_set_field32(®
, TXRX_CSR0_DROP_ACK_CTS
,
544 !(filter_flags
& FIF_CONTROL
));
545 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
548 static void rt61pci_config_intf(struct rt2x00_dev
*rt2x00dev
,
549 struct rt2x00_intf
*intf
,
550 struct rt2x00intf_conf
*conf
,
551 const unsigned int flags
)
553 unsigned int beacon_base
;
556 if (flags
& CONFIG_UPDATE_TYPE
) {
558 * Clear current synchronisation setup.
559 * For the Beacon base registers, we only need to clear
560 * the first byte since that byte contains the VALID and OWNER
561 * bits which (when set to 0) will invalidate the entire beacon.
563 beacon_base
= HW_BEACON_OFFSET(intf
->beacon
->entry_idx
);
564 rt2x00pci_register_write(rt2x00dev
, beacon_base
, 0);
567 * Enable synchronisation.
569 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
570 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 1);
571 rt2x00_set_field32(®
, TXRX_CSR9_TSF_SYNC
, conf
->sync
);
572 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 1);
573 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
576 if (flags
& CONFIG_UPDATE_MAC
) {
577 reg
= le32_to_cpu(conf
->mac
[1]);
578 rt2x00_set_field32(®
, MAC_CSR3_UNICAST_TO_ME_MASK
, 0xff);
579 conf
->mac
[1] = cpu_to_le32(reg
);
581 rt2x00pci_register_multiwrite(rt2x00dev
, MAC_CSR2
,
582 conf
->mac
, sizeof(conf
->mac
));
585 if (flags
& CONFIG_UPDATE_BSSID
) {
586 reg
= le32_to_cpu(conf
->bssid
[1]);
587 rt2x00_set_field32(®
, MAC_CSR5_BSS_ID_MASK
, 3);
588 conf
->bssid
[1] = cpu_to_le32(reg
);
590 rt2x00pci_register_multiwrite(rt2x00dev
, MAC_CSR4
,
591 conf
->bssid
, sizeof(conf
->bssid
));
595 static void rt61pci_config_erp(struct rt2x00_dev
*rt2x00dev
,
596 struct rt2x00lib_erp
*erp
)
600 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
601 rt2x00_set_field32(®
, TXRX_CSR0_RX_ACK_TIMEOUT
, 0x32);
602 rt2x00_set_field32(®
, TXRX_CSR0_TSF_OFFSET
, IEEE80211_HEADER
);
603 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
605 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
606 rt2x00_set_field32(®
, TXRX_CSR4_AUTORESPOND_ENABLE
, 1);
607 rt2x00_set_field32(®
, TXRX_CSR4_AUTORESPOND_PREAMBLE
,
608 !!erp
->short_preamble
);
609 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
611 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR5
, erp
->basic_rates
);
613 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
614 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_INTERVAL
,
615 erp
->beacon_int
* 16);
616 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
618 rt2x00pci_register_read(rt2x00dev
, MAC_CSR9
, ®
);
619 rt2x00_set_field32(®
, MAC_CSR9_SLOT_TIME
, erp
->slot_time
);
620 rt2x00pci_register_write(rt2x00dev
, MAC_CSR9
, reg
);
622 rt2x00pci_register_read(rt2x00dev
, MAC_CSR8
, ®
);
623 rt2x00_set_field32(®
, MAC_CSR8_SIFS
, erp
->sifs
);
624 rt2x00_set_field32(®
, MAC_CSR8_SIFS_AFTER_RX_OFDM
, 3);
625 rt2x00_set_field32(®
, MAC_CSR8_EIFS
, erp
->eifs
);
626 rt2x00pci_register_write(rt2x00dev
, MAC_CSR8
, reg
);
629 static void rt61pci_config_antenna_5x(struct rt2x00_dev
*rt2x00dev
,
630 struct antenna_setup
*ant
)
636 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
637 rt61pci_bbp_read(rt2x00dev
, 4, &r4
);
638 rt61pci_bbp_read(rt2x00dev
, 77, &r77
);
640 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
,
641 rt2x00_rf(&rt2x00dev
->chip
, RF5325
));
644 * Configure the RX antenna.
647 case ANTENNA_HW_DIVERSITY
:
648 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 2);
649 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
,
650 (rt2x00dev
->curr_band
!= IEEE80211_BAND_5GHZ
));
653 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
654 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
, 0);
655 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
)
656 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
658 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
662 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
663 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
, 0);
664 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
)
665 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
667 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
671 rt61pci_bbp_write(rt2x00dev
, 77, r77
);
672 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
673 rt61pci_bbp_write(rt2x00dev
, 4, r4
);
676 static void rt61pci_config_antenna_2x(struct rt2x00_dev
*rt2x00dev
,
677 struct antenna_setup
*ant
)
683 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
684 rt61pci_bbp_read(rt2x00dev
, 4, &r4
);
685 rt61pci_bbp_read(rt2x00dev
, 77, &r77
);
687 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
,
688 rt2x00_rf(&rt2x00dev
->chip
, RF2529
));
689 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
,
690 !test_bit(CONFIG_FRAME_TYPE
, &rt2x00dev
->flags
));
693 * Configure the RX antenna.
696 case ANTENNA_HW_DIVERSITY
:
697 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 2);
700 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
701 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
705 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
706 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
710 rt61pci_bbp_write(rt2x00dev
, 77, r77
);
711 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
712 rt61pci_bbp_write(rt2x00dev
, 4, r4
);
715 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev
*rt2x00dev
,
716 const int p1
, const int p2
)
720 rt2x00pci_register_read(rt2x00dev
, MAC_CSR13
, ®
);
722 rt2x00_set_field32(®
, MAC_CSR13_BIT4
, p1
);
723 rt2x00_set_field32(®
, MAC_CSR13_BIT12
, 0);
725 rt2x00_set_field32(®
, MAC_CSR13_BIT3
, !p2
);
726 rt2x00_set_field32(®
, MAC_CSR13_BIT11
, 0);
728 rt2x00pci_register_write(rt2x00dev
, MAC_CSR13
, reg
);
731 static void rt61pci_config_antenna_2529(struct rt2x00_dev
*rt2x00dev
,
732 struct antenna_setup
*ant
)
738 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
739 rt61pci_bbp_read(rt2x00dev
, 4, &r4
);
740 rt61pci_bbp_read(rt2x00dev
, 77, &r77
);
743 * Configure the RX antenna.
747 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
748 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
749 rt61pci_config_antenna_2529_rx(rt2x00dev
, 0, 0);
751 case ANTENNA_HW_DIVERSITY
:
753 * FIXME: Antenna selection for the rf 2529 is very confusing
754 * in the legacy driver. Just default to antenna B until the
755 * legacy code can be properly translated into rt2x00 code.
759 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
760 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
761 rt61pci_config_antenna_2529_rx(rt2x00dev
, 1, 1);
765 rt61pci_bbp_write(rt2x00dev
, 77, r77
);
766 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
767 rt61pci_bbp_write(rt2x00dev
, 4, r4
);
773 * value[0] -> non-LNA
779 static const struct antenna_sel antenna_sel_a
[] = {
780 { 96, { 0x58, 0x78 } },
781 { 104, { 0x38, 0x48 } },
782 { 75, { 0xfe, 0x80 } },
783 { 86, { 0xfe, 0x80 } },
784 { 88, { 0xfe, 0x80 } },
785 { 35, { 0x60, 0x60 } },
786 { 97, { 0x58, 0x58 } },
787 { 98, { 0x58, 0x58 } },
790 static const struct antenna_sel antenna_sel_bg
[] = {
791 { 96, { 0x48, 0x68 } },
792 { 104, { 0x2c, 0x3c } },
793 { 75, { 0xfe, 0x80 } },
794 { 86, { 0xfe, 0x80 } },
795 { 88, { 0xfe, 0x80 } },
796 { 35, { 0x50, 0x50 } },
797 { 97, { 0x48, 0x48 } },
798 { 98, { 0x48, 0x48 } },
801 static void rt61pci_config_ant(struct rt2x00_dev
*rt2x00dev
,
802 struct antenna_setup
*ant
)
804 const struct antenna_sel
*sel
;
810 * We should never come here because rt2x00lib is supposed
811 * to catch this and send us the correct antenna explicitely.
813 BUG_ON(ant
->rx
== ANTENNA_SW_DIVERSITY
||
814 ant
->tx
== ANTENNA_SW_DIVERSITY
);
816 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
) {
818 lna
= test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
);
820 sel
= antenna_sel_bg
;
821 lna
= test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
);
824 for (i
= 0; i
< ARRAY_SIZE(antenna_sel_a
); i
++)
825 rt61pci_bbp_write(rt2x00dev
, sel
[i
].word
, sel
[i
].value
[lna
]);
827 rt2x00pci_register_read(rt2x00dev
, PHY_CSR0
, ®
);
829 rt2x00_set_field32(®
, PHY_CSR0_PA_PE_BG
,
830 rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
831 rt2x00_set_field32(®
, PHY_CSR0_PA_PE_A
,
832 rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
834 rt2x00pci_register_write(rt2x00dev
, PHY_CSR0
, reg
);
836 if (rt2x00_rf(&rt2x00dev
->chip
, RF5225
) ||
837 rt2x00_rf(&rt2x00dev
->chip
, RF5325
))
838 rt61pci_config_antenna_5x(rt2x00dev
, ant
);
839 else if (rt2x00_rf(&rt2x00dev
->chip
, RF2527
))
840 rt61pci_config_antenna_2x(rt2x00dev
, ant
);
841 else if (rt2x00_rf(&rt2x00dev
->chip
, RF2529
)) {
842 if (test_bit(CONFIG_DOUBLE_ANTENNA
, &rt2x00dev
->flags
))
843 rt61pci_config_antenna_2x(rt2x00dev
, ant
);
845 rt61pci_config_antenna_2529(rt2x00dev
, ant
);
849 static void rt61pci_config_lna_gain(struct rt2x00_dev
*rt2x00dev
,
850 struct rt2x00lib_conf
*libconf
)
855 if (libconf
->conf
->channel
->band
== IEEE80211_BAND_2GHZ
) {
856 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
))
859 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, &eeprom
);
860 lna_gain
-= rt2x00_get_field16(eeprom
, EEPROM_RSSI_OFFSET_BG_1
);
862 if (test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
))
865 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, &eeprom
);
866 lna_gain
-= rt2x00_get_field16(eeprom
, EEPROM_RSSI_OFFSET_A_1
);
869 rt2x00dev
->lna_gain
= lna_gain
;
872 static void rt61pci_config_channel(struct rt2x00_dev
*rt2x00dev
,
873 struct rf_channel
*rf
, const int txpower
)
879 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER
, TXPOWER_TO_DEV(txpower
));
880 rt2x00_set_field32(&rf
->rf4
, RF4_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
882 smart
= !(rt2x00_rf(&rt2x00dev
->chip
, RF5225
) ||
883 rt2x00_rf(&rt2x00dev
->chip
, RF2527
));
885 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
886 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
, smart
);
887 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
890 if (txpower
> MAX_TXPOWER
&& txpower
<= (MAX_TXPOWER
+ r94
))
891 r94
+= txpower
- MAX_TXPOWER
;
892 else if (txpower
< MIN_TXPOWER
&& txpower
>= (MIN_TXPOWER
- r94
))
894 rt61pci_bbp_write(rt2x00dev
, 94, r94
);
896 rt61pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
897 rt61pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
898 rt61pci_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
899 rt61pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
903 rt61pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
904 rt61pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
905 rt61pci_rf_write(rt2x00dev
, 3, rf
->rf3
| 0x00000004);
906 rt61pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
910 rt61pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
911 rt61pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
912 rt61pci_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
913 rt61pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
918 static void rt61pci_config_txpower(struct rt2x00_dev
*rt2x00dev
,
921 struct rf_channel rf
;
923 rt2x00_rf_read(rt2x00dev
, 1, &rf
.rf1
);
924 rt2x00_rf_read(rt2x00dev
, 2, &rf
.rf2
);
925 rt2x00_rf_read(rt2x00dev
, 3, &rf
.rf3
);
926 rt2x00_rf_read(rt2x00dev
, 4, &rf
.rf4
);
928 rt61pci_config_channel(rt2x00dev
, &rf
, txpower
);
931 static void rt61pci_config_retry_limit(struct rt2x00_dev
*rt2x00dev
,
932 struct rt2x00lib_conf
*libconf
)
936 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
937 rt2x00_set_field32(®
, TXRX_CSR4_LONG_RETRY_LIMIT
,
938 libconf
->conf
->long_frame_max_tx_count
);
939 rt2x00_set_field32(®
, TXRX_CSR4_SHORT_RETRY_LIMIT
,
940 libconf
->conf
->short_frame_max_tx_count
);
941 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
944 static void rt61pci_config_ps(struct rt2x00_dev
*rt2x00dev
,
945 struct rt2x00lib_conf
*libconf
)
947 enum dev_state state
=
948 (libconf
->conf
->flags
& IEEE80211_CONF_PS
) ?
949 STATE_SLEEP
: STATE_AWAKE
;
952 if (state
== STATE_SLEEP
) {
953 rt2x00pci_register_read(rt2x00dev
, MAC_CSR11
, ®
);
954 rt2x00_set_field32(®
, MAC_CSR11_DELAY_AFTER_TBCN
,
955 rt2x00dev
->beacon_int
- 10);
956 rt2x00_set_field32(®
, MAC_CSR11_TBCN_BEFORE_WAKEUP
,
957 libconf
->conf
->listen_interval
- 1);
958 rt2x00_set_field32(®
, MAC_CSR11_WAKEUP_LATENCY
, 5);
960 /* We must first disable autowake before it can be enabled */
961 rt2x00_set_field32(®
, MAC_CSR11_AUTOWAKE
, 0);
962 rt2x00pci_register_write(rt2x00dev
, MAC_CSR11
, reg
);
964 rt2x00_set_field32(®
, MAC_CSR11_AUTOWAKE
, 1);
965 rt2x00pci_register_write(rt2x00dev
, MAC_CSR11
, reg
);
967 rt2x00pci_register_write(rt2x00dev
, SOFT_RESET_CSR
, 0x00000005);
968 rt2x00pci_register_write(rt2x00dev
, IO_CNTL_CSR
, 0x0000001c);
969 rt2x00pci_register_write(rt2x00dev
, PCI_USEC_CSR
, 0x00000060);
971 rt61pci_mcu_request(rt2x00dev
, MCU_SLEEP
, 0xff, 0, 0);
973 rt2x00pci_register_read(rt2x00dev
, MAC_CSR11
, ®
);
974 rt2x00_set_field32(®
, MAC_CSR11_DELAY_AFTER_TBCN
, 0);
975 rt2x00_set_field32(®
, MAC_CSR11_TBCN_BEFORE_WAKEUP
, 0);
976 rt2x00_set_field32(®
, MAC_CSR11_AUTOWAKE
, 0);
977 rt2x00_set_field32(®
, MAC_CSR11_WAKEUP_LATENCY
, 0);
978 rt2x00pci_register_write(rt2x00dev
, MAC_CSR11
, reg
);
980 rt2x00pci_register_write(rt2x00dev
, SOFT_RESET_CSR
, 0x00000007);
981 rt2x00pci_register_write(rt2x00dev
, IO_CNTL_CSR
, 0x00000018);
982 rt2x00pci_register_write(rt2x00dev
, PCI_USEC_CSR
, 0x00000020);
984 rt61pci_mcu_request(rt2x00dev
, MCU_WAKEUP
, 0xff, 0, 0);
988 static void rt61pci_config(struct rt2x00_dev
*rt2x00dev
,
989 struct rt2x00lib_conf
*libconf
,
990 const unsigned int flags
)
992 /* Always recalculate LNA gain before changing configuration */
993 rt61pci_config_lna_gain(rt2x00dev
, libconf
);
995 if (flags
& IEEE80211_CONF_CHANGE_CHANNEL
)
996 rt61pci_config_channel(rt2x00dev
, &libconf
->rf
,
997 libconf
->conf
->power_level
);
998 if ((flags
& IEEE80211_CONF_CHANGE_POWER
) &&
999 !(flags
& IEEE80211_CONF_CHANGE_CHANNEL
))
1000 rt61pci_config_txpower(rt2x00dev
, libconf
->conf
->power_level
);
1001 if (flags
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
1002 rt61pci_config_retry_limit(rt2x00dev
, libconf
);
1003 if (flags
& IEEE80211_CONF_CHANGE_PS
)
1004 rt61pci_config_ps(rt2x00dev
, libconf
);
1010 static void rt61pci_link_stats(struct rt2x00_dev
*rt2x00dev
,
1011 struct link_qual
*qual
)
1016 * Update FCS error count from register.
1018 rt2x00pci_register_read(rt2x00dev
, STA_CSR0
, ®
);
1019 qual
->rx_failed
= rt2x00_get_field32(reg
, STA_CSR0_FCS_ERROR
);
1022 * Update False CCA count from register.
1024 rt2x00pci_register_read(rt2x00dev
, STA_CSR1
, ®
);
1025 qual
->false_cca
= rt2x00_get_field32(reg
, STA_CSR1_FALSE_CCA_ERROR
);
1028 static inline void rt61pci_set_vgc(struct rt2x00_dev
*rt2x00dev
,
1029 struct link_qual
*qual
, u8 vgc_level
)
1031 if (qual
->vgc_level
!= vgc_level
) {
1032 rt61pci_bbp_write(rt2x00dev
, 17, vgc_level
);
1033 qual
->vgc_level
= vgc_level
;
1034 qual
->vgc_level_reg
= vgc_level
;
1038 static void rt61pci_reset_tuner(struct rt2x00_dev
*rt2x00dev
,
1039 struct link_qual
*qual
)
1041 rt61pci_set_vgc(rt2x00dev
, qual
, 0x20);
1044 static void rt61pci_link_tuner(struct rt2x00_dev
*rt2x00dev
,
1045 struct link_qual
*qual
, const u32 count
)
1051 * Determine r17 bounds.
1053 if (rt2x00dev
->rx_status
.band
== IEEE80211_BAND_5GHZ
) {
1056 if (test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
)) {
1063 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
)) {
1070 * If we are not associated, we should go straight to the
1071 * dynamic CCA tuning.
1073 if (!rt2x00dev
->intf_associated
)
1074 goto dynamic_cca_tune
;
1077 * Special big-R17 for very short distance
1079 if (qual
->rssi
>= -35) {
1080 rt61pci_set_vgc(rt2x00dev
, qual
, 0x60);
1085 * Special big-R17 for short distance
1087 if (qual
->rssi
>= -58) {
1088 rt61pci_set_vgc(rt2x00dev
, qual
, up_bound
);
1093 * Special big-R17 for middle-short distance
1095 if (qual
->rssi
>= -66) {
1096 rt61pci_set_vgc(rt2x00dev
, qual
, low_bound
+ 0x10);
1101 * Special mid-R17 for middle distance
1103 if (qual
->rssi
>= -74) {
1104 rt61pci_set_vgc(rt2x00dev
, qual
, low_bound
+ 0x08);
1109 * Special case: Change up_bound based on the rssi.
1110 * Lower up_bound when rssi is weaker then -74 dBm.
1112 up_bound
-= 2 * (-74 - qual
->rssi
);
1113 if (low_bound
> up_bound
)
1114 up_bound
= low_bound
;
1116 if (qual
->vgc_level
> up_bound
) {
1117 rt61pci_set_vgc(rt2x00dev
, qual
, up_bound
);
1124 * r17 does not yet exceed upper limit, continue and base
1125 * the r17 tuning on the false CCA count.
1127 if ((qual
->false_cca
> 512) && (qual
->vgc_level
< up_bound
))
1128 rt61pci_set_vgc(rt2x00dev
, qual
, ++qual
->vgc_level
);
1129 else if ((qual
->false_cca
< 100) && (qual
->vgc_level
> low_bound
))
1130 rt61pci_set_vgc(rt2x00dev
, qual
, --qual
->vgc_level
);
1134 * Firmware functions
1136 static char *rt61pci_get_firmware_name(struct rt2x00_dev
*rt2x00dev
)
1140 switch (rt2x00dev
->chip
.rt
) {
1142 fw_name
= FIRMWARE_RT2561
;
1145 fw_name
= FIRMWARE_RT2561s
;
1148 fw_name
= FIRMWARE_RT2661
;
1158 static int rt61pci_check_firmware(struct rt2x00_dev
*rt2x00dev
,
1159 const u8
*data
, const size_t len
)
1165 * Only support 8kb firmware files.
1168 return FW_BAD_LENGTH
;
1171 * The last 2 bytes in the firmware array are the crc checksum itself.
1172 * This means that we should never pass those 2 bytes to the crc
1175 fw_crc
= (data
[len
- 2] << 8 | data
[len
- 1]);
1178 * Use the crc itu-t algorithm.
1180 crc
= crc_itu_t(0, data
, len
- 2);
1181 crc
= crc_itu_t_byte(crc
, 0);
1182 crc
= crc_itu_t_byte(crc
, 0);
1184 return (fw_crc
== crc
) ? FW_OK
: FW_BAD_CRC
;
1187 static int rt61pci_load_firmware(struct rt2x00_dev
*rt2x00dev
,
1188 const u8
*data
, const size_t len
)
1194 * Wait for stable hardware.
1196 for (i
= 0; i
< 100; i
++) {
1197 rt2x00pci_register_read(rt2x00dev
, MAC_CSR0
, ®
);
1204 ERROR(rt2x00dev
, "Unstable hardware.\n");
1209 * Prepare MCU and mailbox for firmware loading.
1212 rt2x00_set_field32(®
, MCU_CNTL_CSR_RESET
, 1);
1213 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1214 rt2x00pci_register_write(rt2x00dev
, M2H_CMD_DONE_CSR
, 0xffffffff);
1215 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
1216 rt2x00pci_register_write(rt2x00dev
, HOST_CMD_CSR
, 0);
1219 * Write firmware to device.
1222 rt2x00_set_field32(®
, MCU_CNTL_CSR_RESET
, 1);
1223 rt2x00_set_field32(®
, MCU_CNTL_CSR_SELECT_BANK
, 1);
1224 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1226 rt2x00pci_register_multiwrite(rt2x00dev
, FIRMWARE_IMAGE_BASE
,
1229 rt2x00_set_field32(®
, MCU_CNTL_CSR_SELECT_BANK
, 0);
1230 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1232 rt2x00_set_field32(®
, MCU_CNTL_CSR_RESET
, 0);
1233 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1235 for (i
= 0; i
< 100; i
++) {
1236 rt2x00pci_register_read(rt2x00dev
, MCU_CNTL_CSR
, ®
);
1237 if (rt2x00_get_field32(reg
, MCU_CNTL_CSR_READY
))
1243 ERROR(rt2x00dev
, "MCU Control register not ready.\n");
1248 * Hardware needs another millisecond before it is ready.
1253 * Reset MAC and BBP registers.
1256 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 1);
1257 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 1);
1258 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1260 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1261 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 0);
1262 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 0);
1263 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1265 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1266 rt2x00_set_field32(®
, MAC_CSR1_HOST_READY
, 1);
1267 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1273 * Initialization functions.
1275 static bool rt61pci_get_entry_state(struct queue_entry
*entry
)
1277 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1280 if (entry
->queue
->qid
== QID_RX
) {
1281 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1283 return rt2x00_get_field32(word
, RXD_W0_OWNER_NIC
);
1285 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1287 return (rt2x00_get_field32(word
, TXD_W0_OWNER_NIC
) ||
1288 rt2x00_get_field32(word
, TXD_W0_VALID
));
1292 static void rt61pci_clear_entry(struct queue_entry
*entry
)
1294 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1295 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
1298 if (entry
->queue
->qid
== QID_RX
) {
1299 rt2x00_desc_read(entry_priv
->desc
, 5, &word
);
1300 rt2x00_set_field32(&word
, RXD_W5_BUFFER_PHYSICAL_ADDRESS
,
1302 rt2x00_desc_write(entry_priv
->desc
, 5, word
);
1304 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1305 rt2x00_set_field32(&word
, RXD_W0_OWNER_NIC
, 1);
1306 rt2x00_desc_write(entry_priv
->desc
, 0, word
);
1308 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1309 rt2x00_set_field32(&word
, TXD_W0_VALID
, 0);
1310 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 0);
1311 rt2x00_desc_write(entry_priv
->desc
, 0, word
);
1315 static int rt61pci_init_queues(struct rt2x00_dev
*rt2x00dev
)
1317 struct queue_entry_priv_pci
*entry_priv
;
1321 * Initialize registers.
1323 rt2x00pci_register_read(rt2x00dev
, TX_RING_CSR0
, ®
);
1324 rt2x00_set_field32(®
, TX_RING_CSR0_AC0_RING_SIZE
,
1325 rt2x00dev
->tx
[0].limit
);
1326 rt2x00_set_field32(®
, TX_RING_CSR0_AC1_RING_SIZE
,
1327 rt2x00dev
->tx
[1].limit
);
1328 rt2x00_set_field32(®
, TX_RING_CSR0_AC2_RING_SIZE
,
1329 rt2x00dev
->tx
[2].limit
);
1330 rt2x00_set_field32(®
, TX_RING_CSR0_AC3_RING_SIZE
,
1331 rt2x00dev
->tx
[3].limit
);
1332 rt2x00pci_register_write(rt2x00dev
, TX_RING_CSR0
, reg
);
1334 rt2x00pci_register_read(rt2x00dev
, TX_RING_CSR1
, ®
);
1335 rt2x00_set_field32(®
, TX_RING_CSR1_TXD_SIZE
,
1336 rt2x00dev
->tx
[0].desc_size
/ 4);
1337 rt2x00pci_register_write(rt2x00dev
, TX_RING_CSR1
, reg
);
1339 entry_priv
= rt2x00dev
->tx
[0].entries
[0].priv_data
;
1340 rt2x00pci_register_read(rt2x00dev
, AC0_BASE_CSR
, ®
);
1341 rt2x00_set_field32(®
, AC0_BASE_CSR_RING_REGISTER
,
1342 entry_priv
->desc_dma
);
1343 rt2x00pci_register_write(rt2x00dev
, AC0_BASE_CSR
, reg
);
1345 entry_priv
= rt2x00dev
->tx
[1].entries
[0].priv_data
;
1346 rt2x00pci_register_read(rt2x00dev
, AC1_BASE_CSR
, ®
);
1347 rt2x00_set_field32(®
, AC1_BASE_CSR_RING_REGISTER
,
1348 entry_priv
->desc_dma
);
1349 rt2x00pci_register_write(rt2x00dev
, AC1_BASE_CSR
, reg
);
1351 entry_priv
= rt2x00dev
->tx
[2].entries
[0].priv_data
;
1352 rt2x00pci_register_read(rt2x00dev
, AC2_BASE_CSR
, ®
);
1353 rt2x00_set_field32(®
, AC2_BASE_CSR_RING_REGISTER
,
1354 entry_priv
->desc_dma
);
1355 rt2x00pci_register_write(rt2x00dev
, AC2_BASE_CSR
, reg
);
1357 entry_priv
= rt2x00dev
->tx
[3].entries
[0].priv_data
;
1358 rt2x00pci_register_read(rt2x00dev
, AC3_BASE_CSR
, ®
);
1359 rt2x00_set_field32(®
, AC3_BASE_CSR_RING_REGISTER
,
1360 entry_priv
->desc_dma
);
1361 rt2x00pci_register_write(rt2x00dev
, AC3_BASE_CSR
, reg
);
1363 rt2x00pci_register_read(rt2x00dev
, RX_RING_CSR
, ®
);
1364 rt2x00_set_field32(®
, RX_RING_CSR_RING_SIZE
, rt2x00dev
->rx
->limit
);
1365 rt2x00_set_field32(®
, RX_RING_CSR_RXD_SIZE
,
1366 rt2x00dev
->rx
->desc_size
/ 4);
1367 rt2x00_set_field32(®
, RX_RING_CSR_RXD_WRITEBACK_SIZE
, 4);
1368 rt2x00pci_register_write(rt2x00dev
, RX_RING_CSR
, reg
);
1370 entry_priv
= rt2x00dev
->rx
->entries
[0].priv_data
;
1371 rt2x00pci_register_read(rt2x00dev
, RX_BASE_CSR
, ®
);
1372 rt2x00_set_field32(®
, RX_BASE_CSR_RING_REGISTER
,
1373 entry_priv
->desc_dma
);
1374 rt2x00pci_register_write(rt2x00dev
, RX_BASE_CSR
, reg
);
1376 rt2x00pci_register_read(rt2x00dev
, TX_DMA_DST_CSR
, ®
);
1377 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC0
, 2);
1378 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC1
, 2);
1379 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC2
, 2);
1380 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC3
, 2);
1381 rt2x00pci_register_write(rt2x00dev
, TX_DMA_DST_CSR
, reg
);
1383 rt2x00pci_register_read(rt2x00dev
, LOAD_TX_RING_CSR
, ®
);
1384 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC0
, 1);
1385 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC1
, 1);
1386 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC2
, 1);
1387 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC3
, 1);
1388 rt2x00pci_register_write(rt2x00dev
, LOAD_TX_RING_CSR
, reg
);
1390 rt2x00pci_register_read(rt2x00dev
, RX_CNTL_CSR
, ®
);
1391 rt2x00_set_field32(®
, RX_CNTL_CSR_LOAD_RXD
, 1);
1392 rt2x00pci_register_write(rt2x00dev
, RX_CNTL_CSR
, reg
);
1397 static int rt61pci_init_registers(struct rt2x00_dev
*rt2x00dev
)
1401 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
1402 rt2x00_set_field32(®
, TXRX_CSR0_AUTO_TX_SEQ
, 1);
1403 rt2x00_set_field32(®
, TXRX_CSR0_DISABLE_RX
, 0);
1404 rt2x00_set_field32(®
, TXRX_CSR0_TX_WITHOUT_WAITING
, 0);
1405 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
1407 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR1
, ®
);
1408 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID0
, 47); /* CCK Signal */
1409 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID0_VALID
, 1);
1410 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID1
, 30); /* Rssi */
1411 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID1_VALID
, 1);
1412 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID2
, 42); /* OFDM Rate */
1413 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID2_VALID
, 1);
1414 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID3
, 30); /* Rssi */
1415 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID3_VALID
, 1);
1416 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR1
, reg
);
1419 * CCK TXD BBP registers
1421 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR2
, ®
);
1422 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID0
, 13);
1423 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID0_VALID
, 1);
1424 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID1
, 12);
1425 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID1_VALID
, 1);
1426 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID2
, 11);
1427 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID2_VALID
, 1);
1428 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID3
, 10);
1429 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID3_VALID
, 1);
1430 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR2
, reg
);
1433 * OFDM TXD BBP registers
1435 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR3
, ®
);
1436 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID0
, 7);
1437 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID0_VALID
, 1);
1438 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID1
, 6);
1439 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID1_VALID
, 1);
1440 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID2
, 5);
1441 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID2_VALID
, 1);
1442 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR3
, reg
);
1444 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR7
, ®
);
1445 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_6MBS
, 59);
1446 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_9MBS
, 53);
1447 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_12MBS
, 49);
1448 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_18MBS
, 46);
1449 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR7
, reg
);
1451 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR8
, ®
);
1452 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_24MBS
, 44);
1453 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_36MBS
, 42);
1454 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_48MBS
, 42);
1455 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_54MBS
, 42);
1456 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR8
, reg
);
1458 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1459 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_INTERVAL
, 0);
1460 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 0);
1461 rt2x00_set_field32(®
, TXRX_CSR9_TSF_SYNC
, 0);
1462 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 0);
1463 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 0);
1464 rt2x00_set_field32(®
, TXRX_CSR9_TIMESTAMP_COMPENSATE
, 0);
1465 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1467 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR15
, 0x0000000f);
1469 rt2x00pci_register_write(rt2x00dev
, MAC_CSR6
, 0x00000fff);
1471 rt2x00pci_register_read(rt2x00dev
, MAC_CSR9
, ®
);
1472 rt2x00_set_field32(®
, MAC_CSR9_CW_SELECT
, 0);
1473 rt2x00pci_register_write(rt2x00dev
, MAC_CSR9
, reg
);
1475 rt2x00pci_register_write(rt2x00dev
, MAC_CSR10
, 0x0000071c);
1477 if (rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, STATE_AWAKE
))
1480 rt2x00pci_register_write(rt2x00dev
, MAC_CSR13
, 0x0000e000);
1483 * Invalidate all Shared Keys (SEC_CSR0),
1484 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1486 rt2x00pci_register_write(rt2x00dev
, SEC_CSR0
, 0x00000000);
1487 rt2x00pci_register_write(rt2x00dev
, SEC_CSR1
, 0x00000000);
1488 rt2x00pci_register_write(rt2x00dev
, SEC_CSR5
, 0x00000000);
1490 rt2x00pci_register_write(rt2x00dev
, PHY_CSR1
, 0x000023b0);
1491 rt2x00pci_register_write(rt2x00dev
, PHY_CSR5
, 0x060a100c);
1492 rt2x00pci_register_write(rt2x00dev
, PHY_CSR6
, 0x00080606);
1493 rt2x00pci_register_write(rt2x00dev
, PHY_CSR7
, 0x00000a08);
1495 rt2x00pci_register_write(rt2x00dev
, PCI_CFG_CSR
, 0x28ca4404);
1497 rt2x00pci_register_write(rt2x00dev
, TEST_MODE_CSR
, 0x00000200);
1499 rt2x00pci_register_write(rt2x00dev
, M2H_CMD_DONE_CSR
, 0xffffffff);
1503 * For the Beacon base registers we only need to clear
1504 * the first byte since that byte contains the VALID and OWNER
1505 * bits which (when set to 0) will invalidate the entire beacon.
1507 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE0
, 0);
1508 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE1
, 0);
1509 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE2
, 0);
1510 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE3
, 0);
1513 * We must clear the error counters.
1514 * These registers are cleared on read,
1515 * so we may pass a useless variable to store the value.
1517 rt2x00pci_register_read(rt2x00dev
, STA_CSR0
, ®
);
1518 rt2x00pci_register_read(rt2x00dev
, STA_CSR1
, ®
);
1519 rt2x00pci_register_read(rt2x00dev
, STA_CSR2
, ®
);
1522 * Reset MAC and BBP registers.
1524 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1525 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 1);
1526 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 1);
1527 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1529 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1530 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 0);
1531 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 0);
1532 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1534 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1535 rt2x00_set_field32(®
, MAC_CSR1_HOST_READY
, 1);
1536 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1541 static int rt61pci_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
1546 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1547 rt61pci_bbp_read(rt2x00dev
, 0, &value
);
1548 if ((value
!= 0xff) && (value
!= 0x00))
1550 udelay(REGISTER_BUSY_DELAY
);
1553 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
1557 static int rt61pci_init_bbp(struct rt2x00_dev
*rt2x00dev
)
1564 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev
)))
1567 rt61pci_bbp_write(rt2x00dev
, 3, 0x00);
1568 rt61pci_bbp_write(rt2x00dev
, 15, 0x30);
1569 rt61pci_bbp_write(rt2x00dev
, 21, 0xc8);
1570 rt61pci_bbp_write(rt2x00dev
, 22, 0x38);
1571 rt61pci_bbp_write(rt2x00dev
, 23, 0x06);
1572 rt61pci_bbp_write(rt2x00dev
, 24, 0xfe);
1573 rt61pci_bbp_write(rt2x00dev
, 25, 0x0a);
1574 rt61pci_bbp_write(rt2x00dev
, 26, 0x0d);
1575 rt61pci_bbp_write(rt2x00dev
, 34, 0x12);
1576 rt61pci_bbp_write(rt2x00dev
, 37, 0x07);
1577 rt61pci_bbp_write(rt2x00dev
, 39, 0xf8);
1578 rt61pci_bbp_write(rt2x00dev
, 41, 0x60);
1579 rt61pci_bbp_write(rt2x00dev
, 53, 0x10);
1580 rt61pci_bbp_write(rt2x00dev
, 54, 0x18);
1581 rt61pci_bbp_write(rt2x00dev
, 60, 0x10);
1582 rt61pci_bbp_write(rt2x00dev
, 61, 0x04);
1583 rt61pci_bbp_write(rt2x00dev
, 62, 0x04);
1584 rt61pci_bbp_write(rt2x00dev
, 75, 0xfe);
1585 rt61pci_bbp_write(rt2x00dev
, 86, 0xfe);
1586 rt61pci_bbp_write(rt2x00dev
, 88, 0xfe);
1587 rt61pci_bbp_write(rt2x00dev
, 90, 0x0f);
1588 rt61pci_bbp_write(rt2x00dev
, 99, 0x00);
1589 rt61pci_bbp_write(rt2x00dev
, 102, 0x16);
1590 rt61pci_bbp_write(rt2x00dev
, 107, 0x04);
1592 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
1593 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
1595 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
1596 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
1597 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
1598 rt61pci_bbp_write(rt2x00dev
, reg_id
, value
);
1606 * Device state switch handlers.
1608 static void rt61pci_toggle_rx(struct rt2x00_dev
*rt2x00dev
,
1609 enum dev_state state
)
1613 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
1614 rt2x00_set_field32(®
, TXRX_CSR0_DISABLE_RX
,
1615 (state
== STATE_RADIO_RX_OFF
) ||
1616 (state
== STATE_RADIO_RX_OFF_LINK
));
1617 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
1620 static void rt61pci_toggle_irq(struct rt2x00_dev
*rt2x00dev
,
1621 enum dev_state state
)
1623 int mask
= (state
== STATE_RADIO_IRQ_OFF
);
1627 * When interrupts are being enabled, the interrupt registers
1628 * should clear the register to assure a clean state.
1630 if (state
== STATE_RADIO_IRQ_ON
) {
1631 rt2x00pci_register_read(rt2x00dev
, INT_SOURCE_CSR
, ®
);
1632 rt2x00pci_register_write(rt2x00dev
, INT_SOURCE_CSR
, reg
);
1634 rt2x00pci_register_read(rt2x00dev
, MCU_INT_SOURCE_CSR
, ®
);
1635 rt2x00pci_register_write(rt2x00dev
, MCU_INT_SOURCE_CSR
, reg
);
1639 * Only toggle the interrupts bits we are going to use.
1640 * Non-checked interrupt bits are disabled by default.
1642 rt2x00pci_register_read(rt2x00dev
, INT_MASK_CSR
, ®
);
1643 rt2x00_set_field32(®
, INT_MASK_CSR_TXDONE
, mask
);
1644 rt2x00_set_field32(®
, INT_MASK_CSR_RXDONE
, mask
);
1645 rt2x00_set_field32(®
, INT_MASK_CSR_ENABLE_MITIGATION
, mask
);
1646 rt2x00_set_field32(®
, INT_MASK_CSR_MITIGATION_PERIOD
, 0xff);
1647 rt2x00pci_register_write(rt2x00dev
, INT_MASK_CSR
, reg
);
1649 rt2x00pci_register_read(rt2x00dev
, MCU_INT_MASK_CSR
, ®
);
1650 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_0
, mask
);
1651 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_1
, mask
);
1652 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_2
, mask
);
1653 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_3
, mask
);
1654 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_4
, mask
);
1655 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_5
, mask
);
1656 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_6
, mask
);
1657 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_7
, mask
);
1658 rt2x00pci_register_write(rt2x00dev
, MCU_INT_MASK_CSR
, reg
);
1661 static int rt61pci_enable_radio(struct rt2x00_dev
*rt2x00dev
)
1666 * Initialize all registers.
1668 if (unlikely(rt61pci_init_queues(rt2x00dev
) ||
1669 rt61pci_init_registers(rt2x00dev
) ||
1670 rt61pci_init_bbp(rt2x00dev
)))
1676 rt2x00pci_register_read(rt2x00dev
, RX_CNTL_CSR
, ®
);
1677 rt2x00_set_field32(®
, RX_CNTL_CSR_ENABLE_RX_DMA
, 1);
1678 rt2x00pci_register_write(rt2x00dev
, RX_CNTL_CSR
, reg
);
1683 static void rt61pci_disable_radio(struct rt2x00_dev
*rt2x00dev
)
1688 rt2x00pci_register_write(rt2x00dev
, MAC_CSR10
, 0x00001818);
1691 static int rt61pci_set_state(struct rt2x00_dev
*rt2x00dev
, enum dev_state state
)
1697 put_to_sleep
= (state
!= STATE_AWAKE
);
1699 rt2x00pci_register_read(rt2x00dev
, MAC_CSR12
, ®
);
1700 rt2x00_set_field32(®
, MAC_CSR12_FORCE_WAKEUP
, !put_to_sleep
);
1701 rt2x00_set_field32(®
, MAC_CSR12_PUT_TO_SLEEP
, put_to_sleep
);
1702 rt2x00pci_register_write(rt2x00dev
, MAC_CSR12
, reg
);
1705 * Device is not guaranteed to be in the requested state yet.
1706 * We must wait until the register indicates that the
1707 * device has entered the correct state.
1709 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1710 rt2x00pci_register_read(rt2x00dev
, MAC_CSR12
, ®
);
1711 state
= rt2x00_get_field32(reg
, MAC_CSR12_BBP_CURRENT_STATE
);
1712 if (state
== !put_to_sleep
)
1720 static int rt61pci_set_device_state(struct rt2x00_dev
*rt2x00dev
,
1721 enum dev_state state
)
1726 case STATE_RADIO_ON
:
1727 retval
= rt61pci_enable_radio(rt2x00dev
);
1729 case STATE_RADIO_OFF
:
1730 rt61pci_disable_radio(rt2x00dev
);
1732 case STATE_RADIO_RX_ON
:
1733 case STATE_RADIO_RX_ON_LINK
:
1734 case STATE_RADIO_RX_OFF
:
1735 case STATE_RADIO_RX_OFF_LINK
:
1736 rt61pci_toggle_rx(rt2x00dev
, state
);
1738 case STATE_RADIO_IRQ_ON
:
1739 case STATE_RADIO_IRQ_OFF
:
1740 rt61pci_toggle_irq(rt2x00dev
, state
);
1742 case STATE_DEEP_SLEEP
:
1746 retval
= rt61pci_set_state(rt2x00dev
, state
);
1753 if (unlikely(retval
))
1754 ERROR(rt2x00dev
, "Device failed to enter state %d (%d).\n",
1761 * TX descriptor initialization
1763 static void rt61pci_write_tx_desc(struct rt2x00_dev
*rt2x00dev
,
1764 struct sk_buff
*skb
,
1765 struct txentry_desc
*txdesc
)
1767 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(skb
);
1768 __le32
*txd
= skbdesc
->desc
;
1772 * Start writing the descriptor words.
1774 rt2x00_desc_read(txd
, 1, &word
);
1775 rt2x00_set_field32(&word
, TXD_W1_HOST_Q_ID
, txdesc
->queue
);
1776 rt2x00_set_field32(&word
, TXD_W1_AIFSN
, txdesc
->aifs
);
1777 rt2x00_set_field32(&word
, TXD_W1_CWMIN
, txdesc
->cw_min
);
1778 rt2x00_set_field32(&word
, TXD_W1_CWMAX
, txdesc
->cw_max
);
1779 rt2x00_set_field32(&word
, TXD_W1_IV_OFFSET
, txdesc
->iv_offset
);
1780 rt2x00_set_field32(&word
, TXD_W1_HW_SEQUENCE
,
1781 test_bit(ENTRY_TXD_GENERATE_SEQ
, &txdesc
->flags
));
1782 rt2x00_set_field32(&word
, TXD_W1_BUFFER_COUNT
, 1);
1783 rt2x00_desc_write(txd
, 1, word
);
1785 rt2x00_desc_read(txd
, 2, &word
);
1786 rt2x00_set_field32(&word
, TXD_W2_PLCP_SIGNAL
, txdesc
->signal
);
1787 rt2x00_set_field32(&word
, TXD_W2_PLCP_SERVICE
, txdesc
->service
);
1788 rt2x00_set_field32(&word
, TXD_W2_PLCP_LENGTH_LOW
, txdesc
->length_low
);
1789 rt2x00_set_field32(&word
, TXD_W2_PLCP_LENGTH_HIGH
, txdesc
->length_high
);
1790 rt2x00_desc_write(txd
, 2, word
);
1792 if (test_bit(ENTRY_TXD_ENCRYPT
, &txdesc
->flags
)) {
1793 _rt2x00_desc_write(txd
, 3, skbdesc
->iv
[0]);
1794 _rt2x00_desc_write(txd
, 4, skbdesc
->iv
[1]);
1797 rt2x00_desc_read(txd
, 5, &word
);
1798 rt2x00_set_field32(&word
, TXD_W5_PID_TYPE
, skbdesc
->entry
->queue
->qid
);
1799 rt2x00_set_field32(&word
, TXD_W5_PID_SUBTYPE
,
1800 skbdesc
->entry
->entry_idx
);
1801 rt2x00_set_field32(&word
, TXD_W5_TX_POWER
,
1802 TXPOWER_TO_DEV(rt2x00dev
->tx_power
));
1803 rt2x00_set_field32(&word
, TXD_W5_WAITING_DMA_DONE_INT
, 1);
1804 rt2x00_desc_write(txd
, 5, word
);
1806 rt2x00_desc_read(txd
, 6, &word
);
1807 rt2x00_set_field32(&word
, TXD_W6_BUFFER_PHYSICAL_ADDRESS
,
1809 rt2x00_desc_write(txd
, 6, word
);
1811 if (skbdesc
->desc_len
> TXINFO_SIZE
) {
1812 rt2x00_desc_read(txd
, 11, &word
);
1813 rt2x00_set_field32(&word
, TXD_W11_BUFFER_LENGTH0
, skb
->len
);
1814 rt2x00_desc_write(txd
, 11, word
);
1817 rt2x00_desc_read(txd
, 0, &word
);
1818 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 1);
1819 rt2x00_set_field32(&word
, TXD_W0_VALID
, 1);
1820 rt2x00_set_field32(&word
, TXD_W0_MORE_FRAG
,
1821 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
1822 rt2x00_set_field32(&word
, TXD_W0_ACK
,
1823 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
1824 rt2x00_set_field32(&word
, TXD_W0_TIMESTAMP
,
1825 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
1826 rt2x00_set_field32(&word
, TXD_W0_OFDM
,
1827 (txdesc
->rate_mode
== RATE_MODE_OFDM
));
1828 rt2x00_set_field32(&word
, TXD_W0_IFS
, txdesc
->ifs
);
1829 rt2x00_set_field32(&word
, TXD_W0_RETRY_MODE
,
1830 test_bit(ENTRY_TXD_RETRY_MODE
, &txdesc
->flags
));
1831 rt2x00_set_field32(&word
, TXD_W0_TKIP_MIC
,
1832 test_bit(ENTRY_TXD_ENCRYPT_MMIC
, &txdesc
->flags
));
1833 rt2x00_set_field32(&word
, TXD_W0_KEY_TABLE
,
1834 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE
, &txdesc
->flags
));
1835 rt2x00_set_field32(&word
, TXD_W0_KEY_INDEX
, txdesc
->key_idx
);
1836 rt2x00_set_field32(&word
, TXD_W0_DATABYTE_COUNT
, skb
->len
);
1837 rt2x00_set_field32(&word
, TXD_W0_BURST
,
1838 test_bit(ENTRY_TXD_BURST
, &txdesc
->flags
));
1839 rt2x00_set_field32(&word
, TXD_W0_CIPHER_ALG
, txdesc
->cipher
);
1840 rt2x00_desc_write(txd
, 0, word
);
1844 * TX data initialization
1846 static void rt61pci_write_beacon(struct queue_entry
*entry
)
1848 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
1849 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
1850 unsigned int beacon_base
;
1854 * Disable beaconing while we are reloading the beacon data,
1855 * otherwise we might be sending out invalid data.
1857 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1858 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 0);
1859 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1862 * Write entire beacon with descriptor to register.
1864 beacon_base
= HW_BEACON_OFFSET(entry
->entry_idx
);
1865 rt2x00pci_register_multiwrite(rt2x00dev
,
1867 skbdesc
->desc
, skbdesc
->desc_len
);
1868 rt2x00pci_register_multiwrite(rt2x00dev
,
1869 beacon_base
+ skbdesc
->desc_len
,
1870 entry
->skb
->data
, entry
->skb
->len
);
1873 * Clean up beacon skb.
1875 dev_kfree_skb_any(entry
->skb
);
1879 static void rt61pci_kick_tx_queue(struct rt2x00_dev
*rt2x00dev
,
1880 const enum data_queue_qid queue
)
1884 if (queue
== QID_BEACON
) {
1886 * For Wi-Fi faily generated beacons between participating
1887 * stations. Set TBTT phase adaptive adjustment step to 8us.
1889 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR10
, 0x00001008);
1891 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1892 if (!rt2x00_get_field32(reg
, TXRX_CSR9_BEACON_GEN
)) {
1893 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 1);
1894 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 1);
1895 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 1);
1896 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1901 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1902 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC0
, (queue
== QID_AC_BE
));
1903 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC1
, (queue
== QID_AC_BK
));
1904 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC2
, (queue
== QID_AC_VI
));
1905 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC3
, (queue
== QID_AC_VO
));
1906 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1909 static void rt61pci_kill_tx_queue(struct rt2x00_dev
*rt2x00dev
,
1910 const enum data_queue_qid qid
)
1914 if (qid
== QID_BEACON
) {
1915 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, 0);
1919 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1920 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC0
, (qid
== QID_AC_BE
));
1921 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC1
, (qid
== QID_AC_BK
));
1922 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC2
, (qid
== QID_AC_VI
));
1923 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC3
, (qid
== QID_AC_VO
));
1924 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1928 * RX control handlers
1930 static int rt61pci_agc_to_rssi(struct rt2x00_dev
*rt2x00dev
, int rxd_w1
)
1932 u8 offset
= rt2x00dev
->lna_gain
;
1935 lna
= rt2x00_get_field32(rxd_w1
, RXD_W1_RSSI_LNA
);
1950 if (rt2x00dev
->rx_status
.band
== IEEE80211_BAND_5GHZ
) {
1951 if (lna
== 3 || lna
== 2)
1955 return rt2x00_get_field32(rxd_w1
, RXD_W1_RSSI_AGC
) * 2 - offset
;
1958 static void rt61pci_fill_rxdone(struct queue_entry
*entry
,
1959 struct rxdone_entry_desc
*rxdesc
)
1961 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
1962 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1966 rt2x00_desc_read(entry_priv
->desc
, 0, &word0
);
1967 rt2x00_desc_read(entry_priv
->desc
, 1, &word1
);
1969 if (rt2x00_get_field32(word0
, RXD_W0_CRC_ERROR
))
1970 rxdesc
->flags
|= RX_FLAG_FAILED_FCS_CRC
;
1972 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO
, &rt2x00dev
->flags
)) {
1974 rt2x00_get_field32(word0
, RXD_W0_CIPHER_ALG
);
1975 rxdesc
->cipher_status
=
1976 rt2x00_get_field32(word0
, RXD_W0_CIPHER_ERROR
);
1979 if (rxdesc
->cipher
!= CIPHER_NONE
) {
1980 _rt2x00_desc_read(entry_priv
->desc
, 2, &rxdesc
->iv
[0]);
1981 _rt2x00_desc_read(entry_priv
->desc
, 3, &rxdesc
->iv
[1]);
1982 rxdesc
->dev_flags
|= RXDONE_CRYPTO_IV
;
1984 _rt2x00_desc_read(entry_priv
->desc
, 4, &rxdesc
->icv
);
1985 rxdesc
->dev_flags
|= RXDONE_CRYPTO_ICV
;
1988 * Hardware has stripped IV/EIV data from 802.11 frame during
1989 * decryption. It has provided the data separately but rt2x00lib
1990 * should decide if it should be reinserted.
1992 rxdesc
->flags
|= RX_FLAG_IV_STRIPPED
;
1995 * FIXME: Legacy driver indicates that the frame does
1996 * contain the Michael Mic. Unfortunately, in rt2x00
1997 * the MIC seems to be missing completely...
1999 rxdesc
->flags
|= RX_FLAG_MMIC_STRIPPED
;
2001 if (rxdesc
->cipher_status
== RX_CRYPTO_SUCCESS
)
2002 rxdesc
->flags
|= RX_FLAG_DECRYPTED
;
2003 else if (rxdesc
->cipher_status
== RX_CRYPTO_FAIL_MIC
)
2004 rxdesc
->flags
|= RX_FLAG_MMIC_ERROR
;
2008 * Obtain the status about this packet.
2009 * When frame was received with an OFDM bitrate,
2010 * the signal is the PLCP value. If it was received with
2011 * a CCK bitrate the signal is the rate in 100kbit/s.
2013 rxdesc
->signal
= rt2x00_get_field32(word1
, RXD_W1_SIGNAL
);
2014 rxdesc
->rssi
= rt61pci_agc_to_rssi(rt2x00dev
, word1
);
2015 rxdesc
->size
= rt2x00_get_field32(word0
, RXD_W0_DATABYTE_COUNT
);
2017 if (rt2x00_get_field32(word0
, RXD_W0_OFDM
))
2018 rxdesc
->dev_flags
|= RXDONE_SIGNAL_PLCP
;
2020 rxdesc
->dev_flags
|= RXDONE_SIGNAL_BITRATE
;
2021 if (rt2x00_get_field32(word0
, RXD_W0_MY_BSS
))
2022 rxdesc
->dev_flags
|= RXDONE_MY_BSS
;
2026 * Interrupt functions.
2028 static void rt61pci_txdone(struct rt2x00_dev
*rt2x00dev
)
2030 struct data_queue
*queue
;
2031 struct queue_entry
*entry
;
2032 struct queue_entry
*entry_done
;
2033 struct queue_entry_priv_pci
*entry_priv
;
2034 struct txdone_entry_desc txdesc
;
2042 * During each loop we will compare the freshly read
2043 * STA_CSR4 register value with the value read from
2044 * the previous loop. If the 2 values are equal then
2045 * we should stop processing because the chance is
2046 * quite big that the device has been unplugged and
2047 * we risk going into an endless loop.
2052 rt2x00pci_register_read(rt2x00dev
, STA_CSR4
, ®
);
2053 if (!rt2x00_get_field32(reg
, STA_CSR4_VALID
))
2061 * Skip this entry when it contains an invalid
2062 * queue identication number.
2064 type
= rt2x00_get_field32(reg
, STA_CSR4_PID_TYPE
);
2065 queue
= rt2x00queue_get_queue(rt2x00dev
, type
);
2066 if (unlikely(!queue
))
2070 * Skip this entry when it contains an invalid
2073 index
= rt2x00_get_field32(reg
, STA_CSR4_PID_SUBTYPE
);
2074 if (unlikely(index
>= queue
->limit
))
2077 entry
= &queue
->entries
[index
];
2078 entry_priv
= entry
->priv_data
;
2079 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
2081 if (rt2x00_get_field32(word
, TXD_W0_OWNER_NIC
) ||
2082 !rt2x00_get_field32(word
, TXD_W0_VALID
))
2085 entry_done
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
2086 while (entry
!= entry_done
) {
2088 * Just report any entries we missed as failed.
2091 "TX status report missed for entry %d\n",
2092 entry_done
->entry_idx
);
2095 __set_bit(TXDONE_UNKNOWN
, &txdesc
.flags
);
2098 rt2x00lib_txdone(entry_done
, &txdesc
);
2099 entry_done
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
2103 * Obtain the status about this packet.
2106 switch (rt2x00_get_field32(reg
, STA_CSR4_TX_RESULT
)) {
2107 case 0: /* Success, maybe with retry */
2108 __set_bit(TXDONE_SUCCESS
, &txdesc
.flags
);
2110 case 6: /* Failure, excessive retries */
2111 __set_bit(TXDONE_EXCESSIVE_RETRY
, &txdesc
.flags
);
2112 /* Don't break, this is a failed frame! */
2113 default: /* Failure */
2114 __set_bit(TXDONE_FAILURE
, &txdesc
.flags
);
2116 txdesc
.retry
= rt2x00_get_field32(reg
, STA_CSR4_RETRY_COUNT
);
2118 rt2x00lib_txdone(entry
, &txdesc
);
2122 static irqreturn_t
rt61pci_interrupt(int irq
, void *dev_instance
)
2124 struct rt2x00_dev
*rt2x00dev
= dev_instance
;
2129 * Get the interrupt sources & saved to local variable.
2130 * Write register value back to clear pending interrupts.
2132 rt2x00pci_register_read(rt2x00dev
, MCU_INT_SOURCE_CSR
, ®_mcu
);
2133 rt2x00pci_register_write(rt2x00dev
, MCU_INT_SOURCE_CSR
, reg_mcu
);
2135 rt2x00pci_register_read(rt2x00dev
, INT_SOURCE_CSR
, ®
);
2136 rt2x00pci_register_write(rt2x00dev
, INT_SOURCE_CSR
, reg
);
2138 if (!reg
&& !reg_mcu
)
2141 if (!test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
2145 * Handle interrupts, walk through all bits
2146 * and run the tasks, the bits are checked in order of
2151 * 1 - Rx ring done interrupt.
2153 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_RXDONE
))
2154 rt2x00pci_rxdone(rt2x00dev
);
2157 * 2 - Tx ring done interrupt.
2159 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_TXDONE
))
2160 rt61pci_txdone(rt2x00dev
);
2163 * 3 - Handle MCU command done.
2166 rt2x00pci_register_write(rt2x00dev
,
2167 M2H_CMD_DONE_CSR
, 0xffffffff);
2173 * Device probe functions.
2175 static int rt61pci_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
2177 struct eeprom_93cx6 eeprom
;
2183 rt2x00pci_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
2185 eeprom
.data
= rt2x00dev
;
2186 eeprom
.register_read
= rt61pci_eepromregister_read
;
2187 eeprom
.register_write
= rt61pci_eepromregister_write
;
2188 eeprom
.width
= rt2x00_get_field32(reg
, E2PROM_CSR_TYPE_93C46
) ?
2189 PCI_EEPROM_WIDTH_93C46
: PCI_EEPROM_WIDTH_93C66
;
2190 eeprom
.reg_data_in
= 0;
2191 eeprom
.reg_data_out
= 0;
2192 eeprom
.reg_data_clock
= 0;
2193 eeprom
.reg_chip_select
= 0;
2195 eeprom_93cx6_multiread(&eeprom
, EEPROM_BASE
, rt2x00dev
->eeprom
,
2196 EEPROM_SIZE
/ sizeof(u16
));
2199 * Start validation of the data that has been read.
2201 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
2202 if (!is_valid_ether_addr(mac
)) {
2203 random_ether_addr(mac
);
2204 EEPROM(rt2x00dev
, "MAC: %pM\n", mac
);
2207 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &word
);
2208 if (word
== 0xffff) {
2209 rt2x00_set_field16(&word
, EEPROM_ANTENNA_NUM
, 2);
2210 rt2x00_set_field16(&word
, EEPROM_ANTENNA_TX_DEFAULT
,
2212 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RX_DEFAULT
,
2214 rt2x00_set_field16(&word
, EEPROM_ANTENNA_FRAME_TYPE
, 0);
2215 rt2x00_set_field16(&word
, EEPROM_ANTENNA_DYN_TXAGC
, 0);
2216 rt2x00_set_field16(&word
, EEPROM_ANTENNA_HARDWARE_RADIO
, 0);
2217 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RF_TYPE
, RF5225
);
2218 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
2219 EEPROM(rt2x00dev
, "Antenna: 0x%04x\n", word
);
2222 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &word
);
2223 if (word
== 0xffff) {
2224 rt2x00_set_field16(&word
, EEPROM_NIC_ENABLE_DIVERSITY
, 0);
2225 rt2x00_set_field16(&word
, EEPROM_NIC_TX_DIVERSITY
, 0);
2226 rt2x00_set_field16(&word
, EEPROM_NIC_RX_FIXED
, 0);
2227 rt2x00_set_field16(&word
, EEPROM_NIC_TX_FIXED
, 0);
2228 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_BG
, 0);
2229 rt2x00_set_field16(&word
, EEPROM_NIC_CARDBUS_ACCEL
, 0);
2230 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_A
, 0);
2231 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC
, word
);
2232 EEPROM(rt2x00dev
, "NIC: 0x%04x\n", word
);
2235 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED
, &word
);
2236 if (word
== 0xffff) {
2237 rt2x00_set_field16(&word
, EEPROM_LED_LED_MODE
,
2239 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED
, word
);
2240 EEPROM(rt2x00dev
, "Led: 0x%04x\n", word
);
2243 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &word
);
2244 if (word
== 0xffff) {
2245 rt2x00_set_field16(&word
, EEPROM_FREQ_OFFSET
, 0);
2246 rt2x00_set_field16(&word
, EEPROM_FREQ_SEQ
, 0);
2247 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
2248 EEPROM(rt2x00dev
, "Freq: 0x%04x\n", word
);
2251 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, &word
);
2252 if (word
== 0xffff) {
2253 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_1
, 0);
2254 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_2
, 0);
2255 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, word
);
2256 EEPROM(rt2x00dev
, "RSSI OFFSET BG: 0x%04x\n", word
);
2258 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_BG_1
);
2259 if (value
< -10 || value
> 10)
2260 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_1
, 0);
2261 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_BG_2
);
2262 if (value
< -10 || value
> 10)
2263 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_2
, 0);
2264 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, word
);
2267 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, &word
);
2268 if (word
== 0xffff) {
2269 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_1
, 0);
2270 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_2
, 0);
2271 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, word
);
2272 EEPROM(rt2x00dev
, "RSSI OFFSET A: 0x%04x\n", word
);
2274 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_A_1
);
2275 if (value
< -10 || value
> 10)
2276 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_1
, 0);
2277 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_A_2
);
2278 if (value
< -10 || value
> 10)
2279 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_2
, 0);
2280 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, word
);
2286 static int rt61pci_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
2293 * Read EEPROM word for configuration.
2295 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
2298 * Identify RF chipset.
2300 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RF_TYPE
);
2301 rt2x00pci_register_read(rt2x00dev
, MAC_CSR0
, ®
);
2302 rt2x00_set_chip_rf(rt2x00dev
, value
, reg
);
2303 rt2x00_print_chip(rt2x00dev
);
2305 if (!rt2x00_rf(&rt2x00dev
->chip
, RF5225
) &&
2306 !rt2x00_rf(&rt2x00dev
->chip
, RF5325
) &&
2307 !rt2x00_rf(&rt2x00dev
->chip
, RF2527
) &&
2308 !rt2x00_rf(&rt2x00dev
->chip
, RF2529
)) {
2309 ERROR(rt2x00dev
, "Invalid RF chipset detected.\n");
2314 * Determine number of antennas.
2316 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_NUM
) == 2)
2317 __set_bit(CONFIG_DOUBLE_ANTENNA
, &rt2x00dev
->flags
);
2320 * Identify default antenna configuration.
2322 rt2x00dev
->default_ant
.tx
=
2323 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TX_DEFAULT
);
2324 rt2x00dev
->default_ant
.rx
=
2325 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RX_DEFAULT
);
2328 * Read the Frame type.
2330 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_FRAME_TYPE
))
2331 __set_bit(CONFIG_FRAME_TYPE
, &rt2x00dev
->flags
);
2334 * Detect if this device has a hardware controlled radio.
2336 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_HARDWARE_RADIO
))
2337 __set_bit(CONFIG_SUPPORT_HW_BUTTON
, &rt2x00dev
->flags
);
2340 * Read frequency offset and RF programming sequence.
2342 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
2343 if (rt2x00_get_field16(eeprom
, EEPROM_FREQ_SEQ
))
2344 __set_bit(CONFIG_RF_SEQUENCE
, &rt2x00dev
->flags
);
2346 rt2x00dev
->freq_offset
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_OFFSET
);
2349 * Read external LNA informations.
2351 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
2353 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_A
))
2354 __set_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
);
2355 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_BG
))
2356 __set_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
);
2359 * When working with a RF2529 chip without double antenna,
2360 * the antenna settings should be gathered from the NIC
2363 if (rt2x00_rf(&rt2x00dev
->chip
, RF2529
) &&
2364 !test_bit(CONFIG_DOUBLE_ANTENNA
, &rt2x00dev
->flags
)) {
2365 rt2x00dev
->default_ant
.rx
=
2366 ANTENNA_A
+ rt2x00_get_field16(eeprom
, EEPROM_NIC_RX_FIXED
);
2367 rt2x00dev
->default_ant
.tx
=
2368 ANTENNA_B
- rt2x00_get_field16(eeprom
, EEPROM_NIC_TX_FIXED
);
2370 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_TX_DIVERSITY
))
2371 rt2x00dev
->default_ant
.tx
= ANTENNA_SW_DIVERSITY
;
2372 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_ENABLE_DIVERSITY
))
2373 rt2x00dev
->default_ant
.rx
= ANTENNA_SW_DIVERSITY
;
2377 * Store led settings, for correct led behaviour.
2378 * If the eeprom value is invalid,
2379 * switch to default led mode.
2381 #ifdef CONFIG_RT2X00_LIB_LEDS
2382 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED
, &eeprom
);
2383 value
= rt2x00_get_field16(eeprom
, EEPROM_LED_LED_MODE
);
2385 rt61pci_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
2386 rt61pci_init_led(rt2x00dev
, &rt2x00dev
->led_assoc
, LED_TYPE_ASSOC
);
2387 if (value
== LED_MODE_SIGNAL_STRENGTH
)
2388 rt61pci_init_led(rt2x00dev
, &rt2x00dev
->led_qual
,
2391 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_LED_MODE
, value
);
2392 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_0
,
2393 rt2x00_get_field16(eeprom
,
2394 EEPROM_LED_POLARITY_GPIO_0
));
2395 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_1
,
2396 rt2x00_get_field16(eeprom
,
2397 EEPROM_LED_POLARITY_GPIO_1
));
2398 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_2
,
2399 rt2x00_get_field16(eeprom
,
2400 EEPROM_LED_POLARITY_GPIO_2
));
2401 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_3
,
2402 rt2x00_get_field16(eeprom
,
2403 EEPROM_LED_POLARITY_GPIO_3
));
2404 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_4
,
2405 rt2x00_get_field16(eeprom
,
2406 EEPROM_LED_POLARITY_GPIO_4
));
2407 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_ACT
,
2408 rt2x00_get_field16(eeprom
, EEPROM_LED_POLARITY_ACT
));
2409 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_READY_BG
,
2410 rt2x00_get_field16(eeprom
,
2411 EEPROM_LED_POLARITY_RDY_G
));
2412 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_READY_A
,
2413 rt2x00_get_field16(eeprom
,
2414 EEPROM_LED_POLARITY_RDY_A
));
2415 #endif /* CONFIG_RT2X00_LIB_LEDS */
2421 * RF value list for RF5225 & RF5325
2422 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2424 static const struct rf_channel rf_vals_noseq
[] = {
2425 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2426 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2427 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2428 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2429 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2430 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2431 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2432 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2433 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2434 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2435 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2436 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2437 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2438 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2440 /* 802.11 UNI / HyperLan 2 */
2441 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2442 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2443 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2444 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2445 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2446 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2447 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2448 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2450 /* 802.11 HyperLan 2 */
2451 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2452 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2453 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2454 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2455 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2456 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2457 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2458 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2459 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2460 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2463 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2464 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2465 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2466 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2467 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2468 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2470 /* MMAC(Japan)J52 ch 34,38,42,46 */
2471 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2472 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2473 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2474 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2478 * RF value list for RF5225 & RF5325
2479 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2481 static const struct rf_channel rf_vals_seq
[] = {
2482 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2483 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2484 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2485 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2486 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2487 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2488 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2489 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2490 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2491 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2492 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2493 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2494 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2495 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2497 /* 802.11 UNI / HyperLan 2 */
2498 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2499 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2500 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2501 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2502 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2503 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2504 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2505 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2507 /* 802.11 HyperLan 2 */
2508 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2509 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2510 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2511 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2512 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2513 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2514 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2515 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2516 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2517 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2520 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2521 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2522 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2523 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2524 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2525 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2527 /* MMAC(Japan)J52 ch 34,38,42,46 */
2528 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2529 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2530 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2531 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2534 static int rt61pci_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
2536 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
2537 struct channel_info
*info
;
2542 * Initialize all hw fields.
2544 rt2x00dev
->hw
->flags
=
2545 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
2546 IEEE80211_HW_SIGNAL_DBM
|
2547 IEEE80211_HW_SUPPORTS_PS
|
2548 IEEE80211_HW_PS_NULLFUNC_STACK
;
2550 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
2551 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
2552 rt2x00_eeprom_addr(rt2x00dev
,
2553 EEPROM_MAC_ADDR_0
));
2556 * Initialize hw_mode information.
2558 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
2559 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
2561 if (!test_bit(CONFIG_RF_SEQUENCE
, &rt2x00dev
->flags
)) {
2562 spec
->num_channels
= 14;
2563 spec
->channels
= rf_vals_noseq
;
2565 spec
->num_channels
= 14;
2566 spec
->channels
= rf_vals_seq
;
2569 if (rt2x00_rf(&rt2x00dev
->chip
, RF5225
) ||
2570 rt2x00_rf(&rt2x00dev
->chip
, RF5325
)) {
2571 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
2572 spec
->num_channels
= ARRAY_SIZE(rf_vals_seq
);
2576 * Create channel information array
2578 info
= kzalloc(spec
->num_channels
* sizeof(*info
), GFP_KERNEL
);
2582 spec
->channels_info
= info
;
2584 tx_power
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_G_START
);
2585 for (i
= 0; i
< 14; i
++)
2586 info
[i
].tx_power1
= TXPOWER_FROM_DEV(tx_power
[i
]);
2588 if (spec
->num_channels
> 14) {
2589 tx_power
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A_START
);
2590 for (i
= 14; i
< spec
->num_channels
; i
++)
2591 info
[i
].tx_power1
= TXPOWER_FROM_DEV(tx_power
[i
]);
2597 static int rt61pci_probe_hw(struct rt2x00_dev
*rt2x00dev
)
2602 * Disable power saving.
2604 rt2x00pci_register_write(rt2x00dev
, SOFT_RESET_CSR
, 0x00000007);
2607 * Allocate eeprom data.
2609 retval
= rt61pci_validate_eeprom(rt2x00dev
);
2613 retval
= rt61pci_init_eeprom(rt2x00dev
);
2618 * Initialize hw specifications.
2620 retval
= rt61pci_probe_hw_mode(rt2x00dev
);
2625 * This device has multiple filters for control frames,
2626 * but has no a separate filter for PS Poll frames.
2628 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS
, &rt2x00dev
->flags
);
2631 * This device requires firmware and DMA mapped skbs.
2633 __set_bit(DRIVER_REQUIRE_FIRMWARE
, &rt2x00dev
->flags
);
2634 __set_bit(DRIVER_REQUIRE_DMA
, &rt2x00dev
->flags
);
2635 if (!modparam_nohwcrypt
)
2636 __set_bit(CONFIG_SUPPORT_HW_CRYPTO
, &rt2x00dev
->flags
);
2639 * Set the rssi offset.
2641 rt2x00dev
->rssi_offset
= DEFAULT_RSSI_OFFSET
;
2647 * IEEE80211 stack callback functions.
2649 static int rt61pci_conf_tx(struct ieee80211_hw
*hw
, u16 queue_idx
,
2650 const struct ieee80211_tx_queue_params
*params
)
2652 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2653 struct data_queue
*queue
;
2654 struct rt2x00_field32 field
;
2660 * First pass the configuration through rt2x00lib, that will
2661 * update the queue settings and validate the input. After that
2662 * we are free to update the registers based on the value
2663 * in the queue parameter.
2665 retval
= rt2x00mac_conf_tx(hw
, queue_idx
, params
);
2670 * We only need to perform additional register initialization
2676 queue
= rt2x00queue_get_queue(rt2x00dev
, queue_idx
);
2678 /* Update WMM TXOP register */
2679 offset
= AC_TXOP_CSR0
+ (sizeof(u32
) * (!!(queue_idx
& 2)));
2680 field
.bit_offset
= (queue_idx
& 1) * 16;
2681 field
.bit_mask
= 0xffff << field
.bit_offset
;
2683 rt2x00pci_register_read(rt2x00dev
, offset
, ®
);
2684 rt2x00_set_field32(®
, field
, queue
->txop
);
2685 rt2x00pci_register_write(rt2x00dev
, offset
, reg
);
2687 /* Update WMM registers */
2688 field
.bit_offset
= queue_idx
* 4;
2689 field
.bit_mask
= 0xf << field
.bit_offset
;
2691 rt2x00pci_register_read(rt2x00dev
, AIFSN_CSR
, ®
);
2692 rt2x00_set_field32(®
, field
, queue
->aifs
);
2693 rt2x00pci_register_write(rt2x00dev
, AIFSN_CSR
, reg
);
2695 rt2x00pci_register_read(rt2x00dev
, CWMIN_CSR
, ®
);
2696 rt2x00_set_field32(®
, field
, queue
->cw_min
);
2697 rt2x00pci_register_write(rt2x00dev
, CWMIN_CSR
, reg
);
2699 rt2x00pci_register_read(rt2x00dev
, CWMAX_CSR
, ®
);
2700 rt2x00_set_field32(®
, field
, queue
->cw_max
);
2701 rt2x00pci_register_write(rt2x00dev
, CWMAX_CSR
, reg
);
2706 static u64
rt61pci_get_tsf(struct ieee80211_hw
*hw
)
2708 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2712 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR13
, ®
);
2713 tsf
= (u64
) rt2x00_get_field32(reg
, TXRX_CSR13_HIGH_TSFTIMER
) << 32;
2714 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR12
, ®
);
2715 tsf
|= rt2x00_get_field32(reg
, TXRX_CSR12_LOW_TSFTIMER
);
2720 static const struct ieee80211_ops rt61pci_mac80211_ops
= {
2722 .start
= rt2x00mac_start
,
2723 .stop
= rt2x00mac_stop
,
2724 .add_interface
= rt2x00mac_add_interface
,
2725 .remove_interface
= rt2x00mac_remove_interface
,
2726 .config
= rt2x00mac_config
,
2727 .configure_filter
= rt2x00mac_configure_filter
,
2728 .set_tim
= rt2x00mac_set_tim
,
2729 .set_key
= rt2x00mac_set_key
,
2730 .get_stats
= rt2x00mac_get_stats
,
2731 .bss_info_changed
= rt2x00mac_bss_info_changed
,
2732 .conf_tx
= rt61pci_conf_tx
,
2733 .get_tx_stats
= rt2x00mac_get_tx_stats
,
2734 .get_tsf
= rt61pci_get_tsf
,
2735 .rfkill_poll
= rt2x00mac_rfkill_poll
,
2738 static const struct rt2x00lib_ops rt61pci_rt2x00_ops
= {
2739 .irq_handler
= rt61pci_interrupt
,
2740 .probe_hw
= rt61pci_probe_hw
,
2741 .get_firmware_name
= rt61pci_get_firmware_name
,
2742 .check_firmware
= rt61pci_check_firmware
,
2743 .load_firmware
= rt61pci_load_firmware
,
2744 .initialize
= rt2x00pci_initialize
,
2745 .uninitialize
= rt2x00pci_uninitialize
,
2746 .get_entry_state
= rt61pci_get_entry_state
,
2747 .clear_entry
= rt61pci_clear_entry
,
2748 .set_device_state
= rt61pci_set_device_state
,
2749 .rfkill_poll
= rt61pci_rfkill_poll
,
2750 .link_stats
= rt61pci_link_stats
,
2751 .reset_tuner
= rt61pci_reset_tuner
,
2752 .link_tuner
= rt61pci_link_tuner
,
2753 .write_tx_desc
= rt61pci_write_tx_desc
,
2754 .write_tx_data
= rt2x00pci_write_tx_data
,
2755 .write_beacon
= rt61pci_write_beacon
,
2756 .kick_tx_queue
= rt61pci_kick_tx_queue
,
2757 .kill_tx_queue
= rt61pci_kill_tx_queue
,
2758 .fill_rxdone
= rt61pci_fill_rxdone
,
2759 .config_shared_key
= rt61pci_config_shared_key
,
2760 .config_pairwise_key
= rt61pci_config_pairwise_key
,
2761 .config_filter
= rt61pci_config_filter
,
2762 .config_intf
= rt61pci_config_intf
,
2763 .config_erp
= rt61pci_config_erp
,
2764 .config_ant
= rt61pci_config_ant
,
2765 .config
= rt61pci_config
,
2768 static const struct data_queue_desc rt61pci_queue_rx
= {
2769 .entry_num
= RX_ENTRIES
,
2770 .data_size
= DATA_FRAME_SIZE
,
2771 .desc_size
= RXD_DESC_SIZE
,
2772 .priv_size
= sizeof(struct queue_entry_priv_pci
),
2775 static const struct data_queue_desc rt61pci_queue_tx
= {
2776 .entry_num
= TX_ENTRIES
,
2777 .data_size
= DATA_FRAME_SIZE
,
2778 .desc_size
= TXD_DESC_SIZE
,
2779 .priv_size
= sizeof(struct queue_entry_priv_pci
),
2782 static const struct data_queue_desc rt61pci_queue_bcn
= {
2783 .entry_num
= 4 * BEACON_ENTRIES
,
2784 .data_size
= 0, /* No DMA required for beacons */
2785 .desc_size
= TXINFO_SIZE
,
2786 .priv_size
= sizeof(struct queue_entry_priv_pci
),
2789 static const struct rt2x00_ops rt61pci_ops
= {
2790 .name
= KBUILD_MODNAME
,
2793 .eeprom_size
= EEPROM_SIZE
,
2795 .tx_queues
= NUM_TX_QUEUES
,
2796 .extra_tx_headroom
= 0,
2797 .rx
= &rt61pci_queue_rx
,
2798 .tx
= &rt61pci_queue_tx
,
2799 .bcn
= &rt61pci_queue_bcn
,
2800 .lib
= &rt61pci_rt2x00_ops
,
2801 .hw
= &rt61pci_mac80211_ops
,
2802 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2803 .debugfs
= &rt61pci_rt2x00debug
,
2804 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2808 * RT61pci module information.
2810 static struct pci_device_id rt61pci_device_table
[] = {
2812 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops
) },
2814 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops
) },
2816 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops
) },
2820 MODULE_AUTHOR(DRV_PROJECT
);
2821 MODULE_VERSION(DRV_VERSION
);
2822 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2823 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2824 "PCI & PCMCIA chipset based cards");
2825 MODULE_DEVICE_TABLE(pci
, rt61pci_device_table
);
2826 MODULE_FIRMWARE(FIRMWARE_RT2561
);
2827 MODULE_FIRMWARE(FIRMWARE_RT2561s
);
2828 MODULE_FIRMWARE(FIRMWARE_RT2661
);
2829 MODULE_LICENSE("GPL");
2831 static struct pci_driver rt61pci_driver
= {
2832 .name
= KBUILD_MODNAME
,
2833 .id_table
= rt61pci_device_table
,
2834 .probe
= rt2x00pci_probe
,
2835 .remove
= __devexit_p(rt2x00pci_remove
),
2836 .suspend
= rt2x00pci_suspend
,
2837 .resume
= rt2x00pci_resume
,
2840 static int __init
rt61pci_init(void)
2842 return pci_register_driver(&rt61pci_driver
);
2845 static void __exit
rt61pci_exit(void)
2847 pci_unregister_driver(&rt61pci_driver
);
2850 module_init(rt61pci_init
);
2851 module_exit(rt61pci_exit
);