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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / ata / sata_sil24.c
blob1370df6c420ceed4317ff3cec8800a7f00a7507d
1 /*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <linux/libata.h>
31
32 #define DRV_NAME "sata_sil24"
33 #define DRV_VERSION "1.1"
34
35 /*
36 * Port request block (PRB) 32 bytes
37 */
38 struct sil24_prb {
39 __le16 ctrl;
40 __le16 prot;
41 __le32 rx_cnt;
42 u8 fis[6 * 4];
43 };
44
45 /*
46 * Scatter gather entry (SGE) 16 bytes
47 */
48 struct sil24_sge {
49 __le64 addr;
50 __le32 cnt;
51 __le32 flags;
52 };
53
54
55 enum {
56 SIL24_HOST_BAR = 0,
57 SIL24_PORT_BAR = 2,
58
59 /* sil24 fetches in chunks of 64bytes. The first block
60 * contains the PRB and two SGEs. From the second block, it's
61 * consisted of four SGEs and called SGT. Calculate the
62 * number of SGTs that fit into one page.
63 */
64 SIL24_PRB_SZ = sizeof(struct sil24_prb)
65 + 2 * sizeof(struct sil24_sge),
66 SIL24_MAX_SGT = (PAGE_SIZE - SIL24_PRB_SZ)
67 / (4 * sizeof(struct sil24_sge)),
68
69 /* This will give us one unused SGEs for ATA. This extra SGE
70 * will be used to store CDB for ATAPI devices.
71 */
72 SIL24_MAX_SGE = 4 * SIL24_MAX_SGT + 1,
73
74 /*
75 * Global controller registers (128 bytes @ BAR0)
76 */
77 /* 32 bit regs */
78 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
79 HOST_CTRL = 0x40,
80 HOST_IRQ_STAT = 0x44,
81 HOST_PHY_CFG = 0x48,
82 HOST_BIST_CTRL = 0x50,
83 HOST_BIST_PTRN = 0x54,
84 HOST_BIST_STAT = 0x58,
85 HOST_MEM_BIST_STAT = 0x5c,
86 HOST_FLASH_CMD = 0x70,
87 /* 8 bit regs */
88 HOST_FLASH_DATA = 0x74,
89 HOST_TRANSITION_DETECT = 0x75,
90 HOST_GPIO_CTRL = 0x76,
91 HOST_I2C_ADDR = 0x78, /* 32 bit */
92 HOST_I2C_DATA = 0x7c,
93 HOST_I2C_XFER_CNT = 0x7e,
94 HOST_I2C_CTRL = 0x7f,
95
96 /* HOST_SLOT_STAT bits */
97 HOST_SSTAT_ATTN = (1 << 31),
98
99 /* HOST_CTRL bits */
100 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
101 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
102 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
103 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
104 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
105 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
106
107 /*
108 * Port registers
109 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
110 */
111 PORT_REGS_SIZE = 0x2000,
112
113 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
114 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
115
116 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
117 PORT_PMP_STATUS = 0x0000, /* port device status offset */
118 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
119 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
120
121 /* 32 bit regs */
122 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
123 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
124 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
125 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
126 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
127 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
128 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
129 PORT_CMD_ERR = 0x1024, /* command error number */
130 PORT_FIS_CFG = 0x1028,
131 PORT_FIFO_THRES = 0x102c,
132 /* 16 bit regs */
133 PORT_DECODE_ERR_CNT = 0x1040,
134 PORT_DECODE_ERR_THRESH = 0x1042,
135 PORT_CRC_ERR_CNT = 0x1044,
136 PORT_CRC_ERR_THRESH = 0x1046,
137 PORT_HSHK_ERR_CNT = 0x1048,
138 PORT_HSHK_ERR_THRESH = 0x104a,
139 /* 32 bit regs */
140 PORT_PHY_CFG = 0x1050,
141 PORT_SLOT_STAT = 0x1800,
142 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
143 PORT_CONTEXT = 0x1e04,
144 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
145 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
146 PORT_SCONTROL = 0x1f00,
147 PORT_SSTATUS = 0x1f04,
148 PORT_SERROR = 0x1f08,
149 PORT_SACTIVE = 0x1f0c,
150
151 /* PORT_CTRL_STAT bits */
152 PORT_CS_PORT_RST = (1 << 0), /* port reset */
153 PORT_CS_DEV_RST = (1 << 1), /* device reset */
154 PORT_CS_INIT = (1 << 2), /* port initialize */
155 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
156 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
157 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
158 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
159 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
160 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
161
162 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
163 /* bits[11:0] are masked */
164 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
165 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
166 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
167 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
168 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
169 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
170 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
171 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
172 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
173 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
174 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
175 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
176
177 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
178 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
179 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
180
181 /* bits[27:16] are unmasked (raw) */
182 PORT_IRQ_RAW_SHIFT = 16,
183 PORT_IRQ_MASKED_MASK = 0x7ff,
184 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
185
186 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
187 PORT_IRQ_STEER_SHIFT = 30,
188 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
189
190 /* PORT_CMD_ERR constants */
191 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
192 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
193 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
194 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
195 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
196 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
197 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
198 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
199 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
200 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
201 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
202 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
203 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
204 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
205 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
206 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
207 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
208 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
209 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
210 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
211 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
212 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
213
214 /* bits of PRB control field */
215 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
216 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
217 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
218 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
219 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
220
221 /* PRB protocol field */
222 PRB_PROT_PACKET = (1 << 0),
223 PRB_PROT_TCQ = (1 << 1),
224 PRB_PROT_NCQ = (1 << 2),
225 PRB_PROT_READ = (1 << 3),
226 PRB_PROT_WRITE = (1 << 4),
227 PRB_PROT_TRANSPARENT = (1 << 5),
228
229 /*
230 * Other constants
231 */
232 SGE_TRM = (1 << 31), /* Last SGE in chain */
233 SGE_LNK = (1 << 30), /* linked list
234 Points to SGT, not SGE */
235 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
236 data address ignored */
237
238 SIL24_MAX_CMDS = 31,
239
240 /* board id */
241 BID_SIL3124 = 0,
242 BID_SIL3132 = 1,
243 BID_SIL3131 = 2,
244
245 /* host flags */
246 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
247 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
248 ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA |
249 ATA_FLAG_AN | ATA_FLAG_PMP,
250 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
251
252 IRQ_STAT_4PORTS = 0xf,
253 };
254
255 struct sil24_ata_block {
256 struct sil24_prb prb;
257 struct sil24_sge sge[SIL24_MAX_SGE];
258 };
259
260 struct sil24_atapi_block {
261 struct sil24_prb prb;
262 u8 cdb[16];
263 struct sil24_sge sge[SIL24_MAX_SGE];
264 };
265
266 union sil24_cmd_block {
267 struct sil24_ata_block ata;
268 struct sil24_atapi_block atapi;
269 };
270
271 static struct sil24_cerr_info {
272 unsigned int err_mask, action;
273 const char *desc;
274 } sil24_cerr_db[] = {
275 [0] = { AC_ERR_DEV, 0,
276 "device error" },
277 [PORT_CERR_DEV] = { AC_ERR_DEV, 0,
278 "device error via D2H FIS" },
279 [PORT_CERR_SDB] = { AC_ERR_DEV, 0,
280 "device error via SDB FIS" },
281 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_RESET,
282 "error in data FIS" },
283 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_RESET,
284 "failed to transmit command FIS" },
285 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_RESET,
286 "protocol mismatch" },
287 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_RESET,
288 "data directon mismatch" },
289 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
290 "ran out of SGEs while writing" },
291 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
292 "ran out of SGEs while reading" },
293 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_RESET,
294 "invalid data directon for ATAPI CDB" },
295 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
296 "SGT not on qword boundary" },
297 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
298 "PCI target abort while fetching SGT" },
299 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
300 "PCI master abort while fetching SGT" },
301 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
302 "PCI parity error while fetching SGT" },
303 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
304 "PRB not on qword boundary" },
305 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
306 "PCI target abort while fetching PRB" },
307 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
308 "PCI master abort while fetching PRB" },
309 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
310 "PCI parity error while fetching PRB" },
311 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
312 "undefined error while transferring data" },
313 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
314 "PCI target abort while transferring data" },
315 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
316 "PCI master abort while transferring data" },
317 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
318 "PCI parity error while transferring data" },
319 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_RESET,
320 "FIS received while sending service FIS" },
321 };
322
323 /*
324 * ap->private_data
325 *
326 * The preview driver always returned 0 for status. We emulate it
327 * here from the previous interrupt.
328 */
329 struct sil24_port_priv {
330 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
331 dma_addr_t cmd_block_dma; /* DMA base addr for them */
332 int do_port_rst;
333 };
334
335 static void sil24_dev_config(struct ata_device *dev);
336 static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val);
337 static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val);
338 static int sil24_qc_defer(struct ata_queued_cmd *qc);
339 static void sil24_qc_prep(struct ata_queued_cmd *qc);
340 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
341 static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc);
342 static void sil24_pmp_attach(struct ata_port *ap);
343 static void sil24_pmp_detach(struct ata_port *ap);
344 static void sil24_freeze(struct ata_port *ap);
345 static void sil24_thaw(struct ata_port *ap);
346 static int sil24_softreset(struct ata_link *link, unsigned int *class,
347 unsigned long deadline);
348 static int sil24_hardreset(struct ata_link *link, unsigned int *class,
349 unsigned long deadline);
350 static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
351 unsigned long deadline);
352 static void sil24_error_handler(struct ata_port *ap);
353 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
354 static int sil24_port_start(struct ata_port *ap);
355 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
356 #ifdef CONFIG_PM
357 static int sil24_pci_device_resume(struct pci_dev *pdev);
358 static int sil24_port_resume(struct ata_port *ap);
359 #endif
360
361 static const struct pci_device_id sil24_pci_tbl[] = {
362 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
363 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
364 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
365 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
366 { PCI_VDEVICE(CMD, 0x0244), BID_SIL3132 },
367 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
368 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
369
370 { } /* terminate list */
371 };
372
373 static struct pci_driver sil24_pci_driver = {
374 .name = DRV_NAME,
375 .id_table = sil24_pci_tbl,
376 .probe = sil24_init_one,
377 .remove = ata_pci_remove_one,
378 #ifdef CONFIG_PM
379 .suspend = ata_pci_device_suspend,
380 .resume = sil24_pci_device_resume,
381 #endif
382 };
383
384 static struct scsi_host_template sil24_sht = {
385 ATA_NCQ_SHT(DRV_NAME),
386 .can_queue = SIL24_MAX_CMDS,
387 .sg_tablesize = SIL24_MAX_SGE,
388 .dma_boundary = ATA_DMA_BOUNDARY,
389 };
390
391 static struct ata_port_operations sil24_ops = {
392 .inherits = &sata_pmp_port_ops,
393
394 .qc_defer = sil24_qc_defer,
395 .qc_prep = sil24_qc_prep,
396 .qc_issue = sil24_qc_issue,
397 .qc_fill_rtf = sil24_qc_fill_rtf,
398
399 .freeze = sil24_freeze,
400 .thaw = sil24_thaw,
401 .softreset = sil24_softreset,
402 .hardreset = sil24_hardreset,
403 .pmp_softreset = sil24_softreset,
404 .pmp_hardreset = sil24_pmp_hardreset,
405 .error_handler = sil24_error_handler,
406 .post_internal_cmd = sil24_post_internal_cmd,
407 .dev_config = sil24_dev_config,
408
409 .scr_read = sil24_scr_read,
410 .scr_write = sil24_scr_write,
411 .pmp_attach = sil24_pmp_attach,
412 .pmp_detach = sil24_pmp_detach,
413
414 .port_start = sil24_port_start,
415 #ifdef CONFIG_PM
416 .port_resume = sil24_port_resume,
417 #endif
418 };
419
420 static int sata_sil24_msi; /* Disable MSI */
421 module_param_named(msi, sata_sil24_msi, bool, S_IRUGO);
422 MODULE_PARM_DESC(msi, "Enable MSI (Default: false)");
423
424 /*
425 * Use bits 30-31 of port_flags to encode available port numbers.
426 * Current maxium is 4.
427 */
428 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
429 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
430
431 static const struct ata_port_info sil24_port_info[] = {
432 /* sil_3124 */
433 {
434 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
435 SIL24_FLAG_PCIX_IRQ_WOC,
436 .pio_mask = ATA_PIO4,
437 .mwdma_mask = ATA_MWDMA2,
438 .udma_mask = ATA_UDMA5,
439 .port_ops = &sil24_ops,
440 },
441 /* sil_3132 */
442 {
443 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
444 .pio_mask = ATA_PIO4,
445 .mwdma_mask = ATA_MWDMA2,
446 .udma_mask = ATA_UDMA5,
447 .port_ops = &sil24_ops,
448 },
449 /* sil_3131/sil_3531 */
450 {
451 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
452 .pio_mask = ATA_PIO4,
453 .mwdma_mask = ATA_MWDMA2,
454 .udma_mask = ATA_UDMA5,
455 .port_ops = &sil24_ops,
456 },
457 };
458
459 static int sil24_tag(int tag)
460 {
461 if (unlikely(ata_tag_internal(tag)))
462 return 0;
463 return tag;
464 }
465
466 static unsigned long sil24_port_offset(struct ata_port *ap)
467 {
468 return ap->port_no * PORT_REGS_SIZE;
469 }
470
471 static void __iomem *sil24_port_base(struct ata_port *ap)
472 {
473 return ap->host->iomap[SIL24_PORT_BAR] + sil24_port_offset(ap);
474 }
475
476 static void sil24_dev_config(struct ata_device *dev)
477 {
478 void __iomem *port = sil24_port_base(dev->link->ap);
479
480 if (dev->cdb_len == 16)
481 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
482 else
483 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
484 }
485
486 static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf)
487 {
488 void __iomem *port = sil24_port_base(ap);
489 struct sil24_prb __iomem *prb;
490 u8 fis[6 * 4];
491
492 prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ;
493 memcpy_fromio(fis, prb->fis, sizeof(fis));
494 ata_tf_from_fis(fis, tf);
495 }
496
497 static int sil24_scr_map[] = {
498 [SCR_CONTROL] = 0,
499 [SCR_STATUS] = 1,
500 [SCR_ERROR] = 2,
501 [SCR_ACTIVE] = 3,
502 };
503
504 static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val)
505 {
506 void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL;
507
508 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
509 void __iomem *addr;
510 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
511 *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4);
512 return 0;
513 }
514 return -EINVAL;
515 }
516
517 static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val)
518 {
519 void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL;
520
521 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
522 void __iomem *addr;
523 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
524 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
525 return 0;
526 }
527 return -EINVAL;
528 }
529
530 static void sil24_config_port(struct ata_port *ap)
531 {
532 void __iomem *port = sil24_port_base(ap);
533
534 /* configure IRQ WoC */
535 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
536 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
537 else
538 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
539
540 /* zero error counters. */
541 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
542 writel(0x8000, port + PORT_CRC_ERR_THRESH);
543 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
544 writel(0x0000, port + PORT_DECODE_ERR_CNT);
545 writel(0x0000, port + PORT_CRC_ERR_CNT);
546 writel(0x0000, port + PORT_HSHK_ERR_CNT);
547
548 /* always use 64bit activation */
549 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
550
551 /* clear port multiplier enable and resume bits */
552 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
553 }
554
555 static void sil24_config_pmp(struct ata_port *ap, int attached)
556 {
557 void __iomem *port = sil24_port_base(ap);
558
559 if (attached)
560 writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT);
561 else
562 writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR);
563 }
564
565 static void sil24_clear_pmp(struct ata_port *ap)
566 {
567 void __iomem *port = sil24_port_base(ap);
568 int i;
569
570 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
571
572 for (i = 0; i < SATA_PMP_MAX_PORTS; i++) {
573 void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE;
574
575 writel(0, pmp_base + PORT_PMP_STATUS);
576 writel(0, pmp_base + PORT_PMP_QACTIVE);
577 }
578 }
579
580 static int sil24_init_port(struct ata_port *ap)
581 {
582 void __iomem *port = sil24_port_base(ap);
583 struct sil24_port_priv *pp = ap->private_data;
584 u32 tmp;
585
586 /* clear PMP error status */
587 if (sata_pmp_attached(ap))
588 sil24_clear_pmp(ap);
589
590 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
591 ata_wait_register(port + PORT_CTRL_STAT,
592 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
593 tmp = ata_wait_register(port + PORT_CTRL_STAT,
594 PORT_CS_RDY, 0, 10, 100);
595
596 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) {
597 pp->do_port_rst = 1;
598 ap->link.eh_context.i.action |= ATA_EH_RESET;
599 return -EIO;
600 }
601
602 return 0;
603 }
604
605 static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
606 const struct ata_taskfile *tf,
607 int is_cmd, u32 ctrl,
608 unsigned long timeout_msec)
609 {
610 void __iomem *port = sil24_port_base(ap);
611 struct sil24_port_priv *pp = ap->private_data;
612 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
613 dma_addr_t paddr = pp->cmd_block_dma;
614 u32 irq_enabled, irq_mask, irq_stat;
615 int rc;
616
617 prb->ctrl = cpu_to_le16(ctrl);
618 ata_tf_to_fis(tf, pmp, is_cmd, prb->fis);
619
620 /* temporarily plug completion and error interrupts */
621 irq_enabled = readl(port + PORT_IRQ_ENABLE_SET);
622 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
623
624 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
625 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
626
627 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
628 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask, 0x0,
629 10, timeout_msec);
630
631 writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
632 irq_stat >>= PORT_IRQ_RAW_SHIFT;
633
634 if (irq_stat & PORT_IRQ_COMPLETE)
635 rc = 0;
636 else {
637 /* force port into known state */
638 sil24_init_port(ap);
639
640 if (irq_stat & PORT_IRQ_ERROR)
641 rc = -EIO;
642 else
643 rc = -EBUSY;
644 }
645
646 /* restore IRQ enabled */
647 writel(irq_enabled, port + PORT_IRQ_ENABLE_SET);
648
649 return rc;
650 }
651
652 static int sil24_softreset(struct ata_link *link, unsigned int *class,
653 unsigned long deadline)
654 {
655 struct ata_port *ap = link->ap;
656 int pmp = sata_srst_pmp(link);
657 unsigned long timeout_msec = 0;
658 struct ata_taskfile tf;
659 const char *reason;
660 int rc;
661
662 DPRINTK("ENTER\n");
663
664 /* put the port into known state */
665 if (sil24_init_port(ap)) {
666 reason = "port not ready";
667 goto err;
668 }
669
670 /* do SRST */
671 if (time_after(deadline, jiffies))
672 timeout_msec = jiffies_to_msecs(deadline - jiffies);
673
674 ata_tf_init(link->device, &tf); /* doesn't really matter */
675 rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST,
676 timeout_msec);
677 if (rc == -EBUSY) {
678 reason = "timeout";
679 goto err;
680 } else if (rc) {
681 reason = "SRST command error";
682 goto err;
683 }
684
685 sil24_read_tf(ap, 0, &tf);
686 *class = ata_dev_classify(&tf);
687
688 DPRINTK("EXIT, class=%u\n", *class);
689 return 0;
690
691 err:
692 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
693 return -EIO;
694 }
695
696 static int sil24_hardreset(struct ata_link *link, unsigned int *class,
697 unsigned long deadline)
698 {
699 struct ata_port *ap = link->ap;
700 void __iomem *port = sil24_port_base(ap);
701 struct sil24_port_priv *pp = ap->private_data;
702 int did_port_rst = 0;
703 const char *reason;
704 int tout_msec, rc;
705 u32 tmp;
706
707 retry:
708 /* Sometimes, DEV_RST is not enough to recover the controller.
709 * This happens often after PM DMA CS errata.
710 */
711 if (pp->do_port_rst) {
712 ata_port_printk(ap, KERN_WARNING, "controller in dubious "
713 "state, performing PORT_RST\n");
714
715 writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT);
716 msleep(10);
717 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
718 ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_RDY, 0,
719 10, 5000);
720
721 /* restore port configuration */
722 sil24_config_port(ap);
723 sil24_config_pmp(ap, ap->nr_pmp_links);
724
725 pp->do_port_rst = 0;
726 did_port_rst = 1;
727 }
728
729 /* sil24 does the right thing(tm) without any protection */
730 sata_set_spd(link);
731
732 tout_msec = 100;
733 if (ata_link_online(link))
734 tout_msec = 5000;
735
736 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
737 tmp = ata_wait_register(port + PORT_CTRL_STAT,
738 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10,
739 tout_msec);
740
741 /* SStatus oscillates between zero and valid status after
742 * DEV_RST, debounce it.
743 */
744 rc = sata_link_debounce(link, sata_deb_timing_long, deadline);
745 if (rc) {
746 reason = "PHY debouncing failed";
747 goto err;
748 }
749
750 if (tmp & PORT_CS_DEV_RST) {
751 if (ata_link_offline(link))
752 return 0;
753 reason = "link not ready";
754 goto err;
755 }
756
757 /* Sil24 doesn't store signature FIS after hardreset, so we
758 * can't wait for BSY to clear. Some devices take a long time
759 * to get ready and those devices will choke if we don't wait
760 * for BSY clearance here. Tell libata to perform follow-up
761 * softreset.
762 */
763 return -EAGAIN;
764
765 err:
766 if (!did_port_rst) {
767 pp->do_port_rst = 1;
768 goto retry;
769 }
770
771 ata_link_printk(link, KERN_ERR, "hardreset failed (%s)\n", reason);
772 return -EIO;
773 }
774
775 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
776 struct sil24_sge *sge)
777 {
778 struct scatterlist *sg;
779 struct sil24_sge *last_sge = NULL;
780 unsigned int si;
781
782 for_each_sg(qc->sg, sg, qc->n_elem, si) {
783 sge->addr = cpu_to_le64(sg_dma_address(sg));
784 sge->cnt = cpu_to_le32(sg_dma_len(sg));
785 sge->flags = 0;
786
787 last_sge = sge;
788 sge++;
789 }
790
791 last_sge->flags = cpu_to_le32(SGE_TRM);
792 }
793
794 static int sil24_qc_defer(struct ata_queued_cmd *qc)
795 {
796 struct ata_link *link = qc->dev->link;
797 struct ata_port *ap = link->ap;
798 u8 prot = qc->tf.protocol;
799
800 /*
801 * There is a bug in the chip:
802 * Port LRAM Causes the PRB/SGT Data to be Corrupted
803 * If the host issues a read request for LRAM and SActive registers
804 * while active commands are available in the port, PRB/SGT data in
805 * the LRAM can become corrupted. This issue applies only when
806 * reading from, but not writing to, the LRAM.
807 *
808 * Therefore, reading LRAM when there is no particular error [and
809 * other commands may be outstanding] is prohibited.
810 *
811 * To avoid this bug there are two situations where a command must run
812 * exclusive of any other commands on the port:
813 *
814 * - ATAPI commands which check the sense data
815 * - Passthrough ATA commands which always have ATA_QCFLAG_RESULT_TF
816 * set.
817 *
818 */
819 int is_excl = (ata_is_atapi(prot) ||
820 (qc->flags & ATA_QCFLAG_RESULT_TF));
821
822 if (unlikely(ap->excl_link)) {
823 if (link == ap->excl_link) {
824 if (ap->nr_active_links)
825 return ATA_DEFER_PORT;
826 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
827 } else
828 return ATA_DEFER_PORT;
829 } else if (unlikely(is_excl)) {
830 ap->excl_link = link;
831 if (ap->nr_active_links)
832 return ATA_DEFER_PORT;
833 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
834 }
835
836 return ata_std_qc_defer(qc);
837 }
838
839 static void sil24_qc_prep(struct ata_queued_cmd *qc)
840 {
841 struct ata_port *ap = qc->ap;
842 struct sil24_port_priv *pp = ap->private_data;
843 union sil24_cmd_block *cb;
844 struct sil24_prb *prb;
845 struct sil24_sge *sge;
846 u16 ctrl = 0;
847
848 cb = &pp->cmd_block[sil24_tag(qc->tag)];
849
850 if (!ata_is_atapi(qc->tf.protocol)) {
851 prb = &cb->ata.prb;
852 sge = cb->ata.sge;
853 if (ata_is_data(qc->tf.protocol)) {
854 u16 prot = 0;
855 ctrl = PRB_CTRL_PROTOCOL;
856 if (ata_is_ncq(qc->tf.protocol))
857 prot |= PRB_PROT_NCQ;
858 if (qc->tf.flags & ATA_TFLAG_WRITE)
859 prot |= PRB_PROT_WRITE;
860 else
861 prot |= PRB_PROT_READ;
862 prb->prot = cpu_to_le16(prot);
863 }
864 } else {
865 prb = &cb->atapi.prb;
866 sge = cb->atapi.sge;
867 memset(cb->atapi.cdb, 0, 32);
868 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
869
870 if (ata_is_data(qc->tf.protocol)) {
871 if (qc->tf.flags & ATA_TFLAG_WRITE)
872 ctrl = PRB_CTRL_PACKET_WRITE;
873 else
874 ctrl = PRB_CTRL_PACKET_READ;
875 }
876 }
877
878 prb->ctrl = cpu_to_le16(ctrl);
879 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis);
880
881 if (qc->flags & ATA_QCFLAG_DMAMAP)
882 sil24_fill_sg(qc, sge);
883 }
884
885 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
886 {
887 struct ata_port *ap = qc->ap;
888 struct sil24_port_priv *pp = ap->private_data;
889 void __iomem *port = sil24_port_base(ap);
890 unsigned int tag = sil24_tag(qc->tag);
891 dma_addr_t paddr;
892 void __iomem *activate;
893
894 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
895 activate = port + PORT_CMD_ACTIVATE + tag * 8;
896
897 writel((u32)paddr, activate);
898 writel((u64)paddr >> 32, activate + 4);
899
900 return 0;
901 }
902
903 static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc)
904 {
905 sil24_read_tf(qc->ap, qc->tag, &qc->result_tf);
906 return true;
907 }
908
909 static void sil24_pmp_attach(struct ata_port *ap)
910 {
911 u32 *gscr = ap->link.device->gscr;
912
913 sil24_config_pmp(ap, 1);
914 sil24_init_port(ap);
915
916 if (sata_pmp_gscr_vendor(gscr) == 0x11ab &&
917 sata_pmp_gscr_devid(gscr) == 0x4140) {
918 ata_port_printk(ap, KERN_INFO,
919 "disabling NCQ support due to sil24-mv4140 quirk\n");
920 ap->flags &= ~ATA_FLAG_NCQ;
921 }
922 }
923
924 static void sil24_pmp_detach(struct ata_port *ap)
925 {
926 sil24_init_port(ap);
927 sil24_config_pmp(ap, 0);
928
929 ap->flags |= ATA_FLAG_NCQ;
930 }
931
932 static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
933 unsigned long deadline)
934 {
935 int rc;
936
937 rc = sil24_init_port(link->ap);
938 if (rc) {
939 ata_link_printk(link, KERN_ERR,
940 "hardreset failed (port not ready)\n");
941 return rc;
942 }
943
944 return sata_std_hardreset(link, class, deadline);
945 }
946
947 static void sil24_freeze(struct ata_port *ap)
948 {
949 void __iomem *port = sil24_port_base(ap);
950
951 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
952 * PORT_IRQ_ENABLE instead.
953 */
954 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
955 }
956
957 static void sil24_thaw(struct ata_port *ap)
958 {
959 void __iomem *port = sil24_port_base(ap);
960 u32 tmp;
961
962 /* clear IRQ */
963 tmp = readl(port + PORT_IRQ_STAT);
964 writel(tmp, port + PORT_IRQ_STAT);
965
966 /* turn IRQ back on */
967 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
968 }
969
970 static void sil24_error_intr(struct ata_port *ap)
971 {
972 void __iomem *port = sil24_port_base(ap);
973 struct sil24_port_priv *pp = ap->private_data;
974 struct ata_queued_cmd *qc = NULL;
975 struct ata_link *link;
976 struct ata_eh_info *ehi;
977 int abort = 0, freeze = 0;
978 u32 irq_stat;
979
980 /* on error, we need to clear IRQ explicitly */
981 irq_stat = readl(port + PORT_IRQ_STAT);
982 writel(irq_stat, port + PORT_IRQ_STAT);
983
984 /* first, analyze and record host port events */
985 link = &ap->link;
986 ehi = &link->eh_info;
987 ata_ehi_clear_desc(ehi);
988
989 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
990
991 if (irq_stat & PORT_IRQ_SDB_NOTIFY) {
992 ata_ehi_push_desc(ehi, "SDB notify");
993 sata_async_notification(ap);
994 }
995
996 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
997 ata_ehi_hotplugged(ehi);
998 ata_ehi_push_desc(ehi, "%s",
999 irq_stat & PORT_IRQ_PHYRDY_CHG ?
1000 "PHY RDY changed" : "device exchanged");
1001 freeze = 1;
1002 }
1003
1004 if (irq_stat & PORT_IRQ_UNK_FIS) {
1005 ehi->err_mask |= AC_ERR_HSM;
1006 ehi->action |= ATA_EH_RESET;
1007 ata_ehi_push_desc(ehi, "unknown FIS");
1008 freeze = 1;
1009 }
1010
1011 /* deal with command error */
1012 if (irq_stat & PORT_IRQ_ERROR) {
1013 struct sil24_cerr_info *ci = NULL;
1014 unsigned int err_mask = 0, action = 0;
1015 u32 context, cerr;
1016 int pmp;
1017
1018 abort = 1;
1019
1020 /* DMA Context Switch Failure in Port Multiplier Mode
1021 * errata. If we have active commands to 3 or more
1022 * devices, any error condition on active devices can
1023 * corrupt DMA context switching.
1024 */
1025 if (ap->nr_active_links >= 3) {
1026 ehi->err_mask |= AC_ERR_OTHER;
1027 ehi->action |= ATA_EH_RESET;
1028 ata_ehi_push_desc(ehi, "PMP DMA CS errata");
1029 pp->do_port_rst = 1;
1030 freeze = 1;
1031 }
1032
1033 /* find out the offending link and qc */
1034 if (sata_pmp_attached(ap)) {
1035 context = readl(port + PORT_CONTEXT);
1036 pmp = (context >> 5) & 0xf;
1037
1038 if (pmp < ap->nr_pmp_links) {
1039 link = &ap->pmp_link[pmp];
1040 ehi = &link->eh_info;
1041 qc = ata_qc_from_tag(ap, link->active_tag);
1042
1043 ata_ehi_clear_desc(ehi);
1044 ata_ehi_push_desc(ehi, "irq_stat 0x%08x",
1045 irq_stat);
1046 } else {
1047 err_mask |= AC_ERR_HSM;
1048 action |= ATA_EH_RESET;
1049 freeze = 1;
1050 }
1051 } else
1052 qc = ata_qc_from_tag(ap, link->active_tag);
1053
1054 /* analyze CMD_ERR */
1055 cerr = readl(port + PORT_CMD_ERR);
1056 if (cerr < ARRAY_SIZE(sil24_cerr_db))
1057 ci = &sil24_cerr_db[cerr];
1058
1059 if (ci && ci->desc) {
1060 err_mask |= ci->err_mask;
1061 action |= ci->action;
1062 if (action & ATA_EH_RESET)
1063 freeze = 1;
1064 ata_ehi_push_desc(ehi, "%s", ci->desc);
1065 } else {
1066 err_mask |= AC_ERR_OTHER;
1067 action |= ATA_EH_RESET;
1068 freeze = 1;
1069 ata_ehi_push_desc(ehi, "unknown command error %d",
1070 cerr);
1071 }
1072
1073 /* record error info */
1074 if (qc)
1075 qc->err_mask |= err_mask;
1076 else
1077 ehi->err_mask |= err_mask;
1078
1079 ehi->action |= action;
1080
1081 /* if PMP, resume */
1082 if (sata_pmp_attached(ap))
1083 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT);
1084 }
1085
1086 /* freeze or abort */
1087 if (freeze)
1088 ata_port_freeze(ap);
1089 else if (abort) {
1090 if (qc)
1091 ata_link_abort(qc->dev->link);
1092 else
1093 ata_port_abort(ap);
1094 }
1095 }
1096
1097 static inline void sil24_host_intr(struct ata_port *ap)
1098 {
1099 void __iomem *port = sil24_port_base(ap);
1100 u32 slot_stat, qc_active;
1101 int rc;
1102
1103 /* If PCIX_IRQ_WOC, there's an inherent race window between
1104 * clearing IRQ pending status and reading PORT_SLOT_STAT
1105 * which may cause spurious interrupts afterwards. This is
1106 * unavoidable and much better than losing interrupts which
1107 * happens if IRQ pending is cleared after reading
1108 * PORT_SLOT_STAT.
1109 */
1110 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
1111 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
1112
1113 slot_stat = readl(port + PORT_SLOT_STAT);
1114
1115 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
1116 sil24_error_intr(ap);
1117 return;
1118 }
1119
1120 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
1121 rc = ata_qc_complete_multiple(ap, qc_active);
1122 if (rc > 0)
1123 return;
1124 if (rc < 0) {
1125 struct ata_eh_info *ehi = &ap->link.eh_info;
1126 ehi->err_mask |= AC_ERR_HSM;
1127 ehi->action |= ATA_EH_RESET;
1128 ata_port_freeze(ap);
1129 return;
1130 }
1131
1132 /* spurious interrupts are expected if PCIX_IRQ_WOC */
1133 if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit())
1134 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1135 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
1136 slot_stat, ap->link.active_tag, ap->link.sactive);
1137 }
1138
1139 static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
1140 {
1141 struct ata_host *host = dev_instance;
1142 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1143 unsigned handled = 0;
1144 u32 status;
1145 int i;
1146
1147 status = readl(host_base + HOST_IRQ_STAT);
1148
1149 if (status == 0xffffffff) {
1150 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
1151 "PCI fault or device removal?\n");
1152 goto out;
1153 }
1154
1155 if (!(status & IRQ_STAT_4PORTS))
1156 goto out;
1157
1158 spin_lock(&host->lock);
1159
1160 for (i = 0; i < host->n_ports; i++)
1161 if (status & (1 << i)) {
1162 struct ata_port *ap = host->ports[i];
1163 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
1164 sil24_host_intr(ap);
1165 handled++;
1166 } else
1167 printk(KERN_ERR DRV_NAME
1168 ": interrupt from disabled port %d\n", i);
1169 }
1170
1171 spin_unlock(&host->lock);
1172 out:
1173 return IRQ_RETVAL(handled);
1174 }
1175
1176 static void sil24_error_handler(struct ata_port *ap)
1177 {
1178 struct sil24_port_priv *pp = ap->private_data;
1179
1180 if (sil24_init_port(ap))
1181 ata_eh_freeze_port(ap);
1182
1183 sata_pmp_error_handler(ap);
1184
1185 pp->do_port_rst = 0;
1186 }
1187
1188 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
1189 {
1190 struct ata_port *ap = qc->ap;
1191
1192 /* make DMA engine forget about the failed command */
1193 if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap))
1194 ata_eh_freeze_port(ap);
1195 }
1196
1197 static int sil24_port_start(struct ata_port *ap)
1198 {
1199 struct device *dev = ap->host->dev;
1200 struct sil24_port_priv *pp;
1201 union sil24_cmd_block *cb;
1202 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
1203 dma_addr_t cb_dma;
1204
1205 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1206 if (!pp)
1207 return -ENOMEM;
1208
1209 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
1210 if (!cb)
1211 return -ENOMEM;
1212 memset(cb, 0, cb_size);
1213
1214 pp->cmd_block = cb;
1215 pp->cmd_block_dma = cb_dma;
1216
1217 ap->private_data = pp;
1218
1219 ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host");
1220 ata_port_pbar_desc(ap, SIL24_PORT_BAR, sil24_port_offset(ap), "port");
1221
1222 return 0;
1223 }
1224
1225 static void sil24_init_controller(struct ata_host *host)
1226 {
1227 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1228 u32 tmp;
1229 int i;
1230
1231 /* GPIO off */
1232 writel(0, host_base + HOST_FLASH_CMD);
1233
1234 /* clear global reset & mask interrupts during initialization */
1235 writel(0, host_base + HOST_CTRL);
1236
1237 /* init ports */
1238 for (i = 0; i < host->n_ports; i++) {
1239 struct ata_port *ap = host->ports[i];
1240 void __iomem *port = sil24_port_base(ap);
1241
1242
1243 /* Initial PHY setting */
1244 writel(0x20c, port + PORT_PHY_CFG);
1245
1246 /* Clear port RST */
1247 tmp = readl(port + PORT_CTRL_STAT);
1248 if (tmp & PORT_CS_PORT_RST) {
1249 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1250 tmp = ata_wait_register(port + PORT_CTRL_STAT,
1251 PORT_CS_PORT_RST,
1252 PORT_CS_PORT_RST, 10, 100);
1253 if (tmp & PORT_CS_PORT_RST)
1254 dev_printk(KERN_ERR, host->dev,
1255 "failed to clear port RST\n");
1256 }
1257
1258 /* configure port */
1259 sil24_config_port(ap);
1260 }
1261
1262 /* Turn on interrupts */
1263 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1264 }
1265
1266 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1267 {
1268 extern int __MARKER__sil24_cmd_block_is_sized_wrongly;
1269 static int printed_version;
1270 struct ata_port_info pi = sil24_port_info[ent->driver_data];
1271 const struct ata_port_info *ppi[] = { &pi, NULL };
1272 void __iomem * const *iomap;
1273 struct ata_host *host;
1274 int rc;
1275 u32 tmp;
1276
1277 /* cause link error if sil24_cmd_block is sized wrongly */
1278 if (sizeof(union sil24_cmd_block) != PAGE_SIZE)
1279 __MARKER__sil24_cmd_block_is_sized_wrongly = 1;
1280
1281 if (!printed_version++)
1282 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1283
1284 /* acquire resources */
1285 rc = pcim_enable_device(pdev);
1286 if (rc)
1287 return rc;
1288
1289 rc = pcim_iomap_regions(pdev,
1290 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
1291 DRV_NAME);
1292 if (rc)
1293 return rc;
1294 iomap = pcim_iomap_table(pdev);
1295
1296 /* apply workaround for completion IRQ loss on PCI-X errata */
1297 if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1298 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
1299 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1300 dev_printk(KERN_INFO, &pdev->dev,
1301 "Applying completion IRQ loss on PCI-X "
1302 "errata fix\n");
1303 else
1304 pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1305 }
1306
1307 /* allocate and fill host */
1308 host = ata_host_alloc_pinfo(&pdev->dev, ppi,
1309 SIL24_FLAG2NPORTS(ppi[0]->flags));
1310 if (!host)
1311 return -ENOMEM;
1312 host->iomap = iomap;
1313
1314 /* configure and activate the device */
1315 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1316 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1317 if (rc) {
1318 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1319 if (rc) {
1320 dev_printk(KERN_ERR, &pdev->dev,
1321 "64-bit DMA enable failed\n");
1322 return rc;
1323 }
1324 }
1325 } else {
1326 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1327 if (rc) {
1328 dev_printk(KERN_ERR, &pdev->dev,
1329 "32-bit DMA enable failed\n");
1330 return rc;
1331 }
1332 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1333 if (rc) {
1334 dev_printk(KERN_ERR, &pdev->dev,
1335 "32-bit consistent DMA enable failed\n");
1336 return rc;
1337 }
1338 }
1339
1340 /* Set max read request size to 4096. This slightly increases
1341 * write throughput for pci-e variants.
1342 */
1343 pcie_set_readrq(pdev, 4096);
1344
1345 sil24_init_controller(host);
1346
1347 if (sata_sil24_msi && !pci_enable_msi(pdev)) {
1348 dev_printk(KERN_INFO, &pdev->dev, "Using MSI\n");
1349 pci_intx(pdev, 0);
1350 }
1351
1352 pci_set_master(pdev);
1353 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
1354 &sil24_sht);
1355 }
1356
1357 #ifdef CONFIG_PM
1358 static int sil24_pci_device_resume(struct pci_dev *pdev)
1359 {
1360 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1361 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1362 int rc;
1363
1364 rc = ata_pci_device_do_resume(pdev);
1365 if (rc)
1366 return rc;
1367
1368 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
1369 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
1370
1371 sil24_init_controller(host);
1372
1373 ata_host_resume(host);
1374
1375 return 0;
1376 }
1377
1378 static int sil24_port_resume(struct ata_port *ap)
1379 {
1380 sil24_config_pmp(ap, ap->nr_pmp_links);
1381 return 0;
1382 }
1383 #endif
1384
1385 static int __init sil24_init(void)
1386 {
1387 return pci_register_driver(&sil24_pci_driver);
1388 }
1389
1390 static void __exit sil24_exit(void)
1391 {
1392 pci_unregister_driver(&sil24_pci_driver);
1393 }
1394
1395 MODULE_AUTHOR("Tejun Heo");
1396 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1397 MODULE_LICENSE("GPL");
1398 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1399
1400 module_init(sil24_init);
1401 module_exit(sil24_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree