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drivers/usb/class/cdc-acm.c: clear dangling pointer
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / tty / serial / atmel_serial.c
blobb989495c763eb15fd548167610555227b3c01d62
1 /*
2 * Driver for Atmel AT91 / AT32 Serial ports
3 * Copyright (C) 2003 Rick Bronson
4 *
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * DMA support added by Chip Coldwell.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25 #include <linux/module.h>
26 #include <linux/tty.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/init.h>
30 #include <linux/serial.h>
31 #include <linux/clk.h>
32 #include <linux/console.h>
33 #include <linux/sysrq.h>
34 #include <linux/tty_flip.h>
35 #include <linux/platform_device.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/atmel_pdc.h>
38 #include <linux/atmel_serial.h>
39 #include <linux/uaccess.h>
40
41 #include <asm/io.h>
42 #include <asm/ioctls.h>
43
44 #include <asm/mach/serial_at91.h>
45 #include <mach/board.h>
46
47 #ifdef CONFIG_ARM
48 #include <mach/cpu.h>
49 #include <mach/gpio.h>
50 #endif
51
52 #define PDC_BUFFER_SIZE 512
53 /* Revisit: We should calculate this based on the actual port settings */
54 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
55
56 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
57 #define SUPPORT_SYSRQ
58 #endif
59
60 #include <linux/serial_core.h>
61
62 static void atmel_start_rx(struct uart_port *port);
63 static void atmel_stop_rx(struct uart_port *port);
64
65 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
66
67 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
68 * should coexist with the 8250 driver, such as if we have an external 16C550
69 * UART. */
70 #define SERIAL_ATMEL_MAJOR 204
71 #define MINOR_START 154
72 #define ATMEL_DEVICENAME "ttyAT"
73
74 #else
75
76 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
77 * name, but it is legally reserved for the 8250 driver. */
78 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
79 #define MINOR_START 64
80 #define ATMEL_DEVICENAME "ttyS"
81
82 #endif
83
84 #define ATMEL_ISR_PASS_LIMIT 256
85
86 /* UART registers. CR is write-only, hence no GET macro */
87 #define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR)
88 #define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR)
89 #define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR)
90 #define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER)
91 #define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR)
92 #define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR)
93 #define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR)
94 #define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR)
95 #define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR)
96 #define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR)
97 #define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR)
98 #define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR)
99 #define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_TTGR)
100
101 /* PDC registers */
102 #define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR)
103 #define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR)
104
105 #define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR)
106 #define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR)
107 #define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR)
108 #define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR)
109 #define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR)
110
111 #define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR)
112 #define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR)
113 #define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR)
114
115 static int (*atmel_open_hook)(struct uart_port *);
116 static void (*atmel_close_hook)(struct uart_port *);
117
118 struct atmel_dma_buffer {
119 unsigned char *buf;
120 dma_addr_t dma_addr;
121 unsigned int dma_size;
122 unsigned int ofs;
123 };
124
125 struct atmel_uart_char {
126 u16 status;
127 u16 ch;
128 };
129
130 #define ATMEL_SERIAL_RINGSIZE 1024
131
132 /*
133 * We wrap our port structure around the generic uart_port.
134 */
135 struct atmel_uart_port {
136 struct uart_port uart; /* uart */
137 struct clk *clk; /* uart clock */
138 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
139 u32 backup_imr; /* IMR saved during suspend */
140 int break_active; /* break being received */
141
142 short use_dma_rx; /* enable PDC receiver */
143 short pdc_rx_idx; /* current PDC RX buffer */
144 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
145
146 short use_dma_tx; /* enable PDC transmitter */
147 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
148
149 struct tasklet_struct tasklet;
150 unsigned int irq_status;
151 unsigned int irq_status_prev;
152
153 struct circ_buf rx_ring;
154
155 struct serial_rs485 rs485; /* rs485 settings */
156 unsigned int tx_done_mask;
157 };
158
159 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
160
161 #ifdef SUPPORT_SYSRQ
162 static struct console atmel_console;
163 #endif
164
165 static inline struct atmel_uart_port *
166 to_atmel_uart_port(struct uart_port *uart)
167 {
168 return container_of(uart, struct atmel_uart_port, uart);
169 }
170
171 #ifdef CONFIG_SERIAL_ATMEL_PDC
172 static bool atmel_use_dma_rx(struct uart_port *port)
173 {
174 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
175
176 return atmel_port->use_dma_rx;
177 }
178
179 static bool atmel_use_dma_tx(struct uart_port *port)
180 {
181 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
182
183 return atmel_port->use_dma_tx;
184 }
185 #else
186 static bool atmel_use_dma_rx(struct uart_port *port)
187 {
188 return false;
189 }
190
191 static bool atmel_use_dma_tx(struct uart_port *port)
192 {
193 return false;
194 }
195 #endif
196
197 /* Enable or disable the rs485 support */
198 void atmel_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
199 {
200 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
201 unsigned int mode;
202 unsigned long flags;
203
204 spin_lock_irqsave(&port->lock, flags);
205
206 /* Disable interrupts */
207 UART_PUT_IDR(port, atmel_port->tx_done_mask);
208
209 mode = UART_GET_MR(port);
210
211 /* Resetting serial mode to RS232 (0x0) */
212 mode &= ~ATMEL_US_USMODE;
213
214 atmel_port->rs485 = *rs485conf;
215
216 if (rs485conf->flags & SER_RS485_ENABLED) {
217 dev_dbg(port->dev, "Setting UART to RS485\n");
218 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
219 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
220 UART_PUT_TTGR(port, rs485conf->delay_rts_after_send);
221 mode |= ATMEL_US_USMODE_RS485;
222 } else {
223 dev_dbg(port->dev, "Setting UART to RS232\n");
224 if (atmel_use_dma_tx(port))
225 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
226 ATMEL_US_TXBUFE;
227 else
228 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
229 }
230 UART_PUT_MR(port, mode);
231
232 /* Enable interrupts */
233 UART_PUT_IER(port, atmel_port->tx_done_mask);
234
235 spin_unlock_irqrestore(&port->lock, flags);
236
237 }
238
239 /*
240 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
241 */
242 static u_int atmel_tx_empty(struct uart_port *port)
243 {
244 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0;
245 }
246
247 /*
248 * Set state of the modem control output lines
249 */
250 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
251 {
252 unsigned int control = 0;
253 unsigned int mode;
254 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
255
256 #ifdef CONFIG_ARCH_AT91RM9200
257 if (cpu_is_at91rm9200()) {
258 /*
259 * AT91RM9200 Errata #39: RTS0 is not internally connected
260 * to PA21. We need to drive the pin manually.
261 */
262 if (port->mapbase == AT91RM9200_BASE_US0) {
263 if (mctrl & TIOCM_RTS)
264 at91_set_gpio_value(AT91_PIN_PA21, 0);
265 else
266 at91_set_gpio_value(AT91_PIN_PA21, 1);
267 }
268 }
269 #endif
270
271 if (mctrl & TIOCM_RTS)
272 control |= ATMEL_US_RTSEN;
273 else
274 control |= ATMEL_US_RTSDIS;
275
276 if (mctrl & TIOCM_DTR)
277 control |= ATMEL_US_DTREN;
278 else
279 control |= ATMEL_US_DTRDIS;
280
281 UART_PUT_CR(port, control);
282
283 /* Local loopback mode? */
284 mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE;
285 if (mctrl & TIOCM_LOOP)
286 mode |= ATMEL_US_CHMODE_LOC_LOOP;
287 else
288 mode |= ATMEL_US_CHMODE_NORMAL;
289
290 /* Resetting serial mode to RS232 (0x0) */
291 mode &= ~ATMEL_US_USMODE;
292
293 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
294 dev_dbg(port->dev, "Setting UART to RS485\n");
295 if (atmel_port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
296 UART_PUT_TTGR(port,
297 atmel_port->rs485.delay_rts_after_send);
298 mode |= ATMEL_US_USMODE_RS485;
299 } else {
300 dev_dbg(port->dev, "Setting UART to RS232\n");
301 }
302 UART_PUT_MR(port, mode);
303 }
304
305 /*
306 * Get state of the modem control input lines
307 */
308 static u_int atmel_get_mctrl(struct uart_port *port)
309 {
310 unsigned int status, ret = 0;
311
312 status = UART_GET_CSR(port);
313
314 /*
315 * The control signals are active low.
316 */
317 if (!(status & ATMEL_US_DCD))
318 ret |= TIOCM_CD;
319 if (!(status & ATMEL_US_CTS))
320 ret |= TIOCM_CTS;
321 if (!(status & ATMEL_US_DSR))
322 ret |= TIOCM_DSR;
323 if (!(status & ATMEL_US_RI))
324 ret |= TIOCM_RI;
325
326 return ret;
327 }
328
329 /*
330 * Stop transmitting.
331 */
332 static void atmel_stop_tx(struct uart_port *port)
333 {
334 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
335
336 if (atmel_use_dma_tx(port)) {
337 /* disable PDC transmit */
338 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
339 }
340 /* Disable interrupts */
341 UART_PUT_IDR(port, atmel_port->tx_done_mask);
342
343 if (atmel_port->rs485.flags & SER_RS485_ENABLED)
344 atmel_start_rx(port);
345 }
346
347 /*
348 * Start transmitting.
349 */
350 static void atmel_start_tx(struct uart_port *port)
351 {
352 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
353
354 if (atmel_use_dma_tx(port)) {
355 if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN)
356 /* The transmitter is already running. Yes, we
357 really need this.*/
358 return;
359
360 if (atmel_port->rs485.flags & SER_RS485_ENABLED)
361 atmel_stop_rx(port);
362
363 /* re-enable PDC transmit */
364 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
365 }
366 /* Enable interrupts */
367 UART_PUT_IER(port, atmel_port->tx_done_mask);
368 }
369
370 /*
371 * start receiving - port is in process of being opened.
372 */
373 static void atmel_start_rx(struct uart_port *port)
374 {
375 UART_PUT_CR(port, ATMEL_US_RSTSTA); /* reset status and receiver */
376
377 if (atmel_use_dma_rx(port)) {
378 /* enable PDC controller */
379 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
380 port->read_status_mask);
381 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
382 } else {
383 UART_PUT_IER(port, ATMEL_US_RXRDY);
384 }
385 }
386
387 /*
388 * Stop receiving - port is in process of being closed.
389 */
390 static void atmel_stop_rx(struct uart_port *port)
391 {
392 if (atmel_use_dma_rx(port)) {
393 /* disable PDC receive */
394 UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS);
395 UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
396 port->read_status_mask);
397 } else {
398 UART_PUT_IDR(port, ATMEL_US_RXRDY);
399 }
400 }
401
402 /*
403 * Enable modem status interrupts
404 */
405 static void atmel_enable_ms(struct uart_port *port)
406 {
407 UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC
408 | ATMEL_US_DCDIC | ATMEL_US_CTSIC);
409 }
410
411 /*
412 * Control the transmission of a break signal
413 */
414 static void atmel_break_ctl(struct uart_port *port, int break_state)
415 {
416 if (break_state != 0)
417 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */
418 else
419 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */
420 }
421
422 /*
423 * Stores the incoming character in the ring buffer
424 */
425 static void
426 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
427 unsigned int ch)
428 {
429 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
430 struct circ_buf *ring = &atmel_port->rx_ring;
431 struct atmel_uart_char *c;
432
433 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
434 /* Buffer overflow, ignore char */
435 return;
436
437 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
438 c->status = status;
439 c->ch = ch;
440
441 /* Make sure the character is stored before we update head. */
442 smp_wmb();
443
444 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
445 }
446
447 /*
448 * Deal with parity, framing and overrun errors.
449 */
450 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
451 {
452 /* clear error */
453 UART_PUT_CR(port, ATMEL_US_RSTSTA);
454
455 if (status & ATMEL_US_RXBRK) {
456 /* ignore side-effect */
457 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
458 port->icount.brk++;
459 }
460 if (status & ATMEL_US_PARE)
461 port->icount.parity++;
462 if (status & ATMEL_US_FRAME)
463 port->icount.frame++;
464 if (status & ATMEL_US_OVRE)
465 port->icount.overrun++;
466 }
467
468 /*
469 * Characters received (called from interrupt handler)
470 */
471 static void atmel_rx_chars(struct uart_port *port)
472 {
473 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
474 unsigned int status, ch;
475
476 status = UART_GET_CSR(port);
477 while (status & ATMEL_US_RXRDY) {
478 ch = UART_GET_CHAR(port);
479
480 /*
481 * note that the error handling code is
482 * out of the main execution path
483 */
484 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
485 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
486 || atmel_port->break_active)) {
487
488 /* clear error */
489 UART_PUT_CR(port, ATMEL_US_RSTSTA);
490
491 if (status & ATMEL_US_RXBRK
492 && !atmel_port->break_active) {
493 atmel_port->break_active = 1;
494 UART_PUT_IER(port, ATMEL_US_RXBRK);
495 } else {
496 /*
497 * This is either the end-of-break
498 * condition or we've received at
499 * least one character without RXBRK
500 * being set. In both cases, the next
501 * RXBRK will indicate start-of-break.
502 */
503 UART_PUT_IDR(port, ATMEL_US_RXBRK);
504 status &= ~ATMEL_US_RXBRK;
505 atmel_port->break_active = 0;
506 }
507 }
508
509 atmel_buffer_rx_char(port, status, ch);
510 status = UART_GET_CSR(port);
511 }
512
513 tasklet_schedule(&atmel_port->tasklet);
514 }
515
516 /*
517 * Transmit characters (called from tasklet with TXRDY interrupt
518 * disabled)
519 */
520 static void atmel_tx_chars(struct uart_port *port)
521 {
522 struct circ_buf *xmit = &port->state->xmit;
523 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
524
525 if (port->x_char && UART_GET_CSR(port) & atmel_port->tx_done_mask) {
526 UART_PUT_CHAR(port, port->x_char);
527 port->icount.tx++;
528 port->x_char = 0;
529 }
530 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
531 return;
532
533 while (UART_GET_CSR(port) & atmel_port->tx_done_mask) {
534 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
535 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
536 port->icount.tx++;
537 if (uart_circ_empty(xmit))
538 break;
539 }
540
541 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
542 uart_write_wakeup(port);
543
544 if (!uart_circ_empty(xmit))
545 /* Enable interrupts */
546 UART_PUT_IER(port, atmel_port->tx_done_mask);
547 }
548
549 /*
550 * receive interrupt handler.
551 */
552 static void
553 atmel_handle_receive(struct uart_port *port, unsigned int pending)
554 {
555 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
556
557 if (atmel_use_dma_rx(port)) {
558 /*
559 * PDC receive. Just schedule the tasklet and let it
560 * figure out the details.
561 *
562 * TODO: We're not handling error flags correctly at
563 * the moment.
564 */
565 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
566 UART_PUT_IDR(port, (ATMEL_US_ENDRX
567 | ATMEL_US_TIMEOUT));
568 tasklet_schedule(&atmel_port->tasklet);
569 }
570
571 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
572 ATMEL_US_FRAME | ATMEL_US_PARE))
573 atmel_pdc_rxerr(port, pending);
574 }
575
576 /* Interrupt receive */
577 if (pending & ATMEL_US_RXRDY)
578 atmel_rx_chars(port);
579 else if (pending & ATMEL_US_RXBRK) {
580 /*
581 * End of break detected. If it came along with a
582 * character, atmel_rx_chars will handle it.
583 */
584 UART_PUT_CR(port, ATMEL_US_RSTSTA);
585 UART_PUT_IDR(port, ATMEL_US_RXBRK);
586 atmel_port->break_active = 0;
587 }
588 }
589
590 /*
591 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
592 */
593 static void
594 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
595 {
596 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
597
598 if (pending & atmel_port->tx_done_mask) {
599 /* Either PDC or interrupt transmission */
600 UART_PUT_IDR(port, atmel_port->tx_done_mask);
601 tasklet_schedule(&atmel_port->tasklet);
602 }
603 }
604
605 /*
606 * status flags interrupt handler.
607 */
608 static void
609 atmel_handle_status(struct uart_port *port, unsigned int pending,
610 unsigned int status)
611 {
612 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
613
614 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
615 | ATMEL_US_CTSIC)) {
616 atmel_port->irq_status = status;
617 tasklet_schedule(&atmel_port->tasklet);
618 }
619 }
620
621 /*
622 * Interrupt handler
623 */
624 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
625 {
626 struct uart_port *port = dev_id;
627 unsigned int status, pending, pass_counter = 0;
628
629 do {
630 status = UART_GET_CSR(port);
631 pending = status & UART_GET_IMR(port);
632 if (!pending)
633 break;
634
635 atmel_handle_receive(port, pending);
636 atmel_handle_status(port, pending, status);
637 atmel_handle_transmit(port, pending);
638 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
639
640 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
641 }
642
643 /*
644 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
645 */
646 static void atmel_tx_dma(struct uart_port *port)
647 {
648 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
649 struct circ_buf *xmit = &port->state->xmit;
650 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
651 int count;
652
653 /* nothing left to transmit? */
654 if (UART_GET_TCR(port))
655 return;
656
657 xmit->tail += pdc->ofs;
658 xmit->tail &= UART_XMIT_SIZE - 1;
659
660 port->icount.tx += pdc->ofs;
661 pdc->ofs = 0;
662
663 /* more to transmit - setup next transfer */
664
665 /* disable PDC transmit */
666 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
667
668 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
669 dma_sync_single_for_device(port->dev,
670 pdc->dma_addr,
671 pdc->dma_size,
672 DMA_TO_DEVICE);
673
674 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
675 pdc->ofs = count;
676
677 UART_PUT_TPR(port, pdc->dma_addr + xmit->tail);
678 UART_PUT_TCR(port, count);
679 /* re-enable PDC transmit */
680 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
681 /* Enable interrupts */
682 UART_PUT_IER(port, atmel_port->tx_done_mask);
683 } else {
684 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
685 /* DMA done, stop TX, start RX for RS485 */
686 atmel_start_rx(port);
687 }
688 }
689
690 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
691 uart_write_wakeup(port);
692 }
693
694 static void atmel_rx_from_ring(struct uart_port *port)
695 {
696 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
697 struct circ_buf *ring = &atmel_port->rx_ring;
698 unsigned int flg;
699 unsigned int status;
700
701 while (ring->head != ring->tail) {
702 struct atmel_uart_char c;
703
704 /* Make sure c is loaded after head. */
705 smp_rmb();
706
707 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
708
709 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
710
711 port->icount.rx++;
712 status = c.status;
713 flg = TTY_NORMAL;
714
715 /*
716 * note that the error handling code is
717 * out of the main execution path
718 */
719 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
720 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
721 if (status & ATMEL_US_RXBRK) {
722 /* ignore side-effect */
723 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
724
725 port->icount.brk++;
726 if (uart_handle_break(port))
727 continue;
728 }
729 if (status & ATMEL_US_PARE)
730 port->icount.parity++;
731 if (status & ATMEL_US_FRAME)
732 port->icount.frame++;
733 if (status & ATMEL_US_OVRE)
734 port->icount.overrun++;
735
736 status &= port->read_status_mask;
737
738 if (status & ATMEL_US_RXBRK)
739 flg = TTY_BREAK;
740 else if (status & ATMEL_US_PARE)
741 flg = TTY_PARITY;
742 else if (status & ATMEL_US_FRAME)
743 flg = TTY_FRAME;
744 }
745
746
747 if (uart_handle_sysrq_char(port, c.ch))
748 continue;
749
750 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
751 }
752
753 /*
754 * Drop the lock here since it might end up calling
755 * uart_start(), which takes the lock.
756 */
757 spin_unlock(&port->lock);
758 tty_flip_buffer_push(port->state->port.tty);
759 spin_lock(&port->lock);
760 }
761
762 static void atmel_rx_from_dma(struct uart_port *port)
763 {
764 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
765 struct tty_struct *tty = port->state->port.tty;
766 struct atmel_dma_buffer *pdc;
767 int rx_idx = atmel_port->pdc_rx_idx;
768 unsigned int head;
769 unsigned int tail;
770 unsigned int count;
771
772 do {
773 /* Reset the UART timeout early so that we don't miss one */
774 UART_PUT_CR(port, ATMEL_US_STTTO);
775
776 pdc = &atmel_port->pdc_rx[rx_idx];
777 head = UART_GET_RPR(port) - pdc->dma_addr;
778 tail = pdc->ofs;
779
780 /* If the PDC has switched buffers, RPR won't contain
781 * any address within the current buffer. Since head
782 * is unsigned, we just need a one-way comparison to
783 * find out.
784 *
785 * In this case, we just need to consume the entire
786 * buffer and resubmit it for DMA. This will clear the
787 * ENDRX bit as well, so that we can safely re-enable
788 * all interrupts below.
789 */
790 head = min(head, pdc->dma_size);
791
792 if (likely(head != tail)) {
793 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
794 pdc->dma_size, DMA_FROM_DEVICE);
795
796 /*
797 * head will only wrap around when we recycle
798 * the DMA buffer, and when that happens, we
799 * explicitly set tail to 0. So head will
800 * always be greater than tail.
801 */
802 count = head - tail;
803
804 tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count);
805
806 dma_sync_single_for_device(port->dev, pdc->dma_addr,
807 pdc->dma_size, DMA_FROM_DEVICE);
808
809 port->icount.rx += count;
810 pdc->ofs = head;
811 }
812
813 /*
814 * If the current buffer is full, we need to check if
815 * the next one contains any additional data.
816 */
817 if (head >= pdc->dma_size) {
818 pdc->ofs = 0;
819 UART_PUT_RNPR(port, pdc->dma_addr);
820 UART_PUT_RNCR(port, pdc->dma_size);
821
822 rx_idx = !rx_idx;
823 atmel_port->pdc_rx_idx = rx_idx;
824 }
825 } while (head >= pdc->dma_size);
826
827 /*
828 * Drop the lock here since it might end up calling
829 * uart_start(), which takes the lock.
830 */
831 spin_unlock(&port->lock);
832 tty_flip_buffer_push(tty);
833 spin_lock(&port->lock);
834
835 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
836 }
837
838 /*
839 * tasklet handling tty stuff outside the interrupt handler.
840 */
841 static void atmel_tasklet_func(unsigned long data)
842 {
843 struct uart_port *port = (struct uart_port *)data;
844 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
845 unsigned int status;
846 unsigned int status_change;
847
848 /* The interrupt handler does not take the lock */
849 spin_lock(&port->lock);
850
851 if (atmel_use_dma_tx(port))
852 atmel_tx_dma(port);
853 else
854 atmel_tx_chars(port);
855
856 status = atmel_port->irq_status;
857 status_change = status ^ atmel_port->irq_status_prev;
858
859 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
860 | ATMEL_US_DCD | ATMEL_US_CTS)) {
861 /* TODO: All reads to CSR will clear these interrupts! */
862 if (status_change & ATMEL_US_RI)
863 port->icount.rng++;
864 if (status_change & ATMEL_US_DSR)
865 port->icount.dsr++;
866 if (status_change & ATMEL_US_DCD)
867 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
868 if (status_change & ATMEL_US_CTS)
869 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
870
871 wake_up_interruptible(&port->state->port.delta_msr_wait);
872
873 atmel_port->irq_status_prev = status;
874 }
875
876 if (atmel_use_dma_rx(port))
877 atmel_rx_from_dma(port);
878 else
879 atmel_rx_from_ring(port);
880
881 spin_unlock(&port->lock);
882 }
883
884 /*
885 * Perform initialization and enable port for reception
886 */
887 static int atmel_startup(struct uart_port *port)
888 {
889 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
890 struct tty_struct *tty = port->state->port.tty;
891 int retval;
892
893 /*
894 * Ensure that no interrupts are enabled otherwise when
895 * request_irq() is called we could get stuck trying to
896 * handle an unexpected interrupt
897 */
898 UART_PUT_IDR(port, -1);
899
900 /*
901 * Allocate the IRQ
902 */
903 retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED,
904 tty ? tty->name : "atmel_serial", port);
905 if (retval) {
906 printk("atmel_serial: atmel_startup - Can't get irq\n");
907 return retval;
908 }
909
910 /*
911 * Initialize DMA (if necessary)
912 */
913 if (atmel_use_dma_rx(port)) {
914 int i;
915
916 for (i = 0; i < 2; i++) {
917 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
918
919 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
920 if (pdc->buf == NULL) {
921 if (i != 0) {
922 dma_unmap_single(port->dev,
923 atmel_port->pdc_rx[0].dma_addr,
924 PDC_BUFFER_SIZE,
925 DMA_FROM_DEVICE);
926 kfree(atmel_port->pdc_rx[0].buf);
927 }
928 free_irq(port->irq, port);
929 return -ENOMEM;
930 }
931 pdc->dma_addr = dma_map_single(port->dev,
932 pdc->buf,
933 PDC_BUFFER_SIZE,
934 DMA_FROM_DEVICE);
935 pdc->dma_size = PDC_BUFFER_SIZE;
936 pdc->ofs = 0;
937 }
938
939 atmel_port->pdc_rx_idx = 0;
940
941 UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr);
942 UART_PUT_RCR(port, PDC_BUFFER_SIZE);
943
944 UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr);
945 UART_PUT_RNCR(port, PDC_BUFFER_SIZE);
946 }
947 if (atmel_use_dma_tx(port)) {
948 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
949 struct circ_buf *xmit = &port->state->xmit;
950
951 pdc->buf = xmit->buf;
952 pdc->dma_addr = dma_map_single(port->dev,
953 pdc->buf,
954 UART_XMIT_SIZE,
955 DMA_TO_DEVICE);
956 pdc->dma_size = UART_XMIT_SIZE;
957 pdc->ofs = 0;
958 }
959
960 /*
961 * If there is a specific "open" function (to register
962 * control line interrupts)
963 */
964 if (atmel_open_hook) {
965 retval = atmel_open_hook(port);
966 if (retval) {
967 free_irq(port->irq, port);
968 return retval;
969 }
970 }
971
972 /* Save current CSR for comparison in atmel_tasklet_func() */
973 atmel_port->irq_status_prev = UART_GET_CSR(port);
974 atmel_port->irq_status = atmel_port->irq_status_prev;
975
976 /*
977 * Finally, enable the serial port
978 */
979 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
980 /* enable xmit & rcvr */
981 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
982
983 if (atmel_use_dma_rx(port)) {
984 /* set UART timeout */
985 UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
986 UART_PUT_CR(port, ATMEL_US_STTTO);
987
988 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
989 /* enable PDC controller */
990 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
991 } else {
992 /* enable receive only */
993 UART_PUT_IER(port, ATMEL_US_RXRDY);
994 }
995
996 return 0;
997 }
998
999 /*
1000 * Disable the port
1001 */
1002 static void atmel_shutdown(struct uart_port *port)
1003 {
1004 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1005 /*
1006 * Ensure everything is stopped.
1007 */
1008 atmel_stop_rx(port);
1009 atmel_stop_tx(port);
1010
1011 /*
1012 * Shut-down the DMA.
1013 */
1014 if (atmel_use_dma_rx(port)) {
1015 int i;
1016
1017 for (i = 0; i < 2; i++) {
1018 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1019
1020 dma_unmap_single(port->dev,
1021 pdc->dma_addr,
1022 pdc->dma_size,
1023 DMA_FROM_DEVICE);
1024 kfree(pdc->buf);
1025 }
1026 }
1027 if (atmel_use_dma_tx(port)) {
1028 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1029
1030 dma_unmap_single(port->dev,
1031 pdc->dma_addr,
1032 pdc->dma_size,
1033 DMA_TO_DEVICE);
1034 }
1035
1036 /*
1037 * Disable all interrupts, port and break condition.
1038 */
1039 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1040 UART_PUT_IDR(port, -1);
1041
1042 /*
1043 * Free the interrupt
1044 */
1045 free_irq(port->irq, port);
1046
1047 /*
1048 * If there is a specific "close" function (to unregister
1049 * control line interrupts)
1050 */
1051 if (atmel_close_hook)
1052 atmel_close_hook(port);
1053 }
1054
1055 /*
1056 * Flush any TX data submitted for DMA. Called when the TX circular
1057 * buffer is reset.
1058 */
1059 static void atmel_flush_buffer(struct uart_port *port)
1060 {
1061 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1062
1063 if (atmel_use_dma_tx(port)) {
1064 UART_PUT_TCR(port, 0);
1065 atmel_port->pdc_tx.ofs = 0;
1066 }
1067 }
1068
1069 /*
1070 * Power / Clock management.
1071 */
1072 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
1073 unsigned int oldstate)
1074 {
1075 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1076
1077 switch (state) {
1078 case 0:
1079 /*
1080 * Enable the peripheral clock for this serial port.
1081 * This is called on uart_open() or a resume event.
1082 */
1083 clk_enable(atmel_port->clk);
1084
1085 /* re-enable interrupts if we disabled some on suspend */
1086 UART_PUT_IER(port, atmel_port->backup_imr);
1087 break;
1088 case 3:
1089 /* Back up the interrupt mask and disable all interrupts */
1090 atmel_port->backup_imr = UART_GET_IMR(port);
1091 UART_PUT_IDR(port, -1);
1092
1093 /*
1094 * Disable the peripheral clock for this serial port.
1095 * This is called on uart_close() or a suspend event.
1096 */
1097 clk_disable(atmel_port->clk);
1098 break;
1099 default:
1100 printk(KERN_ERR "atmel_serial: unknown pm %d\n", state);
1101 }
1102 }
1103
1104 /*
1105 * Change the port parameters
1106 */
1107 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
1108 struct ktermios *old)
1109 {
1110 unsigned long flags;
1111 unsigned int mode, imr, quot, baud;
1112 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1113
1114 /* Get current mode register */
1115 mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL
1116 | ATMEL_US_NBSTOP | ATMEL_US_PAR
1117 | ATMEL_US_USMODE);
1118
1119 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1120 quot = uart_get_divisor(port, baud);
1121
1122 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
1123 quot /= 8;
1124 mode |= ATMEL_US_USCLKS_MCK_DIV8;
1125 }
1126
1127 /* byte size */
1128 switch (termios->c_cflag & CSIZE) {
1129 case CS5:
1130 mode |= ATMEL_US_CHRL_5;
1131 break;
1132 case CS6:
1133 mode |= ATMEL_US_CHRL_6;
1134 break;
1135 case CS7:
1136 mode |= ATMEL_US_CHRL_7;
1137 break;
1138 default:
1139 mode |= ATMEL_US_CHRL_8;
1140 break;
1141 }
1142
1143 /* stop bits */
1144 if (termios->c_cflag & CSTOPB)
1145 mode |= ATMEL_US_NBSTOP_2;
1146
1147 /* parity */
1148 if (termios->c_cflag & PARENB) {
1149 /* Mark or Space parity */
1150 if (termios->c_cflag & CMSPAR) {
1151 if (termios->c_cflag & PARODD)
1152 mode |= ATMEL_US_PAR_MARK;
1153 else
1154 mode |= ATMEL_US_PAR_SPACE;
1155 } else if (termios->c_cflag & PARODD)
1156 mode |= ATMEL_US_PAR_ODD;
1157 else
1158 mode |= ATMEL_US_PAR_EVEN;
1159 } else
1160 mode |= ATMEL_US_PAR_NONE;
1161
1162 /* hardware handshake (RTS/CTS) */
1163 if (termios->c_cflag & CRTSCTS)
1164 mode |= ATMEL_US_USMODE_HWHS;
1165 else
1166 mode |= ATMEL_US_USMODE_NORMAL;
1167
1168 spin_lock_irqsave(&port->lock, flags);
1169
1170 port->read_status_mask = ATMEL_US_OVRE;
1171 if (termios->c_iflag & INPCK)
1172 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1173 if (termios->c_iflag & (BRKINT | PARMRK))
1174 port->read_status_mask |= ATMEL_US_RXBRK;
1175
1176 if (atmel_use_dma_rx(port))
1177 /* need to enable error interrupts */
1178 UART_PUT_IER(port, port->read_status_mask);
1179
1180 /*
1181 * Characters to ignore
1182 */
1183 port->ignore_status_mask = 0;
1184 if (termios->c_iflag & IGNPAR)
1185 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1186 if (termios->c_iflag & IGNBRK) {
1187 port->ignore_status_mask |= ATMEL_US_RXBRK;
1188 /*
1189 * If we're ignoring parity and break indicators,
1190 * ignore overruns too (for real raw support).
1191 */
1192 if (termios->c_iflag & IGNPAR)
1193 port->ignore_status_mask |= ATMEL_US_OVRE;
1194 }
1195 /* TODO: Ignore all characters if CREAD is set.*/
1196
1197 /* update the per-port timeout */
1198 uart_update_timeout(port, termios->c_cflag, baud);
1199
1200 /*
1201 * save/disable interrupts. The tty layer will ensure that the
1202 * transmitter is empty if requested by the caller, so there's
1203 * no need to wait for it here.
1204 */
1205 imr = UART_GET_IMR(port);
1206 UART_PUT_IDR(port, -1);
1207
1208 /* disable receiver and transmitter */
1209 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
1210
1211 /* Resetting serial mode to RS232 (0x0) */
1212 mode &= ~ATMEL_US_USMODE;
1213
1214 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
1215 dev_dbg(port->dev, "Setting UART to RS485\n");
1216 if (atmel_port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1217 UART_PUT_TTGR(port,
1218 atmel_port->rs485.delay_rts_after_send);
1219 mode |= ATMEL_US_USMODE_RS485;
1220 } else {
1221 dev_dbg(port->dev, "Setting UART to RS232\n");
1222 }
1223
1224 /* set the parity, stop bits and data size */
1225 UART_PUT_MR(port, mode);
1226
1227 /* set the baud rate */
1228 UART_PUT_BRGR(port, quot);
1229 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1230 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1231
1232 /* restore interrupts */
1233 UART_PUT_IER(port, imr);
1234
1235 /* CTS flow-control and modem-status interrupts */
1236 if (UART_ENABLE_MS(port, termios->c_cflag))
1237 port->ops->enable_ms(port);
1238
1239 spin_unlock_irqrestore(&port->lock, flags);
1240 }
1241
1242 static void atmel_set_ldisc(struct uart_port *port, int new)
1243 {
1244 int line = port->line;
1245
1246 if (line >= port->state->port.tty->driver->num)
1247 return;
1248
1249 if (port->state->port.tty->ldisc->ops->num == N_PPS) {
1250 port->flags |= UPF_HARDPPS_CD;
1251 atmel_enable_ms(port);
1252 } else {
1253 port->flags &= ~UPF_HARDPPS_CD;
1254 }
1255 }
1256
1257 /*
1258 * Return string describing the specified port
1259 */
1260 static const char *atmel_type(struct uart_port *port)
1261 {
1262 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1263 }
1264
1265 /*
1266 * Release the memory region(s) being used by 'port'.
1267 */
1268 static void atmel_release_port(struct uart_port *port)
1269 {
1270 struct platform_device *pdev = to_platform_device(port->dev);
1271 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
1272
1273 release_mem_region(port->mapbase, size);
1274
1275 if (port->flags & UPF_IOREMAP) {
1276 iounmap(port->membase);
1277 port->membase = NULL;
1278 }
1279 }
1280
1281 /*
1282 * Request the memory region(s) being used by 'port'.
1283 */
1284 static int atmel_request_port(struct uart_port *port)
1285 {
1286 struct platform_device *pdev = to_platform_device(port->dev);
1287 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
1288
1289 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
1290 return -EBUSY;
1291
1292 if (port->flags & UPF_IOREMAP) {
1293 port->membase = ioremap(port->mapbase, size);
1294 if (port->membase == NULL) {
1295 release_mem_region(port->mapbase, size);
1296 return -ENOMEM;
1297 }
1298 }
1299
1300 return 0;
1301 }
1302
1303 /*
1304 * Configure/autoconfigure the port.
1305 */
1306 static void atmel_config_port(struct uart_port *port, int flags)
1307 {
1308 if (flags & UART_CONFIG_TYPE) {
1309 port->type = PORT_ATMEL;
1310 atmel_request_port(port);
1311 }
1312 }
1313
1314 /*
1315 * Verify the new serial_struct (for TIOCSSERIAL).
1316 */
1317 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1318 {
1319 int ret = 0;
1320 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1321 ret = -EINVAL;
1322 if (port->irq != ser->irq)
1323 ret = -EINVAL;
1324 if (ser->io_type != SERIAL_IO_MEM)
1325 ret = -EINVAL;
1326 if (port->uartclk / 16 != ser->baud_base)
1327 ret = -EINVAL;
1328 if ((void *)port->mapbase != ser->iomem_base)
1329 ret = -EINVAL;
1330 if (port->iobase != ser->port)
1331 ret = -EINVAL;
1332 if (ser->hub6 != 0)
1333 ret = -EINVAL;
1334 return ret;
1335 }
1336
1337 #ifdef CONFIG_CONSOLE_POLL
1338 static int atmel_poll_get_char(struct uart_port *port)
1339 {
1340 while (!(UART_GET_CSR(port) & ATMEL_US_RXRDY))
1341 cpu_relax();
1342
1343 return UART_GET_CHAR(port);
1344 }
1345
1346 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
1347 {
1348 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
1349 cpu_relax();
1350
1351 UART_PUT_CHAR(port, ch);
1352 }
1353 #endif
1354
1355 static int
1356 atmel_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
1357 {
1358 struct serial_rs485 rs485conf;
1359
1360 switch (cmd) {
1361 case TIOCSRS485:
1362 if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg,
1363 sizeof(rs485conf)))
1364 return -EFAULT;
1365
1366 atmel_config_rs485(port, &rs485conf);
1367 break;
1368
1369 case TIOCGRS485:
1370 if (copy_to_user((struct serial_rs485 *) arg,
1371 &(to_atmel_uart_port(port)->rs485),
1372 sizeof(rs485conf)))
1373 return -EFAULT;
1374 break;
1375
1376 default:
1377 return -ENOIOCTLCMD;
1378 }
1379 return 0;
1380 }
1381
1382
1383
1384 static struct uart_ops atmel_pops = {
1385 .tx_empty = atmel_tx_empty,
1386 .set_mctrl = atmel_set_mctrl,
1387 .get_mctrl = atmel_get_mctrl,
1388 .stop_tx = atmel_stop_tx,
1389 .start_tx = atmel_start_tx,
1390 .stop_rx = atmel_stop_rx,
1391 .enable_ms = atmel_enable_ms,
1392 .break_ctl = atmel_break_ctl,
1393 .startup = atmel_startup,
1394 .shutdown = atmel_shutdown,
1395 .flush_buffer = atmel_flush_buffer,
1396 .set_termios = atmel_set_termios,
1397 .set_ldisc = atmel_set_ldisc,
1398 .type = atmel_type,
1399 .release_port = atmel_release_port,
1400 .request_port = atmel_request_port,
1401 .config_port = atmel_config_port,
1402 .verify_port = atmel_verify_port,
1403 .pm = atmel_serial_pm,
1404 .ioctl = atmel_ioctl,
1405 #ifdef CONFIG_CONSOLE_POLL
1406 .poll_get_char = atmel_poll_get_char,
1407 .poll_put_char = atmel_poll_put_char,
1408 #endif
1409 };
1410
1411 /*
1412 * Configure the port from the platform device resource info.
1413 */
1414 static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port,
1415 struct platform_device *pdev)
1416 {
1417 struct uart_port *port = &atmel_port->uart;
1418 struct atmel_uart_data *data = pdev->dev.platform_data;
1419
1420 port->iotype = UPIO_MEM;
1421 port->flags = UPF_BOOT_AUTOCONF;
1422 port->ops = &atmel_pops;
1423 port->fifosize = 1;
1424 port->line = data->num;
1425 port->dev = &pdev->dev;
1426 port->mapbase = pdev->resource[0].start;
1427 port->irq = pdev->resource[1].start;
1428
1429 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
1430 (unsigned long)port);
1431
1432 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
1433
1434 if (data->regs)
1435 /* Already mapped by setup code */
1436 port->membase = data->regs;
1437 else {
1438 port->flags |= UPF_IOREMAP;
1439 port->membase = NULL;
1440 }
1441
1442 /* for console, the clock could already be configured */
1443 if (!atmel_port->clk) {
1444 atmel_port->clk = clk_get(&pdev->dev, "usart");
1445 clk_enable(atmel_port->clk);
1446 port->uartclk = clk_get_rate(atmel_port->clk);
1447 clk_disable(atmel_port->clk);
1448 /* only enable clock when USART is in use */
1449 }
1450
1451 atmel_port->use_dma_rx = data->use_dma_rx;
1452 atmel_port->use_dma_tx = data->use_dma_tx;
1453 atmel_port->rs485 = data->rs485;
1454 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
1455 if (atmel_port->rs485.flags & SER_RS485_ENABLED)
1456 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
1457 else if (atmel_use_dma_tx(port)) {
1458 port->fifosize = PDC_BUFFER_SIZE;
1459 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
1460 } else {
1461 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
1462 }
1463 }
1464
1465 /*
1466 * Register board-specific modem-control line handlers.
1467 */
1468 void __init atmel_register_uart_fns(struct atmel_port_fns *fns)
1469 {
1470 if (fns->enable_ms)
1471 atmel_pops.enable_ms = fns->enable_ms;
1472 if (fns->get_mctrl)
1473 atmel_pops.get_mctrl = fns->get_mctrl;
1474 if (fns->set_mctrl)
1475 atmel_pops.set_mctrl = fns->set_mctrl;
1476 atmel_open_hook = fns->open;
1477 atmel_close_hook = fns->close;
1478 atmel_pops.pm = fns->pm;
1479 atmel_pops.set_wake = fns->set_wake;
1480 }
1481
1482 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
1483 static void atmel_console_putchar(struct uart_port *port, int ch)
1484 {
1485 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
1486 cpu_relax();
1487 UART_PUT_CHAR(port, ch);
1488 }
1489
1490 /*
1491 * Interrupts are disabled on entering
1492 */
1493 static void atmel_console_write(struct console *co, const char *s, u_int count)
1494 {
1495 struct uart_port *port = &atmel_ports[co->index].uart;
1496 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1497 unsigned int status, imr;
1498 unsigned int pdc_tx;
1499
1500 /*
1501 * First, save IMR and then disable interrupts
1502 */
1503 imr = UART_GET_IMR(port);
1504 UART_PUT_IDR(port, ATMEL_US_RXRDY | atmel_port->tx_done_mask);
1505
1506 /* Store PDC transmit status and disable it */
1507 pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN;
1508 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
1509
1510 uart_console_write(port, s, count, atmel_console_putchar);
1511
1512 /*
1513 * Finally, wait for transmitter to become empty
1514 * and restore IMR
1515 */
1516 do {
1517 status = UART_GET_CSR(port);
1518 } while (!(status & ATMEL_US_TXRDY));
1519
1520 /* Restore PDC transmit status */
1521 if (pdc_tx)
1522 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
1523
1524 /* set interrupts back the way they were */
1525 UART_PUT_IER(port, imr);
1526 }
1527
1528 /*
1529 * If the port was already initialised (eg, by a boot loader),
1530 * try to determine the current setup.
1531 */
1532 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
1533 int *parity, int *bits)
1534 {
1535 unsigned int mr, quot;
1536
1537 /*
1538 * If the baud rate generator isn't running, the port wasn't
1539 * initialized by the boot loader.
1540 */
1541 quot = UART_GET_BRGR(port) & ATMEL_US_CD;
1542 if (!quot)
1543 return;
1544
1545 mr = UART_GET_MR(port) & ATMEL_US_CHRL;
1546 if (mr == ATMEL_US_CHRL_8)
1547 *bits = 8;
1548 else
1549 *bits = 7;
1550
1551 mr = UART_GET_MR(port) & ATMEL_US_PAR;
1552 if (mr == ATMEL_US_PAR_EVEN)
1553 *parity = 'e';
1554 else if (mr == ATMEL_US_PAR_ODD)
1555 *parity = 'o';
1556
1557 /*
1558 * The serial core only rounds down when matching this to a
1559 * supported baud rate. Make sure we don't end up slightly
1560 * lower than one of those, as it would make us fall through
1561 * to a much lower baud rate than we really want.
1562 */
1563 *baud = port->uartclk / (16 * (quot - 1));
1564 }
1565
1566 static int __init atmel_console_setup(struct console *co, char *options)
1567 {
1568 struct uart_port *port = &atmel_ports[co->index].uart;
1569 int baud = 115200;
1570 int bits = 8;
1571 int parity = 'n';
1572 int flow = 'n';
1573
1574 if (port->membase == NULL) {
1575 /* Port not initialized yet - delay setup */
1576 return -ENODEV;
1577 }
1578
1579 clk_enable(atmel_ports[co->index].clk);
1580
1581 UART_PUT_IDR(port, -1);
1582 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1583 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1584
1585 if (options)
1586 uart_parse_options(options, &baud, &parity, &bits, &flow);
1587 else
1588 atmel_console_get_options(port, &baud, &parity, &bits);
1589
1590 return uart_set_options(port, co, baud, parity, bits, flow);
1591 }
1592
1593 static struct uart_driver atmel_uart;
1594
1595 static struct console atmel_console = {
1596 .name = ATMEL_DEVICENAME,
1597 .write = atmel_console_write,
1598 .device = uart_console_device,
1599 .setup = atmel_console_setup,
1600 .flags = CON_PRINTBUFFER,
1601 .index = -1,
1602 .data = &atmel_uart,
1603 };
1604
1605 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
1606
1607 /*
1608 * Early console initialization (before VM subsystem initialized).
1609 */
1610 static int __init atmel_console_init(void)
1611 {
1612 if (atmel_default_console_device) {
1613 add_preferred_console(ATMEL_DEVICENAME,
1614 atmel_default_console_device->id, NULL);
1615 atmel_init_port(&atmel_ports[atmel_default_console_device->id],
1616 atmel_default_console_device);
1617 register_console(&atmel_console);
1618 }
1619
1620 return 0;
1621 }
1622
1623 console_initcall(atmel_console_init);
1624
1625 /*
1626 * Late console initialization.
1627 */
1628 static int __init atmel_late_console_init(void)
1629 {
1630 if (atmel_default_console_device
1631 && !(atmel_console.flags & CON_ENABLED))
1632 register_console(&atmel_console);
1633
1634 return 0;
1635 }
1636
1637 core_initcall(atmel_late_console_init);
1638
1639 static inline bool atmel_is_console_port(struct uart_port *port)
1640 {
1641 return port->cons && port->cons->index == port->line;
1642 }
1643
1644 #else
1645 #define ATMEL_CONSOLE_DEVICE NULL
1646
1647 static inline bool atmel_is_console_port(struct uart_port *port)
1648 {
1649 return false;
1650 }
1651 #endif
1652
1653 static struct uart_driver atmel_uart = {
1654 .owner = THIS_MODULE,
1655 .driver_name = "atmel_serial",
1656 .dev_name = ATMEL_DEVICENAME,
1657 .major = SERIAL_ATMEL_MAJOR,
1658 .minor = MINOR_START,
1659 .nr = ATMEL_MAX_UART,
1660 .cons = ATMEL_CONSOLE_DEVICE,
1661 };
1662
1663 #ifdef CONFIG_PM
1664 static bool atmel_serial_clk_will_stop(void)
1665 {
1666 #ifdef CONFIG_ARCH_AT91
1667 return at91_suspend_entering_slow_clock();
1668 #else
1669 return false;
1670 #endif
1671 }
1672
1673 static int atmel_serial_suspend(struct platform_device *pdev,
1674 pm_message_t state)
1675 {
1676 struct uart_port *port = platform_get_drvdata(pdev);
1677 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1678
1679 if (atmel_is_console_port(port) && console_suspend_enabled) {
1680 /* Drain the TX shifter */
1681 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY))
1682 cpu_relax();
1683 }
1684
1685 /* we can not wake up if we're running on slow clock */
1686 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
1687 if (atmel_serial_clk_will_stop())
1688 device_set_wakeup_enable(&pdev->dev, 0);
1689
1690 uart_suspend_port(&atmel_uart, port);
1691
1692 return 0;
1693 }
1694
1695 static int atmel_serial_resume(struct platform_device *pdev)
1696 {
1697 struct uart_port *port = platform_get_drvdata(pdev);
1698 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1699
1700 uart_resume_port(&atmel_uart, port);
1701 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
1702
1703 return 0;
1704 }
1705 #else
1706 #define atmel_serial_suspend NULL
1707 #define atmel_serial_resume NULL
1708 #endif
1709
1710 static int __devinit atmel_serial_probe(struct platform_device *pdev)
1711 {
1712 struct atmel_uart_port *port;
1713 struct atmel_uart_data *pdata = pdev->dev.platform_data;
1714 void *data;
1715 int ret;
1716
1717 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
1718
1719 port = &atmel_ports[pdata->num];
1720 port->backup_imr = 0;
1721
1722 atmel_init_port(port, pdev);
1723
1724 if (!atmel_use_dma_rx(&port->uart)) {
1725 ret = -ENOMEM;
1726 data = kmalloc(sizeof(struct atmel_uart_char)
1727 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
1728 if (!data)
1729 goto err_alloc_ring;
1730 port->rx_ring.buf = data;
1731 }
1732
1733 ret = uart_add_one_port(&atmel_uart, &port->uart);
1734 if (ret)
1735 goto err_add_port;
1736
1737 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
1738 if (atmel_is_console_port(&port->uart)
1739 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
1740 /*
1741 * The serial core enabled the clock for us, so undo
1742 * the clk_enable() in atmel_console_setup()
1743 */
1744 clk_disable(port->clk);
1745 }
1746 #endif
1747
1748 device_init_wakeup(&pdev->dev, 1);
1749 platform_set_drvdata(pdev, port);
1750
1751 if (port->rs485.flags & SER_RS485_ENABLED) {
1752 UART_PUT_MR(&port->uart, ATMEL_US_USMODE_NORMAL);
1753 UART_PUT_CR(&port->uart, ATMEL_US_RTSEN);
1754 }
1755
1756 return 0;
1757
1758 err_add_port:
1759 kfree(port->rx_ring.buf);
1760 port->rx_ring.buf = NULL;
1761 err_alloc_ring:
1762 if (!atmel_is_console_port(&port->uart)) {
1763 clk_put(port->clk);
1764 port->clk = NULL;
1765 }
1766
1767 return ret;
1768 }
1769
1770 static int __devexit atmel_serial_remove(struct platform_device *pdev)
1771 {
1772 struct uart_port *port = platform_get_drvdata(pdev);
1773 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1774 int ret = 0;
1775
1776 device_init_wakeup(&pdev->dev, 0);
1777 platform_set_drvdata(pdev, NULL);
1778
1779 ret = uart_remove_one_port(&atmel_uart, port);
1780
1781 tasklet_kill(&atmel_port->tasklet);
1782 kfree(atmel_port->rx_ring.buf);
1783
1784 /* "port" is allocated statically, so we shouldn't free it */
1785
1786 clk_put(atmel_port->clk);
1787
1788 return ret;
1789 }
1790
1791 static struct platform_driver atmel_serial_driver = {
1792 .probe = atmel_serial_probe,
1793 .remove = __devexit_p(atmel_serial_remove),
1794 .suspend = atmel_serial_suspend,
1795 .resume = atmel_serial_resume,
1796 .driver = {
1797 .name = "atmel_usart",
1798 .owner = THIS_MODULE,
1799 },
1800 };
1801
1802 static int __init atmel_serial_init(void)
1803 {
1804 int ret;
1805
1806 ret = uart_register_driver(&atmel_uart);
1807 if (ret)
1808 return ret;
1809
1810 ret = platform_driver_register(&atmel_serial_driver);
1811 if (ret)
1812 uart_unregister_driver(&atmel_uart);
1813
1814 return ret;
1815 }
1816
1817 static void __exit atmel_serial_exit(void)
1818 {
1819 platform_driver_unregister(&atmel_serial_driver);
1820 uart_unregister_driver(&atmel_uart);
1821 }
1822
1823 module_init(atmel_serial_init);
1824 module_exit(atmel_serial_exit);
1825
1826 MODULE_AUTHOR("Rick Bronson");
1827 MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver");
1828 MODULE_LICENSE("GPL");
1829 MODULE_ALIAS("platform:atmel_usart");
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