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intel-gtt: fix gtt_total_entries detection
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / char / agp / intel-gtt.c
blob3b84d8445a434ea09e7b27e4e8197977d3f63a8b
1 /*
2 * Intel GTT (Graphics Translation Table) routines
3 *
4 * Caveat: This driver implements the linux agp interface, but this is far from
5 * a agp driver! GTT support ended up here for purely historical reasons: The
6 * old userspace intel graphics drivers needed an interface to map memory into
7 * the GTT. And the drm provides a default interface for graphic devices sitting
8 * on an agp port. So it made sense to fake the GTT support as an agp port to
9 * avoid having to create a new api.
10 *
11 * With gem this does not make much sense anymore, just needlessly complicates
12 * the code. But as long as the old graphics stack is still support, it's stuck
13 * here.
14 *
15 * /fairy-tale-mode off
16 */
17
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/pagemap.h>
23 #include <linux/agp_backend.h>
24 #include <asm/smp.h>
25 #include "agp.h"
26 #include "intel-agp.h"
27 #include <linux/intel-gtt.h>
28 #include <drm/intel-gtt.h>
29
30 /*
31 * If we have Intel graphics, we're not going to have anything other than
32 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
33 * on the Intel IOMMU support (CONFIG_DMAR).
34 * Only newer chipsets need to bother with this, of course.
35 */
36 #ifdef CONFIG_DMAR
37 #define USE_PCI_DMA_API 1
38 #endif
39
40 /* Max amount of stolen space, anything above will be returned to Linux */
41 int intel_max_stolen = 32 * 1024 * 1024;
42 EXPORT_SYMBOL(intel_max_stolen);
43
44 static const struct aper_size_info_fixed intel_i810_sizes[] =
45 {
46 {64, 16384, 4},
47 /* The 32M mode still requires a 64k gatt */
48 {32, 8192, 4}
49 };
50
51 #define AGP_DCACHE_MEMORY 1
52 #define AGP_PHYS_MEMORY 2
53 #define INTEL_AGP_CACHED_MEMORY 3
54
55 static struct gatt_mask intel_i810_masks[] =
56 {
57 {.mask = I810_PTE_VALID, .type = 0},
58 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
59 {.mask = I810_PTE_VALID, .type = 0},
60 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
61 .type = INTEL_AGP_CACHED_MEMORY}
62 };
63
64 #define INTEL_AGP_UNCACHED_MEMORY 0
65 #define INTEL_AGP_CACHED_MEMORY_LLC 1
66 #define INTEL_AGP_CACHED_MEMORY_LLC_GFDT 2
67 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC 3
68 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT 4
69
70 static struct gatt_mask intel_gen6_masks[] =
71 {
72 {.mask = I810_PTE_VALID | GEN6_PTE_UNCACHED,
73 .type = INTEL_AGP_UNCACHED_MEMORY },
74 {.mask = I810_PTE_VALID | GEN6_PTE_LLC,
75 .type = INTEL_AGP_CACHED_MEMORY_LLC },
76 {.mask = I810_PTE_VALID | GEN6_PTE_LLC | GEN6_PTE_GFDT,
77 .type = INTEL_AGP_CACHED_MEMORY_LLC_GFDT },
78 {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC,
79 .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC },
80 {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC | GEN6_PTE_GFDT,
81 .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT },
82 };
83
84 static struct _intel_private {
85 struct intel_gtt base;
86 struct pci_dev *pcidev; /* device one */
87 struct pci_dev *bridge_dev;
88 u8 __iomem *registers;
89 u32 __iomem *gtt; /* I915G */
90 int num_dcache_entries;
91 union {
92 void __iomem *i9xx_flush_page;
93 void *i8xx_flush_page;
94 };
95 struct page *i8xx_page;
96 struct resource ifp_resource;
97 int resource_valid;
98 } intel_private;
99
100 #ifdef USE_PCI_DMA_API
101 static int intel_agp_map_page(struct page *page, dma_addr_t *ret)
102 {
103 *ret = pci_map_page(intel_private.pcidev, page, 0,
104 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
105 if (pci_dma_mapping_error(intel_private.pcidev, *ret))
106 return -EINVAL;
107 return 0;
108 }
109
110 static void intel_agp_unmap_page(struct page *page, dma_addr_t dma)
111 {
112 pci_unmap_page(intel_private.pcidev, dma,
113 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
114 }
115
116 static void intel_agp_free_sglist(struct agp_memory *mem)
117 {
118 struct sg_table st;
119
120 st.sgl = mem->sg_list;
121 st.orig_nents = st.nents = mem->page_count;
122
123 sg_free_table(&st);
124
125 mem->sg_list = NULL;
126 mem->num_sg = 0;
127 }
128
129 static int intel_agp_map_memory(struct agp_memory *mem)
130 {
131 struct sg_table st;
132 struct scatterlist *sg;
133 int i;
134
135 DBG("try mapping %lu pages\n", (unsigned long)mem->page_count);
136
137 if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL))
138 goto err;
139
140 mem->sg_list = sg = st.sgl;
141
142 for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg))
143 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0);
144
145 mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list,
146 mem->page_count, PCI_DMA_BIDIRECTIONAL);
147 if (unlikely(!mem->num_sg))
148 goto err;
149
150 return 0;
151
152 err:
153 sg_free_table(&st);
154 return -ENOMEM;
155 }
156
157 static void intel_agp_unmap_memory(struct agp_memory *mem)
158 {
159 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
160
161 pci_unmap_sg(intel_private.pcidev, mem->sg_list,
162 mem->page_count, PCI_DMA_BIDIRECTIONAL);
163 intel_agp_free_sglist(mem);
164 }
165
166 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
167 off_t pg_start, int mask_type)
168 {
169 struct scatterlist *sg;
170 int i, j;
171
172 j = pg_start;
173
174 WARN_ON(!mem->num_sg);
175
176 if (mem->num_sg == mem->page_count) {
177 for_each_sg(mem->sg_list, sg, mem->page_count, i) {
178 writel(agp_bridge->driver->mask_memory(agp_bridge,
179 sg_dma_address(sg), mask_type),
180 intel_private.gtt+j);
181 j++;
182 }
183 } else {
184 /* sg may merge pages, but we have to separate
185 * per-page addr for GTT */
186 unsigned int len, m;
187
188 for_each_sg(mem->sg_list, sg, mem->num_sg, i) {
189 len = sg_dma_len(sg) / PAGE_SIZE;
190 for (m = 0; m < len; m++) {
191 writel(agp_bridge->driver->mask_memory(agp_bridge,
192 sg_dma_address(sg) + m * PAGE_SIZE,
193 mask_type),
194 intel_private.gtt+j);
195 j++;
196 }
197 }
198 }
199 readl(intel_private.gtt+j-1);
200 }
201
202 #else
203
204 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
205 off_t pg_start, int mask_type)
206 {
207 int i, j;
208
209 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
210 writel(agp_bridge->driver->mask_memory(agp_bridge,
211 page_to_phys(mem->pages[i]), mask_type),
212 intel_private.gtt+j);
213 }
214
215 readl(intel_private.gtt+j-1);
216 }
217
218 #endif
219
220 static int intel_i810_fetch_size(void)
221 {
222 u32 smram_miscc;
223 struct aper_size_info_fixed *values;
224
225 pci_read_config_dword(intel_private.bridge_dev,
226 I810_SMRAM_MISCC, &smram_miscc);
227 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
228
229 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
230 dev_warn(&intel_private.bridge_dev->dev, "i810 is disabled\n");
231 return 0;
232 }
233 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
234 agp_bridge->current_size = (void *) (values + 1);
235 agp_bridge->aperture_size_idx = 1;
236 return values[1].size;
237 } else {
238 agp_bridge->current_size = (void *) (values);
239 agp_bridge->aperture_size_idx = 0;
240 return values[0].size;
241 }
242
243 return 0;
244 }
245
246 static int intel_i810_configure(void)
247 {
248 struct aper_size_info_fixed *current_size;
249 u32 temp;
250 int i;
251
252 current_size = A_SIZE_FIX(agp_bridge->current_size);
253
254 if (!intel_private.registers) {
255 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
256 temp &= 0xfff80000;
257
258 intel_private.registers = ioremap(temp, 128 * 4096);
259 if (!intel_private.registers) {
260 dev_err(&intel_private.pcidev->dev,
261 "can't remap memory\n");
262 return -ENOMEM;
263 }
264 }
265
266 if ((readl(intel_private.registers+I810_DRAM_CTL)
267 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
268 /* This will need to be dynamically assigned */
269 dev_info(&intel_private.pcidev->dev,
270 "detected 4MB dedicated video ram\n");
271 intel_private.num_dcache_entries = 1024;
272 }
273 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
274 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
275 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
276 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
277
278 if (agp_bridge->driver->needs_scratch_page) {
279 for (i = 0; i < current_size->num_entries; i++) {
280 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
281 }
282 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
283 }
284 global_cache_flush();
285 return 0;
286 }
287
288 static void intel_i810_cleanup(void)
289 {
290 writel(0, intel_private.registers+I810_PGETBL_CTL);
291 readl(intel_private.registers); /* PCI Posting. */
292 iounmap(intel_private.registers);
293 }
294
295 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
296 {
297 return;
298 }
299
300 /* Exists to support ARGB cursors */
301 static struct page *i8xx_alloc_pages(void)
302 {
303 struct page *page;
304
305 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
306 if (page == NULL)
307 return NULL;
308
309 if (set_pages_uc(page, 4) < 0) {
310 set_pages_wb(page, 4);
311 __free_pages(page, 2);
312 return NULL;
313 }
314 get_page(page);
315 atomic_inc(&agp_bridge->current_memory_agp);
316 return page;
317 }
318
319 static void i8xx_destroy_pages(struct page *page)
320 {
321 if (page == NULL)
322 return;
323
324 set_pages_wb(page, 4);
325 put_page(page);
326 __free_pages(page, 2);
327 atomic_dec(&agp_bridge->current_memory_agp);
328 }
329
330 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
331 int type)
332 {
333 if (type < AGP_USER_TYPES)
334 return type;
335 else if (type == AGP_USER_CACHED_MEMORY)
336 return INTEL_AGP_CACHED_MEMORY;
337 else
338 return 0;
339 }
340
341 static int intel_gen6_type_to_mask_type(struct agp_bridge_data *bridge,
342 int type)
343 {
344 unsigned int type_mask = type & ~AGP_USER_CACHED_MEMORY_GFDT;
345 unsigned int gfdt = type & AGP_USER_CACHED_MEMORY_GFDT;
346
347 if (type_mask == AGP_USER_UNCACHED_MEMORY)
348 return INTEL_AGP_UNCACHED_MEMORY;
349 else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC)
350 return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT :
351 INTEL_AGP_CACHED_MEMORY_LLC_MLC;
352 else /* set 'normal'/'cached' to LLC by default */
353 return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_GFDT :
354 INTEL_AGP_CACHED_MEMORY_LLC;
355 }
356
357
358 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
359 int type)
360 {
361 int i, j, num_entries;
362 void *temp;
363 int ret = -EINVAL;
364 int mask_type;
365
366 if (mem->page_count == 0)
367 goto out;
368
369 temp = agp_bridge->current_size;
370 num_entries = A_SIZE_FIX(temp)->num_entries;
371
372 if ((pg_start + mem->page_count) > num_entries)
373 goto out_err;
374
375
376 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
377 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
378 ret = -EBUSY;
379 goto out_err;
380 }
381 }
382
383 if (type != mem->type)
384 goto out_err;
385
386 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
387
388 switch (mask_type) {
389 case AGP_DCACHE_MEMORY:
390 if (!mem->is_flushed)
391 global_cache_flush();
392 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
393 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
394 intel_private.registers+I810_PTE_BASE+(i*4));
395 }
396 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
397 break;
398 case AGP_PHYS_MEMORY:
399 case AGP_NORMAL_MEMORY:
400 if (!mem->is_flushed)
401 global_cache_flush();
402 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
403 writel(agp_bridge->driver->mask_memory(agp_bridge,
404 page_to_phys(mem->pages[i]), mask_type),
405 intel_private.registers+I810_PTE_BASE+(j*4));
406 }
407 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
408 break;
409 default:
410 goto out_err;
411 }
412
413 out:
414 ret = 0;
415 out_err:
416 mem->is_flushed = true;
417 return ret;
418 }
419
420 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
421 int type)
422 {
423 int i;
424
425 if (mem->page_count == 0)
426 return 0;
427
428 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
429 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
430 }
431 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
432
433 return 0;
434 }
435
436 /*
437 * The i810/i830 requires a physical address to program its mouse
438 * pointer into hardware.
439 * However the Xserver still writes to it through the agp aperture.
440 */
441 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
442 {
443 struct agp_memory *new;
444 struct page *page;
445
446 switch (pg_count) {
447 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
448 break;
449 case 4:
450 /* kludge to get 4 physical pages for ARGB cursor */
451 page = i8xx_alloc_pages();
452 break;
453 default:
454 return NULL;
455 }
456
457 if (page == NULL)
458 return NULL;
459
460 new = agp_create_memory(pg_count);
461 if (new == NULL)
462 return NULL;
463
464 new->pages[0] = page;
465 if (pg_count == 4) {
466 /* kludge to get 4 physical pages for ARGB cursor */
467 new->pages[1] = new->pages[0] + 1;
468 new->pages[2] = new->pages[1] + 1;
469 new->pages[3] = new->pages[2] + 1;
470 }
471 new->page_count = pg_count;
472 new->num_scratch_pages = pg_count;
473 new->type = AGP_PHYS_MEMORY;
474 new->physical = page_to_phys(new->pages[0]);
475 return new;
476 }
477
478 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
479 {
480 struct agp_memory *new;
481
482 if (type == AGP_DCACHE_MEMORY) {
483 if (pg_count != intel_private.num_dcache_entries)
484 return NULL;
485
486 new = agp_create_memory(1);
487 if (new == NULL)
488 return NULL;
489
490 new->type = AGP_DCACHE_MEMORY;
491 new->page_count = pg_count;
492 new->num_scratch_pages = 0;
493 agp_free_page_array(new);
494 return new;
495 }
496 if (type == AGP_PHYS_MEMORY)
497 return alloc_agpphysmem_i8xx(pg_count, type);
498 return NULL;
499 }
500
501 static void intel_i810_free_by_type(struct agp_memory *curr)
502 {
503 agp_free_key(curr->key);
504 if (curr->type == AGP_PHYS_MEMORY) {
505 if (curr->page_count == 4)
506 i8xx_destroy_pages(curr->pages[0]);
507 else {
508 agp_bridge->driver->agp_destroy_page(curr->pages[0],
509 AGP_PAGE_DESTROY_UNMAP);
510 agp_bridge->driver->agp_destroy_page(curr->pages[0],
511 AGP_PAGE_DESTROY_FREE);
512 }
513 agp_free_page_array(curr);
514 }
515 kfree(curr);
516 }
517
518 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
519 dma_addr_t addr, int type)
520 {
521 /* Type checking must be done elsewhere */
522 return addr | bridge->driver->masks[type].mask;
523 }
524
525 static struct aper_size_info_fixed intel_fake_agp_sizes[] =
526 {
527 {128, 32768, 5},
528 /* The 64M mode still requires a 128k gatt */
529 {64, 16384, 5},
530 {256, 65536, 6},
531 {512, 131072, 7},
532 };
533
534 static unsigned int intel_gtt_stolen_entries(void)
535 {
536 u16 gmch_ctrl;
537 u8 rdct;
538 int local = 0;
539 static const int ddt[4] = { 0, 16, 32, 64 };
540 unsigned int overhead_entries, stolen_entries;
541 unsigned int stolen_size = 0;
542
543 pci_read_config_word(intel_private.bridge_dev,
544 I830_GMCH_CTRL, &gmch_ctrl);
545
546 if (IS_G4X || IS_PINEVIEW)
547 overhead_entries = 0;
548 else
549 overhead_entries = intel_private.base.gtt_mappable_entries
550 / 1024;
551
552 overhead_entries += 1; /* BIOS popup */
553
554 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
555 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
556 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
557 case I830_GMCH_GMS_STOLEN_512:
558 stolen_size = KB(512);
559 break;
560 case I830_GMCH_GMS_STOLEN_1024:
561 stolen_size = MB(1);
562 break;
563 case I830_GMCH_GMS_STOLEN_8192:
564 stolen_size = MB(8);
565 break;
566 case I830_GMCH_GMS_LOCAL:
567 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
568 stolen_size = (I830_RDRAM_ND(rdct) + 1) *
569 MB(ddt[I830_RDRAM_DDT(rdct)]);
570 local = 1;
571 break;
572 default:
573 stolen_size = 0;
574 break;
575 }
576 } else if (IS_SNB) {
577 /*
578 * SandyBridge has new memory control reg at 0x50.w
579 */
580 u16 snb_gmch_ctl;
581 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
582 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
583 case SNB_GMCH_GMS_STOLEN_32M:
584 stolen_size = MB(32);
585 break;
586 case SNB_GMCH_GMS_STOLEN_64M:
587 stolen_size = MB(64);
588 break;
589 case SNB_GMCH_GMS_STOLEN_96M:
590 stolen_size = MB(96);
591 break;
592 case SNB_GMCH_GMS_STOLEN_128M:
593 stolen_size = MB(128);
594 break;
595 case SNB_GMCH_GMS_STOLEN_160M:
596 stolen_size = MB(160);
597 break;
598 case SNB_GMCH_GMS_STOLEN_192M:
599 stolen_size = MB(192);
600 break;
601 case SNB_GMCH_GMS_STOLEN_224M:
602 stolen_size = MB(224);
603 break;
604 case SNB_GMCH_GMS_STOLEN_256M:
605 stolen_size = MB(256);
606 break;
607 case SNB_GMCH_GMS_STOLEN_288M:
608 stolen_size = MB(288);
609 break;
610 case SNB_GMCH_GMS_STOLEN_320M:
611 stolen_size = MB(320);
612 break;
613 case SNB_GMCH_GMS_STOLEN_352M:
614 stolen_size = MB(352);
615 break;
616 case SNB_GMCH_GMS_STOLEN_384M:
617 stolen_size = MB(384);
618 break;
619 case SNB_GMCH_GMS_STOLEN_416M:
620 stolen_size = MB(416);
621 break;
622 case SNB_GMCH_GMS_STOLEN_448M:
623 stolen_size = MB(448);
624 break;
625 case SNB_GMCH_GMS_STOLEN_480M:
626 stolen_size = MB(480);
627 break;
628 case SNB_GMCH_GMS_STOLEN_512M:
629 stolen_size = MB(512);
630 break;
631 }
632 } else {
633 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
634 case I855_GMCH_GMS_STOLEN_1M:
635 stolen_size = MB(1);
636 break;
637 case I855_GMCH_GMS_STOLEN_4M:
638 stolen_size = MB(4);
639 break;
640 case I855_GMCH_GMS_STOLEN_8M:
641 stolen_size = MB(8);
642 break;
643 case I855_GMCH_GMS_STOLEN_16M:
644 stolen_size = MB(16);
645 break;
646 case I855_GMCH_GMS_STOLEN_32M:
647 stolen_size = MB(32);
648 break;
649 case I915_GMCH_GMS_STOLEN_48M:
650 stolen_size = MB(48);
651 break;
652 case I915_GMCH_GMS_STOLEN_64M:
653 stolen_size = MB(64);
654 break;
655 case G33_GMCH_GMS_STOLEN_128M:
656 stolen_size = MB(128);
657 break;
658 case G33_GMCH_GMS_STOLEN_256M:
659 stolen_size = MB(256);
660 break;
661 case INTEL_GMCH_GMS_STOLEN_96M:
662 stolen_size = MB(96);
663 break;
664 case INTEL_GMCH_GMS_STOLEN_160M:
665 stolen_size = MB(160);
666 break;
667 case INTEL_GMCH_GMS_STOLEN_224M:
668 stolen_size = MB(224);
669 break;
670 case INTEL_GMCH_GMS_STOLEN_352M:
671 stolen_size = MB(352);
672 break;
673 default:
674 stolen_size = 0;
675 break;
676 }
677 }
678
679 if (!local && stolen_size > intel_max_stolen) {
680 dev_info(&intel_private.bridge_dev->dev,
681 "detected %dK stolen memory, trimming to %dK\n",
682 stolen_size / KB(1), intel_max_stolen / KB(1));
683 stolen_size = intel_max_stolen;
684 } else if (stolen_size > 0) {
685 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
686 stolen_size / KB(1), local ? "local" : "stolen");
687 } else {
688 dev_info(&intel_private.bridge_dev->dev,
689 "no pre-allocated video memory detected\n");
690 stolen_size = 0;
691 }
692
693 stolen_entries = stolen_size/KB(4) - overhead_entries;
694
695 return stolen_entries;
696 }
697
698 #if 0 /* extracted code in bad shape, needs some cleaning before use */
699 static unsigned int intel_gtt_total_entries(void)
700 {
701 int size;
702
703 if (IS_G33 || IS_I965 || IS_G4X) {
704 u32 pgetbl_ctl;
705 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
706
707 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
708 case I965_PGETBL_SIZE_128KB:
709 size = KB(128);
710 break;
711 case I965_PGETBL_SIZE_256KB:
712 size = KB(256);
713 break;
714 case I965_PGETBL_SIZE_512KB:
715 size = KB(512);
716 break;
717 case I965_PGETBL_SIZE_1MB:
718 size = KB(1024);
719 break;
720 case I965_PGETBL_SIZE_2MB:
721 size = KB(2048);
722 break;
723 case I965_PGETBL_SIZE_1_5MB:
724 size = KB(1024 + 512);
725 break;
726 default:
727 dev_info(&intel_private.pcidev->dev,
728 "unknown page table size, assuming 512KB\n");
729 size = KB(512);
730 }
731
732 return size/4;
733 } else {
734 /* On previous hardware, the GTT size was just what was
735 * required to map the aperture.
736 */
737 return intel_private.base.gtt_mappable_entries;
738 }
739 }
740 #endif
741
742 static unsigned int intel_gtt_mappable_entries(void)
743 {
744 unsigned int aperture_size;
745 u16 gmch_ctrl;
746
747 aperture_size = 1024 * 1024;
748
749 pci_read_config_word(intel_private.bridge_dev,
750 I830_GMCH_CTRL, &gmch_ctrl);
751
752 switch (intel_private.pcidev->device) {
753 case PCI_DEVICE_ID_INTEL_82830_CGC:
754 case PCI_DEVICE_ID_INTEL_82845G_IG:
755 case PCI_DEVICE_ID_INTEL_82855GM_IG:
756 case PCI_DEVICE_ID_INTEL_82865_IG:
757 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
758 aperture_size *= 64;
759 else
760 aperture_size *= 128;
761 break;
762 default:
763 /* 9xx supports large sizes, just look at the length */
764 aperture_size = pci_resource_len(intel_private.pcidev, 2);
765 break;
766 }
767
768 return aperture_size >> PAGE_SHIFT;
769 }
770
771 static int intel_gtt_init(void)
772 {
773 /* we have to call this as early as possible after the MMIO base address is known */
774 intel_private.base.gtt_stolen_entries = intel_gtt_stolen_entries();
775 if (intel_private.base.gtt_stolen_entries == 0) {
776 iounmap(intel_private.registers);
777 return -ENOMEM;
778 }
779
780 return 0;
781 }
782
783 static int intel_fake_agp_fetch_size(void)
784 {
785 unsigned int aper_size;
786 int i;
787 int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
788
789 aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT)
790 / MB(1);
791
792 for (i = 0; i < num_sizes; i++) {
793 if (aper_size == intel_fake_agp_sizes[i].size) {
794 agp_bridge->current_size = intel_fake_agp_sizes + i;
795 return aper_size;
796 }
797 }
798
799 return 0;
800 }
801
802 static void intel_i830_fini_flush(void)
803 {
804 kunmap(intel_private.i8xx_page);
805 intel_private.i8xx_flush_page = NULL;
806 unmap_page_from_agp(intel_private.i8xx_page);
807
808 __free_page(intel_private.i8xx_page);
809 intel_private.i8xx_page = NULL;
810 }
811
812 static void intel_i830_setup_flush(void)
813 {
814 /* return if we've already set the flush mechanism up */
815 if (intel_private.i8xx_page)
816 return;
817
818 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
819 if (!intel_private.i8xx_page)
820 return;
821
822 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
823 if (!intel_private.i8xx_flush_page)
824 intel_i830_fini_flush();
825 }
826
827 /* The chipset_flush interface needs to get data that has already been
828 * flushed out of the CPU all the way out to main memory, because the GPU
829 * doesn't snoop those buffers.
830 *
831 * The 8xx series doesn't have the same lovely interface for flushing the
832 * chipset write buffers that the later chips do. According to the 865
833 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
834 * that buffer out, we just fill 1KB and clflush it out, on the assumption
835 * that it'll push whatever was in there out. It appears to work.
836 */
837 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
838 {
839 unsigned int *pg = intel_private.i8xx_flush_page;
840
841 memset(pg, 0, 1024);
842
843 if (cpu_has_clflush)
844 clflush_cache_range(pg, 1024);
845 else if (wbinvd_on_all_cpus() != 0)
846 printk(KERN_ERR "Timed out waiting for cache flush.\n");
847 }
848
849 /* The intel i830 automatically initializes the agp aperture during POST.
850 * Use the memory already set aside for in the GTT.
851 */
852 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
853 {
854 int page_order, ret;
855 struct aper_size_info_fixed *size;
856 int num_entries;
857 u32 temp;
858
859 size = agp_bridge->current_size;
860 page_order = size->page_order;
861 num_entries = size->num_entries;
862 agp_bridge->gatt_table_real = NULL;
863
864 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
865 temp &= 0xfff80000;
866
867 intel_private.registers = ioremap(temp, 128 * 4096);
868 if (!intel_private.registers)
869 return -ENOMEM;
870
871 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
872 global_cache_flush(); /* FIXME: ?? */
873
874 ret = intel_gtt_init();
875 if (ret != 0)
876 return ret;
877
878 agp_bridge->gatt_table = NULL;
879
880 agp_bridge->gatt_bus_addr = temp;
881
882 return 0;
883 }
884
885 /* Return the gatt table to a sane state. Use the top of stolen
886 * memory for the GTT.
887 */
888 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
889 {
890 return 0;
891 }
892
893 static int intel_i830_configure(void)
894 {
895 struct aper_size_info_fixed *current_size;
896 u32 temp;
897 u16 gmch_ctrl;
898 int i;
899
900 current_size = A_SIZE_FIX(agp_bridge->current_size);
901
902 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
903 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
904
905 pci_read_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, &gmch_ctrl);
906 gmch_ctrl |= I830_GMCH_ENABLED;
907 pci_write_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, gmch_ctrl);
908
909 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
910 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
911
912 if (agp_bridge->driver->needs_scratch_page) {
913 for (i = intel_private.base.gtt_stolen_entries; i < current_size->num_entries; i++) {
914 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
915 }
916 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
917 }
918
919 global_cache_flush();
920
921 intel_i830_setup_flush();
922 return 0;
923 }
924
925 static void intel_i830_cleanup(void)
926 {
927 iounmap(intel_private.registers);
928 }
929
930 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
931 int type)
932 {
933 int i, j, num_entries;
934 void *temp;
935 int ret = -EINVAL;
936 int mask_type;
937
938 if (mem->page_count == 0)
939 goto out;
940
941 temp = agp_bridge->current_size;
942 num_entries = A_SIZE_FIX(temp)->num_entries;
943
944 if (pg_start < intel_private.base.gtt_stolen_entries) {
945 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
946 "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
947 pg_start, intel_private.base.gtt_stolen_entries);
948
949 dev_info(&intel_private.pcidev->dev,
950 "trying to insert into local/stolen memory\n");
951 goto out_err;
952 }
953
954 if ((pg_start + mem->page_count) > num_entries)
955 goto out_err;
956
957 /* The i830 can't check the GTT for entries since its read only,
958 * depend on the caller to make the correct offset decisions.
959 */
960
961 if (type != mem->type)
962 goto out_err;
963
964 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
965
966 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
967 mask_type != INTEL_AGP_CACHED_MEMORY)
968 goto out_err;
969
970 if (!mem->is_flushed)
971 global_cache_flush();
972
973 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
974 writel(agp_bridge->driver->mask_memory(agp_bridge,
975 page_to_phys(mem->pages[i]), mask_type),
976 intel_private.registers+I810_PTE_BASE+(j*4));
977 }
978 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
979
980 out:
981 ret = 0;
982 out_err:
983 mem->is_flushed = true;
984 return ret;
985 }
986
987 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
988 int type)
989 {
990 int i;
991
992 if (mem->page_count == 0)
993 return 0;
994
995 if (pg_start < intel_private.base.gtt_stolen_entries) {
996 dev_info(&intel_private.pcidev->dev,
997 "trying to disable local/stolen memory\n");
998 return -EINVAL;
999 }
1000
1001 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1002 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
1003 }
1004 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
1005
1006 return 0;
1007 }
1008
1009 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
1010 int type)
1011 {
1012 if (type == AGP_PHYS_MEMORY)
1013 return alloc_agpphysmem_i8xx(pg_count, type);
1014 /* always return NULL for other allocation types for now */
1015 return NULL;
1016 }
1017
1018 static int intel_alloc_chipset_flush_resource(void)
1019 {
1020 int ret;
1021 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1022 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1023 pcibios_align_resource, intel_private.bridge_dev);
1024
1025 return ret;
1026 }
1027
1028 static void intel_i915_setup_chipset_flush(void)
1029 {
1030 int ret;
1031 u32 temp;
1032
1033 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1034 if (!(temp & 0x1)) {
1035 intel_alloc_chipset_flush_resource();
1036 intel_private.resource_valid = 1;
1037 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1038 } else {
1039 temp &= ~1;
1040
1041 intel_private.resource_valid = 1;
1042 intel_private.ifp_resource.start = temp;
1043 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1044 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1045 /* some BIOSes reserve this area in a pnp some don't */
1046 if (ret)
1047 intel_private.resource_valid = 0;
1048 }
1049 }
1050
1051 static void intel_i965_g33_setup_chipset_flush(void)
1052 {
1053 u32 temp_hi, temp_lo;
1054 int ret;
1055
1056 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1057 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1058
1059 if (!(temp_lo & 0x1)) {
1060
1061 intel_alloc_chipset_flush_resource();
1062
1063 intel_private.resource_valid = 1;
1064 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1065 upper_32_bits(intel_private.ifp_resource.start));
1066 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1067 } else {
1068 u64 l64;
1069
1070 temp_lo &= ~0x1;
1071 l64 = ((u64)temp_hi << 32) | temp_lo;
1072
1073 intel_private.resource_valid = 1;
1074 intel_private.ifp_resource.start = l64;
1075 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1076 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1077 /* some BIOSes reserve this area in a pnp some don't */
1078 if (ret)
1079 intel_private.resource_valid = 0;
1080 }
1081 }
1082
1083 static void intel_i9xx_setup_flush(void)
1084 {
1085 /* return if already configured */
1086 if (intel_private.ifp_resource.start)
1087 return;
1088
1089 if (IS_SNB)
1090 return;
1091
1092 /* setup a resource for this object */
1093 intel_private.ifp_resource.name = "Intel Flush Page";
1094 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1095
1096 /* Setup chipset flush for 915 */
1097 if (IS_I965 || IS_G33 || IS_G4X) {
1098 intel_i965_g33_setup_chipset_flush();
1099 } else {
1100 intel_i915_setup_chipset_flush();
1101 }
1102
1103 if (intel_private.ifp_resource.start)
1104 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1105 if (!intel_private.i9xx_flush_page)
1106 dev_err(&intel_private.pcidev->dev,
1107 "can't ioremap flush page - no chipset flushing\n");
1108 }
1109
1110 static int intel_i9xx_configure(void)
1111 {
1112 struct aper_size_info_fixed *current_size;
1113 u32 temp;
1114 u16 gmch_ctrl;
1115 int i;
1116
1117 current_size = A_SIZE_FIX(agp_bridge->current_size);
1118
1119 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
1120
1121 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1122
1123 pci_read_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, &gmch_ctrl);
1124 gmch_ctrl |= I830_GMCH_ENABLED;
1125 pci_write_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, gmch_ctrl);
1126
1127 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
1128 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1129
1130 if (agp_bridge->driver->needs_scratch_page) {
1131 for (i = intel_private.base.gtt_stolen_entries; i <
1132 intel_private.base.gtt_total_entries; i++) {
1133 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1134 }
1135 readl(intel_private.gtt+i-1); /* PCI Posting. */
1136 }
1137
1138 global_cache_flush();
1139
1140 intel_i9xx_setup_flush();
1141
1142 return 0;
1143 }
1144
1145 static void intel_i915_cleanup(void)
1146 {
1147 if (intel_private.i9xx_flush_page)
1148 iounmap(intel_private.i9xx_flush_page);
1149 if (intel_private.resource_valid)
1150 release_resource(&intel_private.ifp_resource);
1151 intel_private.ifp_resource.start = 0;
1152 intel_private.resource_valid = 0;
1153 iounmap(intel_private.gtt);
1154 iounmap(intel_private.registers);
1155 }
1156
1157 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1158 {
1159 if (intel_private.i9xx_flush_page)
1160 writel(1, intel_private.i9xx_flush_page);
1161 }
1162
1163 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1164 int type)
1165 {
1166 int num_entries;
1167 void *temp;
1168 int ret = -EINVAL;
1169 int mask_type;
1170
1171 if (mem->page_count == 0)
1172 goto out;
1173
1174 temp = agp_bridge->current_size;
1175 num_entries = A_SIZE_FIX(temp)->num_entries;
1176
1177 if (pg_start < intel_private.base.gtt_stolen_entries) {
1178 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1179 "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
1180 pg_start, intel_private.base.gtt_stolen_entries);
1181
1182 dev_info(&intel_private.pcidev->dev,
1183 "trying to insert into local/stolen memory\n");
1184 goto out_err;
1185 }
1186
1187 if ((pg_start + mem->page_count) > num_entries)
1188 goto out_err;
1189
1190 /* The i915 can't check the GTT for entries since it's read only;
1191 * depend on the caller to make the correct offset decisions.
1192 */
1193
1194 if (type != mem->type)
1195 goto out_err;
1196
1197 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1198
1199 if (!IS_SNB && mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1200 mask_type != INTEL_AGP_CACHED_MEMORY)
1201 goto out_err;
1202
1203 if (!mem->is_flushed)
1204 global_cache_flush();
1205
1206 intel_agp_insert_sg_entries(mem, pg_start, mask_type);
1207
1208 out:
1209 ret = 0;
1210 out_err:
1211 mem->is_flushed = true;
1212 return ret;
1213 }
1214
1215 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1216 int type)
1217 {
1218 int i;
1219
1220 if (mem->page_count == 0)
1221 return 0;
1222
1223 if (pg_start < intel_private.base.gtt_stolen_entries) {
1224 dev_info(&intel_private.pcidev->dev,
1225 "trying to disable local/stolen memory\n");
1226 return -EINVAL;
1227 }
1228
1229 for (i = pg_start; i < (mem->page_count + pg_start); i++)
1230 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1231
1232 readl(intel_private.gtt+i-1);
1233
1234 return 0;
1235 }
1236
1237 /* Return the aperture size by just checking the resource length. The effect
1238 * described in the spec of the MSAC registers is just changing of the
1239 * resource size.
1240 */
1241 static int intel_i915_get_gtt_size(void)
1242 {
1243 int size;
1244
1245 if (IS_G33) {
1246 u16 gmch_ctrl;
1247
1248 /* G33's GTT size defined in gmch_ctrl */
1249 pci_read_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, &gmch_ctrl);
1250 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
1251 case I830_GMCH_GMS_STOLEN_512:
1252 size = 512;
1253 break;
1254 case I830_GMCH_GMS_STOLEN_1024:
1255 size = 1024;
1256 break;
1257 case I830_GMCH_GMS_STOLEN_8192:
1258 size = 8*1024;
1259 break;
1260 default:
1261 dev_info(&intel_private.bridge_dev->dev,
1262 "unknown page table size 0x%x, assuming 512KB\n",
1263 (gmch_ctrl & I830_GMCH_GMS_MASK));
1264 size = 512;
1265 }
1266 } else {
1267 /* On previous hardware, the GTT size was just what was
1268 * required to map the aperture.
1269 */
1270 size = agp_bridge->driver->fetch_size();
1271 }
1272
1273 return KB(size);
1274 }
1275
1276 /* The intel i915 automatically initializes the agp aperture during POST.
1277 * Use the memory already set aside for in the GTT.
1278 */
1279 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1280 {
1281 int page_order, ret;
1282 struct aper_size_info_fixed *size;
1283 int num_entries;
1284 u32 temp, temp2;
1285 int gtt_map_size;
1286
1287 size = agp_bridge->current_size;
1288 page_order = size->page_order;
1289 num_entries = size->num_entries;
1290 agp_bridge->gatt_table_real = NULL;
1291
1292 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1293 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1294
1295 gtt_map_size = intel_i915_get_gtt_size();
1296
1297 intel_private.gtt = ioremap(temp2, gtt_map_size);
1298 if (!intel_private.gtt)
1299 return -ENOMEM;
1300
1301 intel_private.base.gtt_total_entries = gtt_map_size / 4;
1302
1303 temp &= 0xfff80000;
1304
1305 intel_private.registers = ioremap(temp, 128 * 4096);
1306 if (!intel_private.registers) {
1307 iounmap(intel_private.gtt);
1308 return -ENOMEM;
1309 }
1310
1311 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1312 global_cache_flush(); /* FIXME: ? */
1313
1314 ret = intel_gtt_init();
1315 if (ret != 0) {
1316 iounmap(intel_private.gtt);
1317 return ret;
1318 }
1319
1320 agp_bridge->gatt_table = NULL;
1321
1322 agp_bridge->gatt_bus_addr = temp;
1323
1324 return 0;
1325 }
1326
1327 /*
1328 * The i965 supports 36-bit physical addresses, but to keep
1329 * the format of the GTT the same, the bits that don't fit
1330 * in a 32-bit word are shifted down to bits 4..7.
1331 *
1332 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1333 * is always zero on 32-bit architectures, so no need to make
1334 * this conditional.
1335 */
1336 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1337 dma_addr_t addr, int type)
1338 {
1339 /* Shift high bits down */
1340 addr |= (addr >> 28) & 0xf0;
1341
1342 /* Type checking must be done elsewhere */
1343 return addr | bridge->driver->masks[type].mask;
1344 }
1345
1346 static unsigned long intel_gen6_mask_memory(struct agp_bridge_data *bridge,
1347 dma_addr_t addr, int type)
1348 {
1349 /* gen6 has bit11-4 for physical addr bit39-32 */
1350 addr |= (addr >> 28) & 0xff0;
1351
1352 /* Type checking must be done elsewhere */
1353 return addr | bridge->driver->masks[type].mask;
1354 }
1355
1356 static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1357 {
1358 u16 snb_gmch_ctl;
1359
1360 switch (intel_private.bridge_dev->device) {
1361 case PCI_DEVICE_ID_INTEL_GM45_HB:
1362 case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB:
1363 case PCI_DEVICE_ID_INTEL_Q45_HB:
1364 case PCI_DEVICE_ID_INTEL_G45_HB:
1365 case PCI_DEVICE_ID_INTEL_G41_HB:
1366 case PCI_DEVICE_ID_INTEL_B43_HB:
1367 case PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB:
1368 case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB:
1369 case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB:
1370 case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB:
1371 *gtt_offset = *gtt_size = MB(2);
1372 break;
1373 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB:
1374 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB:
1375 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB:
1376 *gtt_offset = MB(2);
1377
1378 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1379 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
1380 default:
1381 case SNB_GTT_SIZE_0M:
1382 printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
1383 *gtt_size = MB(0);
1384 break;
1385 case SNB_GTT_SIZE_1M:
1386 *gtt_size = MB(1);
1387 break;
1388 case SNB_GTT_SIZE_2M:
1389 *gtt_size = MB(2);
1390 break;
1391 }
1392 break;
1393 default:
1394 *gtt_offset = *gtt_size = KB(512);
1395 }
1396 }
1397
1398 /* The intel i965 automatically initializes the agp aperture during POST.
1399 * Use the memory already set aside for in the GTT.
1400 */
1401 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1402 {
1403 int page_order, ret;
1404 struct aper_size_info_fixed *size;
1405 int num_entries;
1406 u32 temp;
1407 int gtt_offset, gtt_size;
1408
1409 size = agp_bridge->current_size;
1410 page_order = size->page_order;
1411 num_entries = size->num_entries;
1412 agp_bridge->gatt_table_real = NULL;
1413
1414 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1415
1416 temp &= 0xfff00000;
1417
1418 intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
1419
1420 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1421
1422 if (!intel_private.gtt)
1423 return -ENOMEM;
1424
1425 intel_private.base.gtt_total_entries = gtt_size / 4;
1426
1427 intel_private.registers = ioremap(temp, 128 * 4096);
1428 if (!intel_private.registers) {
1429 iounmap(intel_private.gtt);
1430 return -ENOMEM;
1431 }
1432
1433 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1434 global_cache_flush(); /* FIXME: ? */
1435
1436 ret = intel_gtt_init();
1437 if (ret != 0) {
1438 iounmap(intel_private.gtt);
1439 return ret;
1440 }
1441
1442 agp_bridge->gatt_table = NULL;
1443
1444 agp_bridge->gatt_bus_addr = temp;
1445
1446 return 0;
1447 }
1448
1449 static const struct agp_bridge_driver intel_810_driver = {
1450 .owner = THIS_MODULE,
1451 .aperture_sizes = intel_i810_sizes,
1452 .size_type = FIXED_APER_SIZE,
1453 .num_aperture_sizes = 2,
1454 .needs_scratch_page = true,
1455 .configure = intel_i810_configure,
1456 .fetch_size = intel_i810_fetch_size,
1457 .cleanup = intel_i810_cleanup,
1458 .mask_memory = intel_i810_mask_memory,
1459 .masks = intel_i810_masks,
1460 .agp_enable = intel_fake_agp_enable,
1461 .cache_flush = global_cache_flush,
1462 .create_gatt_table = agp_generic_create_gatt_table,
1463 .free_gatt_table = agp_generic_free_gatt_table,
1464 .insert_memory = intel_i810_insert_entries,
1465 .remove_memory = intel_i810_remove_entries,
1466 .alloc_by_type = intel_i810_alloc_by_type,
1467 .free_by_type = intel_i810_free_by_type,
1468 .agp_alloc_page = agp_generic_alloc_page,
1469 .agp_alloc_pages = agp_generic_alloc_pages,
1470 .agp_destroy_page = agp_generic_destroy_page,
1471 .agp_destroy_pages = agp_generic_destroy_pages,
1472 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1473 };
1474
1475 static const struct agp_bridge_driver intel_830_driver = {
1476 .owner = THIS_MODULE,
1477 .aperture_sizes = intel_fake_agp_sizes,
1478 .size_type = FIXED_APER_SIZE,
1479 .num_aperture_sizes = 4,
1480 .needs_scratch_page = true,
1481 .configure = intel_i830_configure,
1482 .fetch_size = intel_fake_agp_fetch_size,
1483 .cleanup = intel_i830_cleanup,
1484 .mask_memory = intel_i810_mask_memory,
1485 .masks = intel_i810_masks,
1486 .agp_enable = intel_fake_agp_enable,
1487 .cache_flush = global_cache_flush,
1488 .create_gatt_table = intel_i830_create_gatt_table,
1489 .free_gatt_table = intel_fake_agp_free_gatt_table,
1490 .insert_memory = intel_i830_insert_entries,
1491 .remove_memory = intel_i830_remove_entries,
1492 .alloc_by_type = intel_fake_agp_alloc_by_type,
1493 .free_by_type = intel_i810_free_by_type,
1494 .agp_alloc_page = agp_generic_alloc_page,
1495 .agp_alloc_pages = agp_generic_alloc_pages,
1496 .agp_destroy_page = agp_generic_destroy_page,
1497 .agp_destroy_pages = agp_generic_destroy_pages,
1498 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1499 .chipset_flush = intel_i830_chipset_flush,
1500 };
1501
1502 static const struct agp_bridge_driver intel_915_driver = {
1503 .owner = THIS_MODULE,
1504 .aperture_sizes = intel_fake_agp_sizes,
1505 .size_type = FIXED_APER_SIZE,
1506 .num_aperture_sizes = 4,
1507 .needs_scratch_page = true,
1508 .configure = intel_i9xx_configure,
1509 .fetch_size = intel_fake_agp_fetch_size,
1510 .cleanup = intel_i915_cleanup,
1511 .mask_memory = intel_i810_mask_memory,
1512 .masks = intel_i810_masks,
1513 .agp_enable = intel_fake_agp_enable,
1514 .cache_flush = global_cache_flush,
1515 .create_gatt_table = intel_i915_create_gatt_table,
1516 .free_gatt_table = intel_fake_agp_free_gatt_table,
1517 .insert_memory = intel_i915_insert_entries,
1518 .remove_memory = intel_i915_remove_entries,
1519 .alloc_by_type = intel_fake_agp_alloc_by_type,
1520 .free_by_type = intel_i810_free_by_type,
1521 .agp_alloc_page = agp_generic_alloc_page,
1522 .agp_alloc_pages = agp_generic_alloc_pages,
1523 .agp_destroy_page = agp_generic_destroy_page,
1524 .agp_destroy_pages = agp_generic_destroy_pages,
1525 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1526 .chipset_flush = intel_i915_chipset_flush,
1527 #ifdef USE_PCI_DMA_API
1528 .agp_map_page = intel_agp_map_page,
1529 .agp_unmap_page = intel_agp_unmap_page,
1530 .agp_map_memory = intel_agp_map_memory,
1531 .agp_unmap_memory = intel_agp_unmap_memory,
1532 #endif
1533 };
1534
1535 static const struct agp_bridge_driver intel_i965_driver = {
1536 .owner = THIS_MODULE,
1537 .aperture_sizes = intel_fake_agp_sizes,
1538 .size_type = FIXED_APER_SIZE,
1539 .num_aperture_sizes = 4,
1540 .needs_scratch_page = true,
1541 .configure = intel_i9xx_configure,
1542 .fetch_size = intel_fake_agp_fetch_size,
1543 .cleanup = intel_i915_cleanup,
1544 .mask_memory = intel_i965_mask_memory,
1545 .masks = intel_i810_masks,
1546 .agp_enable = intel_fake_agp_enable,
1547 .cache_flush = global_cache_flush,
1548 .create_gatt_table = intel_i965_create_gatt_table,
1549 .free_gatt_table = intel_fake_agp_free_gatt_table,
1550 .insert_memory = intel_i915_insert_entries,
1551 .remove_memory = intel_i915_remove_entries,
1552 .alloc_by_type = intel_fake_agp_alloc_by_type,
1553 .free_by_type = intel_i810_free_by_type,
1554 .agp_alloc_page = agp_generic_alloc_page,
1555 .agp_alloc_pages = agp_generic_alloc_pages,
1556 .agp_destroy_page = agp_generic_destroy_page,
1557 .agp_destroy_pages = agp_generic_destroy_pages,
1558 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1559 .chipset_flush = intel_i915_chipset_flush,
1560 #ifdef USE_PCI_DMA_API
1561 .agp_map_page = intel_agp_map_page,
1562 .agp_unmap_page = intel_agp_unmap_page,
1563 .agp_map_memory = intel_agp_map_memory,
1564 .agp_unmap_memory = intel_agp_unmap_memory,
1565 #endif
1566 };
1567
1568 static const struct agp_bridge_driver intel_gen6_driver = {
1569 .owner = THIS_MODULE,
1570 .aperture_sizes = intel_fake_agp_sizes,
1571 .size_type = FIXED_APER_SIZE,
1572 .num_aperture_sizes = 4,
1573 .needs_scratch_page = true,
1574 .configure = intel_i9xx_configure,
1575 .fetch_size = intel_fake_agp_fetch_size,
1576 .cleanup = intel_i915_cleanup,
1577 .mask_memory = intel_gen6_mask_memory,
1578 .masks = intel_gen6_masks,
1579 .agp_enable = intel_fake_agp_enable,
1580 .cache_flush = global_cache_flush,
1581 .create_gatt_table = intel_i965_create_gatt_table,
1582 .free_gatt_table = intel_fake_agp_free_gatt_table,
1583 .insert_memory = intel_i915_insert_entries,
1584 .remove_memory = intel_i915_remove_entries,
1585 .alloc_by_type = intel_fake_agp_alloc_by_type,
1586 .free_by_type = intel_i810_free_by_type,
1587 .agp_alloc_page = agp_generic_alloc_page,
1588 .agp_alloc_pages = agp_generic_alloc_pages,
1589 .agp_destroy_page = agp_generic_destroy_page,
1590 .agp_destroy_pages = agp_generic_destroy_pages,
1591 .agp_type_to_mask_type = intel_gen6_type_to_mask_type,
1592 .chipset_flush = intel_i915_chipset_flush,
1593 #ifdef USE_PCI_DMA_API
1594 .agp_map_page = intel_agp_map_page,
1595 .agp_unmap_page = intel_agp_unmap_page,
1596 .agp_map_memory = intel_agp_map_memory,
1597 .agp_unmap_memory = intel_agp_unmap_memory,
1598 #endif
1599 };
1600
1601 static const struct agp_bridge_driver intel_g33_driver = {
1602 .owner = THIS_MODULE,
1603 .aperture_sizes = intel_fake_agp_sizes,
1604 .size_type = FIXED_APER_SIZE,
1605 .num_aperture_sizes = 4,
1606 .needs_scratch_page = true,
1607 .configure = intel_i9xx_configure,
1608 .fetch_size = intel_fake_agp_fetch_size,
1609 .cleanup = intel_i915_cleanup,
1610 .mask_memory = intel_i965_mask_memory,
1611 .masks = intel_i810_masks,
1612 .agp_enable = intel_fake_agp_enable,
1613 .cache_flush = global_cache_flush,
1614 .create_gatt_table = intel_i915_create_gatt_table,
1615 .free_gatt_table = intel_fake_agp_free_gatt_table,
1616 .insert_memory = intel_i915_insert_entries,
1617 .remove_memory = intel_i915_remove_entries,
1618 .alloc_by_type = intel_fake_agp_alloc_by_type,
1619 .free_by_type = intel_i810_free_by_type,
1620 .agp_alloc_page = agp_generic_alloc_page,
1621 .agp_alloc_pages = agp_generic_alloc_pages,
1622 .agp_destroy_page = agp_generic_destroy_page,
1623 .agp_destroy_pages = agp_generic_destroy_pages,
1624 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1625 .chipset_flush = intel_i915_chipset_flush,
1626 #ifdef USE_PCI_DMA_API
1627 .agp_map_page = intel_agp_map_page,
1628 .agp_unmap_page = intel_agp_unmap_page,
1629 .agp_map_memory = intel_agp_map_memory,
1630 .agp_unmap_memory = intel_agp_unmap_memory,
1631 #endif
1632 };
1633
1634 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1635 * driver and gmch_driver must be non-null, and find_gmch will determine
1636 * which one should be used if a gmch_chip_id is present.
1637 */
1638 static const struct intel_gtt_driver_description {
1639 unsigned int gmch_chip_id;
1640 char *name;
1641 const struct agp_bridge_driver *gmch_driver;
1642 } intel_gtt_chipsets[] = {
1643 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", &intel_810_driver },
1644 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", &intel_810_driver },
1645 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", &intel_810_driver },
1646 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", &intel_810_driver },
1647 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M", &intel_830_driver },
1648 { PCI_DEVICE_ID_INTEL_82845G_IG, "830M", &intel_830_driver },
1649 { PCI_DEVICE_ID_INTEL_82854_IG, "854", &intel_830_driver },
1650 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", &intel_830_driver },
1651 { PCI_DEVICE_ID_INTEL_82865_IG, "865", &intel_830_driver },
1652 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", &intel_915_driver },
1653 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G", &intel_915_driver },
1654 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", &intel_915_driver },
1655 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G", &intel_915_driver },
1656 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", &intel_915_driver },
1657 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", &intel_915_driver },
1658 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", &intel_i965_driver },
1659 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35", &intel_i965_driver },
1660 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", &intel_i965_driver },
1661 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G", &intel_i965_driver },
1662 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", &intel_i965_driver },
1663 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", &intel_i965_driver },
1664 { PCI_DEVICE_ID_INTEL_G33_IG, "G33", &intel_g33_driver },
1665 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", &intel_g33_driver },
1666 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", &intel_g33_driver },
1667 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", &intel_g33_driver },
1668 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", &intel_g33_driver },
1669 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45", &intel_i965_driver },
1670 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake", &intel_i965_driver },
1671 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", &intel_i965_driver },
1672 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", &intel_i965_driver },
1673 { PCI_DEVICE_ID_INTEL_B43_IG, "B43", &intel_i965_driver },
1674 { PCI_DEVICE_ID_INTEL_G41_IG, "G41", &intel_i965_driver },
1675 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1676 "HD Graphics", &intel_i965_driver },
1677 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1678 "HD Graphics", &intel_i965_driver },
1679 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
1680 "Sandybridge", &intel_gen6_driver },
1681 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
1682 "Sandybridge", &intel_gen6_driver },
1683 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
1684 "Sandybridge", &intel_gen6_driver },
1685 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
1686 "Sandybridge", &intel_gen6_driver },
1687 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
1688 "Sandybridge", &intel_gen6_driver },
1689 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
1690 "Sandybridge", &intel_gen6_driver },
1691 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
1692 "Sandybridge", &intel_gen6_driver },
1693 { 0, NULL, NULL }
1694 };
1695
1696 static int find_gmch(u16 device)
1697 {
1698 struct pci_dev *gmch_device;
1699
1700 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1701 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1702 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1703 device, gmch_device);
1704 }
1705
1706 if (!gmch_device)
1707 return 0;
1708
1709 intel_private.pcidev = gmch_device;
1710 return 1;
1711 }
1712
1713 int intel_gmch_probe(struct pci_dev *pdev,
1714 struct agp_bridge_data *bridge)
1715 {
1716 int i, mask;
1717 bridge->driver = NULL;
1718
1719 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1720 if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1721 bridge->driver =
1722 intel_gtt_chipsets[i].gmch_driver;
1723 break;
1724 }
1725 }
1726
1727 if (!bridge->driver)
1728 return 0;
1729
1730 bridge->dev_private_data = &intel_private;
1731 bridge->dev = pdev;
1732
1733 intel_private.bridge_dev = pci_dev_get(pdev);
1734
1735 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1736
1737 if (bridge->driver->mask_memory == intel_gen6_mask_memory)
1738 mask = 40;
1739 else if (bridge->driver->mask_memory == intel_i965_mask_memory)
1740 mask = 36;
1741 else
1742 mask = 32;
1743
1744 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1745 dev_err(&intel_private.pcidev->dev,
1746 "set gfx device dma mask %d-bit failed!\n", mask);
1747 else
1748 pci_set_consistent_dma_mask(intel_private.pcidev,
1749 DMA_BIT_MASK(mask));
1750
1751 if (bridge->driver == &intel_810_driver)
1752 return 1;
1753
1754 intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
1755
1756 return 1;
1757 }
1758 EXPORT_SYMBOL(intel_gmch_probe);
1759
1760 void intel_gmch_remove(struct pci_dev *pdev)
1761 {
1762 if (intel_private.pcidev)
1763 pci_dev_put(intel_private.pcidev);
1764 if (intel_private.bridge_dev)
1765 pci_dev_put(intel_private.bridge_dev);
1766 }
1767 EXPORT_SYMBOL(intel_gmch_remove);
1768
1769 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1770 MODULE_LICENSE("GPL and additional rights");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree