drivers/serial/max3107.c

   1 /*
   2  *  max3107.c - spi uart protocol driver for Maxim 3107
   3  *  Based on max3100.c
   4  *      by Christian Pellegrin <chripell@evolware.org>
   5  *  and max3110.c
   6  *      by Feng Tang <feng.tang@intel.com>
   7  *
   8  *  Copyright (C) Aavamobile 2009
   9  *
  10  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  11  *
  12  *  This program is free software; you can redistribute it and/or modify
  13  *  it under the terms of the GNU General Public License as published by
  14  *  the Free Software Foundation; either version 2 of the License, or
  15  *  (at your option) any later version.
  16  *
  17  *  This program is distributed in the hope that it will be useful,
  18  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *  GNU General Public License for more details.
  21  *
  22  *  You should have received a copy of the GNU General Public License
  23  *  along with this program; if not, write to the Free Software
  24  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  25  *
  26  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  27  *
  28  */
  29
  30 #include <linux/delay.h>
  31 #include <linux/device.h>
  32 #include <linux/serial_core.h>
  33 #include <linux/serial.h>
  34 #include <linux/gpio.h>
  35 #include <linux/spi/spi.h>
  36 #include <linux/freezer.h>
  37 #include "max3107.h"
  38
  39 static const struct baud_table brg26_ext[] = {
  40         { 300,    MAX3107_BRG26_B300 },
  41         { 600,    MAX3107_BRG26_B600 },
  42         { 1200,   MAX3107_BRG26_B1200 },
  43         { 2400,   MAX3107_BRG26_B2400 },
  44         { 4800,   MAX3107_BRG26_B4800 },
  45         { 9600,   MAX3107_BRG26_B9600 },
  46         { 19200,  MAX3107_BRG26_B19200 },
  47         { 57600,  MAX3107_BRG26_B57600 },
  48         { 115200, MAX3107_BRG26_B115200 },
  49         { 230400, MAX3107_BRG26_B230400 },
  50         { 460800, MAX3107_BRG26_B460800 },
  51         { 921600, MAX3107_BRG26_B921600 },
  52         { 0, 0 }
  53 };
  54
  55 static const struct baud_table brg13_int[] = {
  56         { 300,    MAX3107_BRG13_IB300 },
  57         { 600,    MAX3107_BRG13_IB600 },
  58         { 1200,   MAX3107_BRG13_IB1200 },
  59         { 2400,   MAX3107_BRG13_IB2400 },
  60         { 4800,   MAX3107_BRG13_IB4800 },
  61         { 9600,   MAX3107_BRG13_IB9600 },
  62         { 19200,  MAX3107_BRG13_IB19200 },
  63         { 57600,  MAX3107_BRG13_IB57600 },
  64         { 115200, MAX3107_BRG13_IB115200 },
  65         { 230400, MAX3107_BRG13_IB230400 },
  66         { 460800, MAX3107_BRG13_IB460800 },
  67         { 921600, MAX3107_BRG13_IB921600 },
  68         { 0, 0 }
  69 };
  70
  71 static u32 get_new_brg(int baud, struct max3107_port *s)
  72 {
  73         int i;
  74         const struct baud_table *baud_tbl = s->baud_tbl;
  75
  76         for (i = 0; i < 13; i++) {
  77                 if (baud == baud_tbl[i].baud)
  78                         return baud_tbl[i].new_brg;
  79         }
  80
  81         return 0;
  82 }
  83
  84 /* Perform SPI transfer for write/read of device register(s) */
  85 int max3107_rw(struct max3107_port *s, u8 *tx, u8 *rx, int len)
  86 {
  87         struct spi_message spi_msg;
  88         struct spi_transfer spi_xfer;
  89
  90         /* Initialize SPI ,message */
  91         spi_message_init(&spi_msg);
  92
  93         /* Initialize SPI transfer */
  94         memset(&spi_xfer, 0, sizeof spi_xfer);
  95         spi_xfer.len = len;
  96         spi_xfer.tx_buf = tx;
  97         spi_xfer.rx_buf = rx;
  98         spi_xfer.speed_hz = MAX3107_SPI_SPEED;
  99
 100         /* Add SPI transfer to SPI message */
 101         spi_message_add_tail(&spi_xfer, &spi_msg);
 102
 103 #ifdef DBG_TRACE_SPI_DATA
 104         {
 105                 int i;
 106                 pr_info("tx len %d:\n", spi_xfer.len);
 107                 for (i = 0 ; i < spi_xfer.len && i < 32 ; i++)
 108                         pr_info(" %x", ((u8 *)spi_xfer.tx_buf)[i]);
 109                 pr_info("\n");
 110         }
 111 #endif
 112
 113         /* Perform synchronous SPI transfer */
 114         if (spi_sync(s->spi, &spi_msg)) {
 115                 dev_err(&s->spi->dev, "spi_sync failure\n");
 116                 return -EIO;
 117         }
 118
 119 #ifdef DBG_TRACE_SPI_DATA
 120         if (spi_xfer.rx_buf) {
 121                 int i;
 122                 pr_info("rx len %d:\n", spi_xfer.len);
 123                 for (i = 0 ; i < spi_xfer.len && i < 32 ; i++)
 124                         pr_info(" %x", ((u8 *)spi_xfer.rx_buf)[i]);
 125                 pr_info("\n");
 126         }
 127 #endif
 128         return 0;
 129 }
 130 EXPORT_SYMBOL_GPL(max3107_rw);
 131
 132 /* Puts received data to circular buffer */
 133 static void put_data_to_circ_buf(struct max3107_port *s, unsigned char *data,
 134                                         int len)
 135 {
 136         struct uart_port *port = &s->port;
 137         struct tty_struct *tty;
 138
 139         if (!port->state)
 140                 return;
 141
 142         tty = port->state->port.tty;
 143         if (!tty)
 144                 return;
 145
 146         /* Insert received data */
 147         tty_insert_flip_string(tty, data, len);
 148         /* Update RX counter */
 149         port->icount.rx += len;
 150 }
 151
 152 /* Handle data receiving */
 153 static void max3107_handlerx(struct max3107_port *s, u16 rxlvl)
 154 {
 155         int i;
 156         int j;
 157         int len;                                /* SPI transfer buffer length */
 158         u16 *buf;
 159         u8 *valid_str;
 160
 161         if (!s->rx_enabled)
 162                 /* RX is disabled */
 163                 return;
 164
 165         if (rxlvl == 0) {
 166                 /* RX fifo is empty */
 167                 return;
 168         } else if (rxlvl >= MAX3107_RX_FIFO_SIZE) {
 169                 dev_warn(&s->spi->dev, "Possible RX FIFO overrun %d\n", rxlvl);
 170                 /* Ensure sanity of RX level */
 171                 rxlvl = MAX3107_RX_FIFO_SIZE;
 172         }
 173         if ((s->rxbuf == 0) || (s->rxstr == 0)) {
 174                 dev_warn(&s->spi->dev, "Rx buffer/str isn't ready\n");
 175                 return;
 176         }
 177         buf = s->rxbuf;
 178         valid_str = s->rxstr;
 179         while (rxlvl) {
 180                 pr_debug("rxlvl %d\n", rxlvl);
 181                 /* Clear buffer */
 182                 memset(buf, 0, sizeof(u16) * (MAX3107_RX_FIFO_SIZE + 2));
 183                 len = 0;
 184                 if (s->irqen_reg & MAX3107_IRQ_RXFIFO_BIT) {
 185                         /* First disable RX FIFO interrupt */
 186                         pr_debug("Disabling RX INT\n");
 187                         buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
 188                         s->irqen_reg &= ~MAX3107_IRQ_RXFIFO_BIT;
 189                         buf[0] |= s->irqen_reg;
 190                         len++;
 191                 }
 192                 /* Just increase the length by amount of words in FIFO since
 193                  * buffer was zeroed and SPI transfer of 0x0000 means reading
 194                  * from RX FIFO
 195                  */
 196                 len += rxlvl;
 197                 /* Append RX level query */
 198                 buf[len] = MAX3107_RXFIFOLVL_REG;
 199                 len++;
 200
 201                 /* Perform the SPI transfer */
 202                 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, len * 2)) {
 203                         dev_err(&s->spi->dev, "SPI transfer for RX h failed\n");
 204                         return;
 205                 }
 206
 207                 /* Skip RX FIFO interrupt disabling word if it was added */
 208                 j = ((len - 1) - rxlvl);
 209                 /* Read received words */
 210                 for (i = 0; i < rxlvl; i++, j++)
 211                         valid_str[i] = (u8)buf[j];
 212                 put_data_to_circ_buf(s, valid_str, rxlvl);
 213                 /* Get new RX level */
 214                 rxlvl = (buf[len - 1] & MAX3107_SPI_RX_DATA_MASK);
 215         }
 216
 217         if (s->rx_enabled) {
 218                 /* RX still enabled, re-enable RX FIFO interrupt */
 219                 pr_debug("Enabling RX INT\n");
 220                 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
 221                 s->irqen_reg |= MAX3107_IRQ_RXFIFO_BIT;
 222                 buf[0] |= s->irqen_reg;
 223                 if (max3107_rw(s, (u8 *)buf, NULL, 2))
 224                         dev_err(&s->spi->dev, "RX FIFO INT enabling failed\n");
 225         }
 226
 227         /* Push the received data to receivers */
 228         if (s->port.state->port.tty)
 229                 tty_flip_buffer_push(s->port.state->port.tty);
 230 }
 231
 232
 233 /* Handle data sending */
 234 static void max3107_handletx(struct max3107_port *s)
 235 {
 236         struct circ_buf *xmit = &s->port.state->xmit;
 237         int i;
 238         unsigned long flags;
 239         int len;                                /* SPI transfer buffer length */
 240         u16 *buf;
 241
 242         if (!s->tx_fifo_empty)
 243                 /* Don't send more data before previous data is sent */
 244                 return;
 245
 246         if (uart_circ_empty(xmit) || uart_tx_stopped(&s->port))
 247                 /* No data to send or TX is stopped */
 248                 return;
 249
 250         if (!s->txbuf) {
 251                 dev_warn(&s->spi->dev, "Txbuf isn't ready\n");
 252                 return;
 253         }
 254         buf = s->txbuf;
 255         /* Get length of data pending in circular buffer */
 256         len = uart_circ_chars_pending(xmit);
 257         if (len) {
 258                 /* Limit to size of TX FIFO */
 259                 if (len > MAX3107_TX_FIFO_SIZE)
 260                         len = MAX3107_TX_FIFO_SIZE;
 261
 262                 pr_debug("txlen %d\n", len);
 263
 264                 /* Update TX counter */
 265                 s->port.icount.tx += len;
 266
 267                 /* TX FIFO will no longer be empty */
 268                 s->tx_fifo_empty = 0;
 269
 270                 i = 0;
 271                 if (s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT) {
 272                         /* First disable TX empty interrupt */
 273                         pr_debug("Disabling TE INT\n");
 274                         buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
 275                         s->irqen_reg &= ~MAX3107_IRQ_TXEMPTY_BIT;
 276                         buf[i] |= s->irqen_reg;
 277                         i++;
 278                         len++;
 279                 }
 280                 /* Add data to send */
 281                 spin_lock_irqsave(&s->port.lock, flags);
 282                 for ( ; i < len ; i++) {
 283                         buf[i] = (MAX3107_WRITE_BIT | MAX3107_THR_REG);
 284                         buf[i] |= ((u16)xmit->buf[xmit->tail] &
 285                                                 MAX3107_SPI_TX_DATA_MASK);
 286                         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 287                 }
 288                 spin_unlock_irqrestore(&s->port.lock, flags);
 289                 if (!(s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT)) {
 290                         /* Enable TX empty interrupt */
 291                         pr_debug("Enabling TE INT\n");
 292                         buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
 293                         s->irqen_reg |= MAX3107_IRQ_TXEMPTY_BIT;
 294                         buf[i] |= s->irqen_reg;
 295                         i++;
 296                         len++;
 297                 }
 298                 if (!s->tx_enabled) {
 299                         /* Enable TX */
 300                         pr_debug("Enable TX\n");
 301                         buf[i] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
 302                         spin_lock_irqsave(&s->data_lock, flags);
 303                         s->mode1_reg &= ~MAX3107_MODE1_TXDIS_BIT;
 304                         buf[i] |= s->mode1_reg;
 305                         spin_unlock_irqrestore(&s->data_lock, flags);
 306                         s->tx_enabled = 1;
 307                         i++;
 308                         len++;
 309                 }
 310
 311                 /* Perform the SPI transfer */
 312                 if (max3107_rw(s, (u8 *)buf, NULL, len*2)) {
 313                         dev_err(&s->spi->dev,
 314                                 "SPI transfer TX handling failed\n");
 315                         return;
 316                 }
 317         }
 318
 319         /* Indicate wake up if circular buffer is getting low on data */
 320         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 321                 uart_write_wakeup(&s->port);
 322
 323 }
 324
 325 /* Handle interrupts
 326  * Also reads and returns current RX FIFO level
 327  */
 328 static u16 handle_interrupt(struct max3107_port *s)
 329 {
 330         u16 buf[4];     /* Buffer for SPI transfers */
 331         u8 irq_status;
 332         u16 rx_level;
 333         unsigned long flags;
 334
 335         /* Read IRQ status register */
 336         buf[0] = MAX3107_IRQSTS_REG;
 337         /* Read status IRQ status register */
 338         buf[1] = MAX3107_STS_IRQSTS_REG;
 339         /* Read LSR IRQ status register */
 340         buf[2] = MAX3107_LSR_IRQSTS_REG;
 341         /* Query RX level */
 342         buf[3] = MAX3107_RXFIFOLVL_REG;
 343
 344         if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 8)) {
 345                 dev_err(&s->spi->dev,
 346                         "SPI transfer for INTR handling failed\n");
 347                 return 0;
 348         }
 349
 350         irq_status = (u8)buf[0];
 351         pr_debug("IRQSTS %x\n", irq_status);
 352         rx_level = (buf[3] & MAX3107_SPI_RX_DATA_MASK);
 353
 354         if (irq_status & MAX3107_IRQ_LSR_BIT) {
 355                 /* LSR interrupt */
 356                 if (buf[2] & MAX3107_LSR_RXTO_BIT)
 357                         /* RX timeout interrupt,
 358                          * handled by normal RX handling
 359                          */
 360                         pr_debug("RX TO INT\n");
 361         }
 362
 363         if (irq_status & MAX3107_IRQ_TXEMPTY_BIT) {
 364                 /* Tx empty interrupt,
 365                  * disable TX and set tx_fifo_empty flag
 366                  */
 367                 pr_debug("TE INT, disabling TX\n");
 368                 buf[0] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
 369                 spin_lock_irqsave(&s->data_lock, flags);
 370                 s->mode1_reg |= MAX3107_MODE1_TXDIS_BIT;
 371                 buf[0] |= s->mode1_reg;
 372                 spin_unlock_irqrestore(&s->data_lock, flags);
 373                 if (max3107_rw(s, (u8 *)buf, NULL, 2))
 374                         dev_err(&s->spi->dev, "SPI transfer TX dis failed\n");
 375                 s->tx_enabled = 0;
 376                 s->tx_fifo_empty = 1;
 377         }
 378
 379         if (irq_status & MAX3107_IRQ_RXFIFO_BIT)
 380                 /* RX FIFO interrupt,
 381                  * handled by normal RX handling
 382                  */
 383                 pr_debug("RFIFO INT\n");
 384
 385         /* Return RX level */
 386         return rx_level;
 387 }
 388
 389 /* Trigger work thread*/
 390 static void max3107_dowork(struct max3107_port *s)
 391 {
 392         if (!work_pending(&s->work) && !freezing(current) && !s->suspended)
 393                 queue_work(s->workqueue, &s->work);
 394         else
 395                 dev_warn(&s->spi->dev, "interrup isn't serviced normally!\n");
 396 }
 397
 398 /* Work thread */
 399 static void max3107_work(struct work_struct *w)
 400 {
 401         struct max3107_port *s = container_of(w, struct max3107_port, work);
 402         u16 rxlvl = 0;
 403         int len;        /* SPI transfer buffer length */
 404         u16 buf[5];     /* Buffer for SPI transfers */
 405         unsigned long flags;
 406
 407         /* Start by reading current RX FIFO level */
 408         buf[0] = MAX3107_RXFIFOLVL_REG;
 409         if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
 410                 dev_err(&s->spi->dev, "SPI transfer RX lev failed\n");
 411                 rxlvl = 0;
 412         } else {
 413                 rxlvl = (buf[0] & MAX3107_SPI_RX_DATA_MASK);
 414         }
 415
 416         do {
 417                 pr_debug("rxlvl %d\n", rxlvl);
 418
 419                 /* Handle RX */
 420                 max3107_handlerx(s, rxlvl);
 421                 rxlvl = 0;
 422
 423                 if (s->handle_irq) {
 424                         /* Handle pending interrupts
 425                          * We also get new RX FIFO level since new data may
 426                          * have been received while pushing received data to
 427                          * receivers
 428                          */
 429                         s->handle_irq = 0;
 430                         rxlvl = handle_interrupt(s);
 431                 }
 432
 433                 /* Handle TX */
 434                 max3107_handletx(s);
 435
 436                 /* Handle configuration changes */
 437                 len = 0;
 438                 spin_lock_irqsave(&s->data_lock, flags);
 439                 if (s->mode1_commit) {
 440                         pr_debug("mode1_commit\n");
 441                         buf[len] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
 442                         buf[len++] |= s->mode1_reg;
 443                         s->mode1_commit = 0;
 444                 }
 445                 if (s->lcr_commit) {
 446                         pr_debug("lcr_commit\n");
 447                         buf[len] = (MAX3107_WRITE_BIT | MAX3107_LCR_REG);
 448                         buf[len++] |= s->lcr_reg;
 449                         s->lcr_commit = 0;
 450                 }
 451                 if (s->brg_commit) {
 452                         pr_debug("brg_commit\n");
 453                         buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVMSB_REG);
 454                         buf[len++] |= ((s->brg_cfg >> 16) &
 455                                                 MAX3107_SPI_TX_DATA_MASK);
 456                         buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVLSB_REG);
 457                         buf[len++] |= ((s->brg_cfg >> 8) &
 458                                                 MAX3107_SPI_TX_DATA_MASK);
 459                         buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGCFG_REG);
 460                         buf[len++] |= ((s->brg_cfg) & 0xff);
 461                         s->brg_commit = 0;
 462                 }
 463                 spin_unlock_irqrestore(&s->data_lock, flags);
 464
 465                 if (len > 0) {
 466                         if (max3107_rw(s, (u8 *)buf, NULL, len * 2))
 467                                 dev_err(&s->spi->dev,
 468                                         "SPI transfer config failed\n");
 469                 }
 470
 471                 /* Reloop if interrupt handling indicated data in RX FIFO */
 472         } while (rxlvl);
 473
 474 }
 475
 476 /* Set sleep mode */
 477 static void max3107_set_sleep(struct max3107_port *s, int mode)
 478 {
 479         u16 buf[1];     /* Buffer for SPI transfer */
 480         unsigned long flags;
 481         pr_debug("enter, mode %d\n", mode);
 482
 483         buf[0] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
 484         spin_lock_irqsave(&s->data_lock, flags);
 485         switch (mode) {
 486         case MAX3107_DISABLE_FORCED_SLEEP:
 487                         s->mode1_reg &= ~MAX3107_MODE1_FORCESLEEP_BIT;
 488                         break;
 489         case MAX3107_ENABLE_FORCED_SLEEP:
 490                         s->mode1_reg |= MAX3107_MODE1_FORCESLEEP_BIT;
 491                         break;
 492         case MAX3107_DISABLE_AUTOSLEEP:
 493                         s->mode1_reg &= ~MAX3107_MODE1_AUTOSLEEP_BIT;
 494                         break;
 495         case MAX3107_ENABLE_AUTOSLEEP:
 496                         s->mode1_reg |= MAX3107_MODE1_AUTOSLEEP_BIT;
 497                         break;
 498         default:
 499                 spin_unlock_irqrestore(&s->data_lock, flags);
 500                 dev_warn(&s->spi->dev, "invalid sleep mode\n");
 501                 return;
 502         }
 503         buf[0] |= s->mode1_reg;
 504         spin_unlock_irqrestore(&s->data_lock, flags);
 505
 506         if (max3107_rw(s, (u8 *)buf, NULL, 2))
 507                 dev_err(&s->spi->dev, "SPI transfer sleep mode failed\n");
 508
 509         if (mode == MAX3107_DISABLE_AUTOSLEEP ||
 510                         mode == MAX3107_DISABLE_FORCED_SLEEP)
 511                 msleep(MAX3107_WAKEUP_DELAY);
 512 }
 513
 514 /* Perform full register initialization */
 515 static void max3107_register_init(struct max3107_port *s)
 516 {
 517         u16 buf[11];    /* Buffer for SPI transfers */
 518
 519         /* 1. Configure baud rate, 9600 as default */
 520         s->baud = 9600;
 521         /* the below is default*/
 522         if (s->ext_clk) {
 523                 s->brg_cfg = MAX3107_BRG26_B9600;
 524                 s->baud_tbl = (struct baud_table *)brg26_ext;
 525         } else {
 526                 s->brg_cfg = MAX3107_BRG13_IB9600;
 527                 s->baud_tbl = (struct baud_table *)brg13_int;
 528         }
 529
 530         if (s->pdata->init)
 531                 s->pdata->init(s);
 532
 533         buf[0] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVMSB_REG)
 534                 | ((s->brg_cfg >> 16) & MAX3107_SPI_TX_DATA_MASK);
 535         buf[1] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVLSB_REG)
 536                 | ((s->brg_cfg >> 8) & MAX3107_SPI_TX_DATA_MASK);
 537         buf[2] = (MAX3107_WRITE_BIT | MAX3107_BRGCFG_REG)
 538                 | ((s->brg_cfg) & 0xff);
 539
 540         /* 2. Configure LCR register, 8N1 mode by default */
 541         s->lcr_reg = MAX3107_LCR_WORD_LEN_8;
 542         buf[3] = (MAX3107_WRITE_BIT | MAX3107_LCR_REG)
 543                 | s->lcr_reg;
 544
 545         /* 3. Configure MODE 1 register */
 546         s->mode1_reg = 0;
 547         /* Enable IRQ pin */
 548         s->mode1_reg |= MAX3107_MODE1_IRQSEL_BIT;
 549         /* Disable TX */
 550         s->mode1_reg |= MAX3107_MODE1_TXDIS_BIT;
 551         s->tx_enabled = 0;
 552         /* RX is enabled */
 553         s->rx_enabled = 1;
 554         buf[4] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG)
 555                 | s->mode1_reg;
 556
 557         /* 4. Configure MODE 2 register */
 558         buf[5] = (MAX3107_WRITE_BIT | MAX3107_MODE2_REG);
 559         if (s->loopback) {
 560                 /* Enable loopback */
 561                 buf[5] |= MAX3107_MODE2_LOOPBACK_BIT;
 562         }
 563         /* Reset FIFOs */
 564         buf[5] |= MAX3107_MODE2_FIFORST_BIT;
 565         s->tx_fifo_empty = 1;
 566
 567         /* 5. Configure FIFO trigger level register */
 568         buf[6] = (MAX3107_WRITE_BIT | MAX3107_FIFOTRIGLVL_REG);
 569         /* RX FIFO trigger for 16 words, TX FIFO trigger not used */
 570         buf[6] |= (MAX3107_FIFOTRIGLVL_RX(16) | MAX3107_FIFOTRIGLVL_TX(0));
 571
 572         /* 6. Configure flow control levels */
 573         buf[7] = (MAX3107_WRITE_BIT | MAX3107_FLOWLVL_REG);
 574         /* Flow control halt level 96, resume level 48 */
 575         buf[7] |= (MAX3107_FLOWLVL_RES(48) | MAX3107_FLOWLVL_HALT(96));
 576
 577         /* 7. Configure flow control */
 578         buf[8] = (MAX3107_WRITE_BIT | MAX3107_FLOWCTRL_REG);
 579         /* Enable auto CTS and auto RTS flow control */
 580         buf[8] |= (MAX3107_FLOWCTRL_AUTOCTS_BIT | MAX3107_FLOWCTRL_AUTORTS_BIT);
 581
 582         /* 8. Configure RX timeout register */
 583         buf[9] = (MAX3107_WRITE_BIT | MAX3107_RXTO_REG);
 584         /* Timeout after 48 character intervals */
 585         buf[9] |= 0x0030;
 586
 587         /* 9. Configure LSR interrupt enable register */
 588         buf[10] = (MAX3107_WRITE_BIT | MAX3107_LSR_IRQEN_REG);
 589         /* Enable RX timeout interrupt */
 590         buf[10] |= MAX3107_LSR_RXTO_BIT;
 591
 592         /* Perform SPI transfer */
 593         if (max3107_rw(s, (u8 *)buf, NULL, 22))
 594                 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
 595
 596         /* 10. Clear IRQ status register by reading it */
 597         buf[0] = MAX3107_IRQSTS_REG;
 598
 599         /* 11. Configure interrupt enable register */
 600         /* Enable LSR interrupt */
 601         s->irqen_reg = MAX3107_IRQ_LSR_BIT;
 602         /* Enable RX FIFO interrupt */
 603         s->irqen_reg |= MAX3107_IRQ_RXFIFO_BIT;
 604         buf[1] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG)
 605                 | s->irqen_reg;
 606
 607         /* 12. Clear FIFO reset that was set in step 6 */
 608         buf[2] = (MAX3107_WRITE_BIT | MAX3107_MODE2_REG);
 609         if (s->loopback) {
 610                 /* Keep loopback enabled */
 611                 buf[2] |= MAX3107_MODE2_LOOPBACK_BIT;
 612         }
 613
 614         /* Perform SPI transfer */
 615         if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 6))
 616                 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
 617
 618 }
 619
 620 /* IRQ handler */
 621 static irqreturn_t max3107_irq(int irqno, void *dev_id)
 622 {
 623         struct max3107_port *s = dev_id;
 624
 625         if (irqno != s->spi->irq) {
 626                 /* Unexpected IRQ */
 627                 return IRQ_NONE;
 628         }
 629
 630         /* Indicate irq */
 631         s->handle_irq = 1;
 632
 633         /* Trigger work thread */
 634         max3107_dowork(s);
 635
 636         return IRQ_HANDLED;
 637 }
 638
 639 /* HW suspension function
 640  *
 641  * Currently autosleep is used to decrease current consumption, alternative
 642  * approach would be to set the chip to reset mode if UART is not being
 643  * used but that would mess the GPIOs
 644  *
 645  */
 646 void max3107_hw_susp(struct max3107_port *s, int suspend)
 647 {
 648         pr_debug("enter, suspend %d\n", suspend);
 649
 650         if (suspend) {
 651                 /* Suspend requested,
 652                  * enable autosleep to decrease current consumption
 653                  */
 654                 s->suspended = 1;
 655                 max3107_set_sleep(s, MAX3107_ENABLE_AUTOSLEEP);
 656         } else {
 657                 /* Resume requested,
 658                  * disable autosleep
 659                  */
 660                 s->suspended = 0;
 661                 max3107_set_sleep(s, MAX3107_DISABLE_AUTOSLEEP);
 662         }
 663 }
 664 EXPORT_SYMBOL_GPL(max3107_hw_susp);
 665
 666 /* Modem status IRQ enabling */
 667 static void max3107_enable_ms(struct uart_port *port)
 668 {
 669         /* Modem status not supported */
 670 }
 671
 672 /* Data send function */
 673 static void max3107_start_tx(struct uart_port *port)
 674 {
 675         struct max3107_port *s = container_of(port, struct max3107_port, port);
 676
 677         /* Trigger work thread for sending data */
 678         max3107_dowork(s);
 679 }
 680
 681 /* Function for checking that there is no pending transfers */
 682 static unsigned int max3107_tx_empty(struct uart_port *port)
 683 {
 684         struct max3107_port *s = container_of(port, struct max3107_port, port);
 685
 686         pr_debug("returning %d\n",
 687                   (s->tx_fifo_empty && uart_circ_empty(&s->port.state->xmit)));
 688         return s->tx_fifo_empty && uart_circ_empty(&s->port.state->xmit);
 689 }
 690
 691 /* Function for stopping RX */
 692 static void max3107_stop_rx(struct uart_port *port)
 693 {
 694         struct max3107_port *s = container_of(port, struct max3107_port, port);
 695         unsigned long flags;
 696
 697         /* Set RX disabled in MODE 1 register */
 698         spin_lock_irqsave(&s->data_lock, flags);
 699         s->mode1_reg |= MAX3107_MODE1_RXDIS_BIT;
 700         s->mode1_commit = 1;
 701         spin_unlock_irqrestore(&s->data_lock, flags);
 702         /* Set RX disabled */
 703         s->rx_enabled = 0;
 704         /* Trigger work thread for doing the actual configuration change */
 705         max3107_dowork(s);
 706 }
 707
 708 /* Function for returning control pin states */
 709 static unsigned int max3107_get_mctrl(struct uart_port *port)
 710 {
 711         /* DCD and DSR are not wired and CTS/RTS is handled automatically
 712          * so just indicate DSR and CAR asserted
 713          */
 714         return TIOCM_DSR | TIOCM_CAR;
 715 }
 716
 717 /* Function for setting control pin states */
 718 static void max3107_set_mctrl(struct uart_port *port, unsigned int mctrl)
 719 {
 720         /* DCD and DSR are not wired and CTS/RTS is hadnled automatically
 721          * so do nothing
 722          */
 723 }
 724
 725 /* Function for configuring UART parameters */
 726 static void max3107_set_termios(struct uart_port *port,
 727                                 struct ktermios *termios,
 728                                 struct ktermios *old)
 729 {
 730         struct max3107_port *s = container_of(port, struct max3107_port, port);
 731         struct tty_struct *tty;
 732         int baud;
 733         u16 new_lcr = 0;
 734         u32 new_brg = 0;
 735         unsigned long flags;
 736
 737         if (!port->state)
 738                 return;
 739
 740         tty = port->state->port.tty;
 741         if (!tty)
 742                 return;
 743
 744         /* Get new LCR register values */
 745         /* Word size */
 746         if ((termios->c_cflag & CSIZE) == CS7)
 747                 new_lcr |= MAX3107_LCR_WORD_LEN_7;
 748         else
 749                 new_lcr |= MAX3107_LCR_WORD_LEN_8;
 750
 751         /* Parity */
 752         if (termios->c_cflag & PARENB) {
 753                 new_lcr |= MAX3107_LCR_PARITY_BIT;
 754                 if (!(termios->c_cflag & PARODD))
 755                         new_lcr |= MAX3107_LCR_EVENPARITY_BIT;
 756         }
 757
 758         /* Stop bits */
 759         if (termios->c_cflag & CSTOPB) {
 760                 /* 2 stop bits */
 761                 new_lcr |= MAX3107_LCR_STOPLEN_BIT;
 762         }
 763
 764         /* Mask termios capabilities we don't support */
 765         termios->c_cflag &= ~CMSPAR;
 766
 767         /* Set status ignore mask */
 768         s->port.ignore_status_mask = 0;
 769         if (termios->c_iflag & IGNPAR)
 770                 s->port.ignore_status_mask |= MAX3107_ALL_ERRORS;
 771
 772         /* Set low latency to immediately handle pushed data */
 773         s->port.state->port.tty->low_latency = 1;
 774
 775         /* Get new baud rate generator configuration */
 776         baud = tty_get_baud_rate(tty);
 777
 778         spin_lock_irqsave(&s->data_lock, flags);
 779         new_brg = get_new_brg(baud, s);
 780         /* if can't find the corrent config, use previous */
 781         if (!new_brg) {
 782                 baud = s->baud;
 783                 new_brg = s->brg_cfg;
 784         }
 785         spin_unlock_irqrestore(&s->data_lock, flags);
 786         tty_termios_encode_baud_rate(termios, baud, baud);
 787         s->baud = baud;
 788
 789         /* Update timeout according to new baud rate */
 790         uart_update_timeout(port, termios->c_cflag, baud);
 791
 792         spin_lock_irqsave(&s->data_lock, flags);
 793         if (s->lcr_reg != new_lcr) {
 794                 s->lcr_reg = new_lcr;
 795                 s->lcr_commit = 1;
 796         }
 797         if (s->brg_cfg != new_brg) {
 798                 s->brg_cfg = new_brg;
 799                 s->brg_commit = 1;
 800         }
 801         spin_unlock_irqrestore(&s->data_lock, flags);
 802
 803         /* Trigger work thread for doing the actual configuration change */
 804         max3107_dowork(s);
 805 }
 806
 807 /* Port shutdown function */
 808 static void max3107_shutdown(struct uart_port *port)
 809 {
 810         struct max3107_port *s = container_of(port, struct max3107_port, port);
 811
 812         if (s->suspended && s->pdata->hw_suspend)
 813                 s->pdata->hw_suspend(s, 0);
 814
 815         /* Free the interrupt */
 816         free_irq(s->spi->irq, s);
 817
 818         if (s->workqueue) {
 819                 /* Flush and destroy work queue */
 820                 flush_workqueue(s->workqueue);
 821                 destroy_workqueue(s->workqueue);
 822                 s->workqueue = NULL;
 823         }
 824
 825         /* Suspend HW */
 826         if (s->pdata->hw_suspend)
 827                 s->pdata->hw_suspend(s, 1);
 828 }
 829
 830 /* Port startup function */
 831 static int max3107_startup(struct uart_port *port)
 832 {
 833         struct max3107_port *s = container_of(port, struct max3107_port, port);
 834
 835         /* Initialize work queue */
 836         s->workqueue = create_freezeable_workqueue("max3107");
 837         if (!s->workqueue) {
 838                 dev_err(&s->spi->dev, "Workqueue creation failed\n");
 839                 return -EBUSY;
 840         }
 841         INIT_WORK(&s->work, max3107_work);
 842
 843         /* Setup IRQ */
 844         if (request_irq(s->spi->irq, max3107_irq, IRQF_TRIGGER_FALLING,
 845                         "max3107", s)) {
 846                 dev_err(&s->spi->dev, "IRQ reguest failed\n");
 847                 destroy_workqueue(s->workqueue);
 848                 s->workqueue = NULL;
 849                 return -EBUSY;
 850         }
 851
 852         /* Resume HW */
 853         if (s->pdata->hw_suspend)
 854                 s->pdata->hw_suspend(s, 0);
 855
 856         /* Init registers */
 857         max3107_register_init(s);
 858
 859         return 0;
 860 }
 861
 862 /* Port type function */
 863 static const char *max3107_type(struct uart_port *port)
 864 {
 865         struct max3107_port *s = container_of(port, struct max3107_port, port);
 866         return s->spi->modalias;
 867 }
 868
 869 /* Port release function */
 870 static void max3107_release_port(struct uart_port *port)
 871 {
 872         /* Do nothing */
 873 }
 874
 875 /* Port request function */
 876 static int max3107_request_port(struct uart_port *port)
 877 {
 878         /* Do nothing */
 879         return 0;
 880 }
 881
 882 /* Port config function */
 883 static void max3107_config_port(struct uart_port *port, int flags)
 884 {
 885         struct max3107_port *s = container_of(port, struct max3107_port, port);
 886         s->port.type = PORT_MAX3107;
 887 }
 888
 889 /* Port verify function */
 890 static int max3107_verify_port(struct uart_port *port,
 891                                 struct serial_struct *ser)
 892 {
 893         if (ser->type == PORT_UNKNOWN || ser->type == PORT_MAX3107)
 894                 return 0;
 895
 896         return -EINVAL;
 897 }
 898
 899 /* Port stop TX function */
 900 static void max3107_stop_tx(struct uart_port *port)
 901 {
 902         /* Do nothing */
 903 }
 904
 905 /* Port break control function */
 906 static void max3107_break_ctl(struct uart_port *port, int break_state)
 907 {
 908         /* We don't support break control, do nothing */
 909 }
 910
 911
 912 /* Port functions */
 913 static struct uart_ops max3107_ops = {
 914         .tx_empty       = max3107_tx_empty,
 915         .set_mctrl      = max3107_set_mctrl,
 916         .get_mctrl      = max3107_get_mctrl,
 917         .stop_tx        = max3107_stop_tx,
 918         .start_tx       = max3107_start_tx,
 919         .stop_rx        = max3107_stop_rx,
 920         .enable_ms      = max3107_enable_ms,
 921         .break_ctl      = max3107_break_ctl,
 922         .startup        = max3107_startup,
 923         .shutdown       = max3107_shutdown,
 924         .set_termios    = max3107_set_termios,
 925         .type           = max3107_type,
 926         .release_port   = max3107_release_port,
 927         .request_port   = max3107_request_port,
 928         .config_port    = max3107_config_port,
 929         .verify_port    = max3107_verify_port,
 930 };
 931
 932 /* UART driver data */
 933 static struct uart_driver max3107_uart_driver = {
 934         .owner          = THIS_MODULE,
 935         .driver_name    = "ttyMAX",
 936         .dev_name       = "ttyMAX",
 937         .nr             = 1,
 938 };
 939
 940 static int driver_registered = 0;
 941
 942
 943
 944 /* 'Generic' platform data */
 945 static struct max3107_plat generic_plat_data = {
 946         .loopback               = 0,
 947         .ext_clk                = 1,
 948         .hw_suspend             = max3107_hw_susp,
 949         .polled_mode            = 0,
 950         .poll_time              = 0,
 951 };
 952
 953
 954 /*******************************************************************/
 955
 956 /**
 957  *      max3107_probe           -       SPI bus probe entry point
 958  *      @spi: the spi device
 959  *
 960  *      SPI wants us to probe this device and if appropriate claim it.
 961  *      Perform any platform specific requirements and then initialise
 962  *      the device.
 963  */
 964
 965 int max3107_probe(struct spi_device *spi, struct max3107_plat *pdata)
 966 {
 967         struct max3107_port *s;
 968         u16 buf[2];     /* Buffer for SPI transfers */
 969         int retval;
 970
 971         pr_info("enter max3107 probe\n");
 972
 973         /* Allocate port structure */
 974         s = kzalloc(sizeof(*s), GFP_KERNEL);
 975         if (!s) {
 976                 pr_err("Allocating port structure failed\n");
 977                 return -ENOMEM;
 978         }
 979
 980         s->pdata = pdata;
 981
 982         /* SPI Rx buffer
 983          * +2 for RX FIFO interrupt
 984          * disabling and RX level query
 985          */
 986         s->rxbuf = kzalloc(sizeof(u16) * (MAX3107_RX_FIFO_SIZE+2), GFP_KERNEL);
 987         if (!s->rxbuf) {
 988                 pr_err("Allocating RX buffer failed\n");
 989                 retval = -ENOMEM;
 990                 goto err_free4;
 991         }
 992         s->rxstr = kzalloc(sizeof(u8) * MAX3107_RX_FIFO_SIZE, GFP_KERNEL);
 993         if (!s->rxstr) {
 994                 pr_err("Allocating RX buffer failed\n");
 995                 retval = -ENOMEM;
 996                 goto err_free3;
 997         }
 998         /* SPI Tx buffer
 999          * SPI transfer buffer
1000          * +3 for TX FIFO empty
1001          * interrupt disabling and
1002          * enabling and TX enabling
1003          */
1004         s->txbuf = kzalloc(sizeof(u16) * MAX3107_TX_FIFO_SIZE + 3, GFP_KERNEL);
1005         if (!s->txbuf) {
1006                 pr_err("Allocating TX buffer failed\n");
1007                 retval = -ENOMEM;
1008                 goto err_free2;
1009         }
1010         /* Initialize shared data lock */
1011         spin_lock_init(&s->data_lock);
1012
1013         /* SPI intializations */
1014         dev_set_drvdata(&spi->dev, s);
1015         spi->mode = SPI_MODE_0;
1016         spi->dev.platform_data = pdata;
1017         spi->bits_per_word = 16;
1018         s->ext_clk = pdata->ext_clk;
1019         s->loopback = pdata->loopback;
1020         spi_setup(spi);
1021         s->spi = spi;
1022
1023         /* Check REV ID to ensure we are talking to what we expect */
1024         buf[0] = MAX3107_REVID_REG;
1025         if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
1026                 dev_err(&s->spi->dev, "SPI transfer for REVID read failed\n");
1027                 retval = -EIO;
1028                 goto err_free1;
1029         }
1030         if ((buf[0] & MAX3107_SPI_RX_DATA_MASK) != MAX3107_REVID1 &&
1031                 (buf[0] & MAX3107_SPI_RX_DATA_MASK) != MAX3107_REVID2) {
1032                 dev_err(&s->spi->dev, "REVID %x does not match\n",
1033                                 (buf[0] & MAX3107_SPI_RX_DATA_MASK));
1034                 retval = -ENODEV;
1035                 goto err_free1;
1036         }
1037
1038         /* Disable all interrupts */
1039         buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG | 0x0000);
1040         buf[0] |= 0x0000;
1041
1042         /* Configure clock source */
1043         buf[1] = (MAX3107_WRITE_BIT | MAX3107_CLKSRC_REG);
1044         if (s->ext_clk) {
1045                 /* External clock */
1046                 buf[1] |= MAX3107_CLKSRC_EXTCLK_BIT;
1047         }
1048
1049         /* PLL bypass ON */
1050         buf[1] |= MAX3107_CLKSRC_PLLBYP_BIT;
1051
1052         /* Perform SPI transfer */
1053         if (max3107_rw(s, (u8 *)buf, NULL, 4)) {
1054                 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
1055                 retval = -EIO;
1056                 goto err_free1;
1057         }
1058
1059         /* Register UART driver */
1060         if (!driver_registered) {
1061                 retval = uart_register_driver(&max3107_uart_driver);
1062                 if (retval) {
1063                         dev_err(&s->spi->dev, "Registering UART driver failed\n");
1064                         goto err_free1;
1065                 }
1066                 driver_registered = 1;
1067         }
1068
1069         /* Initialize UART port data */
1070         s->port.fifosize = 128;
1071         s->port.ops = &max3107_ops;
1072         s->port.line = 0;
1073         s->port.dev = &spi->dev;
1074         s->port.uartclk = 9600;
1075         s->port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
1076         s->port.irq = s->spi->irq;
1077         s->port.type = PORT_MAX3107;
1078
1079         /* Add UART port */
1080         retval = uart_add_one_port(&max3107_uart_driver, &s->port);
1081         if (retval < 0) {
1082                 dev_err(&s->spi->dev, "Adding UART port failed\n");
1083                 goto err_free1;
1084         }
1085
1086         if (pdata->configure) {
1087                 retval = pdata->configure(s);
1088                 if (retval < 0)
1089                         goto err_free1;
1090         }
1091
1092         /* Go to suspend mode */
1093         if (pdata->hw_suspend)
1094                 pdata->hw_suspend(s, 1);
1095
1096         return 0;
1097
1098 err_free1:
1099         kfree(s->txbuf);
1100 err_free2:
1101         kfree(s->rxstr);
1102 err_free3:
1103         kfree(s->rxbuf);
1104 err_free4:
1105         kfree(s);
1106         return retval;
1107 }
1108 EXPORT_SYMBOL_GPL(max3107_probe);
1109
1110 /* Driver remove function */
1111 int max3107_remove(struct spi_device *spi)
1112 {
1113         struct max3107_port *s = dev_get_drvdata(&spi->dev);
1114
1115         pr_info("enter max3107 remove\n");
1116
1117         /* Remove port */
1118         if (uart_remove_one_port(&max3107_uart_driver, &s->port))
1119                 dev_warn(&s->spi->dev, "Removing UART port failed\n");
1120
1121
1122         /* Free TxRx buffer */
1123         kfree(s->rxbuf);
1124         kfree(s->rxstr);
1125         kfree(s->txbuf);
1126
1127         /* Free port structure */
1128         kfree(s);
1129
1130         return 0;
1131 }
1132 EXPORT_SYMBOL_GPL(max3107_remove);
1133
1134 /* Driver suspend function */
1135 int max3107_suspend(struct spi_device *spi, pm_message_t state)
1136 {
1137 #ifdef CONFIG_PM
1138         struct max3107_port *s = dev_get_drvdata(&spi->dev);
1139
1140         pr_debug("enter suspend\n");
1141
1142         /* Suspend UART port */
1143         uart_suspend_port(&max3107_uart_driver, &s->port);
1144
1145         /* Go to suspend mode */
1146         if (s->pdata->hw_suspend)
1147                 s->pdata->hw_suspend(s, 1);
1148 #endif  /* CONFIG_PM */
1149         return 0;
1150 }
1151 EXPORT_SYMBOL_GPL(max3107_suspend);
1152
1153 /* Driver resume function */
1154 int max3107_resume(struct spi_device *spi)
1155 {
1156 #ifdef CONFIG_PM
1157         struct max3107_port *s = dev_get_drvdata(&spi->dev);
1158
1159         pr_debug("enter resume\n");
1160
1161         /* Resume from suspend */
1162         if (s->pdata->hw_suspend)
1163                 s->pdata->hw_suspend(s, 0);
1164
1165         /* Resume UART port */
1166         uart_resume_port(&max3107_uart_driver, &s->port);
1167 #endif  /* CONFIG_PM */
1168         return 0;
1169 }
1170 EXPORT_SYMBOL_GPL(max3107_resume);
1171
1172 static int max3107_probe_generic(struct spi_device *spi)
1173 {
1174         return max3107_probe(spi, &generic_plat_data);
1175 }
1176
1177 /* Spi driver data */
1178 static struct spi_driver max3107_driver = {
1179         .driver = {
1180                 .name           = "max3107",
1181                 .bus            = &spi_bus_type,
1182                 .owner          = THIS_MODULE,
1183         },
1184         .probe          = max3107_probe_generic,
1185         .remove         = __devexit_p(max3107_remove),
1186         .suspend        = max3107_suspend,
1187         .resume         = max3107_resume,
1188 };
1189
1190 /* Driver init function */
1191 static int __init max3107_init(void)
1192 {
1193         pr_info("enter max3107 init\n");
1194         return spi_register_driver(&max3107_driver);
1195 }
1196
1197 /* Driver exit function */
1198 static void __exit max3107_exit(void)
1199 {
1200         pr_info("enter max3107 exit\n");
1201         /* Unregister UART driver */
1202         if (driver_registered)
1203                 uart_unregister_driver(&max3107_uart_driver);
1204         spi_unregister_driver(&max3107_driver);
1205 }
1206
1207 module_init(max3107_init);
1208 module_exit(max3107_exit);
1209
1210 MODULE_DESCRIPTION("MAX3107 driver");
1211 MODULE_AUTHOR("Aavamobile");
1212 MODULE_ALIAS("max3107-spi");
1213 MODULE_LICENSE("GPL v2");