2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 #include <linux/pci.h>
17 #include <net/mac80211.h>
19 #include <brcm_hw_ids.h>
21 #include <chipcommon.h>
24 #include "phy/phy_hal.h"
27 #include "ucode_loader.h"
28 #include "mac80211_if.h"
31 #define TIMER_INTERVAL_WATCHDOG_BMAC 1000 /* watchdog timer, in unit of ms */
33 #define SYNTHPU_DLY_APHY_US 3700 /* a phy synthpu_dly time in us */
34 #define SYNTHPU_DLY_BPHY_US 1050 /* b/g phy synthpu_dly time in us, default */
35 #define SYNTHPU_DLY_NPHY_US 2048 /* n phy REV3 synthpu_dly time in us, default */
36 #define SYNTHPU_DLY_LPPHY_US 300 /* lpphy synthpu_dly time in us */
38 #define SYNTHPU_DLY_PHY_US_QT 100 /* QT synthpu_dly time in us */
40 #ifndef BMAC_DUP_TO_REMOVE
41 #define WLC_RM_WAIT_TX_SUSPEND 4 /* Wait Tx Suspend */
43 #define ANTCNT 10 /* vanilla M_MAX_ANTCNT value */
45 #endif /* BMAC_DUP_TO_REMOVE */
47 #define DMAREG(wlc_hw, direction, fifonum) \
48 ((direction == DMA_TX) ? \
49 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmaxmt) : \
50 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmarcv))
52 #define APHY_SLOT_TIME 9
53 #define BPHY_SLOT_TIME 20
56 * The following table lists the buffer memory allocated to xmt fifos in HW.
57 * the size is in units of 256bytes(one block), total size is HW dependent
58 * ucode has default fifo partition, sw can overwrite if necessary
60 * This is documented in twiki under the topic UcodeTxFifo. Please ensure
61 * the twiki is updated before making changes.
64 #define XMTFIFOTBL_STARTREV 20 /* Starting corerev for the fifo size table */
66 static u16 xmtfifo_sz
[][NFIFO
] = {
67 {20, 192, 192, 21, 17, 5}, /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
68 {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
69 {20, 192, 192, 21, 17, 5}, /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
70 {20, 192, 192, 21, 17, 5}, /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
71 {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
74 static void brcms_b_clkctl_clk(struct brcms_c_hw_info
*wlc
, uint mode
);
75 static void brcms_b_coreinit(struct brcms_c_info
*wlc
);
77 /* used by wlc_wakeucode_init() */
78 static void brcms_c_write_inits(struct brcms_c_hw_info
*wlc_hw
,
79 const struct d11init
*inits
);
80 static void brcms_ucode_write(struct brcms_c_hw_info
*wlc_hw
, const u32 ucode
[],
82 static void brcms_ucode_download(struct brcms_c_hw_info
*wlc
);
83 static void brcms_c_ucode_txant_set(struct brcms_c_hw_info
*wlc_hw
);
85 /* used by brcms_c_dpc() */
86 static bool brcms_b_dotxstatus(struct brcms_c_hw_info
*wlc
, tx_status_t
*txs
,
88 static bool brcms_b_txstatus(struct brcms_c_hw_info
*wlc
, bool bound
,
90 static bool brcms_b_recv(struct brcms_c_hw_info
*wlc_hw
, uint fifo
, bool bound
);
92 /* used by brcms_c_down() */
93 static void brcms_c_flushqueues(struct brcms_c_info
*wlc
);
95 static void brcms_c_write_mhf(struct brcms_c_hw_info
*wlc_hw
, u16
*mhfs
);
96 static void brcms_c_mctrl_reset(struct brcms_c_hw_info
*wlc_hw
);
97 static void brcms_b_corerev_fifofixup(struct brcms_c_hw_info
*wlc_hw
);
98 static bool brcms_b_tx_fifo_suspended(struct brcms_c_hw_info
*wlc_hw
,
100 static void brcms_b_tx_fifo_suspend(struct brcms_c_hw_info
*wlc_hw
,
102 static void brcms_b_tx_fifo_resume(struct brcms_c_hw_info
*wlc_hw
,
105 /* Low Level Prototypes */
106 static int brcms_b_bandtype(struct brcms_c_hw_info
*wlc_hw
);
107 static void brcms_b_info_init(struct brcms_c_hw_info
*wlc_hw
);
108 static void brcms_b_xtal(struct brcms_c_hw_info
*wlc_hw
, bool want
);
109 static u16
brcms_b_read_objmem(struct brcms_c_hw_info
*wlc_hw
, uint offset
,
111 static void brcms_b_write_objmem(struct brcms_c_hw_info
*wlc_hw
, uint offset
,
113 static void brcms_b_core_phy_clk(struct brcms_c_hw_info
*wlc_hw
, bool clk
);
114 static bool brcms_b_attach_dmapio(struct brcms_c_info
*wlc
, uint j
, bool wme
);
115 static void brcms_b_detach_dmapio(struct brcms_c_hw_info
*wlc_hw
);
116 static void brcms_c_ucode_bsinit(struct brcms_c_hw_info
*wlc_hw
);
117 static bool brcms_c_validboardtype(struct brcms_c_hw_info
*wlc
);
118 static bool brcms_c_isgoodchip(struct brcms_c_hw_info
*wlc_hw
);
119 static bool brcms_b_validate_chip_access(struct brcms_c_hw_info
*wlc_hw
);
120 static char *brcms_c_get_macaddr(struct brcms_c_hw_info
*wlc_hw
);
121 static void brcms_c_mhfdef(struct brcms_c_info
*wlc
, u16
*mhfs
, u16 mhf2_init
);
122 static void brcms_c_mctrl_write(struct brcms_c_hw_info
*wlc_hw
);
123 static void brcms_b_mute(struct brcms_c_hw_info
*wlc_hw
, bool want
,
125 static void brcms_c_ucode_mute_override_set(struct brcms_c_hw_info
*wlc_hw
);
126 static void brcms_c_ucode_mute_override_clear(struct brcms_c_hw_info
*wlc_hw
);
127 static u32
brcms_c_wlintrsoff(struct brcms_c_info
*wlc
);
128 static void brcms_c_wlintrsrestore(struct brcms_c_info
*wlc
, u32 macintmask
);
129 static void brcms_c_gpio_init(struct brcms_c_info
*wlc
);
130 static void brcms_c_write_hw_bcntemplate0(struct brcms_c_hw_info
*wlc_hw
,
132 static void brcms_c_write_hw_bcntemplate1(struct brcms_c_hw_info
*wlc_hw
,
134 static void brcms_b_bsinit(struct brcms_c_info
*wlc
, chanspec_t chanspec
);
135 static u32
brcms_c_setband_inact(struct brcms_c_info
*wlc
, uint bandunit
);
136 static void brcms_b_setband(struct brcms_c_hw_info
*wlc_hw
, uint bandunit
,
137 chanspec_t chanspec
);
138 static void brcms_b_update_slot_timing(struct brcms_c_hw_info
*wlc_hw
,
140 static void brcms_upd_ofdm_pctl1_table(struct brcms_c_hw_info
*wlc_hw
);
141 static u16
brcms_b_ofdm_ratetable_offset(struct brcms_c_hw_info
*wlc_hw
,
144 /* === Low Level functions === */
146 void brcms_b_set_shortslot(struct brcms_c_hw_info
*wlc_hw
, bool shortslot
)
148 wlc_hw
->shortslot
= shortslot
;
150 if (BAND_2G(brcms_b_bandtype(wlc_hw
)) && wlc_hw
->up
) {
151 brcms_c_suspend_mac_and_wait(wlc_hw
->wlc
);
152 brcms_b_update_slot_timing(wlc_hw
, shortslot
);
153 brcms_c_enable_mac(wlc_hw
->wlc
);
158 * Update the slot timing for standard 11b/g (20us slots)
159 * or shortslot 11g (9us slots)
160 * The PSM needs to be suspended for this call.
162 static void brcms_b_update_slot_timing(struct brcms_c_hw_info
*wlc_hw
,
170 /* 11g short slot: 11a timing */
171 W_REG(®s
->ifs_slot
, 0x0207); /* APHY_SLOT_TIME */
172 brcms_b_write_shm(wlc_hw
, M_DOT11_SLOT
, APHY_SLOT_TIME
);
174 /* 11g long slot: 11b timing */
175 W_REG(®s
->ifs_slot
, 0x0212); /* BPHY_SLOT_TIME */
176 brcms_b_write_shm(wlc_hw
, M_DOT11_SLOT
, BPHY_SLOT_TIME
);
180 static void WLBANDINITFN(brcms_c_ucode_bsinit
) (struct brcms_c_hw_info
*wlc_hw
)
182 struct wiphy
*wiphy
= wlc_hw
->wlc
->wiphy
;
184 /* init microcode host flags */
185 brcms_c_write_mhf(wlc_hw
, wlc_hw
->band
->mhfs
);
187 /* do band-specific ucode IHR, SHM, and SCR inits */
188 if (D11REV_IS(wlc_hw
->corerev
, 23)) {
189 if (WLCISNPHY(wlc_hw
->band
)) {
190 brcms_c_write_inits(wlc_hw
, d11n0bsinitvals16
);
192 wiphy_err(wiphy
, "%s: wl%d: unsupported phy in corerev"
193 " %d\n", __func__
, wlc_hw
->unit
,
197 if (D11REV_IS(wlc_hw
->corerev
, 24)) {
198 if (WLCISLCNPHY(wlc_hw
->band
)) {
199 brcms_c_write_inits(wlc_hw
,
200 d11lcn0bsinitvals24
);
202 wiphy_err(wiphy
, "%s: wl%d: unsupported phy in"
203 " core rev %d\n", __func__
,
204 wlc_hw
->unit
, wlc_hw
->corerev
);
206 wiphy_err(wiphy
, "%s: wl%d: unsupported corerev %d\n",
207 __func__
, wlc_hw
->unit
, wlc_hw
->corerev
);
212 /* switch to new band but leave it inactive */
213 static u32
WLBANDINITFN(brcms_c_setband_inact
) (struct brcms_c_info
*wlc
,
216 struct brcms_c_hw_info
*wlc_hw
= wlc
->hw
;
219 BCMMSG(wlc
->wiphy
, "wl%d\n", wlc_hw
->unit
);
221 WARN_ON((R_REG(&wlc_hw
->regs
->maccontrol
) & MCTL_EN_MAC
) != 0);
223 /* disable interrupts */
224 macintmask
= brcms_intrsoff(wlc
->wl
);
227 wlc_phy_switch_radio(wlc_hw
->band
->pi
, OFF
);
229 brcms_b_core_phy_clk(wlc_hw
, OFF
);
231 brcms_c_setxband(wlc_hw
, bandunit
);
236 /* Process received frames */
238 * Return true if more frames need to be processed. false otherwise.
239 * Param 'bound' indicates max. # frames to process before break out.
242 brcms_b_recv(struct brcms_c_hw_info
*wlc_hw
, uint fifo
, bool bound
)
245 struct sk_buff
*head
= NULL
;
246 struct sk_buff
*tail
= NULL
;
248 uint bound_limit
= bound
? wlc_hw
->wlc
->pub
->tunables
->rxbnd
: -1;
249 wlc_d11rxhdr_t
*wlc_rxhdr
= NULL
;
251 BCMMSG(wlc_hw
->wlc
->wiphy
, "wl%d\n", wlc_hw
->unit
);
252 /* gather received frames */
253 while ((p
= dma_rx(wlc_hw
->di
[fifo
]))) {
262 /* !give others some time to run! */
263 if (++n
>= bound_limit
)
267 /* post more rbufs */
268 dma_rxfill(wlc_hw
->di
[fifo
]);
270 /* process each frame */
271 while ((p
= head
) != NULL
) {
275 wlc_rxhdr
= (wlc_d11rxhdr_t
*) p
->data
;
277 /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
278 wlc_phy_rssi_compute(wlc_hw
->band
->pi
, wlc_rxhdr
);
280 brcms_c_recv(wlc_hw
->wlc
, p
);
283 return n
>= bound_limit
;
286 /* second-level interrupt processing
287 * Return true if another dpc needs to be re-scheduled. false otherwise.
288 * Param 'bounded' indicates if applicable loops should be bounded.
290 bool brcms_c_dpc(struct brcms_c_info
*wlc
, bool bounded
)
293 struct brcms_c_hw_info
*wlc_hw
= wlc
->hw
;
294 d11regs_t
*regs
= wlc_hw
->regs
;
296 struct wiphy
*wiphy
= wlc
->wiphy
;
298 if (DEVICEREMOVED(wlc
)) {
299 wiphy_err(wiphy
, "wl%d: %s: dead chip\n", wlc_hw
->unit
,
305 /* grab and clear the saved software intstatus bits */
306 macintstatus
= wlc
->macintstatus
;
307 wlc
->macintstatus
= 0;
309 BCMMSG(wlc
->wiphy
, "wl%d: macintstatus 0x%x\n",
310 wlc_hw
->unit
, macintstatus
);
312 WARN_ON(macintstatus
& MI_PRQ
); /* PRQ Interrupt in non-MBSS */
314 /* BCN template is available */
315 /* ZZZ: Use AP_ACTIVE ? */
316 if (AP_ENAB(wlc
->pub
) && (!APSTA_ENAB(wlc
->pub
))
317 && (macintstatus
& MI_BCNTPL
)) {
318 brcms_c_update_beacon(wlc
);
321 /* PMQ entry addition */
322 if (macintstatus
& MI_PMQ
) {
326 if (macintstatus
& MI_TFS
) {
327 if (brcms_b_txstatus(wlc
->hw
, bounded
, &fatal
))
328 wlc
->macintstatus
|= MI_TFS
;
330 wiphy_err(wiphy
, "MI_TFS: fatal\n");
335 if (macintstatus
& (MI_TBTT
| MI_DTIM_TBTT
))
338 /* ATIM window end */
339 if (macintstatus
& MI_ATIMWINEND
) {
340 BCMMSG(wlc
->wiphy
, "end of ATIM window\n");
341 OR_REG(®s
->maccommand
, wlc
->qvalid
);
345 /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
346 if (macintstatus
& MI_DMAINT
)
347 if (brcms_b_recv(wlc_hw
, RX_FIFO
, bounded
))
348 wlc
->macintstatus
|= MI_DMAINT
;
350 /* TX FIFO suspend/flush completion */
351 if (macintstatus
& MI_TXSTOP
)
352 if (brcms_b_tx_fifo_suspended(wlc_hw
, TX_DATA_FIFO
));
354 /* noise sample collected */
355 if (macintstatus
& MI_BG_NOISE
) {
356 wlc_phy_noise_sample_intr(wlc_hw
->band
->pi
);
359 if (macintstatus
& MI_GP0
) {
360 wiphy_err(wiphy
, "wl%d: PSM microcode watchdog fired at %d "
361 "(seconds). Resetting.\n", wlc_hw
->unit
, wlc_hw
->now
);
363 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
364 __func__
, wlc_hw
->sih
->chip
,
365 wlc_hw
->sih
->chiprev
);
370 /* gptimer timeout */
371 if (macintstatus
& MI_TO
) {
372 W_REG(®s
->gptimer
, 0);
375 if (macintstatus
& MI_RFDISABLE
) {
376 BCMMSG(wlc
->wiphy
, "wl%d: BMAC Detected a change on the"
377 " RF Disable Input\n", wlc_hw
->unit
);
378 brcms_rfkill_set_hw_state(wlc
->wl
);
381 /* send any enq'd tx packets. Just makes sure to jump start tx */
382 if (!pktq_empty(&wlc
->pkt_queue
->q
))
385 /* it isn't done and needs to be resched if macintstatus is non-zero */
386 return wlc
->macintstatus
!= 0;
390 return wlc
->macintstatus
!= 0;
393 /* common low-level watchdog code */
394 void brcms_b_watchdog(void *arg
)
396 struct brcms_c_info
*wlc
= (struct brcms_c_info
*) arg
;
397 struct brcms_c_hw_info
*wlc_hw
= wlc
->hw
;
399 BCMMSG(wlc
->wiphy
, "wl%d\n", wlc_hw
->unit
);
404 /* increment second count */
407 /* Check for FIFO error interrupts */
408 brcms_b_fifoerrors(wlc_hw
);
410 /* make sure RX dma has buffers */
411 dma_rxfill(wlc
->hw
->di
[RX_FIFO
]);
413 wlc_phy_watchdog(wlc_hw
->band
->pi
);
417 brcms_b_set_chanspec(struct brcms_c_hw_info
*wlc_hw
, chanspec_t chanspec
,
418 bool mute
, struct txpwr_limits
*txpwr
)
422 BCMMSG(wlc_hw
->wlc
->wiphy
, "wl%d: 0x%x\n", wlc_hw
->unit
, chanspec
);
424 wlc_hw
->chanspec
= chanspec
;
426 /* Switch bands if necessary */
427 if (NBANDS_HW(wlc_hw
) > 1) {
428 bandunit
= CHSPEC_WLCBANDUNIT(chanspec
);
429 if (wlc_hw
->band
->bandunit
!= bandunit
) {
430 /* brcms_b_setband disables other bandunit,
431 * use light band switch if not up yet
434 wlc_phy_chanspec_radio_set(wlc_hw
->
435 bandstate
[bandunit
]->
437 brcms_b_setband(wlc_hw
, bandunit
, chanspec
);
439 brcms_c_setxband(wlc_hw
, bandunit
);
444 wlc_phy_initcal_enable(wlc_hw
->band
->pi
, !mute
);
448 wlc_phy_txpower_limit_set(wlc_hw
->band
->pi
, txpwr
,
450 wlc_phy_chanspec_radio_set(wlc_hw
->band
->pi
, chanspec
);
452 wlc_phy_chanspec_set(wlc_hw
->band
->pi
, chanspec
);
453 wlc_phy_txpower_limit_set(wlc_hw
->band
->pi
, txpwr
, chanspec
);
455 /* Update muting of the channel */
456 brcms_b_mute(wlc_hw
, mute
, 0);
460 int brcms_b_state_get(struct brcms_c_hw_info
*wlc_hw
, brcms_b_state_t
*state
)
462 state
->machwcap
= wlc_hw
->machwcap
;
467 static bool brcms_b_attach_dmapio(struct brcms_c_info
*wlc
, uint j
, bool wme
)
471 /* ucode host flag 2 needed for pio mode, independent of band and fifo */
473 struct brcms_c_hw_info
*wlc_hw
= wlc
->hw
;
474 uint unit
= wlc_hw
->unit
;
475 wlc_tunables_t
*tune
= wlc
->pub
->tunables
;
476 struct wiphy
*wiphy
= wlc
->wiphy
;
478 /* name and offsets for dma_attach */
479 snprintf(name
, sizeof(name
), "wl%d", unit
);
481 if (wlc_hw
->di
[0] == 0) { /* Init FIFOs */
483 int dma_attach_err
= 0;
484 /* Find out the DMA addressing capability and let OS know
485 * All the channels within one DMA core have 'common-minimum' same
489 dma_addrwidth(wlc_hw
->sih
, DMAREG(wlc_hw
, DMA_TX
, 0));
491 if (!wl_alloc_dma_resources(wlc_hw
->wlc
->wl
, addrwidth
)) {
492 wiphy_err(wiphy
, "wl%d: wlc_attach: alloc_dma_"
493 "resources failed\n", unit
);
499 * TX: TX_AC_BK_FIFO (TX AC Background data packets)
500 * RX: RX_FIFO (RX data packets)
502 wlc_hw
->di
[0] = dma_attach(name
, wlc_hw
->sih
,
503 (wme
? DMAREG(wlc_hw
, DMA_TX
, 0) :
504 NULL
), DMAREG(wlc_hw
, DMA_RX
, 0),
505 (wme
? tune
->ntxd
: 0), tune
->nrxd
,
506 tune
->rxbufsz
, -1, tune
->nrxbufpost
,
507 WL_HWRXOFF
, &brcm_msg_level
);
508 dma_attach_err
|= (NULL
== wlc_hw
->di
[0]);
512 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
513 * (legacy) TX_DATA_FIFO (TX data packets)
516 wlc_hw
->di
[1] = dma_attach(name
, wlc_hw
->sih
,
517 DMAREG(wlc_hw
, DMA_TX
, 1), NULL
,
518 tune
->ntxd
, 0, 0, -1, 0, 0,
520 dma_attach_err
|= (NULL
== wlc_hw
->di
[1]);
524 * TX: TX_AC_VI_FIFO (TX AC Video data packets)
527 wlc_hw
->di
[2] = dma_attach(name
, wlc_hw
->sih
,
528 DMAREG(wlc_hw
, DMA_TX
, 2), NULL
,
529 tune
->ntxd
, 0, 0, -1, 0, 0,
531 dma_attach_err
|= (NULL
== wlc_hw
->di
[2]);
534 * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
535 * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
537 wlc_hw
->di
[3] = dma_attach(name
, wlc_hw
->sih
,
538 DMAREG(wlc_hw
, DMA_TX
, 3),
539 NULL
, tune
->ntxd
, 0, 0, -1,
540 0, 0, &brcm_msg_level
);
541 dma_attach_err
|= (NULL
== wlc_hw
->di
[3]);
542 /* Cleaner to leave this as if with AP defined */
544 if (dma_attach_err
) {
545 wiphy_err(wiphy
, "wl%d: wlc_attach: dma_attach failed"
550 /* get pointer to dma engine tx flow control variable */
551 for (i
= 0; i
< NFIFO
; i
++)
554 (uint
*) dma_getvar(wlc_hw
->di
[i
],
558 /* initial ucode host flags */
559 brcms_c_mhfdef(wlc
, wlc_hw
->band
->mhfs
, pio_mhf2
);
564 static void brcms_b_detach_dmapio(struct brcms_c_hw_info
*wlc_hw
)
568 for (j
= 0; j
< NFIFO
; j
++) {
570 dma_detach(wlc_hw
->di
[j
]);
571 wlc_hw
->di
[j
] = NULL
;
577 * run backplane attach, init nvram
579 * initialize software state for each core and band
580 * put the whole chip in reset(driver down state), no clock
582 int brcms_b_attach(struct brcms_c_info
*wlc
, u16 vendor
, u16 device
, uint unit
,
583 bool piomode
, void *regsva
, uint bustype
, void *btparam
)
585 struct brcms_c_hw_info
*wlc_hw
;
587 char *macaddr
= NULL
;
592 shared_phy_params_t sha_params
;
593 struct wiphy
*wiphy
= wlc
->wiphy
;
595 BCMMSG(wlc
->wiphy
, "wl%d: vendor 0x%x device 0x%x\n", unit
, vendor
,
603 wlc_hw
->band
= wlc_hw
->bandstate
[0];
604 wlc_hw
->_piomode
= piomode
;
606 /* populate struct brcms_c_hw_info with default values */
607 brcms_b_info_init(wlc_hw
);
610 * Do the hardware portion of the attach.
611 * Also initialize software state that depends on the particular hardware
614 wlc_hw
->sih
= ai_attach(regsva
, bustype
, btparam
,
615 &wlc_hw
->vars
, &wlc_hw
->vars_size
);
616 if (wlc_hw
->sih
== NULL
) {
617 wiphy_err(wiphy
, "wl%d: brcms_b_attach: si_attach failed\n",
625 * Get vendid/devid nvram overwrites, which could be different
626 * than those the BIOS recognizes for devices on PCMCIA_BUS,
627 * SDIO_BUS, and SROMless devices on PCI_BUS.
630 bustype
= BCMBUSTYPE
;
632 if (bustype
!= SI_BUS
) {
635 var
= getvar(vars
, "vendid");
637 vendor
= (u16
) simple_strtoul(var
, NULL
, 0);
638 wiphy_err(wiphy
, "Overriding vendor id = 0x%x\n",
641 var
= getvar(vars
, "devid");
643 u16 devid
= (u16
) simple_strtoul(var
, NULL
, 0);
644 if (devid
!= 0xffff) {
646 wiphy_err(wiphy
, "Overriding device id = 0x%x"
651 /* verify again the device is supported */
652 if (!brcms_c_chipmatch(vendor
, device
)) {
653 wiphy_err(wiphy
, "wl%d: brcms_b_attach: Unsupported "
654 "vendor/device (0x%x/0x%x)\n",
655 unit
, vendor
, device
);
661 wlc_hw
->vendorid
= vendor
;
662 wlc_hw
->deviceid
= device
;
664 /* set bar0 window to point at D11 core */
665 wlc_hw
->regs
= (d11regs_t
*) ai_setcore(wlc_hw
->sih
, D11_CORE_ID
, 0);
666 wlc_hw
->corerev
= ai_corerev(wlc_hw
->sih
);
670 wlc
->regs
= wlc_hw
->regs
;
672 /* validate chip, chiprev and corerev */
673 if (!brcms_c_isgoodchip(wlc_hw
)) {
678 /* initialize power control registers */
679 ai_clkctl_init(wlc_hw
->sih
);
681 /* request fastclock and force fastclock for the rest of attach
682 * bring the d11 core out of reset.
683 * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
684 * But it will be called again inside wlc_corereset, after d11 is out of reset.
686 brcms_b_clkctl_clk(wlc_hw
, CLK_FAST
);
687 brcms_b_corereset(wlc_hw
, WLC_USE_COREFLAGS
);
689 if (!brcms_b_validate_chip_access(wlc_hw
)) {
690 wiphy_err(wiphy
, "wl%d: brcms_b_attach: validate_chip_access "
696 /* get the board rev, used just below */
697 j
= getintvar(vars
, "boardrev");
698 /* promote srom boardrev of 0xFF to 1 */
699 if (j
== BOARDREV_PROMOTABLE
)
700 j
= BOARDREV_PROMOTED
;
701 wlc_hw
->boardrev
= (u16
) j
;
702 if (!brcms_c_validboardtype(wlc_hw
)) {
703 wiphy_err(wiphy
, "wl%d: brcms_b_attach: Unsupported Broadcom "
704 "board type (0x%x)" " or revision level (0x%x)\n",
705 unit
, wlc_hw
->sih
->boardtype
, wlc_hw
->boardrev
);
709 wlc_hw
->sromrev
= (u8
) getintvar(vars
, "sromrev");
710 wlc_hw
->boardflags
= (u32
) getintvar(vars
, "boardflags");
711 wlc_hw
->boardflags2
= (u32
) getintvar(vars
, "boardflags2");
713 if (wlc_hw
->boardflags
& BFL_NOPLLDOWN
)
714 brcms_b_pllreq(wlc_hw
, true, WLC_PLLREQ_SHARED
);
716 if ((wlc_hw
->sih
->bustype
== PCI_BUS
)
717 && (ai_pci_war16165(wlc_hw
->sih
)))
718 wlc
->war16165
= true;
720 /* check device id(srom, nvram etc.) to set bands */
721 if (wlc_hw
->deviceid
== BCM43224_D11N_ID
||
722 wlc_hw
->deviceid
== BCM43224_D11N_ID_VEN1
) {
723 /* Dualband boards */
728 if ((wlc_hw
->sih
->chip
== BCM43225_CHIP_ID
))
731 /* BMAC_NOTE: remove init of pub values when brcms_c_attach()
732 * unconditionally does the init of these values
734 wlc
->vendorid
= wlc_hw
->vendorid
;
735 wlc
->deviceid
= wlc_hw
->deviceid
;
736 wlc
->pub
->sih
= wlc_hw
->sih
;
737 wlc
->pub
->corerev
= wlc_hw
->corerev
;
738 wlc
->pub
->sromrev
= wlc_hw
->sromrev
;
739 wlc
->pub
->boardrev
= wlc_hw
->boardrev
;
740 wlc
->pub
->boardflags
= wlc_hw
->boardflags
;
741 wlc
->pub
->boardflags2
= wlc_hw
->boardflags2
;
742 wlc
->pub
->_nbands
= wlc_hw
->_nbands
;
744 wlc_hw
->physhim
= wlc_phy_shim_attach(wlc_hw
, wlc
->wl
, wlc
);
746 if (wlc_hw
->physhim
== NULL
) {
747 wiphy_err(wiphy
, "wl%d: brcms_b_attach: wlc_phy_shim_attach "
753 /* pass all the parameters to wlc_phy_shared_attach in one struct */
754 sha_params
.sih
= wlc_hw
->sih
;
755 sha_params
.physhim
= wlc_hw
->physhim
;
756 sha_params
.unit
= unit
;
757 sha_params
.corerev
= wlc_hw
->corerev
;
758 sha_params
.vars
= vars
;
759 sha_params
.vid
= wlc_hw
->vendorid
;
760 sha_params
.did
= wlc_hw
->deviceid
;
761 sha_params
.chip
= wlc_hw
->sih
->chip
;
762 sha_params
.chiprev
= wlc_hw
->sih
->chiprev
;
763 sha_params
.chippkg
= wlc_hw
->sih
->chippkg
;
764 sha_params
.sromrev
= wlc_hw
->sromrev
;
765 sha_params
.boardtype
= wlc_hw
->sih
->boardtype
;
766 sha_params
.boardrev
= wlc_hw
->boardrev
;
767 sha_params
.boardvendor
= wlc_hw
->sih
->boardvendor
;
768 sha_params
.boardflags
= wlc_hw
->boardflags
;
769 sha_params
.boardflags2
= wlc_hw
->boardflags2
;
770 sha_params
.bustype
= wlc_hw
->sih
->bustype
;
771 sha_params
.buscorerev
= wlc_hw
->sih
->buscorerev
;
773 /* alloc and save pointer to shared phy state area */
774 wlc_hw
->phy_sh
= wlc_phy_shared_attach(&sha_params
);
775 if (!wlc_hw
->phy_sh
) {
780 /* initialize software state for each core and band */
781 for (j
= 0; j
< NBANDS_HW(wlc_hw
); j
++) {
783 * band0 is always 2.4Ghz
784 * band1, if present, is 5Ghz
787 /* So if this is a single band 11a card, use band 1 */
788 if (IS_SINGLEBAND_5G(wlc_hw
->deviceid
))
791 brcms_c_setxband(wlc_hw
, j
);
793 wlc_hw
->band
->bandunit
= j
;
794 wlc_hw
->band
->bandtype
= j
? WLC_BAND_5G
: WLC_BAND_2G
;
795 wlc
->band
->bandunit
= j
;
796 wlc
->band
->bandtype
= j
? WLC_BAND_5G
: WLC_BAND_2G
;
797 wlc
->core
->coreidx
= ai_coreidx(wlc_hw
->sih
);
799 wlc_hw
->machwcap
= R_REG(®s
->machwcap
);
800 wlc_hw
->machwcap_backup
= wlc_hw
->machwcap
;
802 /* init tx fifo size */
804 xmtfifo_sz
[(wlc_hw
->corerev
- XMTFIFOTBL_STARTREV
)];
806 /* Get a phy for this band */
807 wlc_hw
->band
->pi
= wlc_phy_attach(wlc_hw
->phy_sh
,
808 (void *)regs
, brcms_b_bandtype(wlc_hw
), vars
,
810 if (wlc_hw
->band
->pi
== NULL
) {
811 wiphy_err(wiphy
, "wl%d: brcms_b_attach: wlc_phy_"
812 "attach failed\n", unit
);
817 wlc_phy_machwcap_set(wlc_hw
->band
->pi
, wlc_hw
->machwcap
);
819 wlc_phy_get_phyversion(wlc_hw
->band
->pi
, &wlc_hw
->band
->phytype
,
820 &wlc_hw
->band
->phyrev
,
821 &wlc_hw
->band
->radioid
,
822 &wlc_hw
->band
->radiorev
);
823 wlc_hw
->band
->abgphy_encore
=
824 wlc_phy_get_encore(wlc_hw
->band
->pi
);
825 wlc
->band
->abgphy_encore
= wlc_phy_get_encore(wlc_hw
->band
->pi
);
826 wlc_hw
->band
->core_flags
=
827 wlc_phy_get_coreflags(wlc_hw
->band
->pi
);
829 /* verify good phy_type & supported phy revision */
830 if (WLCISNPHY(wlc_hw
->band
)) {
831 if (NCONF_HAS(wlc_hw
->band
->phyrev
))
835 } else if (WLCISLCNPHY(wlc_hw
->band
)) {
836 if (LCNCONF_HAS(wlc_hw
->band
->phyrev
))
842 wiphy_err(wiphy
, "wl%d: brcms_b_attach: unsupported "
843 "phy type/rev (%d/%d)\n", unit
,
844 wlc_hw
->band
->phytype
, wlc_hw
->band
->phyrev
);
850 /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
851 * high level attach. However we can not make that change until all low level access
852 * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
853 * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
854 * low only init when all fns updated.
856 wlc
->band
->pi
= wlc_hw
->band
->pi
;
857 wlc
->band
->phytype
= wlc_hw
->band
->phytype
;
858 wlc
->band
->phyrev
= wlc_hw
->band
->phyrev
;
859 wlc
->band
->radioid
= wlc_hw
->band
->radioid
;
860 wlc
->band
->radiorev
= wlc_hw
->band
->radiorev
;
862 /* default contention windows size limits */
863 wlc_hw
->band
->CWmin
= APHY_CWMIN
;
864 wlc_hw
->band
->CWmax
= PHY_CWMAX
;
866 if (!brcms_b_attach_dmapio(wlc
, j
, wme
)) {
872 /* disable core to match driver "down" state */
873 brcms_c_coredisable(wlc_hw
);
875 /* Match driver "down" state */
876 if (wlc_hw
->sih
->bustype
== PCI_BUS
)
877 ai_pci_down(wlc_hw
->sih
);
879 /* register sb interrupt callback functions */
880 ai_register_intr_callback(wlc_hw
->sih
, (void *)brcms_c_wlintrsoff
,
881 (void *)brcms_c_wlintrsrestore
, NULL
, wlc
);
883 /* turn off pll and xtal to match driver "down" state */
884 brcms_b_xtal(wlc_hw
, OFF
);
886 /* *********************************************************************
887 * The hardware is in the DOWN state at this point. D11 core
888 * or cores are in reset with clocks off, and the board PLLs
889 * are off if possible.
891 * Beyond this point, wlc->sbclk == false and chip registers
892 * should not be touched.
893 *********************************************************************
896 /* init etheraddr state variables */
897 macaddr
= brcms_c_get_macaddr(wlc_hw
);
898 if (macaddr
== NULL
) {
899 wiphy_err(wiphy
, "wl%d: brcms_b_attach: macaddr not found\n",
904 brcmu_ether_atoe(macaddr
, wlc_hw
->etheraddr
);
905 if (is_broadcast_ether_addr(wlc_hw
->etheraddr
) ||
906 is_zero_ether_addr(wlc_hw
->etheraddr
)) {
907 wiphy_err(wiphy
, "wl%d: brcms_b_attach: bad macaddr %s\n",
914 "deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
915 wlc_hw
->deviceid
, wlc_hw
->_nbands
,
916 wlc_hw
->sih
->boardtype
, macaddr
);
921 wiphy_err(wiphy
, "wl%d: brcms_b_attach: failed with err %d\n", unit
,
927 * Initialize brcms_c_info default values ...
928 * may get overrides later in this function
929 * BMAC_NOTES, move low out and resolve the dangling ones
931 static void brcms_b_info_init(struct brcms_c_hw_info
*wlc_hw
)
933 struct brcms_c_info
*wlc
= wlc_hw
->wlc
;
935 /* set default sw macintmask value */
936 wlc
->defmacintmask
= DEF_MACINTMASK
;
938 /* various 802.11g modes */
939 wlc_hw
->shortslot
= false;
941 wlc_hw
->SFBL
= RETRY_SHORT_FB
;
942 wlc_hw
->LFBL
= RETRY_LONG_FB
;
944 /* default mac retry limits */
945 wlc_hw
->SRL
= RETRY_SHORT_DEF
;
946 wlc_hw
->LRL
= RETRY_LONG_DEF
;
947 wlc_hw
->chanspec
= CH20MHZ_CHSPEC(1);
953 int brcms_b_detach(struct brcms_c_info
*wlc
)
956 struct brcms_c_hwband
*band
;
957 struct brcms_c_hw_info
*wlc_hw
= wlc
->hw
;
963 /* detach interrupt sync mechanism since interrupt is disabled and per-port
964 * interrupt object may has been freed. this must be done before sb core switch
966 ai_deregister_intr_callback(wlc_hw
->sih
);
968 if (wlc_hw
->sih
->bustype
== PCI_BUS
)
969 ai_pci_sleep(wlc_hw
->sih
);
972 brcms_b_detach_dmapio(wlc_hw
);
975 for (i
= 0; i
< NBANDS_HW(wlc_hw
); i
++) {
977 /* Detach this band's phy */
978 wlc_phy_detach(band
->pi
);
981 band
= wlc_hw
->bandstate
[OTHERBANDUNIT(wlc
)];
984 /* Free shared phy state */
985 wlc_phy_shared_detach(wlc_hw
->phy_sh
);
987 wlc_phy_shim_detach(wlc_hw
->physhim
);
994 ai_detach(wlc_hw
->sih
);
1002 void brcms_b_reset(struct brcms_c_hw_info
*wlc_hw
)
1004 BCMMSG(wlc_hw
->wlc
->wiphy
, "wl%d\n", wlc_hw
->unit
);
1006 /* reset the core */
1007 if (!DEVICEREMOVED(wlc_hw
->wlc
))
1008 brcms_b_corereset(wlc_hw
, WLC_USE_COREFLAGS
);
1010 /* purge the dma rings */
1011 brcms_c_flushqueues(wlc_hw
->wlc
);
1013 brcms_c_reset_bmac_done(wlc_hw
->wlc
);
1017 brcms_b_init(struct brcms_c_hw_info
*wlc_hw
, chanspec_t chanspec
,
1021 struct brcms_c_info
*wlc
= wlc_hw
->wlc
;
1023 BCMMSG(wlc_hw
->wlc
->wiphy
, "wl%d\n", wlc_hw
->unit
);
1025 /* request FAST clock if not on */
1026 fastclk
= wlc_hw
->forcefastclk
;
1028 brcms_b_clkctl_clk(wlc_hw
, CLK_FAST
);
1030 /* disable interrupts */
1031 macintmask
= brcms_intrsoff(wlc
->wl
);
1033 /* set up the specified band and chanspec */
1034 brcms_c_setxband(wlc_hw
, CHSPEC_WLCBANDUNIT(chanspec
));
1035 wlc_phy_chanspec_radio_set(wlc_hw
->band
->pi
, chanspec
);
1037 /* do one-time phy inits and calibration */
1038 wlc_phy_cal_init(wlc_hw
->band
->pi
);
1040 /* core-specific initialization */
1041 brcms_b_coreinit(wlc
);
1043 /* suspend the tx fifos and mute the phy for preism cac time */
1045 brcms_b_mute(wlc_hw
, ON
, PHY_MUTE_FOR_PREISM
);
1047 /* band-specific inits */
1048 brcms_b_bsinit(wlc
, chanspec
);
1050 /* restore macintmask */
1051 brcms_intrsrestore(wlc
->wl
, macintmask
);
1053 /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
1054 * and brcms_c_enable_mac() will clear this override bit.
1056 mboolset(wlc_hw
->wake_override
, WLC_WAKE_OVERRIDE_MACSUSPEND
);
1059 * initialize mac_suspend_depth to 1 to match ucode initial suspended state
1061 wlc_hw
->mac_suspend_depth
= 1;
1063 /* restore the clk */
1065 brcms_b_clkctl_clk(wlc_hw
, CLK_DYNAMIC
);
1068 int brcms_b_up_prep(struct brcms_c_hw_info
*wlc_hw
)
1072 BCMMSG(wlc_hw
->wlc
->wiphy
, "wl%d\n", wlc_hw
->unit
);
1075 * Enable pll and xtal, initialize the power control registers,
1076 * and force fastclock for the remainder of brcms_c_up().
1078 brcms_b_xtal(wlc_hw
, ON
);
1079 ai_clkctl_init(wlc_hw
->sih
);
1080 brcms_b_clkctl_clk(wlc_hw
, CLK_FAST
);
1083 * Configure pci/pcmcia here instead of in brcms_c_attach()
1084 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
1086 coremask
= (1 << wlc_hw
->wlc
->core
->coreidx
);
1088 if (wlc_hw
->sih
->bustype
== PCI_BUS
)
1089 ai_pci_setup(wlc_hw
->sih
, coremask
);
1092 * Need to read the hwradio status here to cover the case where the system
1093 * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1095 if (brcms_b_radio_read_hwdisabled(wlc_hw
)) {
1096 /* put SB PCI in down state again */
1097 if (wlc_hw
->sih
->bustype
== PCI_BUS
)
1098 ai_pci_down(wlc_hw
->sih
);
1099 brcms_b_xtal(wlc_hw
, OFF
);
1103 if (wlc_hw
->sih
->bustype
== PCI_BUS
)
1104 ai_pci_up(wlc_hw
->sih
);
1106 /* reset the d11 core */
1107 brcms_b_corereset(wlc_hw
, WLC_USE_COREFLAGS
);
1112 int brcms_b_up_finish(struct brcms_c_hw_info
*wlc_hw
)
1114 BCMMSG(wlc_hw
->wlc
->wiphy
, "wl%d\n", wlc_hw
->unit
);
1117 wlc_phy_hw_state_upd(wlc_hw
->band
->pi
, true);
1119 /* FULLY enable dynamic power control and d11 core interrupt */
1120 brcms_b_clkctl_clk(wlc_hw
, CLK_DYNAMIC
);
1121 brcms_intrson(wlc_hw
->wlc
->wl
);
1125 int brcms_b_bmac_down_prep(struct brcms_c_hw_info
*wlc_hw
)
1130 BCMMSG(wlc_hw
->wlc
->wiphy
, "wl%d\n", wlc_hw
->unit
);
1135 dev_gone
= DEVICEREMOVED(wlc_hw
->wlc
);
1137 /* disable interrupts */
1139 wlc_hw
->wlc
->macintmask
= 0;
1141 /* now disable interrupts */
1142 brcms_intrsoff(wlc_hw
->wlc
->wl
);
1144 /* ensure we're running on the pll clock again */
1145 brcms_b_clkctl_clk(wlc_hw
, CLK_FAST
);
1147 /* down phy at the last of this stage */
1148 callbacks
+= wlc_phy_down(wlc_hw
->band
->pi
);
1153 int brcms_b_down_finish(struct brcms_c_hw_info
*wlc_hw
)
1158 BCMMSG(wlc_hw
->wlc
->wiphy
, "wl%d\n", wlc_hw
->unit
);
1164 wlc_phy_hw_state_upd(wlc_hw
->band
->pi
, false);
1166 dev_gone
= DEVICEREMOVED(wlc_hw
->wlc
);
1169 wlc_hw
->sbclk
= false;
1170 wlc_hw
->clk
= false;
1171 wlc_phy_hw_clk_state_upd(wlc_hw
->band
->pi
, false);
1173 /* reclaim any posted packets */
1174 brcms_c_flushqueues(wlc_hw
->wlc
);
1177 /* Reset and disable the core */
1178 if (ai_iscoreup(wlc_hw
->sih
)) {
1179 if (R_REG(&wlc_hw
->regs
->maccontrol
) &
1181 brcms_c_suspend_mac_and_wait(wlc_hw
->wlc
);
1182 callbacks
+= brcms_reset(wlc_hw
->wlc
->wl
);
1183 brcms_c_coredisable(wlc_hw
);
1186 /* turn off primary xtal and pll */
1187 if (!wlc_hw
->noreset
) {
1188 if (wlc_hw
->sih
->bustype
== PCI_BUS
)
1189 ai_pci_down(wlc_hw
->sih
);
1190 brcms_b_xtal(wlc_hw
, OFF
);
1197 void brcms_b_wait_for_wake(struct brcms_c_hw_info
*wlc_hw
)
1199 /* delay before first read of ucode state */
1202 /* wait until ucode is no longer asleep */
1203 SPINWAIT((brcms_b_read_shm(wlc_hw
, M_UCODE_DBGST
) ==
1204 DBGST_ASLEEP
), wlc_hw
->wlc
->fastpwrup_dly
);
1207 void brcms_b_hw_etheraddr(struct brcms_c_hw_info
*wlc_hw
, u8
*ea
)
1209 memcpy(ea
, wlc_hw
->etheraddr
, ETH_ALEN
);
1212 static int brcms_b_bandtype(struct brcms_c_hw_info
*wlc_hw
)
1214 return wlc_hw
->band
->bandtype
;
1217 /* control chip clock to save power, enable dynamic clock or force fast clock */
1218 static void brcms_b_clkctl_clk(struct brcms_c_hw_info
*wlc_hw
, uint mode
)
1220 if (PMUCTL_ENAB(wlc_hw
->sih
)) {
1221 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1222 * but mac core will still run on ALP(not HT) when it enters powersave mode,
1223 * which means the FCA bit may not be set.
1224 * should wakeup mac if driver wants it to run on HT.
1228 if (mode
== CLK_FAST
) {
1229 OR_REG(&wlc_hw
->regs
->clk_ctl_st
,
1236 clk_ctl_st
) & CCS_HTAVAIL
) == 0),
1237 PMU_MAX_TRANSITION_DLY
);
1240 clk_ctl_st
) & CCS_HTAVAIL
));
1242 if ((wlc_hw
->sih
->pmurev
== 0) &&
1245 clk_ctl_st
) & (CCS_FORCEHT
| CCS_HTAREQ
)))
1248 clk_ctl_st
) & CCS_HTAVAIL
)
1250 PMU_MAX_TRANSITION_DLY
);
1251 AND_REG(&wlc_hw
->regs
->clk_ctl_st
,
1255 wlc_hw
->forcefastclk
= (mode
== CLK_FAST
);
1258 /* old chips w/o PMU, force HT through cc,
1259 * then use FCA to verify mac is running fast clock
1262 wlc_hw
->forcefastclk
= ai_clkctl_cc(wlc_hw
->sih
, mode
);
1264 /* check fast clock is available (if core is not in reset) */
1265 if (wlc_hw
->forcefastclk
&& wlc_hw
->clk
)
1266 WARN_ON(!(ai_core_sflags(wlc_hw
->sih
, 0, 0) &
1269 /* keep the ucode wake bit on if forcefastclk is on
1270 * since we do not want ucode to put us back to slow clock
1271 * when it dozes for PM mode.
1272 * Code below matches the wake override bit with current forcefastclk state
1273 * Only setting bit in wake_override instead of waking ucode immediately
1274 * since old code (wlc.c 1.4499) had this behavior. Older code set
1275 * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1276 * (protected by an up check) was executed just below.
1278 if (wlc_hw
->forcefastclk
)
1279 mboolset(wlc_hw
->wake_override
,
1280 WLC_WAKE_OVERRIDE_FORCEFAST
);
1282 mboolclr(wlc_hw
->wake_override
,
1283 WLC_WAKE_OVERRIDE_FORCEFAST
);
1287 /* set initial host flags value */
1289 brcms_c_mhfdef(struct brcms_c_info
*wlc
, u16
*mhfs
, u16 mhf2_init
)
1291 struct brcms_c_hw_info
*wlc_hw
= wlc
->hw
;
1293 memset(mhfs
, 0, MHFMAX
* sizeof(u16
));
1295 mhfs
[MHF2
] |= mhf2_init
;
1297 /* prohibit use of slowclock on multifunction boards */
1298 if (wlc_hw
->boardflags
& BFL_NOPLLDOWN
)
1299 mhfs
[MHF1
] |= MHF1_FORCEFASTCLK
;
1301 if (WLCISNPHY(wlc_hw
->band
) && NREV_LT(wlc_hw
->band
->phyrev
, 2)) {
1302 mhfs
[MHF2
] |= MHF2_NPHY40MHZ_WAR
;
1303 mhfs
[MHF1
] |= MHF1_IQSWAP_WAR
;
1307 /* set or clear ucode host flag bits
1308 * it has an optimization for no-change write
1309 * it only writes through shared memory when the core has clock;
1310 * pre-CLK changes should use wlc_write_mhf to get around the optimization
1313 * bands values are: WLC_BAND_AUTO <--- Current band only
1314 * WLC_BAND_5G <--- 5G band only
1315 * WLC_BAND_2G <--- 2G band only
1316 * WLC_BAND_ALL <--- All bands
1319 brcms_b_mhf(struct brcms_c_hw_info
*wlc_hw
, u8 idx
, u16 mask
, u16 val
,
1323 u16 addr
[MHFMAX
] = {
1324 M_HOST_FLAGS1
, M_HOST_FLAGS2
, M_HOST_FLAGS3
, M_HOST_FLAGS4
,
1327 struct brcms_c_hwband
*band
;
1329 if ((val
& ~mask
) || idx
>= MHFMAX
)
1330 return; /* error condition */
1333 /* Current band only or all bands,
1334 * then set the band to current band
1338 band
= wlc_hw
->band
;
1341 band
= wlc_hw
->bandstate
[BAND_5G_INDEX
];
1344 band
= wlc_hw
->bandstate
[BAND_2G_INDEX
];
1347 band
= NULL
; /* error condition */
1351 save
= band
->mhfs
[idx
];
1352 band
->mhfs
[idx
] = (band
->mhfs
[idx
] & ~mask
) | val
;
1354 /* optimization: only write through if changed, and
1355 * changed band is the current band
1357 if (wlc_hw
->clk
&& (band
->mhfs
[idx
] != save
)
1358 && (band
== wlc_hw
->band
))
1359 brcms_b_write_shm(wlc_hw
, addr
[idx
],
1360 (u16
) band
->mhfs
[idx
]);
1363 if (bands
== WLC_BAND_ALL
) {
1364 wlc_hw
->bandstate
[0]->mhfs
[idx
] =
1365 (wlc_hw
->bandstate
[0]->mhfs
[idx
] & ~mask
) | val
;
1366 wlc_hw
->bandstate
[1]->mhfs
[idx
] =
1367 (wlc_hw
->bandstate
[1]->mhfs
[idx
] & ~mask
) | val
;
1371 u16
brcms_b_mhf_get(struct brcms_c_hw_info
*wlc_hw
, u8 idx
, int bands
)
1373 struct brcms_c_hwband
*band
;
1376 return 0; /* error condition */
1379 band
= wlc_hw
->band
;
1382 band
= wlc_hw
->bandstate
[BAND_5G_INDEX
];
1385 band
= wlc_hw
->bandstate
[BAND_2G_INDEX
];
1388 band
= NULL
; /* error condition */
1394 return band
->mhfs
[idx
];
1397 static void brcms_c_write_mhf(struct brcms_c_hw_info
*wlc_hw
, u16
*mhfs
)
1401 M_HOST_FLAGS1
, M_HOST_FLAGS2
, M_HOST_FLAGS3
, M_HOST_FLAGS4
,
1405 for (idx
= 0; idx
< MHFMAX
; idx
++) {
1406 brcms_b_write_shm(wlc_hw
, addr
[idx
], mhfs
[idx
]);
1410 /* set the maccontrol register to desired reset state and
1411 * initialize the sw cache of the register
1413 static void brcms_c_mctrl_reset(struct brcms_c_hw_info
*wlc_hw
)
1415 /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1416 wlc_hw
->maccontrol
= 0;
1417 wlc_hw
->suspended_fifos
= 0;
1418 wlc_hw
->wake_override
= 0;
1419 wlc_hw
->mute_override
= 0;
1420 brcms_b_mctrl(wlc_hw
, ~0, MCTL_IHR_EN
| MCTL_WAKE
);
1423 /* set or clear maccontrol bits */
1424 void brcms_b_mctrl(struct brcms_c_hw_info
*wlc_hw
, u32 mask
, u32 val
)
1430 return; /* error condition */
1431 maccontrol
= wlc_hw
->maccontrol
;
1432 new_maccontrol
= (maccontrol
& ~mask
) | val
;
1434 /* if the new maccontrol value is the same as the old, nothing to do */
1435 if (new_maccontrol
== maccontrol
)
1438 /* something changed, cache the new value */
1439 wlc_hw
->maccontrol
= new_maccontrol
;
1441 /* write the new values with overrides applied */
1442 brcms_c_mctrl_write(wlc_hw
);
1445 /* write the software state of maccontrol and overrides to the maccontrol register */
1446 static void brcms_c_mctrl_write(struct brcms_c_hw_info
*wlc_hw
)
1448 u32 maccontrol
= wlc_hw
->maccontrol
;
1450 /* OR in the wake bit if overridden */
1451 if (wlc_hw
->wake_override
)
1452 maccontrol
|= MCTL_WAKE
;
1454 /* set AP and INFRA bits for mute if needed */
1455 if (wlc_hw
->mute_override
) {
1456 maccontrol
&= ~(MCTL_AP
);
1457 maccontrol
|= MCTL_INFRA
;
1460 W_REG(&wlc_hw
->regs
->maccontrol
, maccontrol
);
1463 void brcms_c_ucode_wake_override_set(struct brcms_c_hw_info
*wlc_hw
,
1466 if (wlc_hw
->wake_override
|| (wlc_hw
->maccontrol
& MCTL_WAKE
)) {
1467 mboolset(wlc_hw
->wake_override
, override_bit
);
1471 mboolset(wlc_hw
->wake_override
, override_bit
);
1473 brcms_c_mctrl_write(wlc_hw
);
1474 brcms_b_wait_for_wake(wlc_hw
);
1479 void brcms_c_ucode_wake_override_clear(struct brcms_c_hw_info
*wlc_hw
,
1482 mboolclr(wlc_hw
->wake_override
, override_bit
);
1484 if (wlc_hw
->wake_override
|| (wlc_hw
->maccontrol
& MCTL_WAKE
))
1487 brcms_c_mctrl_write(wlc_hw
);
1492 /* When driver needs ucode to stop beaconing, it has to make sure that
1493 * MCTL_AP is clear and MCTL_INFRA is set
1494 * Mode MCTL_AP MCTL_INFRA
1496 * STA 0 1 <--- This will ensure no beacons
1499 static void brcms_c_ucode_mute_override_set(struct brcms_c_hw_info
*wlc_hw
)
1501 wlc_hw
->mute_override
= 1;
1503 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1504 * override, then there is no change to write
1506 if ((wlc_hw
->maccontrol
& (MCTL_AP
| MCTL_INFRA
)) == MCTL_INFRA
)
1509 brcms_c_mctrl_write(wlc_hw
);
1514 /* Clear the override on AP and INFRA bits */
1515 static void brcms_c_ucode_mute_override_clear(struct brcms_c_hw_info
*wlc_hw
)
1517 if (wlc_hw
->mute_override
== 0)
1520 wlc_hw
->mute_override
= 0;
1522 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1523 * override, then there is no change to write
1525 if ((wlc_hw
->maccontrol
& (MCTL_AP
| MCTL_INFRA
)) == MCTL_INFRA
)
1528 brcms_c_mctrl_write(wlc_hw
);
1532 * Write a MAC address to the given match reg offset in the RXE match engine.
1535 brcms_b_set_addrmatch(struct brcms_c_hw_info
*wlc_hw
, int match_reg_offset
,
1543 BCMMSG(wlc_hw
->wlc
->wiphy
, "wl%d: brcms_b_set_addrmatch\n",
1546 regs
= wlc_hw
->regs
;
1547 mac_l
= addr
[0] | (addr
[1] << 8);
1548 mac_m
= addr
[2] | (addr
[3] << 8);
1549 mac_h
= addr
[4] | (addr
[5] << 8);
1551 /* enter the MAC addr into the RXE match registers */
1552 W_REG(®s
->rcm_ctl
, RCM_INC_DATA
| match_reg_offset
);
1553 W_REG(®s
->rcm_mat_data
, mac_l
);
1554 W_REG(®s
->rcm_mat_data
, mac_m
);
1555 W_REG(®s
->rcm_mat_data
, mac_h
);
1560 brcms_b_write_template_ram(struct brcms_c_hw_info
*wlc_hw
, int offset
, int len
,
1566 BCMMSG(wlc_hw
->wlc
->wiphy
, "wl%d\n", wlc_hw
->unit
);
1568 regs
= wlc_hw
->regs
;
1569 W_REG(®s
->tplatewrptr
, offset
);
1571 /* if MCTL_BIGEND bit set in mac control register,
1572 * the chip swaps data in fifo, as well as data in
1575 be_bit
= (R_REG(®s
->maccontrol
) & MCTL_BIGEND
) != 0;
1578 memcpy(&word
, buf
, sizeof(u32
));
1581 word
= cpu_to_be32(word
);
1583 word
= cpu_to_le32(word
);
1585 W_REG(®s
->tplatewrdata
, word
);
1587 buf
= (u8
*) buf
+ sizeof(u32
);
1592 void brcms_b_set_cwmin(struct brcms_c_hw_info
*wlc_hw
, u16 newmin
)
1594 wlc_hw
->band
->CWmin
= newmin
;
1596 W_REG(&wlc_hw
->regs
->objaddr
, OBJADDR_SCR_SEL
| S_DOT11_CWMIN
);
1597 (void)R_REG(&wlc_hw
->regs
->objaddr
);
1598 W_REG(&wlc_hw
->regs
->objdata
, newmin
);
1601 void brcms_b_set_cwmax(struct brcms_c_hw_info
*wlc_hw
, u16 newmax
)
1603 wlc_hw
->band
->CWmax
= newmax
;
1605 W_REG(&wlc_hw
->regs
->objaddr
, OBJADDR_SCR_SEL
| S_DOT11_CWMAX
);
1606 (void)R_REG(&wlc_hw
->regs
->objaddr
);
1607 W_REG(&wlc_hw
->regs
->objdata
, newmax
);
1610 void brcms_b_bw_set(struct brcms_c_hw_info
*wlc_hw
, u16 bw
)
1614 /* request FAST clock if not on */
1615 fastclk
= wlc_hw
->forcefastclk
;
1617 brcms_b_clkctl_clk(wlc_hw
, CLK_FAST
);
1619 wlc_phy_bw_state_set(wlc_hw
->band
->pi
, bw
);
1621 brcms_b_phy_reset(wlc_hw
);
1622 wlc_phy_init(wlc_hw
->band
->pi
, wlc_phy_chanspec_get(wlc_hw
->band
->pi
));
1624 /* restore the clk */
1626 brcms_b_clkctl_clk(wlc_hw
, CLK_DYNAMIC
);
1630 brcms_c_write_hw_bcntemplate0(struct brcms_c_hw_info
*wlc_hw
, void *bcn
,
1633 d11regs_t
*regs
= wlc_hw
->regs
;
1635 brcms_b_write_template_ram(wlc_hw
, T_BCN0_TPL_BASE
, (len
+ 3) & ~3,
1637 /* write beacon length to SCR */
1638 brcms_b_write_shm(wlc_hw
, M_BCN0_FRM_BYTESZ
, (u16
) len
);
1639 /* mark beacon0 valid */
1640 OR_REG(®s
->maccommand
, MCMD_BCN0VLD
);
1644 brcms_c_write_hw_bcntemplate1(struct brcms_c_hw_info
*wlc_hw
, void *bcn
,
1647 d11regs_t
*regs
= wlc_hw
->regs
;
1649 brcms_b_write_template_ram(wlc_hw
, T_BCN1_TPL_BASE
, (len
+ 3) & ~3,
1651 /* write beacon length to SCR */
1652 brcms_b_write_shm(wlc_hw
, M_BCN1_FRM_BYTESZ
, (u16
) len
);
1653 /* mark beacon1 valid */
1654 OR_REG(®s
->maccommand
, MCMD_BCN1VLD
);
1657 /* mac is assumed to be suspended at this point */
1659 brcms_b_write_hw_bcntemplates(struct brcms_c_hw_info
*wlc_hw
, void *bcn
,
1662 d11regs_t
*regs
= wlc_hw
->regs
;
1665 brcms_c_write_hw_bcntemplate0(wlc_hw
, bcn
, len
);
1666 brcms_c_write_hw_bcntemplate1(wlc_hw
, bcn
, len
);
1669 if (!(R_REG(®s
->maccommand
) & MCMD_BCN0VLD
))
1670 brcms_c_write_hw_bcntemplate0(wlc_hw
, bcn
, len
);
1673 (R_REG(®s
->maccommand
) & MCMD_BCN1VLD
))
1674 brcms_c_write_hw_bcntemplate1(wlc_hw
, bcn
, len
);
1678 static void WLBANDINITFN(brcms_b_upd_synthpu
) (struct brcms_c_hw_info
*wlc_hw
)
1681 struct brcms_c_info
*wlc
= wlc_hw
->wlc
;
1682 /* update SYNTHPU_DLY */
1684 if (WLCISLCNPHY(wlc
->band
)) {
1685 v
= SYNTHPU_DLY_LPPHY_US
;
1686 } else if (WLCISNPHY(wlc
->band
) && (NREV_GE(wlc
->band
->phyrev
, 3))) {
1687 v
= SYNTHPU_DLY_NPHY_US
;
1689 v
= SYNTHPU_DLY_BPHY_US
;
1692 brcms_b_write_shm(wlc_hw
, M_SYNTHPU_DLY
, v
);
1695 /* band-specific init */
1697 WLBANDINITFN(brcms_b_bsinit
) (struct brcms_c_info
*wlc
, chanspec_t chanspec
)
1699 struct brcms_c_hw_info
*wlc_hw
= wlc
->hw
;
1701 BCMMSG(wlc
->wiphy
, "wl%d: bandunit %d\n", wlc_hw
->unit
,
1702 wlc_hw
->band
->bandunit
);
1704 brcms_c_ucode_bsinit(wlc_hw
);
1706 wlc_phy_init(wlc_hw
->band
->pi
, chanspec
);
1708 brcms_c_ucode_txant_set(wlc_hw
);
1710 /* cwmin is band-specific, update hardware with value for current band */
1711 brcms_b_set_cwmin(wlc_hw
, wlc_hw
->band
->CWmin
);
1712 brcms_b_set_cwmax(wlc_hw
, wlc_hw
->band
->CWmax
);
1714 brcms_b_update_slot_timing(wlc_hw
,
1715 BAND_5G(wlc_hw
->band
->
1716 bandtype
) ? true : wlc_hw
->
1719 /* write phytype and phyvers */
1720 brcms_b_write_shm(wlc_hw
, M_PHYTYPE
, (u16
) wlc_hw
->band
->phytype
);
1721 brcms_b_write_shm(wlc_hw
, M_PHYVER
, (u16
) wlc_hw
->band
->phyrev
);
1723 /* initialize the txphyctl1 rate table since shmem is shared between bands */
1724 brcms_upd_ofdm_pctl1_table(wlc_hw
);
1726 brcms_b_upd_synthpu(wlc_hw
);
1729 static void brcms_b_core_phy_clk(struct brcms_c_hw_info
*wlc_hw
, bool clk
)
1731 BCMMSG(wlc_hw
->wlc
->wiphy
, "wl%d: clk %d\n", wlc_hw
->unit
, clk
);
1733 wlc_hw
->phyclk
= clk
;
1735 if (OFF
== clk
) { /* clear gmode bit, put phy into reset */
1737 ai_core_cflags(wlc_hw
->sih
, (SICF_PRST
| SICF_FGC
| SICF_GMODE
),
1738 (SICF_PRST
| SICF_FGC
));
1740 ai_core_cflags(wlc_hw
->sih
, (SICF_PRST
| SICF_FGC
), SICF_PRST
);
1743 } else { /* take phy out of reset */
1745 ai_core_cflags(wlc_hw
->sih
, (SICF_PRST
| SICF_FGC
), SICF_FGC
);
1747 ai_core_cflags(wlc_hw
->sih
, (SICF_FGC
), 0);
1753 /* Perform a soft reset of the PHY PLL */
1754 void brcms_b_core_phypll_reset(struct brcms_c_hw_info
*wlc_hw
)
1756 BCMMSG(wlc_hw
->wlc
->wiphy
, "wl%d\n", wlc_hw
->unit
);
1758 ai_corereg(wlc_hw
->sih
, SI_CC_IDX
,
1759 offsetof(chipcregs_t
, chipcontrol_addr
), ~0, 0);
1761 ai_corereg(wlc_hw
->sih
, SI_CC_IDX
,
1762 offsetof(chipcregs_t
, chipcontrol_data
), 0x4, 0);
1764 ai_corereg(wlc_hw
->sih
, SI_CC_IDX
,
1765 offsetof(chipcregs_t
, chipcontrol_data
), 0x4, 4);
1767 ai_corereg(wlc_hw
->sih
, SI_CC_IDX
,
1768 offsetof(chipcregs_t
, chipcontrol_data
), 0x4, 0);
1772 /* light way to turn on phy clock without reset for NPHY only
1773 * refer to brcms_b_core_phy_clk for full version
1775 void brcms_b_phyclk_fgc(struct brcms_c_hw_info
*wlc_hw
, bool clk
)
1777 /* support(necessary for NPHY and HYPHY) only */
1778 if (!WLCISNPHY(wlc_hw
->band
))
1782 ai_core_cflags(wlc_hw
->sih
, SICF_FGC
, SICF_FGC
);
1784 ai_core_cflags(wlc_hw
->sih
, SICF_FGC
, 0);
1788 void brcms_b_macphyclk_set(struct brcms_c_hw_info
*wlc_hw
, bool clk
)
1791 ai_core_cflags(wlc_hw
->sih
, SICF_MPCLKE
, SICF_MPCLKE
);
1793 ai_core_cflags(wlc_hw
->sih
, SICF_MPCLKE
, 0);
1796 void brcms_b_phy_reset(struct brcms_c_hw_info
*wlc_hw
)
1798 wlc_phy_t
*pih
= wlc_hw
->band
->pi
;
1800 bool phy_in_reset
= false;
1802 BCMMSG(wlc_hw
->wlc
->wiphy
, "wl%d\n", wlc_hw
->unit
);
1807 phy_bw_clkbits
= wlc_phy_clk_bwbits(wlc_hw
->band
->pi
);
1809 /* Specific reset sequence required for NPHY rev 3 and 4 */
1810 if (WLCISNPHY(wlc_hw
->band
) && NREV_GE(wlc_hw
->band
->phyrev
, 3) &&
1811 NREV_LE(wlc_hw
->band
->phyrev
, 4)) {
1812 /* Set the PHY bandwidth */
1813 ai_core_cflags(wlc_hw
->sih
, SICF_BWMASK
, phy_bw_clkbits
);
1817 /* Perform a soft reset of the PHY PLL */
1818 brcms_b_core_phypll_reset(wlc_hw
);
1821 ai_core_cflags(wlc_hw
->sih
, (SICF_PRST
| SICF_PCLKE
),
1822 (SICF_PRST
| SICF_PCLKE
));
1823 phy_in_reset
= true;
1826 ai_core_cflags(wlc_hw
->sih
,
1827 (SICF_PRST
| SICF_PCLKE
| SICF_BWMASK
),
1828 (SICF_PRST
| SICF_PCLKE
| phy_bw_clkbits
));
1832 brcms_b_core_phy_clk(wlc_hw
, ON
);
1835 wlc_phy_anacore(pih
, ON
);
1838 /* switch to and initialize new band */
1840 WLBANDINITFN(brcms_b_setband
) (struct brcms_c_hw_info
*wlc_hw
, uint bandunit
,
1841 chanspec_t chanspec
) {
1842 struct brcms_c_info
*wlc
= wlc_hw
->wlc
;
1845 /* Enable the d11 core before accessing it */
1846 if (!ai_iscoreup(wlc_hw
->sih
)) {
1847 ai_core_reset(wlc_hw
->sih
, 0, 0);
1848 brcms_c_mctrl_reset(wlc_hw
);
1851 macintmask
= brcms_c_setband_inact(wlc
, bandunit
);
1856 brcms_b_core_phy_clk(wlc_hw
, ON
);
1858 /* band-specific initializations */
1859 brcms_b_bsinit(wlc
, chanspec
);
1862 * If there are any pending software interrupt bits,
1863 * then replace these with a harmless nonzero value
1864 * so brcms_c_dpc() will re-enable interrupts when done.
1866 if (wlc
->macintstatus
)
1867 wlc
->macintstatus
= MI_DMAINT
;
1869 /* restore macintmask */
1870 brcms_intrsrestore(wlc
->wl
, macintmask
);
1872 /* ucode should still be suspended.. */
1873 WARN_ON((R_REG(&wlc_hw
->regs
->maccontrol
) & MCTL_EN_MAC
) != 0);
1876 /* low-level band switch utility routine */
1877 void WLBANDINITFN(brcms_c_setxband
) (struct brcms_c_hw_info
*wlc_hw
,
1880 BCMMSG(wlc_hw
->wlc
->wiphy
, "wl%d: bandunit %d\n", wlc_hw
->unit
,
1883 wlc_hw
->band
= wlc_hw
->bandstate
[bandunit
];
1885 /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
1886 wlc_hw
->wlc
->band
= wlc_hw
->wlc
->bandstate
[bandunit
];
1888 /* set gmode core flag */
1889 if (wlc_hw
->sbclk
&& !wlc_hw
->noreset
) {
1890 ai_core_cflags(wlc_hw
->sih
, SICF_GMODE
,
1891 ((bandunit
== 0) ? SICF_GMODE
: 0));
1895 static bool brcms_c_isgoodchip(struct brcms_c_hw_info
*wlc_hw
)
1898 /* reject unsupported corerev */
1899 if (!VALID_COREREV(wlc_hw
->corerev
)) {
1900 wiphy_err(wlc_hw
->wlc
->wiphy
, "unsupported core rev %d\n",
1908 static bool brcms_c_validboardtype(struct brcms_c_hw_info
*wlc_hw
)
1910 bool goodboard
= true;
1911 uint boardrev
= wlc_hw
->boardrev
;
1915 else if (boardrev
> 0xff) {
1916 uint brt
= (boardrev
& 0xf000) >> 12;
1917 uint b0
= (boardrev
& 0xf00) >> 8;
1918 uint b1
= (boardrev
& 0xf0) >> 4;
1919 uint b2
= boardrev
& 0xf;
1921 if ((brt
> 2) || (brt
== 0) || (b0
> 9) || (b0
== 0) || (b1
> 9)
1926 if (wlc_hw
->sih
->boardvendor
!= PCI_VENDOR_ID_BROADCOM
)
1932 static char *brcms_c_get_macaddr(struct brcms_c_hw_info
*wlc_hw
)
1934 const char *varname
= "macaddr";
1937 /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1938 macaddr
= getvar(wlc_hw
->vars
, varname
);
1939 if (macaddr
!= NULL
)
1942 if (NBANDS_HW(wlc_hw
) > 1)
1943 varname
= "et1macaddr";
1945 varname
= "il0macaddr";
1947 macaddr
= getvar(wlc_hw
->vars
, varname
);
1948 if (macaddr
== NULL
) {
1949 wiphy_err(wlc_hw
->wlc
->wiphy
, "wl%d: wlc_get_macaddr: macaddr "
1950 "getvar(%s) not found\n", wlc_hw
->unit
, varname
);
1957 * Return true if radio is disabled, otherwise false.
1958 * hw radio disable signal is an external pin, users activate it asynchronously
1959 * this function could be called when driver is down and w/o clock
1960 * it operates on different registers depending on corerev and boardflag.
1962 bool brcms_b_radio_read_hwdisabled(struct brcms_c_hw_info
*wlc_hw
)
1965 u32 resetbits
= 0, flags
= 0;
1967 xtal
= wlc_hw
->sbclk
;
1969 brcms_b_xtal(wlc_hw
, ON
);
1971 /* may need to take core out of reset first */
1975 * mac no longer enables phyclk automatically when driver
1976 * accesses phyreg throughput mac. This can be skipped since
1977 * only mac reg is accessed below
1979 flags
|= SICF_PCLKE
;
1981 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
1982 if ((wlc_hw
->sih
->chip
== BCM43224_CHIP_ID
) ||
1983 (wlc_hw
->sih
->chip
== BCM43225_CHIP_ID
))
1985 (d11regs_t
*) ai_setcore(wlc_hw
->sih
, D11_CORE_ID
,
1987 ai_core_reset(wlc_hw
->sih
, flags
, resetbits
);
1988 brcms_c_mctrl_reset(wlc_hw
);
1991 v
= ((R_REG(&wlc_hw
->regs
->phydebug
) & PDBG_RFD
) != 0);
1993 /* put core back into reset */
1995 ai_core_disable(wlc_hw
->sih
, 0);
1998 brcms_b_xtal(wlc_hw
, OFF
);
2003 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
2004 void brcms_b_hw_up(struct brcms_c_hw_info
*wlc_hw
)
2006 if (wlc_hw
->wlc
->pub
->hw_up
)
2009 BCMMSG(wlc_hw
->wlc
->wiphy
, "wl%d\n", wlc_hw
->unit
);
2012 * Enable pll and xtal, initialize the power control registers,
2013 * and force fastclock for the remainder of brcms_c_up().
2015 brcms_b_xtal(wlc_hw
, ON
);
2016 ai_clkctl_init(wlc_hw
->sih
);
2017 brcms_b_clkctl_clk(wlc_hw
, CLK_FAST
);
2019 if (wlc_hw
->sih
->bustype
== PCI_BUS
) {
2020 ai_pci_fixcfg(wlc_hw
->sih
);
2022 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2023 if ((wlc_hw
->sih
->chip
== BCM43224_CHIP_ID
) ||
2024 (wlc_hw
->sih
->chip
== BCM43225_CHIP_ID
))
2026 (d11regs_t
*) ai_setcore(wlc_hw
->sih
, D11_CORE_ID
,
2030 /* Inform phy that a POR reset has occurred so it does a complete phy init */
2031 wlc_phy_por_inform(wlc_hw
->band
->pi
);
2033 wlc_hw
->ucode_loaded
= false;
2034 wlc_hw
->wlc
->pub
->hw_up
= true;
2036 if ((wlc_hw
->boardflags
& BFL_FEM
)
2037 && (wlc_hw
->sih
->chip
== BCM4313_CHIP_ID
)) {
2039 (wlc_hw
->boardrev
>= 0x1250
2040 && (wlc_hw
->boardflags
& BFL_FEM_BT
)))
2041 ai_epa_4313war(wlc_hw
->sih
);
2045 static bool wlc_dma_rxreset(struct brcms_c_hw_info
*wlc_hw
, uint fifo
)
2047 struct dma_pub
*di
= wlc_hw
->di
[fifo
];
2048 return dma_rxreset(di
);
2052 * ensure fask clock during reset
2054 * reset d11(out of reset)
2055 * reset phy(out of reset)
2056 * clear software macintstatus for fresh new start
2057 * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2059 void brcms_b_corereset(struct brcms_c_hw_info
*wlc_hw
, u32 flags
)
2066 if (flags
== WLC_USE_COREFLAGS
)
2067 flags
= (wlc_hw
->band
->pi
? wlc_hw
->band
->core_flags
: 0);
2069 BCMMSG(wlc_hw
->wlc
->wiphy
, "wl%d\n", wlc_hw
->unit
);
2071 regs
= wlc_hw
->regs
;
2073 /* request FAST clock if not on */
2074 fastclk
= wlc_hw
->forcefastclk
;
2076 brcms_b_clkctl_clk(wlc_hw
, CLK_FAST
);
2078 /* reset the dma engines except first time thru */
2079 if (ai_iscoreup(wlc_hw
->sih
)) {
2080 for (i
= 0; i
< NFIFO
; i
++)
2081 if ((wlc_hw
->di
[i
]) && (!dma_txreset(wlc_hw
->di
[i
]))) {
2082 wiphy_err(wlc_hw
->wlc
->wiphy
, "wl%d: %s: "
2083 "dma_txreset[%d]: cannot stop dma\n",
2084 wlc_hw
->unit
, __func__
, i
);
2087 if ((wlc_hw
->di
[RX_FIFO
])
2088 && (!wlc_dma_rxreset(wlc_hw
, RX_FIFO
))) {
2089 wiphy_err(wlc_hw
->wlc
->wiphy
, "wl%d: %s: dma_rxreset"
2090 "[%d]: cannot stop dma\n",
2091 wlc_hw
->unit
, __func__
, RX_FIFO
);
2094 /* if noreset, just stop the psm and return */
2095 if (wlc_hw
->noreset
) {
2096 wlc_hw
->wlc
->macintstatus
= 0; /* skip wl_dpc after down */
2097 brcms_b_mctrl(wlc_hw
, MCTL_PSM_RUN
| MCTL_EN_MAC
, 0);
2102 * mac no longer enables phyclk automatically when driver accesses
2103 * phyreg throughput mac, AND phy_reset is skipped at early stage when
2104 * band->pi is invalid. need to enable PHY CLK
2106 flags
|= SICF_PCLKE
;
2109 * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2110 * is cleared by the core_reset. have to re-request it.
2111 * This adds some delay and we can optimize it by also requesting fastclk through
2112 * chipcommon during this period if necessary. But that has to work coordinate
2113 * with other driver like mips/arm since they may touch chipcommon as well.
2115 wlc_hw
->clk
= false;
2116 ai_core_reset(wlc_hw
->sih
, flags
, resetbits
);
2118 if (wlc_hw
->band
&& wlc_hw
->band
->pi
)
2119 wlc_phy_hw_clk_state_upd(wlc_hw
->band
->pi
, true);
2121 brcms_c_mctrl_reset(wlc_hw
);
2123 if (PMUCTL_ENAB(wlc_hw
->sih
))
2124 brcms_b_clkctl_clk(wlc_hw
, CLK_FAST
);
2126 brcms_b_phy_reset(wlc_hw
);
2128 /* turn on PHY_PLL */
2129 brcms_b_core_phypll_ctl(wlc_hw
, true);
2131 /* clear sw intstatus */
2132 wlc_hw
->wlc
->macintstatus
= 0;
2134 /* restore the clk setting */
2136 brcms_b_clkctl_clk(wlc_hw
, CLK_DYNAMIC
);
2139 /* txfifo sizes needs to be modified(increased) since the newer cores
2142 static void brcms_b_corerev_fifofixup(struct brcms_c_hw_info
*wlc_hw
)
2144 d11regs_t
*regs
= wlc_hw
->regs
;
2146 u16 txfifo_startblk
= TXFIFO_START_BLK
, txfifo_endblk
;
2147 u16 txfifo_def
, txfifo_def1
;
2150 /* tx fifos start at TXFIFO_START_BLK from the Base address */
2151 txfifo_startblk
= TXFIFO_START_BLK
;
2153 /* sequence of operations: reset fifo, set fifo size, reset fifo */
2154 for (fifo_nu
= 0; fifo_nu
< NFIFO
; fifo_nu
++) {
2156 txfifo_endblk
= txfifo_startblk
+ wlc_hw
->xmtfifo_sz
[fifo_nu
];
2157 txfifo_def
= (txfifo_startblk
& 0xff) |
2158 (((txfifo_endblk
- 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT
);
2159 txfifo_def1
= ((txfifo_startblk
>> 8) & 0x1) |
2161 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT
);
2163 TXFIFOCMD_RESET_MASK
| (fifo_nu
<< TXFIFOCMD_FIFOSEL_SHIFT
);
2165 W_REG(®s
->xmtfifocmd
, txfifo_cmd
);
2166 W_REG(®s
->xmtfifodef
, txfifo_def
);
2167 W_REG(®s
->xmtfifodef1
, txfifo_def1
);
2169 W_REG(®s
->xmtfifocmd
, txfifo_cmd
);
2171 txfifo_startblk
+= wlc_hw
->xmtfifo_sz
[fifo_nu
];
2174 * need to propagate to shm location to be in sync since ucode/hw won't
2177 brcms_b_write_shm(wlc_hw
, M_FIFOSIZE0
,
2178 wlc_hw
->xmtfifo_sz
[TX_AC_BE_FIFO
]);
2179 brcms_b_write_shm(wlc_hw
, M_FIFOSIZE1
,
2180 wlc_hw
->xmtfifo_sz
[TX_AC_VI_FIFO
]);
2181 brcms_b_write_shm(wlc_hw
, M_FIFOSIZE2
,
2182 ((wlc_hw
->xmtfifo_sz
[TX_AC_VO_FIFO
] << 8) | wlc_hw
->
2183 xmtfifo_sz
[TX_AC_BK_FIFO
]));
2184 brcms_b_write_shm(wlc_hw
, M_FIFOSIZE3
,
2185 ((wlc_hw
->xmtfifo_sz
[TX_ATIM_FIFO
] << 8) | wlc_hw
->
2186 xmtfifo_sz
[TX_BCMC_FIFO
]));
2191 * download ucode/PCM
2192 * let ucode run to suspended
2193 * download ucode inits
2194 * config other core registers
2197 static void brcms_b_coreinit(struct brcms_c_info
*wlc
)
2199 struct brcms_c_hw_info
*wlc_hw
= wlc
->hw
;
2204 bool fifosz_fixup
= false;
2207 struct wiphy
*wiphy
= wlc
->wiphy
;
2209 regs
= wlc_hw
->regs
;
2211 BCMMSG(wlc
->wiphy
, "wl%d\n", wlc_hw
->unit
);
2214 brcms_b_mctrl(wlc_hw
, ~0, (MCTL_IHR_EN
| MCTL_PSM_JMP_0
| MCTL_WAKE
));
2216 brcms_ucode_download(wlc_hw
);
2218 * FIFOSZ fixup. driver wants to controls the fifo allocation.
2220 fifosz_fixup
= true;
2222 /* let the PSM run to the suspended state, set mode to BSS STA */
2223 W_REG(®s
->macintstatus
, -1);
2224 brcms_b_mctrl(wlc_hw
, ~0,
2225 (MCTL_IHR_EN
| MCTL_INFRA
| MCTL_PSM_RUN
| MCTL_WAKE
));
2227 /* wait for ucode to self-suspend after auto-init */
2228 SPINWAIT(((R_REG(®s
->macintstatus
) & MI_MACSSPNDD
) == 0),
2230 if ((R_REG(®s
->macintstatus
) & MI_MACSSPNDD
) == 0)
2231 wiphy_err(wiphy
, "wl%d: wlc_coreinit: ucode did not self-"
2232 "suspend!\n", wlc_hw
->unit
);
2234 brcms_c_gpio_init(wlc
);
2236 sflags
= ai_core_sflags(wlc_hw
->sih
, 0, 0);
2238 if (D11REV_IS(wlc_hw
->corerev
, 23)) {
2239 if (WLCISNPHY(wlc_hw
->band
))
2240 brcms_c_write_inits(wlc_hw
, d11n0initvals16
);
2242 wiphy_err(wiphy
, "%s: wl%d: unsupported phy in corerev"
2243 " %d\n", __func__
, wlc_hw
->unit
,
2245 } else if (D11REV_IS(wlc_hw
->corerev
, 24)) {
2246 if (WLCISLCNPHY(wlc_hw
->band
)) {
2247 brcms_c_write_inits(wlc_hw
, d11lcn0initvals24
);
2249 wiphy_err(wiphy
, "%s: wl%d: unsupported phy in corerev"
2250 " %d\n", __func__
, wlc_hw
->unit
,
2254 wiphy_err(wiphy
, "%s: wl%d: unsupported corerev %d\n",
2255 __func__
, wlc_hw
->unit
, wlc_hw
->corerev
);
2258 /* For old ucode, txfifo sizes needs to be modified(increased) */
2259 if (fifosz_fixup
== true) {
2260 brcms_b_corerev_fifofixup(wlc_hw
);
2263 /* check txfifo allocations match between ucode and driver */
2264 buf
[TX_AC_BE_FIFO
] = brcms_b_read_shm(wlc_hw
, M_FIFOSIZE0
);
2265 if (buf
[TX_AC_BE_FIFO
] != wlc_hw
->xmtfifo_sz
[TX_AC_BE_FIFO
]) {
2269 buf
[TX_AC_VI_FIFO
] = brcms_b_read_shm(wlc_hw
, M_FIFOSIZE1
);
2270 if (buf
[TX_AC_VI_FIFO
] != wlc_hw
->xmtfifo_sz
[TX_AC_VI_FIFO
]) {
2274 buf
[TX_AC_BK_FIFO
] = brcms_b_read_shm(wlc_hw
, M_FIFOSIZE2
);
2275 buf
[TX_AC_VO_FIFO
] = (buf
[TX_AC_BK_FIFO
] >> 8) & 0xff;
2276 buf
[TX_AC_BK_FIFO
] &= 0xff;
2277 if (buf
[TX_AC_BK_FIFO
] != wlc_hw
->xmtfifo_sz
[TX_AC_BK_FIFO
]) {
2281 if (buf
[TX_AC_VO_FIFO
] != wlc_hw
->xmtfifo_sz
[TX_AC_VO_FIFO
]) {
2285 buf
[TX_BCMC_FIFO
] = brcms_b_read_shm(wlc_hw
, M_FIFOSIZE3
);
2286 buf
[TX_ATIM_FIFO
] = (buf
[TX_BCMC_FIFO
] >> 8) & 0xff;
2287 buf
[TX_BCMC_FIFO
] &= 0xff;
2288 if (buf
[TX_BCMC_FIFO
] != wlc_hw
->xmtfifo_sz
[TX_BCMC_FIFO
]) {
2292 if (buf
[TX_ATIM_FIFO
] != wlc_hw
->xmtfifo_sz
[TX_ATIM_FIFO
]) {
2297 wiphy_err(wiphy
, "wlc_coreinit: txfifo mismatch: ucode size %d"
2298 " driver size %d index %d\n", buf
[i
],
2299 wlc_hw
->xmtfifo_sz
[i
], i
);
2302 /* make sure we can still talk to the mac */
2303 WARN_ON(R_REG(®s
->maccontrol
) == 0xffffffff);
2305 /* band-specific inits done by wlc_bsinit() */
2307 /* Set up frame burst size and antenna swap threshold init values */
2308 brcms_b_write_shm(wlc_hw
, M_MBURST_SIZE
, MAXTXFRAMEBURST
);
2309 brcms_b_write_shm(wlc_hw
, M_MAX_ANTCNT
, ANTCNT
);
2311 /* enable one rx interrupt per received frame */
2312 W_REG(®s
->intrcvlazy
[0], (1 << IRL_FC_SHIFT
));
2314 /* set the station mode (BSS STA) */
2315 brcms_b_mctrl(wlc_hw
,
2316 (MCTL_INFRA
| MCTL_DISCARD_PMQ
| MCTL_AP
),
2317 (MCTL_INFRA
| MCTL_DISCARD_PMQ
));
2319 /* set up Beacon interval */
2320 bcnint_us
= 0x8000 << 10;
2321 W_REG(®s
->tsf_cfprep
, (bcnint_us
<< CFPREP_CBI_SHIFT
));
2322 W_REG(®s
->tsf_cfpstart
, bcnint_us
);
2323 W_REG(®s
->macintstatus
, MI_GP1
);
2325 /* write interrupt mask */
2326 W_REG(®s
->intctrlregs
[RX_FIFO
].intmask
, DEF_RXINTMASK
);
2328 /* allow the MAC to control the PHY clock (dynamic on/off) */
2329 brcms_b_macphyclk_set(wlc_hw
, ON
);
2331 /* program dynamic clock control fast powerup delay register */
2332 wlc
->fastpwrup_dly
= ai_clkctl_fast_pwrup_delay(wlc_hw
->sih
);
2333 W_REG(®s
->scc_fastpwrup_dly
, wlc
->fastpwrup_dly
);
2335 /* tell the ucode the corerev */
2336 brcms_b_write_shm(wlc_hw
, M_MACHW_VER
, (u16
) wlc_hw
->corerev
);
2338 /* tell the ucode MAC capabilities */
2339 brcms_b_write_shm(wlc_hw
, M_MACHW_CAP_L
,
2340 (u16
) (wlc_hw
->machwcap
& 0xffff));
2341 brcms_b_write_shm(wlc_hw
, M_MACHW_CAP_H
,
2343 machwcap
>> 16) & 0xffff));
2345 /* write retry limits to SCR, this done after PSM init */
2346 W_REG(®s
->objaddr
, OBJADDR_SCR_SEL
| S_DOT11_SRC_LMT
);
2347 (void)R_REG(®s
->objaddr
);
2348 W_REG(®s
->objdata
, wlc_hw
->SRL
);
2349 W_REG(®s
->objaddr
, OBJADDR_SCR_SEL
| S_DOT11_LRC_LMT
);
2350 (void)R_REG(®s
->objaddr
);
2351 W_REG(®s
->objdata
, wlc_hw
->LRL
);
2353 /* write rate fallback retry limits */
2354 brcms_b_write_shm(wlc_hw
, M_SFRMTXCNTFBRTHSD
, wlc_hw
->SFBL
);
2355 brcms_b_write_shm(wlc_hw
, M_LFRMTXCNTFBRTHSD
, wlc_hw
->LFBL
);
2357 AND_REG(®s
->ifs_ctl
, 0x0FFF);
2358 W_REG(®s
->ifs_aifsn
, EDCF_AIFSN_MIN
);
2360 /* dma initializations */
2361 wlc
->txpend16165war
= 0;
2363 /* init the tx dma engines */
2364 for (i
= 0; i
< NFIFO
; i
++) {
2366 dma_txinit(wlc_hw
->di
[i
]);
2369 /* init the rx dma engine(s) and post receive buffers */
2370 dma_rxinit(wlc_hw
->di
[RX_FIFO
]);
2371 dma_rxfill(wlc_hw
->di
[RX_FIFO
]);
2374 /* This function is used for changing the tsf frac register
2375 * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2376 * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2377 * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2378 * HTPHY Formula is 2^26/freq(MHz) e.g.
2379 * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2380 * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2381 * For spuron: 123MHz -> 2^26/123 = 545600.5
2382 * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2383 * For spur off: 120MHz -> 2^26/120 = 559240.5
2384 * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2387 void brcms_b_switch_macfreq(struct brcms_c_hw_info
*wlc_hw
, u8 spurmode
)
2390 regs
= wlc_hw
->regs
;
2392 if ((wlc_hw
->sih
->chip
== BCM43224_CHIP_ID
) ||
2393 (wlc_hw
->sih
->chip
== BCM43225_CHIP_ID
)) {
2394 if (spurmode
== WL_SPURAVOID_ON2
) { /* 126Mhz */
2395 W_REG(®s
->tsf_clk_frac_l
, 0x2082);
2396 W_REG(®s
->tsf_clk_frac_h
, 0x8);
2397 } else if (spurmode
== WL_SPURAVOID_ON1
) { /* 123Mhz */
2398 W_REG(®s
->tsf_clk_frac_l
, 0x5341);
2399 W_REG(®s
->tsf_clk_frac_h
, 0x8);
2400 } else { /* 120Mhz */
2401 W_REG(®s
->tsf_clk_frac_l
, 0x8889);
2402 W_REG(®s
->tsf_clk_frac_h
, 0x8);
2404 } else if (WLCISLCNPHY(wlc_hw
->band
)) {
2405 if (spurmode
== WL_SPURAVOID_ON1
) { /* 82Mhz */
2406 W_REG(®s
->tsf_clk_frac_l
, 0x7CE0);
2407 W_REG(®s
->tsf_clk_frac_h
, 0xC);
2408 } else { /* 80Mhz */
2409 W_REG(®s
->tsf_clk_frac_l
, 0xCCCD);
2410 W_REG(®s
->tsf_clk_frac_h
, 0xC);
2415 /* Initialize GPIOs that are controlled by D11 core */
2416 static void brcms_c_gpio_init(struct brcms_c_info
*wlc
)
2418 struct brcms_c_hw_info
*wlc_hw
= wlc
->hw
;
2422 regs
= wlc_hw
->regs
;
2424 /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2425 brcms_b_mctrl(wlc_hw
, MCTL_GPOUT_SEL_MASK
, 0);
2428 * Common GPIO setup:
2429 * G0 = LED 0 = WLAN Activity
2430 * G1 = LED 1 = WLAN 2.4 GHz Radio State
2431 * G2 = LED 2 = WLAN 5 GHz Radio State
2432 * G4 = radio disable input (HI enabled, LO disabled)
2437 /* Allocate GPIOs for mimo antenna diversity feature */
2438 if (wlc_hw
->antsel_type
== ANTSEL_2x3
) {
2439 /* Enable antenna diversity, use 2x3 mode */
2440 brcms_b_mhf(wlc_hw
, MHF3
, MHF3_ANTSEL_EN
,
2441 MHF3_ANTSEL_EN
, WLC_BAND_ALL
);
2442 brcms_b_mhf(wlc_hw
, MHF3
, MHF3_ANTSEL_MODE
,
2443 MHF3_ANTSEL_MODE
, WLC_BAND_ALL
);
2445 /* init superswitch control */
2446 wlc_phy_antsel_init(wlc_hw
->band
->pi
, false);
2448 } else if (wlc_hw
->antsel_type
== ANTSEL_2x4
) {
2449 gm
|= gc
|= (BOARD_GPIO_12
| BOARD_GPIO_13
);
2451 * The board itself is powered by these GPIOs
2452 * (when not sending pattern) so set them high
2454 OR_REG(®s
->psm_gpio_oe
,
2455 (BOARD_GPIO_12
| BOARD_GPIO_13
));
2456 OR_REG(®s
->psm_gpio_out
,
2457 (BOARD_GPIO_12
| BOARD_GPIO_13
));
2459 /* Enable antenna diversity, use 2x4 mode */
2460 brcms_b_mhf(wlc_hw
, MHF3
, MHF3_ANTSEL_EN
,
2461 MHF3_ANTSEL_EN
, WLC_BAND_ALL
);
2462 brcms_b_mhf(wlc_hw
, MHF3
, MHF3_ANTSEL_MODE
, 0,
2465 /* Configure the desired clock to be 4Mhz */
2466 brcms_b_write_shm(wlc_hw
, M_ANTSEL_CLKDIV
,
2467 ANTSEL_CLKDIV_4MHZ
);
2470 /* gpio 9 controls the PA. ucode is responsible for wiggling out and oe */
2471 if (wlc_hw
->boardflags
& BFL_PACTRL
)
2472 gm
|= gc
|= BOARD_GPIO_PACTRL
;
2474 /* apply to gpiocontrol register */
2475 ai_gpiocontrol(wlc_hw
->sih
, gm
, gc
, GPIO_DRV_PRIORITY
);
2478 static void brcms_ucode_download(struct brcms_c_hw_info
*wlc_hw
)
2480 struct brcms_c_info
*wlc
;
2483 if (wlc_hw
->ucode_loaded
)
2486 if (D11REV_IS(wlc_hw
->corerev
, 23)) {
2487 if (WLCISNPHY(wlc_hw
->band
)) {
2488 brcms_ucode_write(wlc_hw
, bcm43xx_16_mimo
,
2490 wlc_hw
->ucode_loaded
= true;
2492 wiphy_err(wlc
->wiphy
, "%s: wl%d: unsupported phy in "
2494 __func__
, wlc_hw
->unit
, wlc_hw
->corerev
);
2495 } else if (D11REV_IS(wlc_hw
->corerev
, 24)) {
2496 if (WLCISLCNPHY(wlc_hw
->band
)) {
2497 brcms_ucode_write(wlc_hw
, bcm43xx_24_lcn
,
2499 wlc_hw
->ucode_loaded
= true;
2501 wiphy_err(wlc
->wiphy
, "%s: wl%d: unsupported phy in "
2503 __func__
, wlc_hw
->unit
, wlc_hw
->corerev
);
2508 static void brcms_ucode_write(struct brcms_c_hw_info
*wlc_hw
, const u32 ucode
[],
2509 const uint nbytes
) {
2510 d11regs_t
*regs
= wlc_hw
->regs
;
2514 BCMMSG(wlc_hw
->wlc
->wiphy
, "wl%d\n", wlc_hw
->unit
);
2516 count
= (nbytes
/ sizeof(u32
));
2518 W_REG(®s
->objaddr
, (OBJADDR_AUTO_INC
| OBJADDR_UCM_SEL
));
2519 (void)R_REG(®s
->objaddr
);
2520 for (i
= 0; i
< count
; i
++)
2521 W_REG(®s
->objdata
, ucode
[i
]);
2524 static void brcms_c_write_inits(struct brcms_c_hw_info
*wlc_hw
,
2525 const struct d11init
*inits
)
2530 BCMMSG(wlc_hw
->wlc
->wiphy
, "wl%d\n", wlc_hw
->unit
);
2532 base
= (volatile u8
*)wlc_hw
->regs
;
2534 for (i
= 0; inits
[i
].addr
!= 0xffff; i
++) {
2535 if (inits
[i
].size
== 2)
2536 W_REG((u16
*)(base
+ inits
[i
].addr
),
2538 else if (inits
[i
].size
== 4)
2539 W_REG((u32
*)(base
+ inits
[i
].addr
),
2544 static void brcms_c_ucode_txant_set(struct brcms_c_hw_info
*wlc_hw
)
2547 u16 phytxant
= wlc_hw
->bmac_phytxant
;
2548 u16 mask
= PHY_TXC_ANT_MASK
;
2550 /* set the Probe Response frame phy control word */
2551 phyctl
= brcms_b_read_shm(wlc_hw
, M_CTXPRS_BLK
+ C_CTX_PCTLWD_POS
);
2552 phyctl
= (phyctl
& ~mask
) | phytxant
;
2553 brcms_b_write_shm(wlc_hw
, M_CTXPRS_BLK
+ C_CTX_PCTLWD_POS
, phyctl
);
2555 /* set the Response (ACK/CTS) frame phy control word */
2556 phyctl
= brcms_b_read_shm(wlc_hw
, M_RSP_PCTLWD
);
2557 phyctl
= (phyctl
& ~mask
) | phytxant
;
2558 brcms_b_write_shm(wlc_hw
, M_RSP_PCTLWD
, phyctl
);
2561 void brcms_b_txant_set(struct brcms_c_hw_info
*wlc_hw
, u16 phytxant
)
2563 /* update sw state */
2564 wlc_hw
->bmac_phytxant
= phytxant
;
2566 /* push to ucode if up */
2569 brcms_c_ucode_txant_set(wlc_hw
);
2573 u16
brcms_b_get_txant(struct brcms_c_hw_info
*wlc_hw
)
2575 return (u16
) wlc_hw
->wlc
->stf
->txant
;
2578 void brcms_b_antsel_type_set(struct brcms_c_hw_info
*wlc_hw
, u8 antsel_type
)
2580 wlc_hw
->antsel_type
= antsel_type
;
2582 /* Update the antsel type for phy module to use */
2583 wlc_phy_antsel_type_set(wlc_hw
->band
->pi
, antsel_type
);
2586 void brcms_b_fifoerrors(struct brcms_c_hw_info
*wlc_hw
)
2590 uint intstatus
, idx
;
2591 d11regs_t
*regs
= wlc_hw
->regs
;
2592 struct wiphy
*wiphy
= wlc_hw
->wlc
->wiphy
;
2594 unit
= wlc_hw
->unit
;
2596 for (idx
= 0; idx
< NFIFO
; idx
++) {
2597 /* read intstatus register and ignore any non-error bits */
2599 R_REG(®s
->intctrlregs
[idx
].intstatus
) & I_ERRORS
;
2603 BCMMSG(wlc_hw
->wlc
->wiphy
, "wl%d: intstatus%d 0x%x\n",
2604 unit
, idx
, intstatus
);
2606 if (intstatus
& I_RO
) {
2607 wiphy_err(wiphy
, "wl%d: fifo %d: receive fifo "
2608 "overflow\n", unit
, idx
);
2612 if (intstatus
& I_PC
) {
2613 wiphy_err(wiphy
, "wl%d: fifo %d: descriptor error\n",
2618 if (intstatus
& I_PD
) {
2619 wiphy_err(wiphy
, "wl%d: fifo %d: data error\n", unit
,
2624 if (intstatus
& I_DE
) {
2625 wiphy_err(wiphy
, "wl%d: fifo %d: descriptor protocol "
2626 "error\n", unit
, idx
);
2630 if (intstatus
& I_RU
) {
2631 wiphy_err(wiphy
, "wl%d: fifo %d: receive descriptor "
2632 "underflow\n", idx
, unit
);
2635 if (intstatus
& I_XU
) {
2636 wiphy_err(wiphy
, "wl%d: fifo %d: transmit fifo "
2637 "underflow\n", idx
, unit
);
2642 brcms_c_fatal_error(wlc_hw
->wlc
); /* big hammer */
2645 W_REG(®s
->intctrlregs
[idx
].intstatus
,
2650 void brcms_c_intrson(struct brcms_c_info
*wlc
)
2652 struct brcms_c_hw_info
*wlc_hw
= wlc
->hw
;
2653 wlc
->macintmask
= wlc
->defmacintmask
;
2654 W_REG(&wlc_hw
->regs
->macintmask
, wlc
->macintmask
);
2657 /* callback for siutils.c, which has only wlc handler, no wl
2658 * they both check up, not only because there is no need to off/restore d11 interrupt
2659 * but also because per-port code may require sync with valid interrupt.
2662 static u32
brcms_c_wlintrsoff(struct brcms_c_info
*wlc
)
2667 return brcms_intrsoff(wlc
->wl
);
2670 static void brcms_c_wlintrsrestore(struct brcms_c_info
*wlc
, u32 macintmask
)
2675 brcms_intrsrestore(wlc
->wl
, macintmask
);
2678 u32
brcms_c_intrsoff(struct brcms_c_info
*wlc
)
2680 struct brcms_c_hw_info
*wlc_hw
= wlc
->hw
;
2686 macintmask
= wlc
->macintmask
; /* isr can still happen */
2688 W_REG(&wlc_hw
->regs
->macintmask
, 0);
2689 (void)R_REG(&wlc_hw
->regs
->macintmask
); /* sync readback */
2690 udelay(1); /* ensure int line is no longer driven */
2691 wlc
->macintmask
= 0;
2693 /* return previous macintmask; resolve race between us and our isr */
2694 return wlc
->macintstatus
? 0 : macintmask
;
2697 void brcms_c_intrsrestore(struct brcms_c_info
*wlc
, u32 macintmask
)
2699 struct brcms_c_hw_info
*wlc_hw
= wlc
->hw
;
2703 wlc
->macintmask
= macintmask
;
2704 W_REG(&wlc_hw
->regs
->macintmask
, wlc
->macintmask
);
2707 static void brcms_b_mute(struct brcms_c_hw_info
*wlc_hw
, bool on
, mbool flags
)
2709 u8 null_ether_addr
[ETH_ALEN
] = {0, 0, 0, 0, 0, 0};
2712 /* suspend tx fifos */
2713 brcms_b_tx_fifo_suspend(wlc_hw
, TX_DATA_FIFO
);
2714 brcms_b_tx_fifo_suspend(wlc_hw
, TX_CTL_FIFO
);
2715 brcms_b_tx_fifo_suspend(wlc_hw
, TX_AC_BK_FIFO
);
2716 brcms_b_tx_fifo_suspend(wlc_hw
, TX_AC_VI_FIFO
);
2718 /* zero the address match register so we do not send ACKs */
2719 brcms_b_set_addrmatch(wlc_hw
, RCM_MAC_OFFSET
,
2722 /* resume tx fifos */
2723 if (!wlc_hw
->wlc
->tx_suspended
) {
2724 brcms_b_tx_fifo_resume(wlc_hw
, TX_DATA_FIFO
);
2726 brcms_b_tx_fifo_resume(wlc_hw
, TX_CTL_FIFO
);
2727 brcms_b_tx_fifo_resume(wlc_hw
, TX_AC_BK_FIFO
);
2728 brcms_b_tx_fifo_resume(wlc_hw
, TX_AC_VI_FIFO
);
2730 /* Restore address */
2731 brcms_b_set_addrmatch(wlc_hw
, RCM_MAC_OFFSET
,
2735 wlc_phy_mute_upd(wlc_hw
->band
->pi
, on
, flags
);
2738 brcms_c_ucode_mute_override_set(wlc_hw
);
2740 brcms_c_ucode_mute_override_clear(wlc_hw
);
2743 int brcms_b_xmtfifo_sz_get(struct brcms_c_hw_info
*wlc_hw
, uint fifo
,
2749 *blocks
= wlc_hw
->xmtfifo_sz
[fifo
];
2754 /* brcms_b_tx_fifo_suspended:
2755 * Check the MAC's tx suspend status for a tx fifo.
2757 * When the MAC acknowledges a tx suspend, it indicates that no more
2758 * packets will be transmitted out the radio. This is independent of
2759 * DMA channel suspension---the DMA may have finished suspending, or may still
2760 * be pulling data into a tx fifo, by the time the MAC acks the suspend
2763 static bool brcms_b_tx_fifo_suspended(struct brcms_c_hw_info
*wlc_hw
,
2766 /* check that a suspend has been requested and is no longer pending */
2769 * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
2770 * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
2771 * chnstatus register.
2772 * The tx fifo suspend completion is independent of the DMA suspend completion and
2773 * may be acked before or after the DMA is suspended.
2775 if (dma_txsuspended(wlc_hw
->di
[tx_fifo
]) &&
2776 (R_REG(&wlc_hw
->regs
->chnstatus
) &
2777 (1 << tx_fifo
)) == 0)
2783 static void brcms_b_tx_fifo_suspend(struct brcms_c_hw_info
*wlc_hw
,
2786 u8 fifo
= 1 << tx_fifo
;
2788 /* Two clients of this code, 11h Quiet period and scanning. */
2790 /* only suspend if not already suspended */
2791 if ((wlc_hw
->suspended_fifos
& fifo
) == fifo
)
2794 /* force the core awake only if not already */
2795 if (wlc_hw
->suspended_fifos
== 0)
2796 brcms_c_ucode_wake_override_set(wlc_hw
,
2797 WLC_WAKE_OVERRIDE_TXFIFO
);
2799 wlc_hw
->suspended_fifos
|= fifo
;
2801 if (wlc_hw
->di
[tx_fifo
]) {
2802 /* Suspending AMPDU transmissions in the middle can cause underflow
2803 * which may result in mismatch between ucode and driver
2804 * so suspend the mac before suspending the FIFO
2806 if (WLC_PHY_11N_CAP(wlc_hw
->band
))
2807 brcms_c_suspend_mac_and_wait(wlc_hw
->wlc
);
2809 dma_txsuspend(wlc_hw
->di
[tx_fifo
]);
2811 if (WLC_PHY_11N_CAP(wlc_hw
->band
))
2812 brcms_c_enable_mac(wlc_hw
->wlc
);
2816 static void brcms_b_tx_fifo_resume(struct brcms_c_hw_info
*wlc_hw
,
2819 /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case
2820 * but need to be done here for PIO otherwise the watchdog will catch
2821 * the inconsistency and fire
2823 /* Two clients of this code, 11h Quiet period and scanning. */
2824 if (wlc_hw
->di
[tx_fifo
])
2825 dma_txresume(wlc_hw
->di
[tx_fifo
]);
2827 /* allow core to sleep again */
2828 if (wlc_hw
->suspended_fifos
== 0)
2831 wlc_hw
->suspended_fifos
&= ~(1 << tx_fifo
);
2832 if (wlc_hw
->suspended_fifos
== 0)
2833 brcms_c_ucode_wake_override_clear(wlc_hw
,
2834 WLC_WAKE_OVERRIDE_TXFIFO
);
2839 * Read and clear macintmask and macintstatus and intstatus registers.
2840 * This routine should be called with interrupts off
2842 * -1 if DEVICEREMOVED(wlc) evaluates to true;
2843 * 0 if the interrupt is not for us, or we are in some special cases;
2844 * device interrupt status bits otherwise.
2846 static inline u32
wlc_intstatus(struct brcms_c_info
*wlc
, bool in_isr
)
2848 struct brcms_c_hw_info
*wlc_hw
= wlc
->hw
;
2849 d11regs_t
*regs
= wlc_hw
->regs
;
2852 /* macintstatus includes a DMA interrupt summary bit */
2853 macintstatus
= R_REG(®s
->macintstatus
);
2855 BCMMSG(wlc
->wiphy
, "wl%d: macintstatus: 0x%x\n", wlc_hw
->unit
,
2858 /* detect cardbus removed, in power down(suspend) and in reset */
2859 if (DEVICEREMOVED(wlc
))
2862 /* DEVICEREMOVED succeeds even when the core is still resetting,
2863 * handle that case here.
2865 if (macintstatus
== 0xffffffff)
2868 /* defer unsolicited interrupts */
2869 macintstatus
&= (in_isr
? wlc
->macintmask
: wlc
->defmacintmask
);
2872 if (macintstatus
== 0)
2875 /* interrupts are already turned off for CFE build
2876 * Caution: For CFE Turning off the interrupts again has some undesired
2879 /* turn off the interrupts */
2880 W_REG(®s
->macintmask
, 0);
2881 (void)R_REG(®s
->macintmask
); /* sync readback */
2882 wlc
->macintmask
= 0;
2884 /* clear device interrupts */
2885 W_REG(®s
->macintstatus
, macintstatus
);
2887 /* MI_DMAINT is indication of non-zero intstatus */
2888 if (macintstatus
& MI_DMAINT
) {
2890 * only fifo interrupt enabled is I_RI in
2891 * RX_FIFO. If MI_DMAINT is set, assume it
2892 * is set and clear the interrupt.
2894 W_REG(®s
->intctrlregs
[RX_FIFO
].intstatus
,
2898 return macintstatus
;
2901 /* Update wlc->macintstatus and wlc->intstatus[]. */
2902 /* Return true if they are updated successfully. false otherwise */
2903 bool brcms_c_intrsupd(struct brcms_c_info
*wlc
)
2907 /* read and clear macintstatus and intstatus registers */
2908 macintstatus
= wlc_intstatus(wlc
, false);
2910 /* device is removed */
2911 if (macintstatus
== 0xffffffff)
2914 /* update interrupt status in software */
2915 wlc
->macintstatus
|= macintstatus
;
2921 * First-level interrupt processing.
2922 * Return true if this was our interrupt, false otherwise.
2923 * *wantdpc will be set to true if further brcms_c_dpc() processing is required,
2926 bool brcms_c_isr(struct brcms_c_info
*wlc
, bool *wantdpc
)
2928 struct brcms_c_hw_info
*wlc_hw
= wlc
->hw
;
2933 if (!wlc_hw
->up
|| !wlc
->macintmask
)
2936 /* read and clear macintstatus and intstatus registers */
2937 macintstatus
= wlc_intstatus(wlc
, true);
2939 if (macintstatus
== 0xffffffff)
2940 wiphy_err(wlc
->wiphy
, "DEVICEREMOVED detected in the ISR code"
2943 /* it is not for us */
2944 if (macintstatus
== 0)
2949 /* save interrupt status bits */
2950 wlc
->macintstatus
= macintstatus
;
2957 brcms_b_dotxstatus(struct brcms_c_hw_info
*wlc_hw
, tx_status_t
*txs
, u32 s2
)
2959 /* discard intermediate indications for ucode with one legitimate case:
2960 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
2961 * tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
2962 * transmission count)
2964 if (!(txs
->status
& TX_STATUS_AMPDU
)
2965 && (txs
->status
& TX_STATUS_INTERMEDIATE
)) {
2969 return brcms_c_dotxstatus(wlc_hw
->wlc
, txs
, s2
);
2972 /* process tx completion events in BMAC
2973 * Return true if more tx status need to be processed. false otherwise.
2976 brcms_b_txstatus(struct brcms_c_hw_info
*wlc_hw
, bool bound
, bool *fatal
)
2978 bool morepending
= false;
2979 struct brcms_c_info
*wlc
= wlc_hw
->wlc
;
2981 tx_status_t txstatus
, *txs
;
2985 * Param 'max_tx_num' indicates max. # tx status to process before
2988 uint max_tx_num
= bound
? wlc
->pub
->tunables
->txsbnd
: -1;
2990 BCMMSG(wlc
->wiphy
, "wl%d\n", wlc_hw
->unit
);
2993 regs
= wlc_hw
->regs
;
2995 && (s1
= R_REG(®s
->frmtxstatus
)) & TXS_V
) {
2997 if (s1
== 0xffffffff) {
2998 wiphy_err(wlc
->wiphy
, "wl%d: %s: dead chip\n",
2999 wlc_hw
->unit
, __func__
);
3003 s2
= R_REG(®s
->frmtxstatus2
);
3005 txs
->status
= s1
& TXS_STATUS_MASK
;
3006 txs
->frameid
= (s1
& TXS_FID_MASK
) >> TXS_FID_SHIFT
;
3007 txs
->sequence
= s2
& TXS_SEQ_MASK
;
3008 txs
->phyerr
= (s2
& TXS_PTX_MASK
) >> TXS_PTX_SHIFT
;
3009 txs
->lasttxtime
= 0;
3011 *fatal
= brcms_b_dotxstatus(wlc_hw
, txs
, s2
);
3013 /* !give others some time to run! */
3014 if (++n
>= max_tx_num
)
3021 if (n
>= max_tx_num
)
3024 if (!pktq_empty(&wlc
->pkt_queue
->q
))
3025 brcms_c_send_q(wlc
);
3030 void brcms_c_suspend_mac_and_wait(struct brcms_c_info
*wlc
)
3032 struct brcms_c_hw_info
*wlc_hw
= wlc
->hw
;
3033 d11regs_t
*regs
= wlc_hw
->regs
;
3035 struct wiphy
*wiphy
= wlc
->wiphy
;
3037 BCMMSG(wlc
->wiphy
, "wl%d: bandunit %d\n", wlc_hw
->unit
,
3038 wlc_hw
->band
->bandunit
);
3041 * Track overlapping suspend requests
3043 wlc_hw
->mac_suspend_depth
++;
3044 if (wlc_hw
->mac_suspend_depth
> 1)
3047 /* force the core awake */
3048 brcms_c_ucode_wake_override_set(wlc_hw
, WLC_WAKE_OVERRIDE_MACSUSPEND
);
3050 mc
= R_REG(®s
->maccontrol
);
3052 if (mc
== 0xffffffff) {
3053 wiphy_err(wiphy
, "wl%d: %s: dead chip\n", wlc_hw
->unit
,
3055 brcms_down(wlc
->wl
);
3058 WARN_ON(mc
& MCTL_PSM_JMP_0
);
3059 WARN_ON(!(mc
& MCTL_PSM_RUN
));
3060 WARN_ON(!(mc
& MCTL_EN_MAC
));
3062 mi
= R_REG(®s
->macintstatus
);
3063 if (mi
== 0xffffffff) {
3064 wiphy_err(wiphy
, "wl%d: %s: dead chip\n", wlc_hw
->unit
,
3066 brcms_down(wlc
->wl
);
3069 WARN_ON(mi
& MI_MACSSPNDD
);
3071 brcms_b_mctrl(wlc_hw
, MCTL_EN_MAC
, 0);
3073 SPINWAIT(!(R_REG(®s
->macintstatus
) & MI_MACSSPNDD
),
3074 WLC_MAX_MAC_SUSPEND
);
3076 if (!(R_REG(®s
->macintstatus
) & MI_MACSSPNDD
)) {
3077 wiphy_err(wiphy
, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
3078 " and MI_MACSSPNDD is still not on.\n",
3079 wlc_hw
->unit
, WLC_MAX_MAC_SUSPEND
);
3080 wiphy_err(wiphy
, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
3081 "psm_brc 0x%04x\n", wlc_hw
->unit
,
3082 R_REG(®s
->psmdebug
),
3083 R_REG(®s
->phydebug
),
3084 R_REG(®s
->psm_brc
));
3087 mc
= R_REG(®s
->maccontrol
);
3088 if (mc
== 0xffffffff) {
3089 wiphy_err(wiphy
, "wl%d: %s: dead chip\n", wlc_hw
->unit
,
3091 brcms_down(wlc
->wl
);
3094 WARN_ON(mc
& MCTL_PSM_JMP_0
);
3095 WARN_ON(!(mc
& MCTL_PSM_RUN
));
3096 WARN_ON(mc
& MCTL_EN_MAC
);
3099 void brcms_c_enable_mac(struct brcms_c_info
*wlc
)
3101 struct brcms_c_hw_info
*wlc_hw
= wlc
->hw
;
3102 d11regs_t
*regs
= wlc_hw
->regs
;
3105 BCMMSG(wlc
->wiphy
, "wl%d: bandunit %d\n", wlc_hw
->unit
,
3106 wlc
->band
->bandunit
);
3109 * Track overlapping suspend requests
3111 wlc_hw
->mac_suspend_depth
--;
3112 if (wlc_hw
->mac_suspend_depth
> 0)
3115 mc
= R_REG(®s
->maccontrol
);
3116 WARN_ON(mc
& MCTL_PSM_JMP_0
);
3117 WARN_ON(mc
& MCTL_EN_MAC
);
3118 WARN_ON(!(mc
& MCTL_PSM_RUN
));
3120 brcms_b_mctrl(wlc_hw
, MCTL_EN_MAC
, MCTL_EN_MAC
);
3121 W_REG(®s
->macintstatus
, MI_MACSSPNDD
);
3123 mc
= R_REG(®s
->maccontrol
);
3124 WARN_ON(mc
& MCTL_PSM_JMP_0
);
3125 WARN_ON(!(mc
& MCTL_EN_MAC
));
3126 WARN_ON(!(mc
& MCTL_PSM_RUN
));
3128 mi
= R_REG(®s
->macintstatus
);
3129 WARN_ON(mi
& MI_MACSSPNDD
);
3131 brcms_c_ucode_wake_override_clear(wlc_hw
, WLC_WAKE_OVERRIDE_MACSUSPEND
);
3134 static void brcms_upd_ofdm_pctl1_table(struct brcms_c_hw_info
*wlc_hw
)
3138 WLC_RATE_6M
, WLC_RATE_9M
, WLC_RATE_12M
, WLC_RATE_18M
,
3139 WLC_RATE_24M
, WLC_RATE_36M
, WLC_RATE_48M
, WLC_RATE_54M
3145 if (!WLC_PHY_11N_CAP(wlc_hw
->band
))
3148 /* walk the phy rate table and update the entries */
3149 for (i
= 0; i
< ARRAY_SIZE(rates
); i
++) {
3152 entry_ptr
= brcms_b_ofdm_ratetable_offset(wlc_hw
, rate
);
3154 /* read the SHM Rate Table entry OFDM PCTL1 values */
3156 brcms_b_read_shm(wlc_hw
, entry_ptr
+ M_RT_OFDM_PCTL1_POS
);
3158 /* modify the value */
3159 pctl1
&= ~PHY_TXC1_MODE_MASK
;
3160 pctl1
|= (wlc_hw
->hw_stf_ss_opmode
<< PHY_TXC1_MODE_SHIFT
);
3162 /* Update the SHM Rate Table entry OFDM PCTL1 values */
3163 brcms_b_write_shm(wlc_hw
, entry_ptr
+ M_RT_OFDM_PCTL1_POS
,
3168 static u16
brcms_b_ofdm_ratetable_offset(struct brcms_c_hw_info
*wlc_hw
,
3173 struct plcp_signal_rate_lookup
{
3177 /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3178 const struct plcp_signal_rate_lookup rate_lookup
[] = {
3181 {WLC_RATE_12M
, 0xA},
3182 {WLC_RATE_18M
, 0xE},
3183 {WLC_RATE_24M
, 0x9},
3184 {WLC_RATE_36M
, 0xD},
3185 {WLC_RATE_48M
, 0x8},
3189 for (i
= 0; i
< ARRAY_SIZE(rate_lookup
); i
++) {
3190 if (rate
== rate_lookup
[i
].rate
) {
3191 plcp_rate
= rate_lookup
[i
].signal_rate
;
3196 /* Find the SHM pointer to the rate table entry by looking in the
3199 return 2 * brcms_b_read_shm(wlc_hw
, M_RT_DIRMAP_A
+ (plcp_rate
* 2));
3202 void brcms_b_band_stf_ss_set(struct brcms_c_hw_info
*wlc_hw
, u8 stf_mode
)
3204 wlc_hw
->hw_stf_ss_opmode
= stf_mode
;
3207 brcms_upd_ofdm_pctl1_table(wlc_hw
);
3211 brcms_b_read_tsf(struct brcms_c_hw_info
*wlc_hw
, u32
*tsf_l_ptr
,
3214 d11regs_t
*regs
= wlc_hw
->regs
;
3216 /* read the tsf timer low, then high to get an atomic read */
3217 *tsf_l_ptr
= R_REG(®s
->tsf_timerlow
);
3218 *tsf_h_ptr
= R_REG(®s
->tsf_timerhigh
);
3223 static bool brcms_b_validate_chip_access(struct brcms_c_hw_info
*wlc_hw
)
3227 struct wiphy
*wiphy
= wlc_hw
->wlc
->wiphy
;
3229 BCMMSG(wiphy
, "wl%d\n", wlc_hw
->unit
);
3231 regs
= wlc_hw
->regs
;
3233 /* Validate dchip register access */
3235 W_REG(®s
->objaddr
, OBJADDR_SHM_SEL
| 0);
3236 (void)R_REG(®s
->objaddr
);
3237 w
= R_REG(®s
->objdata
);
3239 /* Can we write and read back a 32bit register? */
3240 W_REG(®s
->objaddr
, OBJADDR_SHM_SEL
| 0);
3241 (void)R_REG(®s
->objaddr
);
3242 W_REG(®s
->objdata
, (u32
) 0xaa5555aa);
3244 W_REG(®s
->objaddr
, OBJADDR_SHM_SEL
| 0);
3245 (void)R_REG(®s
->objaddr
);
3246 val
= R_REG(®s
->objdata
);
3247 if (val
!= (u32
) 0xaa5555aa) {
3248 wiphy_err(wiphy
, "wl%d: validate_chip_access: SHM = 0x%x, "
3249 "expected 0xaa5555aa\n", wlc_hw
->unit
, val
);
3253 W_REG(®s
->objaddr
, OBJADDR_SHM_SEL
| 0);
3254 (void)R_REG(®s
->objaddr
);
3255 W_REG(®s
->objdata
, (u32
) 0x55aaaa55);
3257 W_REG(®s
->objaddr
, OBJADDR_SHM_SEL
| 0);
3258 (void)R_REG(®s
->objaddr
);
3259 val
= R_REG(®s
->objdata
);
3260 if (val
!= (u32
) 0x55aaaa55) {
3261 wiphy_err(wiphy
, "wl%d: validate_chip_access: SHM = 0x%x, "
3262 "expected 0x55aaaa55\n", wlc_hw
->unit
, val
);
3266 W_REG(®s
->objaddr
, OBJADDR_SHM_SEL
| 0);
3267 (void)R_REG(®s
->objaddr
);
3268 W_REG(®s
->objdata
, w
);
3270 /* clear CFPStart */
3271 W_REG(®s
->tsf_cfpstart
, 0);
3273 w
= R_REG(®s
->maccontrol
);
3274 if ((w
!= (MCTL_IHR_EN
| MCTL_WAKE
)) &&
3275 (w
!= (MCTL_IHR_EN
| MCTL_GMODE
| MCTL_WAKE
))) {
3276 wiphy_err(wiphy
, "wl%d: validate_chip_access: maccontrol = "
3277 "0x%x, expected 0x%x or 0x%x\n", wlc_hw
->unit
, w
,
3278 (MCTL_IHR_EN
| MCTL_WAKE
),
3279 (MCTL_IHR_EN
| MCTL_GMODE
| MCTL_WAKE
));
3286 #define PHYPLL_WAIT_US 100000
3288 void brcms_b_core_phypll_ctl(struct brcms_c_hw_info
*wlc_hw
, bool on
)
3293 BCMMSG(wlc_hw
->wlc
->wiphy
, "wl%d\n", wlc_hw
->unit
);
3296 regs
= wlc_hw
->regs
;
3299 if ((wlc_hw
->sih
->chip
== BCM4313_CHIP_ID
)) {
3300 OR_REG(®s
->clk_ctl_st
,
3301 (CCS_ERSRC_REQ_HT
| CCS_ERSRC_REQ_D11PLL
|
3302 CCS_ERSRC_REQ_PHYPLL
));
3303 SPINWAIT((R_REG(®s
->clk_ctl_st
) &
3304 (CCS_ERSRC_AVAIL_HT
)) != (CCS_ERSRC_AVAIL_HT
),
3307 tmp
= R_REG(®s
->clk_ctl_st
);
3308 if ((tmp
& (CCS_ERSRC_AVAIL_HT
)) !=
3309 (CCS_ERSRC_AVAIL_HT
)) {
3310 wiphy_err(wlc_hw
->wlc
->wiphy
, "%s: turn on PHY"
3311 " PLL failed\n", __func__
);
3314 OR_REG(®s
->clk_ctl_st
,
3315 (CCS_ERSRC_REQ_D11PLL
| CCS_ERSRC_REQ_PHYPLL
));
3316 SPINWAIT((R_REG(®s
->clk_ctl_st
) &
3317 (CCS_ERSRC_AVAIL_D11PLL
|
3318 CCS_ERSRC_AVAIL_PHYPLL
)) !=
3319 (CCS_ERSRC_AVAIL_D11PLL
|
3320 CCS_ERSRC_AVAIL_PHYPLL
), PHYPLL_WAIT_US
);
3322 tmp
= R_REG(®s
->clk_ctl_st
);
3324 (CCS_ERSRC_AVAIL_D11PLL
| CCS_ERSRC_AVAIL_PHYPLL
))
3326 (CCS_ERSRC_AVAIL_D11PLL
| CCS_ERSRC_AVAIL_PHYPLL
)) {
3327 wiphy_err(wlc_hw
->wlc
->wiphy
, "%s: turn on "
3328 "PHY PLL failed\n", __func__
);
3332 /* Since the PLL may be shared, other cores can still be requesting it;
3333 * so we'll deassert the request but not wait for status to comply.
3335 AND_REG(®s
->clk_ctl_st
, ~CCS_ERSRC_REQ_PHYPLL
);
3336 tmp
= R_REG(®s
->clk_ctl_st
);
3340 void brcms_c_coredisable(struct brcms_c_hw_info
*wlc_hw
)
3344 BCMMSG(wlc_hw
->wlc
->wiphy
, "wl%d\n", wlc_hw
->unit
);
3346 dev_gone
= DEVICEREMOVED(wlc_hw
->wlc
);
3351 if (wlc_hw
->noreset
)
3355 wlc_phy_switch_radio(wlc_hw
->band
->pi
, OFF
);
3357 /* turn off analog core */
3358 wlc_phy_anacore(wlc_hw
->band
->pi
, OFF
);
3360 /* turn off PHYPLL to save power */
3361 brcms_b_core_phypll_ctl(wlc_hw
, false);
3363 /* No need to set wlc->pub->radio_active = OFF
3364 * because this function needs down capability and
3365 * radio_active is designed for BCMNODOWN.
3368 /* remove gpio controls */
3369 if (wlc_hw
->ucode_dbgsel
)
3370 ai_gpiocontrol(wlc_hw
->sih
, ~0, 0, GPIO_DRV_PRIORITY
);
3372 wlc_hw
->clk
= false;
3373 ai_core_disable(wlc_hw
->sih
, 0);
3374 wlc_phy_hw_clk_state_upd(wlc_hw
->band
->pi
, false);
3377 /* power both the pll and external oscillator on/off */
3378 static void brcms_b_xtal(struct brcms_c_hw_info
*wlc_hw
, bool want
)
3380 BCMMSG(wlc_hw
->wlc
->wiphy
, "wl%d: want %d\n", wlc_hw
->unit
, want
);
3382 /* dont power down if plldown is false or we must poll hw radio disable */
3383 if (!want
&& wlc_hw
->pllreq
)
3387 ai_clkctl_xtal(wlc_hw
->sih
, XTAL
| PLL
, want
);
3389 wlc_hw
->sbclk
= want
;
3390 if (!wlc_hw
->sbclk
) {
3391 wlc_hw
->clk
= false;
3392 if (wlc_hw
->band
&& wlc_hw
->band
->pi
)
3393 wlc_phy_hw_clk_state_upd(wlc_hw
->band
->pi
, false);
3397 static void brcms_c_flushqueues(struct brcms_c_info
*wlc
)
3399 struct brcms_c_hw_info
*wlc_hw
= wlc
->hw
;
3402 wlc
->txpend16165war
= 0;
3404 /* free any posted tx packets */
3405 for (i
= 0; i
< NFIFO
; i
++)
3406 if (wlc_hw
->di
[i
]) {
3407 dma_txreclaim(wlc_hw
->di
[i
], DMA_RANGE_ALL
);
3408 TXPKTPENDCLR(wlc
, i
);
3409 BCMMSG(wlc
->wiphy
, "pktpend fifo %d clrd\n", i
);
3412 /* free any posted rx packets */
3413 dma_rxreclaim(wlc_hw
->di
[RX_FIFO
]);
3416 u16
brcms_b_read_shm(struct brcms_c_hw_info
*wlc_hw
, uint offset
)
3418 return brcms_b_read_objmem(wlc_hw
, offset
, OBJADDR_SHM_SEL
);
3421 void brcms_b_write_shm(struct brcms_c_hw_info
*wlc_hw
, uint offset
, u16 v
)
3423 brcms_b_write_objmem(wlc_hw
, offset
, v
, OBJADDR_SHM_SEL
);
3427 brcms_b_read_objmem(struct brcms_c_hw_info
*wlc_hw
, uint offset
, u32 sel
)
3429 d11regs_t
*regs
= wlc_hw
->regs
;
3430 volatile u16
*objdata_lo
= (volatile u16
*)®s
->objdata
;
3431 volatile u16
*objdata_hi
= objdata_lo
+ 1;
3434 W_REG(®s
->objaddr
, sel
| (offset
>> 2));
3435 (void)R_REG(®s
->objaddr
);
3437 v
= R_REG(objdata_hi
);
3439 v
= R_REG(objdata_lo
);
3446 brcms_b_write_objmem(struct brcms_c_hw_info
*wlc_hw
, uint offset
, u16 v
,
3449 d11regs_t
*regs
= wlc_hw
->regs
;
3450 volatile u16
*objdata_lo
= (volatile u16
*)®s
->objdata
;
3451 volatile u16
*objdata_hi
= objdata_lo
+ 1;
3453 W_REG(®s
->objaddr
, sel
| (offset
>> 2));
3454 (void)R_REG(®s
->objaddr
);
3456 W_REG(objdata_hi
, v
);
3458 W_REG(objdata_lo
, v
);
3462 /* Copy a buffer to shared memory of specified type .
3463 * SHM 'offset' needs to be an even address and
3464 * Buffer length 'len' must be an even number of bytes
3465 * 'sel' selects the type of memory
3468 brcms_b_copyto_objmem(struct brcms_c_hw_info
*wlc_hw
, uint offset
,
3469 const void *buf
, int len
, u32 sel
)
3472 const u8
*p
= (const u8
*)buf
;
3475 if (len
<= 0 || (offset
& 1) || (len
& 1))
3478 for (i
= 0; i
< len
; i
+= 2) {
3479 v
= p
[i
] | (p
[i
+ 1] << 8);
3480 brcms_b_write_objmem(wlc_hw
, offset
+ i
, v
, sel
);
3484 /* Copy a piece of shared memory of specified type to a buffer .
3485 * SHM 'offset' needs to be an even address and
3486 * Buffer length 'len' must be an even number of bytes
3487 * 'sel' selects the type of memory
3490 brcms_b_copyfrom_objmem(struct brcms_c_hw_info
*wlc_hw
, uint offset
, void *buf
,
3497 if (len
<= 0 || (offset
& 1) || (len
& 1))
3500 for (i
= 0; i
< len
; i
+= 2) {
3501 v
= brcms_b_read_objmem(wlc_hw
, offset
+ i
, sel
);
3503 p
[i
+ 1] = (v
>> 8) & 0xFF;
3507 void brcms_b_copyfrom_vars(struct brcms_c_hw_info
*wlc_hw
, char **buf
,
3510 BCMMSG(wlc_hw
->wlc
->wiphy
, "nvram vars totlen=%d\n",
3513 *buf
= wlc_hw
->vars
;
3514 *len
= wlc_hw
->vars_size
;
3517 void brcms_b_retrylimit_upd(struct brcms_c_hw_info
*wlc_hw
, u16 SRL
, u16 LRL
)
3522 /* write retry limit to SCR, shouldn't need to suspend */
3524 W_REG(&wlc_hw
->regs
->objaddr
,
3525 OBJADDR_SCR_SEL
| S_DOT11_SRC_LMT
);
3526 (void)R_REG(&wlc_hw
->regs
->objaddr
);
3527 W_REG(&wlc_hw
->regs
->objdata
, wlc_hw
->SRL
);
3528 W_REG(&wlc_hw
->regs
->objaddr
,
3529 OBJADDR_SCR_SEL
| S_DOT11_LRC_LMT
);
3530 (void)R_REG(&wlc_hw
->regs
->objaddr
);
3531 W_REG(&wlc_hw
->regs
->objdata
, wlc_hw
->LRL
);
3535 void brcms_b_pllreq(struct brcms_c_hw_info
*wlc_hw
, bool set
, mbool req_bit
)
3538 if (mboolisset(wlc_hw
->pllreq
, req_bit
))
3541 mboolset(wlc_hw
->pllreq
, req_bit
);
3543 if (mboolisset(wlc_hw
->pllreq
, WLC_PLLREQ_FLIP
)) {
3544 if (!wlc_hw
->sbclk
) {
3545 brcms_b_xtal(wlc_hw
, ON
);
3549 if (!mboolisset(wlc_hw
->pllreq
, req_bit
))
3552 mboolclr(wlc_hw
->pllreq
, req_bit
);
3554 if (mboolisset(wlc_hw
->pllreq
, WLC_PLLREQ_FLIP
)) {
3555 if (wlc_hw
->sbclk
) {
3556 brcms_b_xtal(wlc_hw
, OFF
);
3564 u16
brcms_b_rate_shm_offset(struct brcms_c_hw_info
*wlc_hw
, u8 rate
)
3569 /* get the phy specific rate encoding for the PLCP SIGNAL field */
3571 table_ptr
= M_RT_DIRMAP_A
;
3573 table_ptr
= M_RT_DIRMAP_B
;
3575 /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
3576 * the index into the rate table.
3578 phy_rate
= rate_info
[rate
] & WLC_RATE_MASK
;
3579 index
= phy_rate
& 0xf;
3581 /* Find the SHM pointer to the rate table entry by looking in the
3584 return 2 * brcms_b_read_shm(wlc_hw
, table_ptr
+ (index
* 2));
3587 void brcms_b_antsel_set(struct brcms_c_hw_info
*wlc_hw
, u32 antsel_avail
)
3589 wlc_hw
->antsel_avail
= antsel_avail
;