1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <drm/intel-gtt.h>
40 /* General customization:
43 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
45 #define DRIVER_NAME "i915"
46 #define DRIVER_DESC "Intel Graphics"
47 #define DRIVER_DATE "20080730"
59 #define I915_NUM_PIPE 2
61 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
66 * 1.2: Add Power Management
67 * 1.3: Add vblank support
68 * 1.4: Fix cmdbuffer path, add heap destroy
69 * 1.5: Add vblank pipe configuration
70 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
71 * - Support vertical blank on secondary display pipe
73 #define DRIVER_MAJOR 1
74 #define DRIVER_MINOR 6
75 #define DRIVER_PATCHLEVEL 0
77 #define WATCH_COHERENCY 0
81 #define WATCH_PWRITE 0
83 #define I915_GEM_PHYS_CURSOR_0 1
84 #define I915_GEM_PHYS_CURSOR_1 2
85 #define I915_GEM_PHYS_OVERLAY_REGS 3
86 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
88 struct drm_i915_gem_phys_object
{
90 struct page
**page_list
;
91 drm_dma_handle_t
*handle
;
92 struct drm_gem_object
*cur_obj
;
96 struct mem_block
*next
;
97 struct mem_block
*prev
;
100 struct drm_file
*file_priv
; /* NULL: free, -1: heap, other: real files */
103 struct opregion_header
;
104 struct opregion_acpi
;
105 struct opregion_swsci
;
106 struct opregion_asle
;
108 struct intel_opregion
{
109 struct opregion_header
*header
;
110 struct opregion_acpi
*acpi
;
111 struct opregion_swsci
*swsci
;
112 struct opregion_asle
*asle
;
115 #define OPREGION_SIZE (8*1024)
117 struct intel_overlay
;
118 struct intel_overlay_error_state
;
120 struct drm_i915_master_private
{
121 drm_local_map_t
*sarea
;
122 struct _drm_i915_sarea
*sarea_priv
;
124 #define I915_FENCE_REG_NONE -1
126 struct drm_i915_fence_reg
{
127 struct drm_gem_object
*obj
;
128 struct list_head lru_list
;
132 struct sdvo_device_mapping
{
142 struct drm_i915_error_state
{
145 u32 error
; /* gen6+ */
158 struct drm_i915_error_object
{
162 } *ringbuffer
, *batchbuffer
[2];
163 struct drm_i915_error_buffer
{
177 struct intel_overlay_error_state
*overlay
;
180 struct drm_i915_display_funcs
{
181 void (*dpms
)(struct drm_crtc
*crtc
, int mode
);
182 bool (*fbc_enabled
)(struct drm_device
*dev
);
183 void (*enable_fbc
)(struct drm_crtc
*crtc
, unsigned long interval
);
184 void (*disable_fbc
)(struct drm_device
*dev
);
185 int (*get_display_clock_speed
)(struct drm_device
*dev
);
186 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
187 void (*update_wm
)(struct drm_device
*dev
, int planea_clock
,
188 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
190 /* clock updates for mode set */
192 /* render clock increase/decrease */
193 /* display clock increase/decrease */
194 /* pll clock increase/decrease */
195 /* clock gating init */
198 struct intel_device_info
{
208 u8 is_broadwater
: 1;
212 u8 has_pipe_cxsr
: 1;
214 u8 cursor_needs_physical
: 1;
216 u8 overlay_needs_physical
: 1;
223 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
224 FBC_STOLEN_TOO_SMALL
, /* not enough space to hold compressed buffers */
225 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
226 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
227 FBC_BAD_PLANE
, /* fbc not supported on plane */
228 FBC_NOT_TILED
, /* buffer not tiled */
229 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
233 PCH_IBX
, /* Ibexpeak PCH */
234 PCH_CPT
, /* Cougarpoint PCH */
237 #define QUIRK_PIPEA_FORCE (1<<0)
241 typedef struct drm_i915_private
{
242 struct drm_device
*dev
;
244 const struct intel_device_info
*info
;
251 struct i2c_adapter adapter
;
252 struct i2c_adapter
*force_bit
;
256 struct pci_dev
*bridge_dev
;
257 struct intel_ring_buffer render_ring
;
258 struct intel_ring_buffer bsd_ring
;
259 struct intel_ring_buffer blt_ring
;
262 drm_dma_handle_t
*status_page_dmah
;
264 dma_addr_t dma_status_page
;
266 unsigned int seqno_gfx_addr
;
267 drm_local_map_t hws_map
;
268 struct drm_gem_object
*seqno_obj
;
269 struct drm_gem_object
*pwrctx
;
270 struct drm_gem_object
*renderctx
;
272 struct resource mch_res
;
279 #define I915_DEBUG_READ (1<<0)
280 #define I915_DEBUG_WRITE (1<<1)
281 unsigned long debug_flags
;
283 wait_queue_head_t irq_queue
;
284 atomic_t irq_received
;
285 /** Protects user_irq_refcount and irq_mask_reg */
286 spinlock_t user_irq_lock
;
288 /** Cached value of IMR to avoid reads in updating the bitfield */
291 /** splitted irq regs for graphics and display engine on Ironlake,
292 irq_mask_reg is still used for display irq. */
294 u32 gt_irq_enable_reg
;
295 u32 de_irq_enable_reg
;
296 u32 pch_irq_mask_reg
;
297 u32 pch_irq_enable_reg
;
299 u32 hotplug_supported_mask
;
300 struct work_struct hotplug_work
;
302 int tex_lru_log_granularity
;
303 int allow_batchbuffer
;
304 struct mem_block
*agp_heap
;
305 unsigned int sr01
, adpa
, ppcr
, dvob
, dvoc
, lvds
;
309 /* For hangcheck timer */
310 #define DRM_I915_HANGCHECK_PERIOD 250 /* in ms */
311 struct timer_list hangcheck_timer
;
314 uint32_t last_instdone
;
315 uint32_t last_instdone1
;
317 unsigned long cfb_size
;
318 unsigned long cfb_pitch
;
319 unsigned long cfb_offset
;
326 struct intel_opregion opregion
;
329 struct intel_overlay
*overlay
;
332 int backlight_level
; /* restore backlight to this value */
333 struct drm_display_mode
*panel_fixed_mode
;
334 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
335 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
337 /* Feature bits from the VBIOS */
338 unsigned int int_tv_support
:1;
339 unsigned int lvds_dither
:1;
340 unsigned int lvds_vbt
:1;
341 unsigned int int_crt_support
:1;
342 unsigned int lvds_use_ssc
:1;
353 struct edp_power_seq pps
;
355 bool no_aux_handshake
;
357 struct notifier_block lid_notifier
;
360 struct drm_i915_fence_reg fence_regs
[16]; /* assume 965 */
361 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
362 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
364 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
366 spinlock_t error_lock
;
367 struct drm_i915_error_state
*first_error
;
368 struct work_struct error_work
;
369 struct completion error_completion
;
370 struct workqueue_struct
*wq
;
372 /* Display functions */
373 struct drm_i915_display_funcs display
;
375 /* PCH chipset type */
376 enum intel_pch pch_type
;
378 unsigned long quirks
;
403 u32 saveTRANS_HTOTAL_A
;
404 u32 saveTRANS_HBLANK_A
;
405 u32 saveTRANS_HSYNC_A
;
406 u32 saveTRANS_VTOTAL_A
;
407 u32 saveTRANS_VBLANK_A
;
408 u32 saveTRANS_VSYNC_A
;
416 u32 savePFIT_PGM_RATIOS
;
417 u32 saveBLC_HIST_CTL
;
419 u32 saveBLC_PWM_CTL2
;
420 u32 saveBLC_CPU_PWM_CTL
;
421 u32 saveBLC_CPU_PWM_CTL2
;
434 u32 saveTRANS_HTOTAL_B
;
435 u32 saveTRANS_HBLANK_B
;
436 u32 saveTRANS_HSYNC_B
;
437 u32 saveTRANS_VTOTAL_B
;
438 u32 saveTRANS_VBLANK_B
;
439 u32 saveTRANS_VSYNC_B
;
453 u32 savePP_ON_DELAYS
;
454 u32 savePP_OFF_DELAYS
;
462 u32 savePFIT_CONTROL
;
463 u32 save_palette_a
[256];
464 u32 save_palette_b
[256];
465 u32 saveDPFC_CB_BASE
;
466 u32 saveFBC_CFB_BASE
;
469 u32 saveFBC_CONTROL2
;
479 u32 saveCACHE_MODE_0
;
480 u32 saveMI_ARB_STATE
;
491 uint64_t saveFENCE
[16];
502 u32 savePIPEA_GMCH_DATA_M
;
503 u32 savePIPEB_GMCH_DATA_M
;
504 u32 savePIPEA_GMCH_DATA_N
;
505 u32 savePIPEB_GMCH_DATA_N
;
506 u32 savePIPEA_DP_LINK_M
;
507 u32 savePIPEB_DP_LINK_M
;
508 u32 savePIPEA_DP_LINK_N
;
509 u32 savePIPEB_DP_LINK_N
;
520 u32 savePCH_DREF_CONTROL
;
521 u32 saveDISP_ARB_CTL
;
522 u32 savePIPEA_DATA_M1
;
523 u32 savePIPEA_DATA_N1
;
524 u32 savePIPEA_LINK_M1
;
525 u32 savePIPEA_LINK_N1
;
526 u32 savePIPEB_DATA_M1
;
527 u32 savePIPEB_DATA_N1
;
528 u32 savePIPEB_LINK_M1
;
529 u32 savePIPEB_LINK_N1
;
530 u32 saveMCHBAR_RENDER_STANDBY
;
533 /** Bridge to intel-gtt-ko */
534 struct intel_gtt
*gtt
;
535 /** Memory allocator for GTT stolen memory */
537 /** Memory allocator for GTT */
538 struct drm_mm gtt_space
;
539 /** End of mappable part of GTT */
540 unsigned long gtt_mappable_end
;
542 struct io_mapping
*gtt_mapping
;
545 struct shrinker inactive_shrinker
;
548 * List of objects currently involved in rendering.
550 * Includes buffers having the contents of their GPU caches
551 * flushed, not necessarily primitives. last_rendering_seqno
552 * represents when the rendering involved will be completed.
554 * A reference is held on the buffer while on this list.
556 struct list_head active_list
;
559 * List of objects which are not in the ringbuffer but which
560 * still have a write_domain which needs to be flushed before
563 * last_rendering_seqno is 0 while an object is in this list.
565 * A reference is held on the buffer while on this list.
567 struct list_head flushing_list
;
570 * LRU list of objects which are not in the ringbuffer and
571 * are ready to unbind, but are still in the GTT.
573 * last_rendering_seqno is 0 while an object is in this list.
575 * A reference is not held on the buffer while on this list,
576 * as merely being GTT-bound shouldn't prevent its being
577 * freed, and we'll pull it off the list in the free path.
579 struct list_head inactive_list
;
582 * LRU list of objects which are not in the ringbuffer but
583 * are still pinned in the GTT.
585 struct list_head pinned_list
;
587 /** LRU list of objects with fence regs on them. */
588 struct list_head fence_list
;
591 * List of objects currently pending being freed.
593 * These objects are no longer in use, but due to a signal
594 * we were prevented from freeing them at the appointed time.
596 struct list_head deferred_free_list
;
599 * We leave the user IRQ off as much as possible,
600 * but this means that requests will finish and never
601 * be retired once the system goes idle. Set a timer to
602 * fire periodically while the ring is running. When it
603 * fires, go retire requests.
605 struct delayed_work retire_work
;
608 * Flag if the X Server, and thus DRM, is not currently in
609 * control of the device.
611 * This is set between LeaveVT and EnterVT. It needs to be
612 * replaced with a semaphore. It also needs to be
613 * transitioned away from for kernel modesetting.
618 * Flag if the hardware appears to be wedged.
620 * This is set when attempts to idle the device timeout.
621 * It prevents command submission from occuring and makes
622 * every pending request fail
626 /** Bit 6 swizzling required for X tiling */
627 uint32_t bit_6_swizzle_x
;
628 /** Bit 6 swizzling required for Y tiling */
629 uint32_t bit_6_swizzle_y
;
631 /* storage for physical objects */
632 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
634 uint32_t flush_rings
;
636 /* accounting, useful for userland debugging */
637 size_t object_memory
;
640 size_t gtt_mappable_memory
;
641 size_t mappable_gtt_used
;
642 size_t mappable_gtt_total
;
646 u32 gtt_mappable_count
;
649 struct sdvo_device_mapping sdvo_mappings
[2];
650 /* indicate whether the LVDS_BORDER should be enabled or not */
651 unsigned int lvds_border_bits
;
652 /* Panel fitter placement and size for Ironlake+ */
653 u32 pch_pf_pos
, pch_pf_size
;
655 struct drm_crtc
*plane_to_crtc_mapping
[2];
656 struct drm_crtc
*pipe_to_crtc_mapping
[2];
657 wait_queue_head_t pending_flip_queue
;
658 bool flip_pending_is_done
;
660 /* Reclocking support */
661 bool render_reclock_avail
;
662 bool lvds_downclock_avail
;
663 /* indicates the reduced downclock for LVDS*/
665 struct work_struct idle_work
;
666 struct timer_list idle_timer
;
670 struct child_device_config
*child_dev
;
671 struct drm_connector
*int_lvds_connector
;
673 bool mchbar_need_disable
;
682 unsigned long last_time1
;
684 struct timespec last_time2
;
685 unsigned long gfx_power
;
689 spinlock_t
*mchdev_lock
;
691 enum no_fbc_reason no_fbc_reason
;
693 struct drm_mm_node
*compressed_fb
;
694 struct drm_mm_node
*compressed_llb
;
696 unsigned long last_gpu_reset
;
698 /* list of fbdev register on this device */
699 struct intel_fbdev
*fbdev
;
700 } drm_i915_private_t
;
702 /** driver private structure attached to each drm_gem_object */
703 struct drm_i915_gem_object
{
704 struct drm_gem_object base
;
706 /** Current space allocated to this object in the GTT, if any. */
707 struct drm_mm_node
*gtt_space
;
709 /** This object's place on the active/flushing/inactive lists */
710 struct list_head ring_list
;
711 struct list_head mm_list
;
712 /** This object's place on GPU write list */
713 struct list_head gpu_write_list
;
714 /** This object's place on eviction list */
715 struct list_head evict_list
;
718 * This is set if the object is on the active or flushing lists
719 * (has pending rendering), and is not set if it's on inactive (ready
722 unsigned int active
: 1;
725 * This is set if the object has been written to since last bound
728 unsigned int dirty
: 1;
731 * Fence register bits (if any) for this object. Will be set
732 * as needed when mapped into the GTT.
733 * Protected by dev->struct_mutex.
735 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
737 signed int fence_reg
: 5;
740 * Used for checking the object doesn't appear more than once
741 * in an execbuffer object list.
743 unsigned int in_execbuffer
: 1;
746 * Advice: are the backing pages purgeable?
748 unsigned int madv
: 2;
751 * Current tiling mode for the object.
753 unsigned int tiling_mode
: 2;
755 /** How many users have pinned this object in GTT space. The following
756 * users can each hold at most one reference: pwrite/pread, pin_ioctl
757 * (via user_pin_count), execbuffer (objects are not allowed multiple
758 * times for the same batchbuffer), and the framebuffer code. When
759 * switching/pageflipping, the framebuffer code has at most two buffers
762 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
763 * bits with absolutely no headroom. So use 4 bits. */
764 unsigned int pin_count
: 4;
765 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
768 * Whether the current gtt mapping needs to be mappable (and isn't just
769 * mappable by accident). Track pin and fault separate for a more
770 * accurate mappable working set.
772 unsigned int fault_mappable
: 1;
773 unsigned int pin_mappable
: 1;
775 /** AGP memory structure for our GTT binding. */
776 DRM_AGP_MEM
*agp_mem
;
781 * Current offset of the object in GTT space.
783 * This is the same as gtt_space->start
787 /* Which ring is refering to is this object */
788 struct intel_ring_buffer
*ring
;
790 /** Breadcrumb of last rendering to the buffer. */
791 uint32_t last_rendering_seqno
;
793 /** Current tiling stride for the object, if it's tiled. */
796 /** Record of address bit 17 of each page at last unbind. */
797 unsigned long *bit_17
;
799 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
803 * If present, while GEM_DOMAIN_CPU is in the read domain this array
804 * flags which individual pages are valid.
806 uint8_t *page_cpu_valid
;
808 /** User space pin count and filp owning the pin */
809 uint32_t user_pin_count
;
810 struct drm_file
*pin_filp
;
812 /** for phy allocated objects */
813 struct drm_i915_gem_phys_object
*phys_obj
;
816 * Number of crtcs where this object is currently the fb, but
817 * will be page flipped away on the next vblank. When it
818 * reaches 0, dev_priv->pending_flip_queue will be woken up.
820 atomic_t pending_flip
;
823 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
826 * Request queue structure.
828 * The request queue allows us to note sequence numbers that have been emitted
829 * and may be associated with active buffers to be retired.
831 * By keeping this list, we can avoid having to do questionable
832 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
833 * an emission time with seqnos for tracking how far ahead of the GPU we are.
835 struct drm_i915_gem_request
{
836 /** On Which ring this request was generated */
837 struct intel_ring_buffer
*ring
;
839 /** GEM sequence number associated with this request. */
842 /** Time at which this request was emitted, in jiffies. */
843 unsigned long emitted_jiffies
;
845 /** global list entry for this request */
846 struct list_head list
;
848 struct drm_i915_file_private
*file_priv
;
849 /** file_priv list entry for this request */
850 struct list_head client_list
;
853 struct drm_i915_file_private
{
855 struct spinlock lock
;
856 struct list_head request_list
;
860 enum intel_chip_family
{
867 extern struct drm_ioctl_desc i915_ioctls
[];
868 extern int i915_max_ioctl
;
869 extern unsigned int i915_fbpercrtc
;
870 extern unsigned int i915_powersave
;
871 extern unsigned int i915_lvds_downclock
;
873 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
874 extern int i915_resume(struct drm_device
*dev
);
875 extern void i915_save_display(struct drm_device
*dev
);
876 extern void i915_restore_display(struct drm_device
*dev
);
877 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
878 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
881 extern void i915_kernel_lost_context(struct drm_device
* dev
);
882 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
883 extern int i915_driver_unload(struct drm_device
*);
884 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
885 extern void i915_driver_lastclose(struct drm_device
* dev
);
886 extern void i915_driver_preclose(struct drm_device
*dev
,
887 struct drm_file
*file_priv
);
888 extern void i915_driver_postclose(struct drm_device
*dev
,
889 struct drm_file
*file_priv
);
890 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
891 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
893 extern int i915_emit_box(struct drm_device
*dev
,
894 struct drm_clip_rect
*boxes
,
895 int i
, int DR1
, int DR4
);
896 extern int i915_reset(struct drm_device
*dev
, u8 flags
);
897 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
898 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
899 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
900 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
904 void i915_hangcheck_elapsed(unsigned long data
);
905 extern int i915_irq_emit(struct drm_device
*dev
, void *data
,
906 struct drm_file
*file_priv
);
907 extern int i915_irq_wait(struct drm_device
*dev
, void *data
,
908 struct drm_file
*file_priv
);
909 void i915_trace_irq_get(struct drm_device
*dev
, u32 seqno
);
910 extern void i915_enable_interrupt (struct drm_device
*dev
);
912 extern irqreturn_t
i915_driver_irq_handler(DRM_IRQ_ARGS
);
913 extern void i915_driver_irq_preinstall(struct drm_device
* dev
);
914 extern int i915_driver_irq_postinstall(struct drm_device
*dev
);
915 extern void i915_driver_irq_uninstall(struct drm_device
* dev
);
916 extern int i915_vblank_pipe_set(struct drm_device
*dev
, void *data
,
917 struct drm_file
*file_priv
);
918 extern int i915_vblank_pipe_get(struct drm_device
*dev
, void *data
,
919 struct drm_file
*file_priv
);
920 extern int i915_enable_vblank(struct drm_device
*dev
, int crtc
);
921 extern void i915_disable_vblank(struct drm_device
*dev
, int crtc
);
922 extern u32
i915_get_vblank_counter(struct drm_device
*dev
, int crtc
);
923 extern u32
gm45_get_vblank_counter(struct drm_device
*dev
, int crtc
);
924 extern int i915_vblank_swap(struct drm_device
*dev
, void *data
,
925 struct drm_file
*file_priv
);
926 extern void i915_enable_irq(drm_i915_private_t
*dev_priv
, u32 mask
);
927 extern void i915_disable_irq(drm_i915_private_t
*dev_priv
, u32 mask
);
928 extern void ironlake_enable_graphics_irq(drm_i915_private_t
*dev_priv
,
930 extern void ironlake_disable_graphics_irq(drm_i915_private_t
*dev_priv
,
934 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
937 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
939 void intel_enable_asle (struct drm_device
*dev
);
941 #ifdef CONFIG_DEBUG_FS
942 extern void i915_destroy_error_state(struct drm_device
*dev
);
944 #define i915_destroy_error_state(x)
949 extern int i915_mem_alloc(struct drm_device
*dev
, void *data
,
950 struct drm_file
*file_priv
);
951 extern int i915_mem_free(struct drm_device
*dev
, void *data
,
952 struct drm_file
*file_priv
);
953 extern int i915_mem_init_heap(struct drm_device
*dev
, void *data
,
954 struct drm_file
*file_priv
);
955 extern int i915_mem_destroy_heap(struct drm_device
*dev
, void *data
,
956 struct drm_file
*file_priv
);
957 extern void i915_mem_takedown(struct mem_block
**heap
);
958 extern void i915_mem_release(struct drm_device
* dev
,
959 struct drm_file
*file_priv
, struct mem_block
*heap
);
961 int i915_gem_check_is_wedged(struct drm_device
*dev
);
962 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
963 struct drm_file
*file_priv
);
964 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
965 struct drm_file
*file_priv
);
966 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
967 struct drm_file
*file_priv
);
968 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
969 struct drm_file
*file_priv
);
970 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
971 struct drm_file
*file_priv
);
972 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
973 struct drm_file
*file_priv
);
974 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
975 struct drm_file
*file_priv
);
976 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
977 struct drm_file
*file_priv
);
978 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
979 struct drm_file
*file_priv
);
980 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
981 struct drm_file
*file_priv
);
982 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
983 struct drm_file
*file_priv
);
984 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
985 struct drm_file
*file_priv
);
986 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
987 struct drm_file
*file_priv
);
988 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
989 struct drm_file
*file_priv
);
990 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
991 struct drm_file
*file_priv
);
992 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
993 struct drm_file
*file_priv
);
994 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
995 struct drm_file
*file_priv
);
996 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
997 struct drm_file
*file_priv
);
998 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
999 struct drm_file
*file_priv
);
1000 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
1001 struct drm_file
*file_priv
);
1002 void i915_gem_load(struct drm_device
*dev
);
1003 int i915_gem_init_object(struct drm_gem_object
*obj
);
1004 struct drm_gem_object
* i915_gem_alloc_object(struct drm_device
*dev
,
1006 void i915_gem_free_object(struct drm_gem_object
*obj
);
1007 int i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
,
1009 void i915_gem_object_unpin(struct drm_gem_object
*obj
);
1010 int i915_gem_object_unbind(struct drm_gem_object
*obj
);
1011 void i915_gem_release_mmap(struct drm_gem_object
*obj
);
1012 void i915_gem_lastclose(struct drm_device
*dev
);
1015 * Returns true if seq1 is later than seq2.
1018 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1020 return (int32_t)(seq1
- seq2
) >= 0;
1023 int i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
,
1024 bool interruptible
);
1025 int i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
,
1026 bool interruptible
);
1027 void i915_gem_retire_requests(struct drm_device
*dev
);
1028 void i915_gem_reset(struct drm_device
*dev
);
1029 void i915_gem_clflush_object(struct drm_gem_object
*obj
);
1030 int i915_gem_object_set_domain(struct drm_gem_object
*obj
,
1031 uint32_t read_domains
,
1032 uint32_t write_domain
);
1033 int i915_gem_init_ringbuffer(struct drm_device
*dev
);
1034 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
1035 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
1036 unsigned long mappable_end
, unsigned long end
);
1037 int i915_gpu_idle(struct drm_device
*dev
);
1038 int i915_gem_idle(struct drm_device
*dev
);
1039 int i915_add_request(struct drm_device
*dev
,
1040 struct drm_file
*file_priv
,
1041 struct drm_i915_gem_request
*request
,
1042 struct intel_ring_buffer
*ring
);
1043 int i915_do_wait_request(struct drm_device
*dev
,
1046 struct intel_ring_buffer
*ring
);
1047 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
1048 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
,
1050 int i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
,
1052 int i915_gem_attach_phys_object(struct drm_device
*dev
,
1053 struct drm_gem_object
*obj
,
1056 void i915_gem_detach_phys_object(struct drm_device
*dev
,
1057 struct drm_gem_object
*obj
);
1058 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
1059 void i915_gem_release(struct drm_device
* dev
, struct drm_file
*file_priv
);
1061 /* i915_gem_evict.c */
1062 int i915_gem_evict_something(struct drm_device
*dev
, int min_size
,
1063 unsigned alignment
, bool mappable
);
1064 int i915_gem_evict_everything(struct drm_device
*dev
);
1065 int i915_gem_evict_inactive(struct drm_device
*dev
);
1067 /* i915_gem_tiling.c */
1068 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
1069 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object
*obj
);
1070 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object
*obj
);
1071 bool i915_tiling_ok(struct drm_device
*dev
, int stride
, int size
,
1073 bool i915_gem_object_fence_offset_ok(struct drm_gem_object
*obj
,
1076 /* i915_gem_debug.c */
1077 void i915_gem_dump_object(struct drm_gem_object
*obj
, int len
,
1078 const char *where
, uint32_t mark
);
1080 int i915_verify_lists(struct drm_device
*dev
);
1082 #define i915_verify_lists(dev) 0
1084 void i915_gem_object_check_coherency(struct drm_gem_object
*obj
, int handle
);
1085 void i915_gem_dump_object(struct drm_gem_object
*obj
, int len
,
1086 const char *where
, uint32_t mark
);
1088 /* i915_debugfs.c */
1089 int i915_debugfs_init(struct drm_minor
*minor
);
1090 void i915_debugfs_cleanup(struct drm_minor
*minor
);
1092 /* i915_suspend.c */
1093 extern int i915_save_state(struct drm_device
*dev
);
1094 extern int i915_restore_state(struct drm_device
*dev
);
1096 /* i915_suspend.c */
1097 extern int i915_save_state(struct drm_device
*dev
);
1098 extern int i915_restore_state(struct drm_device
*dev
);
1101 extern int intel_setup_gmbus(struct drm_device
*dev
);
1102 extern void intel_teardown_gmbus(struct drm_device
*dev
);
1103 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
1104 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
1105 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
1107 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
1109 extern void intel_i2c_reset(struct drm_device
*dev
);
1111 /* intel_opregion.c */
1112 extern int intel_opregion_setup(struct drm_device
*dev
);
1114 extern void intel_opregion_init(struct drm_device
*dev
);
1115 extern void intel_opregion_fini(struct drm_device
*dev
);
1116 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
1117 extern void intel_opregion_gse_intr(struct drm_device
*dev
);
1118 extern void intel_opregion_enable_asle(struct drm_device
*dev
);
1120 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
1121 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
1122 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
1123 static inline void intel_opregion_gse_intr(struct drm_device
*dev
) { return; }
1124 static inline void intel_opregion_enable_asle(struct drm_device
*dev
) { return; }
1129 extern void intel_register_dsm_handler(void);
1130 extern void intel_unregister_dsm_handler(void);
1132 static inline void intel_register_dsm_handler(void) { return; }
1133 static inline void intel_unregister_dsm_handler(void) { return; }
1134 #endif /* CONFIG_ACPI */
1137 extern void intel_modeset_init(struct drm_device
*dev
);
1138 extern void intel_modeset_cleanup(struct drm_device
*dev
);
1139 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
1140 extern void i8xx_disable_fbc(struct drm_device
*dev
);
1141 extern void g4x_disable_fbc(struct drm_device
*dev
);
1142 extern void ironlake_disable_fbc(struct drm_device
*dev
);
1143 extern void intel_disable_fbc(struct drm_device
*dev
);
1144 extern void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
);
1145 extern bool intel_fbc_enabled(struct drm_device
*dev
);
1146 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
1147 extern void intel_detect_pch (struct drm_device
*dev
);
1148 extern int intel_trans_dp_port_sel (struct drm_crtc
*crtc
);
1151 #ifdef CONFIG_DEBUG_FS
1152 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
1153 extern void intel_overlay_print_error_state(struct seq_file
*m
, struct intel_overlay_error_state
*error
);
1157 * Lock test for when it's just for synchronization of ring access.
1159 * In that case, we don't need to do it when GEM is initialized as nobody else
1160 * has access to the ring.
1162 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
1163 if (((drm_i915_private_t *)dev->dev_private)->render_ring.gem_object \
1165 LOCK_TEST_WITH_RETURN(dev, file_priv); \
1168 static inline u32
i915_read(struct drm_i915_private
*dev_priv
, u32 reg
)
1172 val
= readl(dev_priv
->regs
+ reg
);
1173 if (dev_priv
->debug_flags
& I915_DEBUG_READ
)
1174 printk(KERN_ERR
"read 0x%08x from 0x%08x\n", val
, reg
);
1178 static inline void i915_write(struct drm_i915_private
*dev_priv
, u32 reg
,
1181 writel(val
, dev_priv
->regs
+ reg
);
1182 if (dev_priv
->debug_flags
& I915_DEBUG_WRITE
)
1183 printk(KERN_ERR
"wrote 0x%08x to 0x%08x\n", val
, reg
);
1186 #define I915_READ(reg) i915_read(dev_priv, (reg))
1187 #define I915_WRITE(reg, val) i915_write(dev_priv, (reg), (val))
1188 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
1189 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
1190 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
1191 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
1192 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
1193 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
1194 #define POSTING_READ(reg) (void)I915_READ(reg)
1195 #define POSTING_READ16(reg) (void)I915_READ16(reg)
1197 #define I915_DEBUG_ENABLE_IO() (dev_priv->debug_flags |= I915_DEBUG_READ | \
1199 #define I915_DEBUG_DISABLE_IO() (dev_priv->debug_flags &= ~(I915_DEBUG_READ | \
1202 #define BEGIN_LP_RING(n) \
1203 intel_ring_begin(&dev_priv->render_ring, (n))
1205 #define OUT_RING(x) \
1206 intel_ring_emit(&dev_priv->render_ring, x)
1208 #define ADVANCE_LP_RING() \
1209 intel_ring_advance(&dev_priv->render_ring)
1212 * Reads a dword out of the status page, which is written to from the command
1213 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1214 * MI_STORE_DATA_IMM.
1216 * The following dwords have a reserved meaning:
1217 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1218 * 0x04: ring 0 head pointer
1219 * 0x05: ring 1 head pointer (915-class)
1220 * 0x06: ring 2 head pointer (915-class)
1221 * 0x10-0x1b: Context status DWords (GM45)
1222 * 0x1f: Last written status offset. (GM45)
1224 * The area from dword 0x20 to 0x3ff is available for driver usage.
1226 #define READ_HWSP(dev_priv, reg) (((volatile u32 *)\
1227 (dev_priv->render_ring.status_page.page_addr))[reg])
1228 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1229 #define I915_GEM_HWS_INDEX 0x20
1230 #define I915_BREADCRUMB_INDEX 0x21
1232 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1234 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1235 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1236 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1237 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1238 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1239 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1240 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1241 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1242 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1243 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1244 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1245 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1246 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1247 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1248 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1249 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1250 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1251 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1252 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1254 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1255 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1256 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1257 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1258 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1260 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1261 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1262 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1264 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1265 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1267 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1268 * rows, which changed the alignment requirements and fence programming.
1270 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1272 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1273 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1274 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1275 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1276 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1277 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1278 /* dsparb controlled by hw only */
1279 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1281 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1282 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1283 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1284 #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
1286 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
1287 #define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
1289 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1290 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1292 #define PRIMARY_RINGBUFFER_SIZE (128*1024)