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usb: musb: be careful when using different fifo_modes
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / usb / musb / musb_core.c
blobb1faed7806f5e13a73692af36fcfc7ccfaaf9bc2
1 /*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 /*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82 /*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/prefetch.h>
100 #include <linux/platform_device.h>
101 #include <linux/io.h>
102
103 #include "musb_core.h"
104
105 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
106
107
108 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
110
111 #define MUSB_VERSION "6.0"
112
113 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
114
115 #define MUSB_DRIVER_NAME "musb-hdrc"
116 const char musb_driver_name[] = MUSB_DRIVER_NAME;
117
118 MODULE_DESCRIPTION(DRIVER_INFO);
119 MODULE_AUTHOR(DRIVER_AUTHOR);
120 MODULE_LICENSE("GPL");
121 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
122
123
124 /*-------------------------------------------------------------------------*/
125
126 static inline struct musb *dev_to_musb(struct device *dev)
127 {
128 return dev_get_drvdata(dev);
129 }
130
131 /*-------------------------------------------------------------------------*/
132
133 #ifndef CONFIG_BLACKFIN
134 static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset)
135 {
136 void __iomem *addr = otg->io_priv;
137 int i = 0;
138 u8 r;
139 u8 power;
140
141 /* Make sure the transceiver is not in low power mode */
142 power = musb_readb(addr, MUSB_POWER);
143 power &= ~MUSB_POWER_SUSPENDM;
144 musb_writeb(addr, MUSB_POWER, power);
145
146 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
147 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
148 */
149
150 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
151 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
152 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
153
154 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
155 & MUSB_ULPI_REG_CMPLT)) {
156 i++;
157 if (i == 10000)
158 return -ETIMEDOUT;
159
160 }
161 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
162 r &= ~MUSB_ULPI_REG_CMPLT;
163 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
164
165 return musb_readb(addr, MUSB_ULPI_REG_DATA);
166 }
167
168 static int musb_ulpi_write(struct otg_transceiver *otg,
169 u32 offset, u32 data)
170 {
171 void __iomem *addr = otg->io_priv;
172 int i = 0;
173 u8 r = 0;
174 u8 power;
175
176 /* Make sure the transceiver is not in low power mode */
177 power = musb_readb(addr, MUSB_POWER);
178 power &= ~MUSB_POWER_SUSPENDM;
179 musb_writeb(addr, MUSB_POWER, power);
180
181 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
182 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
183 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
184
185 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
186 & MUSB_ULPI_REG_CMPLT)) {
187 i++;
188 if (i == 10000)
189 return -ETIMEDOUT;
190 }
191
192 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
193 r &= ~MUSB_ULPI_REG_CMPLT;
194 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
195
196 return 0;
197 }
198 #else
199 #define musb_ulpi_read NULL
200 #define musb_ulpi_write NULL
201 #endif
202
203 static struct otg_io_access_ops musb_ulpi_access = {
204 .read = musb_ulpi_read,
205 .write = musb_ulpi_write,
206 };
207
208 /*-------------------------------------------------------------------------*/
209
210 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
211
212 /*
213 * Load an endpoint's FIFO
214 */
215 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
216 {
217 struct musb *musb = hw_ep->musb;
218 void __iomem *fifo = hw_ep->fifo;
219
220 prefetch((u8 *)src);
221
222 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
223 'T', hw_ep->epnum, fifo, len, src);
224
225 /* we can't assume unaligned reads work */
226 if (likely((0x01 & (unsigned long) src) == 0)) {
227 u16 index = 0;
228
229 /* best case is 32bit-aligned source address */
230 if ((0x02 & (unsigned long) src) == 0) {
231 if (len >= 4) {
232 writesl(fifo, src + index, len >> 2);
233 index += len & ~0x03;
234 }
235 if (len & 0x02) {
236 musb_writew(fifo, 0, *(u16 *)&src[index]);
237 index += 2;
238 }
239 } else {
240 if (len >= 2) {
241 writesw(fifo, src + index, len >> 1);
242 index += len & ~0x01;
243 }
244 }
245 if (len & 0x01)
246 musb_writeb(fifo, 0, src[index]);
247 } else {
248 /* byte aligned */
249 writesb(fifo, src, len);
250 }
251 }
252
253 #if !defined(CONFIG_USB_MUSB_AM35X)
254 /*
255 * Unload an endpoint's FIFO
256 */
257 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
258 {
259 struct musb *musb = hw_ep->musb;
260 void __iomem *fifo = hw_ep->fifo;
261
262 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
263 'R', hw_ep->epnum, fifo, len, dst);
264
265 /* we can't assume unaligned writes work */
266 if (likely((0x01 & (unsigned long) dst) == 0)) {
267 u16 index = 0;
268
269 /* best case is 32bit-aligned destination address */
270 if ((0x02 & (unsigned long) dst) == 0) {
271 if (len >= 4) {
272 readsl(fifo, dst, len >> 2);
273 index = len & ~0x03;
274 }
275 if (len & 0x02) {
276 *(u16 *)&dst[index] = musb_readw(fifo, 0);
277 index += 2;
278 }
279 } else {
280 if (len >= 2) {
281 readsw(fifo, dst, len >> 1);
282 index = len & ~0x01;
283 }
284 }
285 if (len & 0x01)
286 dst[index] = musb_readb(fifo, 0);
287 } else {
288 /* byte aligned */
289 readsb(fifo, dst, len);
290 }
291 }
292 #endif
293
294 #endif /* normal PIO */
295
296
297 /*-------------------------------------------------------------------------*/
298
299 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
300 static const u8 musb_test_packet[53] = {
301 /* implicit SYNC then DATA0 to start */
302
303 /* JKJKJKJK x9 */
304 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
305 /* JJKKJJKK x8 */
306 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
307 /* JJJJKKKK x8 */
308 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
309 /* JJJJJJJKKKKKKK x8 */
310 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
311 /* JJJJJJJK x8 */
312 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
313 /* JKKKKKKK x10, JK */
314 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
315
316 /* implicit CRC16 then EOP to end */
317 };
318
319 void musb_load_testpacket(struct musb *musb)
320 {
321 void __iomem *regs = musb->endpoints[0].regs;
322
323 musb_ep_select(musb->mregs, 0);
324 musb_write_fifo(musb->control_ep,
325 sizeof(musb_test_packet), musb_test_packet);
326 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
327 }
328
329 /*-------------------------------------------------------------------------*/
330
331 #ifdef CONFIG_USB_MUSB_OTG
332
333 /*
334 * Handles OTG hnp timeouts, such as b_ase0_brst
335 */
336 void musb_otg_timer_func(unsigned long data)
337 {
338 struct musb *musb = (struct musb *)data;
339 unsigned long flags;
340
341 spin_lock_irqsave(&musb->lock, flags);
342 switch (musb->xceiv->state) {
343 case OTG_STATE_B_WAIT_ACON:
344 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
345 musb_g_disconnect(musb);
346 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
347 musb->is_active = 0;
348 break;
349 case OTG_STATE_A_SUSPEND:
350 case OTG_STATE_A_WAIT_BCON:
351 dev_dbg(musb->controller, "HNP: %s timeout\n",
352 otg_state_string(musb->xceiv->state));
353 musb_platform_set_vbus(musb, 0);
354 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
355 break;
356 default:
357 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
358 otg_state_string(musb->xceiv->state));
359 }
360 musb->ignore_disconnect = 0;
361 spin_unlock_irqrestore(&musb->lock, flags);
362 }
363
364 /*
365 * Stops the HNP transition. Caller must take care of locking.
366 */
367 void musb_hnp_stop(struct musb *musb)
368 {
369 struct usb_hcd *hcd = musb_to_hcd(musb);
370 void __iomem *mbase = musb->mregs;
371 u8 reg;
372
373 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
374
375 switch (musb->xceiv->state) {
376 case OTG_STATE_A_PERIPHERAL:
377 musb_g_disconnect(musb);
378 dev_dbg(musb->controller, "HNP: back to %s\n",
379 otg_state_string(musb->xceiv->state));
380 break;
381 case OTG_STATE_B_HOST:
382 dev_dbg(musb->controller, "HNP: Disabling HR\n");
383 hcd->self.is_b_host = 0;
384 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
385 MUSB_DEV_MODE(musb);
386 reg = musb_readb(mbase, MUSB_POWER);
387 reg |= MUSB_POWER_SUSPENDM;
388 musb_writeb(mbase, MUSB_POWER, reg);
389 /* REVISIT: Start SESSION_REQUEST here? */
390 break;
391 default:
392 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
393 otg_state_string(musb->xceiv->state));
394 }
395
396 /*
397 * When returning to A state after HNP, avoid hub_port_rebounce(),
398 * which cause occasional OPT A "Did not receive reset after connect"
399 * errors.
400 */
401 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
402 }
403
404 #endif
405
406 /*
407 * Interrupt Service Routine to record USB "global" interrupts.
408 * Since these do not happen often and signify things of
409 * paramount importance, it seems OK to check them individually;
410 * the order of the tests is specified in the manual
411 *
412 * @param musb instance pointer
413 * @param int_usb register contents
414 * @param devctl
415 * @param power
416 */
417
418 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
419 u8 devctl, u8 power)
420 {
421 irqreturn_t handled = IRQ_NONE;
422
423 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
424 int_usb);
425
426 /* in host mode, the peripheral may issue remote wakeup.
427 * in peripheral mode, the host may resume the link.
428 * spurious RESUME irqs happen too, paired with SUSPEND.
429 */
430 if (int_usb & MUSB_INTR_RESUME) {
431 handled = IRQ_HANDLED;
432 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
433
434 if (devctl & MUSB_DEVCTL_HM) {
435 #ifdef CONFIG_USB_MUSB_HDRC_HCD
436 void __iomem *mbase = musb->mregs;
437
438 switch (musb->xceiv->state) {
439 case OTG_STATE_A_SUSPEND:
440 /* remote wakeup? later, GetPortStatus
441 * will stop RESUME signaling
442 */
443
444 if (power & MUSB_POWER_SUSPENDM) {
445 /* spurious */
446 musb->int_usb &= ~MUSB_INTR_SUSPEND;
447 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
448 break;
449 }
450
451 power &= ~MUSB_POWER_SUSPENDM;
452 musb_writeb(mbase, MUSB_POWER,
453 power | MUSB_POWER_RESUME);
454
455 musb->port1_status |=
456 (USB_PORT_STAT_C_SUSPEND << 16)
457 | MUSB_PORT_STAT_RESUME;
458 musb->rh_timer = jiffies
459 + msecs_to_jiffies(20);
460
461 musb->xceiv->state = OTG_STATE_A_HOST;
462 musb->is_active = 1;
463 usb_hcd_resume_root_hub(musb_to_hcd(musb));
464 break;
465 case OTG_STATE_B_WAIT_ACON:
466 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
467 musb->is_active = 1;
468 MUSB_DEV_MODE(musb);
469 break;
470 default:
471 WARNING("bogus %s RESUME (%s)\n",
472 "host",
473 otg_state_string(musb->xceiv->state));
474 }
475 #endif
476 } else {
477 switch (musb->xceiv->state) {
478 #ifdef CONFIG_USB_MUSB_HDRC_HCD
479 case OTG_STATE_A_SUSPEND:
480 /* possibly DISCONNECT is upcoming */
481 musb->xceiv->state = OTG_STATE_A_HOST;
482 usb_hcd_resume_root_hub(musb_to_hcd(musb));
483 break;
484 #endif
485 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
486 case OTG_STATE_B_WAIT_ACON:
487 case OTG_STATE_B_PERIPHERAL:
488 /* disconnect while suspended? we may
489 * not get a disconnect irq...
490 */
491 if ((devctl & MUSB_DEVCTL_VBUS)
492 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
493 ) {
494 musb->int_usb |= MUSB_INTR_DISCONNECT;
495 musb->int_usb &= ~MUSB_INTR_SUSPEND;
496 break;
497 }
498 musb_g_resume(musb);
499 break;
500 case OTG_STATE_B_IDLE:
501 musb->int_usb &= ~MUSB_INTR_SUSPEND;
502 break;
503 #endif
504 default:
505 WARNING("bogus %s RESUME (%s)\n",
506 "peripheral",
507 otg_state_string(musb->xceiv->state));
508 }
509 }
510 }
511
512 #ifdef CONFIG_USB_MUSB_HDRC_HCD
513 /* see manual for the order of the tests */
514 if (int_usb & MUSB_INTR_SESSREQ) {
515 void __iomem *mbase = musb->mregs;
516
517 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
518 && (devctl & MUSB_DEVCTL_BDEVICE)) {
519 dev_dbg(musb->controller, "SessReq while on B state\n");
520 return IRQ_HANDLED;
521 }
522
523 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
524 otg_state_string(musb->xceiv->state));
525
526 /* IRQ arrives from ID pin sense or (later, if VBUS power
527 * is removed) SRP. responses are time critical:
528 * - turn on VBUS (with silicon-specific mechanism)
529 * - go through A_WAIT_VRISE
530 * - ... to A_WAIT_BCON.
531 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
532 */
533 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
534 musb->ep0_stage = MUSB_EP0_START;
535 musb->xceiv->state = OTG_STATE_A_IDLE;
536 MUSB_HST_MODE(musb);
537 musb_platform_set_vbus(musb, 1);
538
539 handled = IRQ_HANDLED;
540 }
541
542 if (int_usb & MUSB_INTR_VBUSERROR) {
543 int ignore = 0;
544
545 /* During connection as an A-Device, we may see a short
546 * current spikes causing voltage drop, because of cable
547 * and peripheral capacitance combined with vbus draw.
548 * (So: less common with truly self-powered devices, where
549 * vbus doesn't act like a power supply.)
550 *
551 * Such spikes are short; usually less than ~500 usec, max
552 * of ~2 msec. That is, they're not sustained overcurrent
553 * errors, though they're reported using VBUSERROR irqs.
554 *
555 * Workarounds: (a) hardware: use self powered devices.
556 * (b) software: ignore non-repeated VBUS errors.
557 *
558 * REVISIT: do delays from lots of DEBUG_KERNEL checks
559 * make trouble here, keeping VBUS < 4.4V ?
560 */
561 switch (musb->xceiv->state) {
562 case OTG_STATE_A_HOST:
563 /* recovery is dicey once we've gotten past the
564 * initial stages of enumeration, but if VBUS
565 * stayed ok at the other end of the link, and
566 * another reset is due (at least for high speed,
567 * to redo the chirp etc), it might work OK...
568 */
569 case OTG_STATE_A_WAIT_BCON:
570 case OTG_STATE_A_WAIT_VRISE:
571 if (musb->vbuserr_retry) {
572 void __iomem *mbase = musb->mregs;
573
574 musb->vbuserr_retry--;
575 ignore = 1;
576 devctl |= MUSB_DEVCTL_SESSION;
577 musb_writeb(mbase, MUSB_DEVCTL, devctl);
578 } else {
579 musb->port1_status |=
580 USB_PORT_STAT_OVERCURRENT
581 | (USB_PORT_STAT_C_OVERCURRENT << 16);
582 }
583 break;
584 default:
585 break;
586 }
587
588 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
589 otg_state_string(musb->xceiv->state),
590 devctl,
591 ({ char *s;
592 switch (devctl & MUSB_DEVCTL_VBUS) {
593 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
594 s = "<SessEnd"; break;
595 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
596 s = "<AValid"; break;
597 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
598 s = "<VBusValid"; break;
599 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
600 default:
601 s = "VALID"; break;
602 }; s; }),
603 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
604 musb->port1_status);
605
606 /* go through A_WAIT_VFALL then start a new session */
607 if (!ignore)
608 musb_platform_set_vbus(musb, 0);
609 handled = IRQ_HANDLED;
610 }
611
612 #endif
613 if (int_usb & MUSB_INTR_SUSPEND) {
614 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n",
615 otg_state_string(musb->xceiv->state), devctl, power);
616 handled = IRQ_HANDLED;
617
618 switch (musb->xceiv->state) {
619 #ifdef CONFIG_USB_MUSB_OTG
620 case OTG_STATE_A_PERIPHERAL:
621 /* We also come here if the cable is removed, since
622 * this silicon doesn't report ID-no-longer-grounded.
623 *
624 * We depend on T(a_wait_bcon) to shut us down, and
625 * hope users don't do anything dicey during this
626 * undesired detour through A_WAIT_BCON.
627 */
628 musb_hnp_stop(musb);
629 usb_hcd_resume_root_hub(musb_to_hcd(musb));
630 musb_root_disconnect(musb);
631 musb_platform_try_idle(musb, jiffies
632 + msecs_to_jiffies(musb->a_wait_bcon
633 ? : OTG_TIME_A_WAIT_BCON));
634
635 break;
636 #endif
637 case OTG_STATE_B_IDLE:
638 if (!musb->is_active)
639 break;
640 case OTG_STATE_B_PERIPHERAL:
641 musb_g_suspend(musb);
642 musb->is_active = is_otg_enabled(musb)
643 && musb->xceiv->gadget->b_hnp_enable;
644 if (musb->is_active) {
645 #ifdef CONFIG_USB_MUSB_OTG
646 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
647 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
648 mod_timer(&musb->otg_timer, jiffies
649 + msecs_to_jiffies(
650 OTG_TIME_B_ASE0_BRST));
651 #endif
652 }
653 break;
654 case OTG_STATE_A_WAIT_BCON:
655 if (musb->a_wait_bcon != 0)
656 musb_platform_try_idle(musb, jiffies
657 + msecs_to_jiffies(musb->a_wait_bcon));
658 break;
659 case OTG_STATE_A_HOST:
660 musb->xceiv->state = OTG_STATE_A_SUSPEND;
661 musb->is_active = is_otg_enabled(musb)
662 && musb->xceiv->host->b_hnp_enable;
663 break;
664 case OTG_STATE_B_HOST:
665 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
666 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
667 break;
668 default:
669 /* "should not happen" */
670 musb->is_active = 0;
671 break;
672 }
673 }
674
675 #ifdef CONFIG_USB_MUSB_HDRC_HCD
676 if (int_usb & MUSB_INTR_CONNECT) {
677 struct usb_hcd *hcd = musb_to_hcd(musb);
678
679 handled = IRQ_HANDLED;
680 musb->is_active = 1;
681 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
682
683 musb->ep0_stage = MUSB_EP0_START;
684
685 #ifdef CONFIG_USB_MUSB_OTG
686 /* flush endpoints when transitioning from Device Mode */
687 if (is_peripheral_active(musb)) {
688 /* REVISIT HNP; just force disconnect */
689 }
690 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
691 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
692 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
693 #endif
694 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
695 |USB_PORT_STAT_HIGH_SPEED
696 |USB_PORT_STAT_ENABLE
697 );
698 musb->port1_status |= USB_PORT_STAT_CONNECTION
699 |(USB_PORT_STAT_C_CONNECTION << 16);
700
701 /* high vs full speed is just a guess until after reset */
702 if (devctl & MUSB_DEVCTL_LSDEV)
703 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
704
705 /* indicate new connection to OTG machine */
706 switch (musb->xceiv->state) {
707 case OTG_STATE_B_PERIPHERAL:
708 if (int_usb & MUSB_INTR_SUSPEND) {
709 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
710 int_usb &= ~MUSB_INTR_SUSPEND;
711 goto b_host;
712 } else
713 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
714 break;
715 case OTG_STATE_B_WAIT_ACON:
716 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
717 b_host:
718 musb->xceiv->state = OTG_STATE_B_HOST;
719 hcd->self.is_b_host = 1;
720 musb->ignore_disconnect = 0;
721 del_timer(&musb->otg_timer);
722 break;
723 default:
724 if ((devctl & MUSB_DEVCTL_VBUS)
725 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
726 musb->xceiv->state = OTG_STATE_A_HOST;
727 hcd->self.is_b_host = 0;
728 }
729 break;
730 }
731
732 /* poke the root hub */
733 MUSB_HST_MODE(musb);
734 if (hcd->status_urb)
735 usb_hcd_poll_rh_status(hcd);
736 else
737 usb_hcd_resume_root_hub(hcd);
738
739 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
740 otg_state_string(musb->xceiv->state), devctl);
741 }
742 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
743
744 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
745 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
746 otg_state_string(musb->xceiv->state),
747 MUSB_MODE(musb), devctl);
748 handled = IRQ_HANDLED;
749
750 switch (musb->xceiv->state) {
751 #ifdef CONFIG_USB_MUSB_HDRC_HCD
752 case OTG_STATE_A_HOST:
753 case OTG_STATE_A_SUSPEND:
754 usb_hcd_resume_root_hub(musb_to_hcd(musb));
755 musb_root_disconnect(musb);
756 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
757 musb_platform_try_idle(musb, jiffies
758 + msecs_to_jiffies(musb->a_wait_bcon));
759 break;
760 #endif /* HOST */
761 #ifdef CONFIG_USB_MUSB_OTG
762 case OTG_STATE_B_HOST:
763 /* REVISIT this behaves for "real disconnect"
764 * cases; make sure the other transitions from
765 * from B_HOST act right too. The B_HOST code
766 * in hnp_stop() is currently not used...
767 */
768 musb_root_disconnect(musb);
769 musb_to_hcd(musb)->self.is_b_host = 0;
770 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
771 MUSB_DEV_MODE(musb);
772 musb_g_disconnect(musb);
773 break;
774 case OTG_STATE_A_PERIPHERAL:
775 musb_hnp_stop(musb);
776 musb_root_disconnect(musb);
777 /* FALLTHROUGH */
778 case OTG_STATE_B_WAIT_ACON:
779 /* FALLTHROUGH */
780 #endif /* OTG */
781 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
782 case OTG_STATE_B_PERIPHERAL:
783 case OTG_STATE_B_IDLE:
784 musb_g_disconnect(musb);
785 break;
786 #endif /* GADGET */
787 default:
788 WARNING("unhandled DISCONNECT transition (%s)\n",
789 otg_state_string(musb->xceiv->state));
790 break;
791 }
792 }
793
794 /* mentor saves a bit: bus reset and babble share the same irq.
795 * only host sees babble; only peripheral sees bus reset.
796 */
797 if (int_usb & MUSB_INTR_RESET) {
798 handled = IRQ_HANDLED;
799 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
800 /*
801 * Looks like non-HS BABBLE can be ignored, but
802 * HS BABBLE is an error condition. For HS the solution
803 * is to avoid babble in the first place and fix what
804 * caused BABBLE. When HS BABBLE happens we can only
805 * stop the session.
806 */
807 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
808 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
809 else {
810 ERR("Stopping host session -- babble\n");
811 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
812 }
813 } else if (is_peripheral_capable()) {
814 dev_dbg(musb->controller, "BUS RESET as %s\n",
815 otg_state_string(musb->xceiv->state));
816 switch (musb->xceiv->state) {
817 #ifdef CONFIG_USB_OTG
818 case OTG_STATE_A_SUSPEND:
819 /* We need to ignore disconnect on suspend
820 * otherwise tusb 2.0 won't reconnect after a
821 * power cycle, which breaks otg compliance.
822 */
823 musb->ignore_disconnect = 1;
824 musb_g_reset(musb);
825 /* FALLTHROUGH */
826 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
827 /* never use invalid T(a_wait_bcon) */
828 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
829 otg_state_string(musb->xceiv->state),
830 TA_WAIT_BCON(musb));
831 mod_timer(&musb->otg_timer, jiffies
832 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
833 break;
834 case OTG_STATE_A_PERIPHERAL:
835 musb->ignore_disconnect = 0;
836 del_timer(&musb->otg_timer);
837 musb_g_reset(musb);
838 break;
839 case OTG_STATE_B_WAIT_ACON:
840 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
841 otg_state_string(musb->xceiv->state));
842 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
843 musb_g_reset(musb);
844 break;
845 #endif
846 case OTG_STATE_B_IDLE:
847 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
848 /* FALLTHROUGH */
849 case OTG_STATE_B_PERIPHERAL:
850 musb_g_reset(musb);
851 break;
852 default:
853 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
854 otg_state_string(musb->xceiv->state));
855 }
856 }
857 }
858
859 #if 0
860 /* REVISIT ... this would be for multiplexing periodic endpoints, or
861 * supporting transfer phasing to prevent exceeding ISO bandwidth
862 * limits of a given frame or microframe.
863 *
864 * It's not needed for peripheral side, which dedicates endpoints;
865 * though it _might_ use SOF irqs for other purposes.
866 *
867 * And it's not currently needed for host side, which also dedicates
868 * endpoints, relies on TX/RX interval registers, and isn't claimed
869 * to support ISO transfers yet.
870 */
871 if (int_usb & MUSB_INTR_SOF) {
872 void __iomem *mbase = musb->mregs;
873 struct musb_hw_ep *ep;
874 u8 epnum;
875 u16 frame;
876
877 dev_dbg(musb->controller, "START_OF_FRAME\n");
878 handled = IRQ_HANDLED;
879
880 /* start any periodic Tx transfers waiting for current frame */
881 frame = musb_readw(mbase, MUSB_FRAME);
882 ep = musb->endpoints;
883 for (epnum = 1; (epnum < musb->nr_endpoints)
884 && (musb->epmask >= (1 << epnum));
885 epnum++, ep++) {
886 /*
887 * FIXME handle framecounter wraps (12 bits)
888 * eliminate duplicated StartUrb logic
889 */
890 if (ep->dwWaitFrame >= frame) {
891 ep->dwWaitFrame = 0;
892 pr_debug("SOF --> periodic TX%s on %d\n",
893 ep->tx_channel ? " DMA" : "",
894 epnum);
895 if (!ep->tx_channel)
896 musb_h_tx_start(musb, epnum);
897 else
898 cppi_hostdma_start(musb, epnum);
899 }
900 } /* end of for loop */
901 }
902 #endif
903
904 schedule_work(&musb->irq_work);
905
906 return handled;
907 }
908
909 /*-------------------------------------------------------------------------*/
910
911 /*
912 * Program the HDRC to start (enable interrupts, dma, etc.).
913 */
914 void musb_start(struct musb *musb)
915 {
916 void __iomem *regs = musb->mregs;
917 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
918
919 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
920
921 /* Set INT enable registers, enable interrupts */
922 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
923 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
924 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
925
926 musb_writeb(regs, MUSB_TESTMODE, 0);
927
928 /* put into basic highspeed mode and start session */
929 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
930 | MUSB_POWER_SOFTCONN
931 | MUSB_POWER_HSENAB
932 /* ENSUSPEND wedges tusb */
933 /* | MUSB_POWER_ENSUSPEND */
934 );
935
936 musb->is_active = 0;
937 devctl = musb_readb(regs, MUSB_DEVCTL);
938 devctl &= ~MUSB_DEVCTL_SESSION;
939
940 if (is_otg_enabled(musb)) {
941 /* session started after:
942 * (a) ID-grounded irq, host mode;
943 * (b) vbus present/connect IRQ, peripheral mode;
944 * (c) peripheral initiates, using SRP
945 */
946 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
947 musb->is_active = 1;
948 else
949 devctl |= MUSB_DEVCTL_SESSION;
950
951 } else if (is_host_enabled(musb)) {
952 /* assume ID pin is hard-wired to ground */
953 devctl |= MUSB_DEVCTL_SESSION;
954
955 } else /* peripheral is enabled */ {
956 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
957 musb->is_active = 1;
958 }
959 musb_platform_enable(musb);
960 musb_writeb(regs, MUSB_DEVCTL, devctl);
961 }
962
963
964 static void musb_generic_disable(struct musb *musb)
965 {
966 void __iomem *mbase = musb->mregs;
967 u16 temp;
968
969 /* disable interrupts */
970 musb_writeb(mbase, MUSB_INTRUSBE, 0);
971 musb_writew(mbase, MUSB_INTRTXE, 0);
972 musb_writew(mbase, MUSB_INTRRXE, 0);
973
974 /* off */
975 musb_writeb(mbase, MUSB_DEVCTL, 0);
976
977 /* flush pending interrupts */
978 temp = musb_readb(mbase, MUSB_INTRUSB);
979 temp = musb_readw(mbase, MUSB_INTRTX);
980 temp = musb_readw(mbase, MUSB_INTRRX);
981
982 }
983
984 /*
985 * Make the HDRC stop (disable interrupts, etc.);
986 * reversible by musb_start
987 * called on gadget driver unregister
988 * with controller locked, irqs blocked
989 * acts as a NOP unless some role activated the hardware
990 */
991 void musb_stop(struct musb *musb)
992 {
993 /* stop IRQs, timers, ... */
994 musb_platform_disable(musb);
995 musb_generic_disable(musb);
996 dev_dbg(musb->controller, "HDRC disabled\n");
997
998 /* FIXME
999 * - mark host and/or peripheral drivers unusable/inactive
1000 * - disable DMA (and enable it in HdrcStart)
1001 * - make sure we can musb_start() after musb_stop(); with
1002 * OTG mode, gadget driver module rmmod/modprobe cycles that
1003 * - ...
1004 */
1005 musb_platform_try_idle(musb, 0);
1006 }
1007
1008 static void musb_shutdown(struct platform_device *pdev)
1009 {
1010 struct musb *musb = dev_to_musb(&pdev->dev);
1011 unsigned long flags;
1012
1013 pm_runtime_get_sync(musb->controller);
1014 spin_lock_irqsave(&musb->lock, flags);
1015 musb_platform_disable(musb);
1016 musb_generic_disable(musb);
1017 spin_unlock_irqrestore(&musb->lock, flags);
1018
1019 if (!is_otg_enabled(musb) && is_host_enabled(musb))
1020 usb_remove_hcd(musb_to_hcd(musb));
1021 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1022 musb_platform_exit(musb);
1023
1024 pm_runtime_put(musb->controller);
1025 /* FIXME power down */
1026 }
1027
1028
1029 /*-------------------------------------------------------------------------*/
1030
1031 /*
1032 * The silicon either has hard-wired endpoint configurations, or else
1033 * "dynamic fifo" sizing. The driver has support for both, though at this
1034 * writing only the dynamic sizing is very well tested. Since we switched
1035 * away from compile-time hardware parameters, we can no longer rely on
1036 * dead code elimination to leave only the relevant one in the object file.
1037 *
1038 * We don't currently use dynamic fifo setup capability to do anything
1039 * more than selecting one of a bunch of predefined configurations.
1040 */
1041 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1042 || defined(CONFIG_USB_MUSB_AM35X)
1043 static ushort __initdata fifo_mode = 4;
1044 #elif defined(CONFIG_USB_MUSB_UX500)
1045 static ushort __initdata fifo_mode = 5;
1046 #else
1047 static ushort __initdata fifo_mode = 2;
1048 #endif
1049
1050 /* "modprobe ... fifo_mode=1" etc */
1051 module_param(fifo_mode, ushort, 0);
1052 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1053
1054 /*
1055 * tables defining fifo_mode values. define more if you like.
1056 * for host side, make sure both halves of ep1 are set up.
1057 */
1058
1059 /* mode 0 - fits in 2KB */
1060 static struct musb_fifo_cfg __initdata mode_0_cfg[] = {
1061 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1062 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1063 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1064 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1065 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1066 };
1067
1068 /* mode 1 - fits in 4KB */
1069 static struct musb_fifo_cfg __initdata mode_1_cfg[] = {
1070 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1071 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1072 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1073 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1074 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1075 };
1076
1077 /* mode 2 - fits in 4KB */
1078 static struct musb_fifo_cfg __initdata mode_2_cfg[] = {
1079 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1080 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1081 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1082 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1083 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1084 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1085 };
1086
1087 /* mode 3 - fits in 4KB */
1088 static struct musb_fifo_cfg __initdata mode_3_cfg[] = {
1089 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1090 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1091 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1092 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1093 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1094 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1095 };
1096
1097 /* mode 4 - fits in 16KB */
1098 static struct musb_fifo_cfg __initdata mode_4_cfg[] = {
1099 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1100 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1101 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1102 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1103 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1104 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1105 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1106 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1107 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1108 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1109 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1110 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1111 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1112 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1113 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1114 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1115 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1116 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1117 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1118 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1119 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1120 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1121 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1122 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1123 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1124 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1125 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1126 };
1127
1128 /* mode 5 - fits in 8KB */
1129 static struct musb_fifo_cfg __initdata mode_5_cfg[] = {
1130 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1131 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1132 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1133 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1134 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1135 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1136 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1137 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1138 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1139 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1140 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1141 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1142 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1143 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1144 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1145 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1146 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1147 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1148 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1149 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1150 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1151 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1152 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1153 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1154 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1155 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1156 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1157 };
1158
1159 /*
1160 * configure a fifo; for non-shared endpoints, this may be called
1161 * once for a tx fifo and once for an rx fifo.
1162 *
1163 * returns negative errno or offset for next fifo.
1164 */
1165 static int __init
1166 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1167 const struct musb_fifo_cfg *cfg, u16 offset)
1168 {
1169 void __iomem *mbase = musb->mregs;
1170 int size = 0;
1171 u16 maxpacket = cfg->maxpacket;
1172 u16 c_off = offset >> 3;
1173 u8 c_size;
1174
1175 /* expect hw_ep has already been zero-initialized */
1176
1177 size = ffs(max(maxpacket, (u16) 8)) - 1;
1178 maxpacket = 1 << size;
1179
1180 c_size = size - 3;
1181 if (cfg->mode == BUF_DOUBLE) {
1182 if ((offset + (maxpacket << 1)) >
1183 (1 << (musb->config->ram_bits + 2)))
1184 return -EMSGSIZE;
1185 c_size |= MUSB_FIFOSZ_DPB;
1186 } else {
1187 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1188 return -EMSGSIZE;
1189 }
1190
1191 /* configure the FIFO */
1192 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1193
1194 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1195 /* EP0 reserved endpoint for control, bidirectional;
1196 * EP1 reserved for bulk, two unidirection halves.
1197 */
1198 if (hw_ep->epnum == 1)
1199 musb->bulk_ep = hw_ep;
1200 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1201 #endif
1202 switch (cfg->style) {
1203 case FIFO_TX:
1204 musb_write_txfifosz(mbase, c_size);
1205 musb_write_txfifoadd(mbase, c_off);
1206 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1207 hw_ep->max_packet_sz_tx = maxpacket;
1208 break;
1209 case FIFO_RX:
1210 musb_write_rxfifosz(mbase, c_size);
1211 musb_write_rxfifoadd(mbase, c_off);
1212 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1213 hw_ep->max_packet_sz_rx = maxpacket;
1214 break;
1215 case FIFO_RXTX:
1216 musb_write_txfifosz(mbase, c_size);
1217 musb_write_txfifoadd(mbase, c_off);
1218 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1219 hw_ep->max_packet_sz_rx = maxpacket;
1220
1221 musb_write_rxfifosz(mbase, c_size);
1222 musb_write_rxfifoadd(mbase, c_off);
1223 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1224 hw_ep->max_packet_sz_tx = maxpacket;
1225
1226 hw_ep->is_shared_fifo = true;
1227 break;
1228 }
1229
1230 /* NOTE rx and tx endpoint irqs aren't managed separately,
1231 * which happens to be ok
1232 */
1233 musb->epmask |= (1 << hw_ep->epnum);
1234
1235 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1236 }
1237
1238 static struct musb_fifo_cfg __initdata ep0_cfg = {
1239 .style = FIFO_RXTX, .maxpacket = 64,
1240 };
1241
1242 static int __init ep_config_from_table(struct musb *musb)
1243 {
1244 const struct musb_fifo_cfg *cfg;
1245 unsigned i, n;
1246 int offset;
1247 struct musb_hw_ep *hw_ep = musb->endpoints;
1248
1249 if (musb->config->fifo_cfg) {
1250 cfg = musb->config->fifo_cfg;
1251 n = musb->config->fifo_cfg_size;
1252 goto done;
1253 }
1254
1255 switch (fifo_mode) {
1256 default:
1257 fifo_mode = 0;
1258 /* FALLTHROUGH */
1259 case 0:
1260 cfg = mode_0_cfg;
1261 n = ARRAY_SIZE(mode_0_cfg);
1262 break;
1263 case 1:
1264 cfg = mode_1_cfg;
1265 n = ARRAY_SIZE(mode_1_cfg);
1266 break;
1267 case 2:
1268 cfg = mode_2_cfg;
1269 n = ARRAY_SIZE(mode_2_cfg);
1270 break;
1271 case 3:
1272 cfg = mode_3_cfg;
1273 n = ARRAY_SIZE(mode_3_cfg);
1274 break;
1275 case 4:
1276 cfg = mode_4_cfg;
1277 n = ARRAY_SIZE(mode_4_cfg);
1278 break;
1279 case 5:
1280 cfg = mode_5_cfg;
1281 n = ARRAY_SIZE(mode_5_cfg);
1282 break;
1283 }
1284
1285 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1286 musb_driver_name, fifo_mode);
1287
1288
1289 done:
1290 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1291 /* assert(offset > 0) */
1292
1293 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1294 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1295 */
1296
1297 for (i = 0; i < n; i++) {
1298 u8 epn = cfg->hw_ep_num;
1299
1300 if (epn >= musb->config->num_eps) {
1301 pr_debug("%s: invalid ep %d\n",
1302 musb_driver_name, epn);
1303 return -EINVAL;
1304 }
1305 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1306 if (offset < 0) {
1307 pr_debug("%s: mem overrun, ep %d\n",
1308 musb_driver_name, epn);
1309 return -EINVAL;
1310 }
1311 epn++;
1312 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1313 }
1314
1315 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1316 musb_driver_name,
1317 n + 1, musb->config->num_eps * 2 - 1,
1318 offset, (1 << (musb->config->ram_bits + 2)));
1319
1320 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1321 if (!musb->bulk_ep) {
1322 pr_debug("%s: missing bulk\n", musb_driver_name);
1323 return -EINVAL;
1324 }
1325 #endif
1326
1327 return 0;
1328 }
1329
1330
1331 /*
1332 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1333 * @param musb the controller
1334 */
1335 static int __init ep_config_from_hw(struct musb *musb)
1336 {
1337 u8 epnum = 0;
1338 struct musb_hw_ep *hw_ep;
1339 void *mbase = musb->mregs;
1340 int ret = 0;
1341
1342 dev_dbg(musb->controller, "<== static silicon ep config\n");
1343
1344 /* FIXME pick up ep0 maxpacket size */
1345
1346 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1347 musb_ep_select(mbase, epnum);
1348 hw_ep = musb->endpoints + epnum;
1349
1350 ret = musb_read_fifosize(musb, hw_ep, epnum);
1351 if (ret < 0)
1352 break;
1353
1354 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1355
1356 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1357 /* pick an RX/TX endpoint for bulk */
1358 if (hw_ep->max_packet_sz_tx < 512
1359 || hw_ep->max_packet_sz_rx < 512)
1360 continue;
1361
1362 /* REVISIT: this algorithm is lazy, we should at least
1363 * try to pick a double buffered endpoint.
1364 */
1365 if (musb->bulk_ep)
1366 continue;
1367 musb->bulk_ep = hw_ep;
1368 #endif
1369 }
1370
1371 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1372 if (!musb->bulk_ep) {
1373 pr_debug("%s: missing bulk\n", musb_driver_name);
1374 return -EINVAL;
1375 }
1376 #endif
1377
1378 return 0;
1379 }
1380
1381 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1382
1383 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1384 * configure endpoints, or take their config from silicon
1385 */
1386 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1387 {
1388 u8 reg;
1389 char *type;
1390 char aInfo[90], aRevision[32], aDate[12];
1391 void __iomem *mbase = musb->mregs;
1392 int status = 0;
1393 int i;
1394
1395 /* log core options (read using indexed model) */
1396 reg = musb_read_configdata(mbase);
1397
1398 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1399 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1400 strcat(aInfo, ", dyn FIFOs");
1401 musb->dyn_fifo = true;
1402 }
1403 if (reg & MUSB_CONFIGDATA_MPRXE) {
1404 strcat(aInfo, ", bulk combine");
1405 musb->bulk_combine = true;
1406 }
1407 if (reg & MUSB_CONFIGDATA_MPTXE) {
1408 strcat(aInfo, ", bulk split");
1409 musb->bulk_split = true;
1410 }
1411 if (reg & MUSB_CONFIGDATA_HBRXE) {
1412 strcat(aInfo, ", HB-ISO Rx");
1413 musb->hb_iso_rx = true;
1414 }
1415 if (reg & MUSB_CONFIGDATA_HBTXE) {
1416 strcat(aInfo, ", HB-ISO Tx");
1417 musb->hb_iso_tx = true;
1418 }
1419 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1420 strcat(aInfo, ", SoftConn");
1421
1422 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1423 musb_driver_name, reg, aInfo);
1424
1425 aDate[0] = 0;
1426 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1427 musb->is_multipoint = 1;
1428 type = "M";
1429 } else {
1430 musb->is_multipoint = 0;
1431 type = "";
1432 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1433 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1434 printk(KERN_ERR
1435 "%s: kernel must blacklist external hubs\n",
1436 musb_driver_name);
1437 #endif
1438 #endif
1439 }
1440
1441 /* log release info */
1442 musb->hwvers = musb_read_hwvers(mbase);
1443 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1444 MUSB_HWVERS_MINOR(musb->hwvers),
1445 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1446 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1447 musb_driver_name, type, aRevision, aDate);
1448
1449 /* configure ep0 */
1450 musb_configure_ep0(musb);
1451
1452 /* discover endpoint configuration */
1453 musb->nr_endpoints = 1;
1454 musb->epmask = 1;
1455
1456 if (musb->dyn_fifo)
1457 status = ep_config_from_table(musb);
1458 else
1459 status = ep_config_from_hw(musb);
1460
1461 if (status < 0)
1462 return status;
1463
1464 /* finish init, and print endpoint config */
1465 for (i = 0; i < musb->nr_endpoints; i++) {
1466 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1467
1468 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1469 #ifdef CONFIG_USB_MUSB_TUSB6010
1470 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1471 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1472 hw_ep->fifo_sync_va =
1473 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1474
1475 if (i == 0)
1476 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1477 else
1478 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1479 #endif
1480
1481 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1482 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1483 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1484 hw_ep->rx_reinit = 1;
1485 hw_ep->tx_reinit = 1;
1486 #endif
1487
1488 if (hw_ep->max_packet_sz_tx) {
1489 dev_dbg(musb->controller,
1490 "%s: hw_ep %d%s, %smax %d\n",
1491 musb_driver_name, i,
1492 hw_ep->is_shared_fifo ? "shared" : "tx",
1493 hw_ep->tx_double_buffered
1494 ? "doublebuffer, " : "",
1495 hw_ep->max_packet_sz_tx);
1496 }
1497 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1498 dev_dbg(musb->controller,
1499 "%s: hw_ep %d%s, %smax %d\n",
1500 musb_driver_name, i,
1501 "rx",
1502 hw_ep->rx_double_buffered
1503 ? "doublebuffer, " : "",
1504 hw_ep->max_packet_sz_rx);
1505 }
1506 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1507 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1508 }
1509
1510 return 0;
1511 }
1512
1513 /*-------------------------------------------------------------------------*/
1514
1515 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \
1516 defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500) || \
1517 defined(CONFIG_ARCH_U5500)
1518
1519 static irqreturn_t generic_interrupt(int irq, void *__hci)
1520 {
1521 unsigned long flags;
1522 irqreturn_t retval = IRQ_NONE;
1523 struct musb *musb = __hci;
1524
1525 spin_lock_irqsave(&musb->lock, flags);
1526
1527 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1528 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1529 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1530
1531 if (musb->int_usb || musb->int_tx || musb->int_rx)
1532 retval = musb_interrupt(musb);
1533
1534 spin_unlock_irqrestore(&musb->lock, flags);
1535
1536 return retval;
1537 }
1538
1539 #else
1540 #define generic_interrupt NULL
1541 #endif
1542
1543 /*
1544 * handle all the irqs defined by the HDRC core. for now we expect: other
1545 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1546 * will be assigned, and the irq will already have been acked.
1547 *
1548 * called in irq context with spinlock held, irqs blocked
1549 */
1550 irqreturn_t musb_interrupt(struct musb *musb)
1551 {
1552 irqreturn_t retval = IRQ_NONE;
1553 u8 devctl, power;
1554 int ep_num;
1555 u32 reg;
1556
1557 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1558 power = musb_readb(musb->mregs, MUSB_POWER);
1559
1560 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1561 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1562 musb->int_usb, musb->int_tx, musb->int_rx);
1563
1564 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1565 if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
1566 if (!musb->gadget_driver) {
1567 dev_dbg(musb->controller, "No gadget driver loaded\n");
1568 return IRQ_HANDLED;
1569 }
1570 #endif
1571
1572 /* the core can interrupt us for multiple reasons; docs have
1573 * a generic interrupt flowchart to follow
1574 */
1575 if (musb->int_usb)
1576 retval |= musb_stage0_irq(musb, musb->int_usb,
1577 devctl, power);
1578
1579 /* "stage 1" is handling endpoint irqs */
1580
1581 /* handle endpoint 0 first */
1582 if (musb->int_tx & 1) {
1583 if (devctl & MUSB_DEVCTL_HM)
1584 retval |= musb_h_ep0_irq(musb);
1585 else
1586 retval |= musb_g_ep0_irq(musb);
1587 }
1588
1589 /* RX on endpoints 1-15 */
1590 reg = musb->int_rx >> 1;
1591 ep_num = 1;
1592 while (reg) {
1593 if (reg & 1) {
1594 /* musb_ep_select(musb->mregs, ep_num); */
1595 /* REVISIT just retval = ep->rx_irq(...) */
1596 retval = IRQ_HANDLED;
1597 if (devctl & MUSB_DEVCTL_HM) {
1598 if (is_host_capable())
1599 musb_host_rx(musb, ep_num);
1600 } else {
1601 if (is_peripheral_capable())
1602 musb_g_rx(musb, ep_num);
1603 }
1604 }
1605
1606 reg >>= 1;
1607 ep_num++;
1608 }
1609
1610 /* TX on endpoints 1-15 */
1611 reg = musb->int_tx >> 1;
1612 ep_num = 1;
1613 while (reg) {
1614 if (reg & 1) {
1615 /* musb_ep_select(musb->mregs, ep_num); */
1616 /* REVISIT just retval |= ep->tx_irq(...) */
1617 retval = IRQ_HANDLED;
1618 if (devctl & MUSB_DEVCTL_HM) {
1619 if (is_host_capable())
1620 musb_host_tx(musb, ep_num);
1621 } else {
1622 if (is_peripheral_capable())
1623 musb_g_tx(musb, ep_num);
1624 }
1625 }
1626 reg >>= 1;
1627 ep_num++;
1628 }
1629
1630 return retval;
1631 }
1632 EXPORT_SYMBOL_GPL(musb_interrupt);
1633
1634 #ifndef CONFIG_MUSB_PIO_ONLY
1635 static int __initdata use_dma = 1;
1636
1637 /* "modprobe ... use_dma=0" etc */
1638 module_param(use_dma, bool, 0);
1639 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1640
1641 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1642 {
1643 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1644
1645 /* called with controller lock already held */
1646
1647 if (!epnum) {
1648 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1649 if (!is_cppi_enabled()) {
1650 /* endpoint 0 */
1651 if (devctl & MUSB_DEVCTL_HM)
1652 musb_h_ep0_irq(musb);
1653 else
1654 musb_g_ep0_irq(musb);
1655 }
1656 #endif
1657 } else {
1658 /* endpoints 1..15 */
1659 if (transmit) {
1660 if (devctl & MUSB_DEVCTL_HM) {
1661 if (is_host_capable())
1662 musb_host_tx(musb, epnum);
1663 } else {
1664 if (is_peripheral_capable())
1665 musb_g_tx(musb, epnum);
1666 }
1667 } else {
1668 /* receive */
1669 if (devctl & MUSB_DEVCTL_HM) {
1670 if (is_host_capable())
1671 musb_host_rx(musb, epnum);
1672 } else {
1673 if (is_peripheral_capable())
1674 musb_g_rx(musb, epnum);
1675 }
1676 }
1677 }
1678 }
1679
1680 #else
1681 #define use_dma 0
1682 #endif
1683
1684 /*-------------------------------------------------------------------------*/
1685
1686 #ifdef CONFIG_SYSFS
1687
1688 static ssize_t
1689 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1690 {
1691 struct musb *musb = dev_to_musb(dev);
1692 unsigned long flags;
1693 int ret = -EINVAL;
1694
1695 spin_lock_irqsave(&musb->lock, flags);
1696 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state));
1697 spin_unlock_irqrestore(&musb->lock, flags);
1698
1699 return ret;
1700 }
1701
1702 static ssize_t
1703 musb_mode_store(struct device *dev, struct device_attribute *attr,
1704 const char *buf, size_t n)
1705 {
1706 struct musb *musb = dev_to_musb(dev);
1707 unsigned long flags;
1708 int status;
1709
1710 spin_lock_irqsave(&musb->lock, flags);
1711 if (sysfs_streq(buf, "host"))
1712 status = musb_platform_set_mode(musb, MUSB_HOST);
1713 else if (sysfs_streq(buf, "peripheral"))
1714 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1715 else if (sysfs_streq(buf, "otg"))
1716 status = musb_platform_set_mode(musb, MUSB_OTG);
1717 else
1718 status = -EINVAL;
1719 spin_unlock_irqrestore(&musb->lock, flags);
1720
1721 return (status == 0) ? n : status;
1722 }
1723 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1724
1725 static ssize_t
1726 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1727 const char *buf, size_t n)
1728 {
1729 struct musb *musb = dev_to_musb(dev);
1730 unsigned long flags;
1731 unsigned long val;
1732
1733 if (sscanf(buf, "%lu", &val) < 1) {
1734 dev_err(dev, "Invalid VBUS timeout ms value\n");
1735 return -EINVAL;
1736 }
1737
1738 spin_lock_irqsave(&musb->lock, flags);
1739 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1740 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1741 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1742 musb->is_active = 0;
1743 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1744 spin_unlock_irqrestore(&musb->lock, flags);
1745
1746 return n;
1747 }
1748
1749 static ssize_t
1750 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1751 {
1752 struct musb *musb = dev_to_musb(dev);
1753 unsigned long flags;
1754 unsigned long val;
1755 int vbus;
1756
1757 spin_lock_irqsave(&musb->lock, flags);
1758 val = musb->a_wait_bcon;
1759 /* FIXME get_vbus_status() is normally #defined as false...
1760 * and is effectively TUSB-specific.
1761 */
1762 vbus = musb_platform_get_vbus_status(musb);
1763 spin_unlock_irqrestore(&musb->lock, flags);
1764
1765 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1766 vbus ? "on" : "off", val);
1767 }
1768 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1769
1770 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1771
1772 /* Gadget drivers can't know that a host is connected so they might want
1773 * to start SRP, but users can. This allows userspace to trigger SRP.
1774 */
1775 static ssize_t
1776 musb_srp_store(struct device *dev, struct device_attribute *attr,
1777 const char *buf, size_t n)
1778 {
1779 struct musb *musb = dev_to_musb(dev);
1780 unsigned short srp;
1781
1782 if (sscanf(buf, "%hu", &srp) != 1
1783 || (srp != 1)) {
1784 dev_err(dev, "SRP: Value must be 1\n");
1785 return -EINVAL;
1786 }
1787
1788 if (srp == 1)
1789 musb_g_wakeup(musb);
1790
1791 return n;
1792 }
1793 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1794
1795 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1796
1797 static struct attribute *musb_attributes[] = {
1798 &dev_attr_mode.attr,
1799 &dev_attr_vbus.attr,
1800 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1801 &dev_attr_srp.attr,
1802 #endif
1803 NULL
1804 };
1805
1806 static const struct attribute_group musb_attr_group = {
1807 .attrs = musb_attributes,
1808 };
1809
1810 #endif /* sysfs */
1811
1812 /* Only used to provide driver mode change events */
1813 static void musb_irq_work(struct work_struct *data)
1814 {
1815 struct musb *musb = container_of(data, struct musb, irq_work);
1816 static int old_state;
1817
1818 if (musb->xceiv->state != old_state) {
1819 old_state = musb->xceiv->state;
1820 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1821 }
1822 }
1823
1824 /* --------------------------------------------------------------------------
1825 * Init support
1826 */
1827
1828 static struct musb *__init
1829 allocate_instance(struct device *dev,
1830 struct musb_hdrc_config *config, void __iomem *mbase)
1831 {
1832 struct musb *musb;
1833 struct musb_hw_ep *ep;
1834 int epnum;
1835 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1836 struct usb_hcd *hcd;
1837
1838 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1839 if (!hcd)
1840 return NULL;
1841 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1842
1843 musb = hcd_to_musb(hcd);
1844 INIT_LIST_HEAD(&musb->control);
1845 INIT_LIST_HEAD(&musb->in_bulk);
1846 INIT_LIST_HEAD(&musb->out_bulk);
1847
1848 hcd->uses_new_polling = 1;
1849 hcd->has_tt = 1;
1850
1851 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1852 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1853 #else
1854 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1855 if (!musb)
1856 return NULL;
1857
1858 #endif
1859 dev_set_drvdata(dev, musb);
1860 musb->mregs = mbase;
1861 musb->ctrl_base = mbase;
1862 musb->nIrq = -ENODEV;
1863 musb->config = config;
1864 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1865 for (epnum = 0, ep = musb->endpoints;
1866 epnum < musb->config->num_eps;
1867 epnum++, ep++) {
1868 ep->musb = musb;
1869 ep->epnum = epnum;
1870 }
1871
1872 musb->controller = dev;
1873
1874 return musb;
1875 }
1876
1877 static void musb_free(struct musb *musb)
1878 {
1879 /* this has multiple entry modes. it handles fault cleanup after
1880 * probe(), where things may be partially set up, as well as rmmod
1881 * cleanup after everything's been de-activated.
1882 */
1883
1884 #ifdef CONFIG_SYSFS
1885 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1886 #endif
1887
1888 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1889 musb_gadget_cleanup(musb);
1890 #endif
1891
1892 if (musb->nIrq >= 0) {
1893 if (musb->irq_wake)
1894 disable_irq_wake(musb->nIrq);
1895 free_irq(musb->nIrq, musb);
1896 }
1897 if (is_dma_capable() && musb->dma_controller) {
1898 struct dma_controller *c = musb->dma_controller;
1899
1900 (void) c->stop(c);
1901 dma_controller_destroy(c);
1902 }
1903
1904 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1905 usb_put_hcd(musb_to_hcd(musb));
1906 #else
1907 kfree(musb);
1908 #endif
1909 }
1910
1911 /*
1912 * Perform generic per-controller initialization.
1913 *
1914 * @pDevice: the controller (already clocked, etc)
1915 * @nIrq: irq
1916 * @mregs: virtual address of controller registers,
1917 * not yet corrected for platform-specific offsets
1918 */
1919 static int __init
1920 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1921 {
1922 int status;
1923 struct musb *musb;
1924 struct musb_hdrc_platform_data *plat = dev->platform_data;
1925
1926 /* The driver might handle more features than the board; OK.
1927 * Fail when the board needs a feature that's not enabled.
1928 */
1929 if (!plat) {
1930 dev_dbg(dev, "no platform_data?\n");
1931 status = -ENODEV;
1932 goto fail0;
1933 }
1934
1935 /* allocate */
1936 musb = allocate_instance(dev, plat->config, ctrl);
1937 if (!musb) {
1938 status = -ENOMEM;
1939 goto fail0;
1940 }
1941
1942 pm_runtime_use_autosuspend(musb->controller);
1943 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1944 pm_runtime_enable(musb->controller);
1945
1946 spin_lock_init(&musb->lock);
1947 musb->board_mode = plat->mode;
1948 musb->board_set_power = plat->set_power;
1949 musb->min_power = plat->min_power;
1950 musb->ops = plat->platform_ops;
1951
1952 /* The musb_platform_init() call:
1953 * - adjusts musb->mregs and musb->isr if needed,
1954 * - may initialize an integrated tranceiver
1955 * - initializes musb->xceiv, usually by otg_get_transceiver()
1956 * - stops powering VBUS
1957 *
1958 * There are various transciever configurations. Blackfin,
1959 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1960 * external/discrete ones in various flavors (twl4030 family,
1961 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1962 */
1963 musb->isr = generic_interrupt;
1964 status = musb_platform_init(musb);
1965 if (status < 0)
1966 goto fail1;
1967
1968 if (!musb->isr) {
1969 status = -ENODEV;
1970 goto fail3;
1971 }
1972
1973 if (!musb->xceiv->io_ops) {
1974 musb->xceiv->io_priv = musb->mregs;
1975 musb->xceiv->io_ops = &musb_ulpi_access;
1976 }
1977
1978 #ifndef CONFIG_MUSB_PIO_ONLY
1979 if (use_dma && dev->dma_mask) {
1980 struct dma_controller *c;
1981
1982 c = dma_controller_create(musb, musb->mregs);
1983 musb->dma_controller = c;
1984 if (c)
1985 (void) c->start(c);
1986 }
1987 #endif
1988 /* ideally this would be abstracted in platform setup */
1989 if (!is_dma_capable() || !musb->dma_controller)
1990 dev->dma_mask = NULL;
1991
1992 /* be sure interrupts are disabled before connecting ISR */
1993 musb_platform_disable(musb);
1994 musb_generic_disable(musb);
1995
1996 /* setup musb parts of the core (especially endpoints) */
1997 status = musb_core_init(plat->config->multipoint
1998 ? MUSB_CONTROLLER_MHDRC
1999 : MUSB_CONTROLLER_HDRC, musb);
2000 if (status < 0)
2001 goto fail3;
2002
2003 #ifdef CONFIG_USB_MUSB_OTG
2004 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2005 #endif
2006
2007 /* Init IRQ workqueue before request_irq */
2008 INIT_WORK(&musb->irq_work, musb_irq_work);
2009
2010 /* attach to the IRQ */
2011 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2012 dev_err(dev, "request_irq %d failed!\n", nIrq);
2013 status = -ENODEV;
2014 goto fail3;
2015 }
2016 musb->nIrq = nIrq;
2017 /* FIXME this handles wakeup irqs wrong */
2018 if (enable_irq_wake(nIrq) == 0) {
2019 musb->irq_wake = 1;
2020 device_init_wakeup(dev, 1);
2021 } else {
2022 musb->irq_wake = 0;
2023 }
2024
2025 /* host side needs more setup */
2026 if (is_host_enabled(musb)) {
2027 struct usb_hcd *hcd = musb_to_hcd(musb);
2028
2029 otg_set_host(musb->xceiv, &hcd->self);
2030
2031 if (is_otg_enabled(musb))
2032 hcd->self.otg_port = 1;
2033 musb->xceiv->host = &hcd->self;
2034 hcd->power_budget = 2 * (plat->power ? : 250);
2035
2036 /* program PHY to use external vBus if required */
2037 if (plat->extvbus) {
2038 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2039 busctl |= MUSB_ULPI_USE_EXTVBUS;
2040 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2041 }
2042 }
2043
2044 /* For the host-only role, we can activate right away.
2045 * (We expect the ID pin to be forcibly grounded!!)
2046 * Otherwise, wait till the gadget driver hooks up.
2047 */
2048 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2049 struct usb_hcd *hcd = musb_to_hcd(musb);
2050
2051 MUSB_HST_MODE(musb);
2052 musb->xceiv->default_a = 1;
2053 musb->xceiv->state = OTG_STATE_A_IDLE;
2054
2055 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2056
2057 hcd->self.uses_pio_for_control = 1;
2058 dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n",
2059 "HOST", status,
2060 musb_readb(musb->mregs, MUSB_DEVCTL),
2061 (musb_readb(musb->mregs, MUSB_DEVCTL)
2062 & MUSB_DEVCTL_BDEVICE
2063 ? 'B' : 'A'));
2064
2065 } else /* peripheral is enabled */ {
2066 MUSB_DEV_MODE(musb);
2067 musb->xceiv->default_a = 0;
2068 musb->xceiv->state = OTG_STATE_B_IDLE;
2069
2070 status = musb_gadget_setup(musb);
2071
2072 dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n",
2073 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2074 status,
2075 musb_readb(musb->mregs, MUSB_DEVCTL));
2076
2077 }
2078 if (status < 0)
2079 goto fail3;
2080
2081 pm_runtime_put(musb->controller);
2082
2083 status = musb_init_debugfs(musb);
2084 if (status < 0)
2085 goto fail4;
2086
2087 #ifdef CONFIG_SYSFS
2088 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2089 if (status)
2090 goto fail5;
2091 #endif
2092
2093 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
2094 ({char *s;
2095 switch (musb->board_mode) {
2096 case MUSB_HOST: s = "Host"; break;
2097 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2098 default: s = "OTG"; break;
2099 }; s; }),
2100 ctrl,
2101 (is_dma_capable() && musb->dma_controller)
2102 ? "DMA" : "PIO",
2103 musb->nIrq);
2104
2105 return 0;
2106
2107 fail5:
2108 musb_exit_debugfs(musb);
2109
2110 fail4:
2111 if (!is_otg_enabled(musb) && is_host_enabled(musb))
2112 usb_remove_hcd(musb_to_hcd(musb));
2113 else
2114 musb_gadget_cleanup(musb);
2115
2116 fail3:
2117 if (musb->irq_wake)
2118 device_init_wakeup(dev, 0);
2119 musb_platform_exit(musb);
2120
2121 fail1:
2122 dev_err(musb->controller,
2123 "musb_init_controller failed with status %d\n", status);
2124
2125 musb_free(musb);
2126
2127 fail0:
2128
2129 return status;
2130
2131 }
2132
2133 /*-------------------------------------------------------------------------*/
2134
2135 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2136 * bridge to a platform device; this driver then suffices.
2137 */
2138
2139 #ifndef CONFIG_MUSB_PIO_ONLY
2140 static u64 *orig_dma_mask;
2141 #endif
2142
2143 static int __init musb_probe(struct platform_device *pdev)
2144 {
2145 struct device *dev = &pdev->dev;
2146 int irq = platform_get_irq_byname(pdev, "mc");
2147 int status;
2148 struct resource *iomem;
2149 void __iomem *base;
2150
2151 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2152 if (!iomem || irq <= 0)
2153 return -ENODEV;
2154
2155 base = ioremap(iomem->start, resource_size(iomem));
2156 if (!base) {
2157 dev_err(dev, "ioremap failed\n");
2158 return -ENOMEM;
2159 }
2160
2161 #ifndef CONFIG_MUSB_PIO_ONLY
2162 /* clobbered by use_dma=n */
2163 orig_dma_mask = dev->dma_mask;
2164 #endif
2165 status = musb_init_controller(dev, irq, base);
2166 if (status < 0)
2167 iounmap(base);
2168
2169 return status;
2170 }
2171
2172 static int __exit musb_remove(struct platform_device *pdev)
2173 {
2174 struct musb *musb = dev_to_musb(&pdev->dev);
2175 void __iomem *ctrl_base = musb->ctrl_base;
2176
2177 /* this gets called on rmmod.
2178 * - Host mode: host may still be active
2179 * - Peripheral mode: peripheral is deactivated (or never-activated)
2180 * - OTG mode: both roles are deactivated (or never-activated)
2181 */
2182 pm_runtime_get_sync(musb->controller);
2183 musb_exit_debugfs(musb);
2184 musb_shutdown(pdev);
2185
2186 pm_runtime_put(musb->controller);
2187 musb_free(musb);
2188 iounmap(ctrl_base);
2189 device_init_wakeup(&pdev->dev, 0);
2190 #ifndef CONFIG_MUSB_PIO_ONLY
2191 pdev->dev.dma_mask = orig_dma_mask;
2192 #endif
2193 return 0;
2194 }
2195
2196 #ifdef CONFIG_PM
2197
2198 static void musb_save_context(struct musb *musb)
2199 {
2200 int i;
2201 void __iomem *musb_base = musb->mregs;
2202 void __iomem *epio;
2203
2204 if (is_host_enabled(musb)) {
2205 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2206 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2207 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2208 }
2209 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2210 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2211 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2212 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2213 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2214 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2215
2216 for (i = 0; i < musb->config->num_eps; ++i) {
2217 struct musb_hw_ep *hw_ep;
2218
2219 hw_ep = &musb->endpoints[i];
2220 if (!hw_ep)
2221 continue;
2222
2223 epio = hw_ep->regs;
2224 if (!epio)
2225 continue;
2226
2227 musb->context.index_regs[i].txmaxp =
2228 musb_readw(epio, MUSB_TXMAXP);
2229 musb->context.index_regs[i].txcsr =
2230 musb_readw(epio, MUSB_TXCSR);
2231 musb->context.index_regs[i].rxmaxp =
2232 musb_readw(epio, MUSB_RXMAXP);
2233 musb->context.index_regs[i].rxcsr =
2234 musb_readw(epio, MUSB_RXCSR);
2235
2236 if (musb->dyn_fifo) {
2237 musb->context.index_regs[i].txfifoadd =
2238 musb_read_txfifoadd(musb_base);
2239 musb->context.index_regs[i].rxfifoadd =
2240 musb_read_rxfifoadd(musb_base);
2241 musb->context.index_regs[i].txfifosz =
2242 musb_read_txfifosz(musb_base);
2243 musb->context.index_regs[i].rxfifosz =
2244 musb_read_rxfifosz(musb_base);
2245 }
2246 if (is_host_enabled(musb)) {
2247 musb->context.index_regs[i].txtype =
2248 musb_readb(epio, MUSB_TXTYPE);
2249 musb->context.index_regs[i].txinterval =
2250 musb_readb(epio, MUSB_TXINTERVAL);
2251 musb->context.index_regs[i].rxtype =
2252 musb_readb(epio, MUSB_RXTYPE);
2253 musb->context.index_regs[i].rxinterval =
2254 musb_readb(epio, MUSB_RXINTERVAL);
2255
2256 musb->context.index_regs[i].txfunaddr =
2257 musb_read_txfunaddr(musb_base, i);
2258 musb->context.index_regs[i].txhubaddr =
2259 musb_read_txhubaddr(musb_base, i);
2260 musb->context.index_regs[i].txhubport =
2261 musb_read_txhubport(musb_base, i);
2262
2263 musb->context.index_regs[i].rxfunaddr =
2264 musb_read_rxfunaddr(musb_base, i);
2265 musb->context.index_regs[i].rxhubaddr =
2266 musb_read_rxhubaddr(musb_base, i);
2267 musb->context.index_regs[i].rxhubport =
2268 musb_read_rxhubport(musb_base, i);
2269 }
2270 }
2271 }
2272
2273 static void musb_restore_context(struct musb *musb)
2274 {
2275 int i;
2276 void __iomem *musb_base = musb->mregs;
2277 void __iomem *ep_target_regs;
2278 void __iomem *epio;
2279
2280 if (is_host_enabled(musb)) {
2281 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2282 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2283 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2284 }
2285 musb_writeb(musb_base, MUSB_POWER, musb->context.power);
2286 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe);
2287 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe);
2288 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2289 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2290
2291 for (i = 0; i < musb->config->num_eps; ++i) {
2292 struct musb_hw_ep *hw_ep;
2293
2294 hw_ep = &musb->endpoints[i];
2295 if (!hw_ep)
2296 continue;
2297
2298 epio = hw_ep->regs;
2299 if (!epio)
2300 continue;
2301
2302 musb_writew(epio, MUSB_TXMAXP,
2303 musb->context.index_regs[i].txmaxp);
2304 musb_writew(epio, MUSB_TXCSR,
2305 musb->context.index_regs[i].txcsr);
2306 musb_writew(epio, MUSB_RXMAXP,
2307 musb->context.index_regs[i].rxmaxp);
2308 musb_writew(epio, MUSB_RXCSR,
2309 musb->context.index_regs[i].rxcsr);
2310
2311 if (musb->dyn_fifo) {
2312 musb_write_txfifosz(musb_base,
2313 musb->context.index_regs[i].txfifosz);
2314 musb_write_rxfifosz(musb_base,
2315 musb->context.index_regs[i].rxfifosz);
2316 musb_write_txfifoadd(musb_base,
2317 musb->context.index_regs[i].txfifoadd);
2318 musb_write_rxfifoadd(musb_base,
2319 musb->context.index_regs[i].rxfifoadd);
2320 }
2321
2322 if (is_host_enabled(musb)) {
2323 musb_writeb(epio, MUSB_TXTYPE,
2324 musb->context.index_regs[i].txtype);
2325 musb_writeb(epio, MUSB_TXINTERVAL,
2326 musb->context.index_regs[i].txinterval);
2327 musb_writeb(epio, MUSB_RXTYPE,
2328 musb->context.index_regs[i].rxtype);
2329 musb_writeb(epio, MUSB_RXINTERVAL,
2330
2331 musb->context.index_regs[i].rxinterval);
2332 musb_write_txfunaddr(musb_base, i,
2333 musb->context.index_regs[i].txfunaddr);
2334 musb_write_txhubaddr(musb_base, i,
2335 musb->context.index_regs[i].txhubaddr);
2336 musb_write_txhubport(musb_base, i,
2337 musb->context.index_regs[i].txhubport);
2338
2339 ep_target_regs =
2340 musb_read_target_reg_base(i, musb_base);
2341
2342 musb_write_rxfunaddr(ep_target_regs,
2343 musb->context.index_regs[i].rxfunaddr);
2344 musb_write_rxhubaddr(ep_target_regs,
2345 musb->context.index_regs[i].rxhubaddr);
2346 musb_write_rxhubport(ep_target_regs,
2347 musb->context.index_regs[i].rxhubport);
2348 }
2349 }
2350 }
2351
2352 static int musb_suspend(struct device *dev)
2353 {
2354 struct platform_device *pdev = to_platform_device(dev);
2355 unsigned long flags;
2356 struct musb *musb = dev_to_musb(&pdev->dev);
2357
2358 spin_lock_irqsave(&musb->lock, flags);
2359
2360 if (is_peripheral_active(musb)) {
2361 /* FIXME force disconnect unless we know USB will wake
2362 * the system up quickly enough to respond ...
2363 */
2364 } else if (is_host_active(musb)) {
2365 /* we know all the children are suspended; sometimes
2366 * they will even be wakeup-enabled.
2367 */
2368 }
2369
2370 musb_save_context(musb);
2371
2372 spin_unlock_irqrestore(&musb->lock, flags);
2373 return 0;
2374 }
2375
2376 static int musb_resume_noirq(struct device *dev)
2377 {
2378 struct platform_device *pdev = to_platform_device(dev);
2379 struct musb *musb = dev_to_musb(&pdev->dev);
2380
2381 musb_restore_context(musb);
2382
2383 /* for static cmos like DaVinci, register values were preserved
2384 * unless for some reason the whole soc powered down or the USB
2385 * module got reset through the PSC (vs just being disabled).
2386 */
2387 return 0;
2388 }
2389
2390 static int musb_runtime_suspend(struct device *dev)
2391 {
2392 struct musb *musb = dev_to_musb(dev);
2393
2394 musb_save_context(musb);
2395
2396 return 0;
2397 }
2398
2399 static int musb_runtime_resume(struct device *dev)
2400 {
2401 struct musb *musb = dev_to_musb(dev);
2402 static int first = 1;
2403
2404 /*
2405 * When pm_runtime_get_sync called for the first time in driver
2406 * init, some of the structure is still not initialized which is
2407 * used in restore function. But clock needs to be
2408 * enabled before any register access, so
2409 * pm_runtime_get_sync has to be called.
2410 * Also context restore without save does not make
2411 * any sense
2412 */
2413 if (!first)
2414 musb_restore_context(musb);
2415 first = 0;
2416
2417 return 0;
2418 }
2419
2420 static const struct dev_pm_ops musb_dev_pm_ops = {
2421 .suspend = musb_suspend,
2422 .resume_noirq = musb_resume_noirq,
2423 .runtime_suspend = musb_runtime_suspend,
2424 .runtime_resume = musb_runtime_resume,
2425 };
2426
2427 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2428 #else
2429 #define MUSB_DEV_PM_OPS NULL
2430 #endif
2431
2432 static struct platform_driver musb_driver = {
2433 .driver = {
2434 .name = (char *)musb_driver_name,
2435 .bus = &platform_bus_type,
2436 .owner = THIS_MODULE,
2437 .pm = MUSB_DEV_PM_OPS,
2438 },
2439 .remove = __exit_p(musb_remove),
2440 .shutdown = musb_shutdown,
2441 };
2442
2443 /*-------------------------------------------------------------------------*/
2444
2445 static int __init musb_init(void)
2446 {
2447 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2448 if (usb_disabled())
2449 return 0;
2450 #endif
2451
2452 pr_info("%s: version " MUSB_VERSION ", "
2453 #ifdef CONFIG_MUSB_PIO_ONLY
2454 "pio"
2455 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2456 "cppi-dma"
2457 #elif defined(CONFIG_USB_INVENTRA_DMA)
2458 "musb-dma"
2459 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2460 "tusb-omap-dma"
2461 #elif defined(CONFIG_USB_UX500_DMA)
2462 "ux500-dma"
2463 #else
2464 "?dma?"
2465 #endif
2466 ", "
2467 #ifdef CONFIG_USB_MUSB_OTG
2468 "otg (peripheral+host)"
2469 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2470 "peripheral"
2471 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2472 "host"
2473 #endif
2474 ,
2475 musb_driver_name);
2476 return platform_driver_probe(&musb_driver, musb_probe);
2477 }
2478
2479 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2480 * and before usb gadget and host-side drivers start to register
2481 */
2482 fs_initcall(musb_init);
2483
2484 static void __exit musb_cleanup(void)
2485 {
2486 platform_driver_unregister(&musb_driver);
2487 }
2488 module_exit(musb_cleanup);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree