include/asm-ppc/reg_booke.h

   1 /*
   2  * Contains register definitions common to the Book E PowerPC
   3  * specification.  Notice that while the IBM-40x series of CPUs
   4  * are not true Book E PowerPCs, they borrowed a number of features
   5  * before Book E was finalized, and are included here as well.  Unfortunatly,
   6  * they sometimes used different locations than true Book E CPUs did.
   7  */
   8 #ifdef __KERNEL__
   9 #ifndef __ASM_PPC_REG_BOOKE_H__
  10 #define __ASM_PPC_REG_BOOKE_H__
  11
  12 #ifndef __ASSEMBLY__
  13 /* Device Control Registers */
  14 void __mtdcr(int reg, unsigned int val);
  15 unsigned int __mfdcr(int reg);
  16 #define mfdcr(rn)                                               \
  17         ({unsigned int rval;                                    \
  18         if (__builtin_constant_p(rn))                           \
  19                 asm volatile("mfdcr %0," __stringify(rn)        \
  20                               : "=r" (rval));                   \
  21         else                                                    \
  22                 rval = __mfdcr(rn);                             \
  23         rval;})
  24
  25 #define mtdcr(rn, v)                                            \
  26 do {                                                            \
  27         if (__builtin_constant_p(rn))                           \
  28                 asm volatile("mtdcr " __stringify(rn) ",%0"     \
  29                               : : "r" (v));                     \
  30         else                                                    \
  31                 __mtdcr(rn, v);                                 \
  32 } while (0)
  33
  34 /* R/W of indirect DCRs make use of standard naming conventions for DCRs */
  35 #define mfdcri(base, reg)                       \
  36 ({                                              \
  37         mtdcr(base ## _CFGADDR, base ## _ ## reg);      \
  38         mfdcr(base ## _CFGDATA);                        \
  39 })
  40
  41 #define mtdcri(base, reg, data)                 \
  42 do {                                            \
  43         mtdcr(base ## _CFGADDR, base ## _ ## reg);      \
  44         mtdcr(base ## _CFGDATA, data);          \
  45 } while (0)
  46
  47 /* Performance Monitor Registers */
  48 #define mfpmr(rn)       ({unsigned int rval; \
  49                         asm volatile("mfpmr %0," __stringify(rn) \
  50                                      : "=r" (rval)); rval;})
  51 #define mtpmr(rn, v)    asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v))
  52 #endif /* __ASSEMBLY__ */
  53
  54 /* Freescale Book E Performance Monitor APU Registers */
  55 #define PMRN_PMC0       0x010   /* Performance Monitor Counter 0 */
  56 #define PMRN_PMC1       0x011   /* Performance Monitor Counter 1 */
  57 #define PMRN_PMC2       0x012   /* Performance Monitor Counter 1 */
  58 #define PMRN_PMC3       0x013   /* Performance Monitor Counter 1 */
  59 #define PMRN_PMLCA0     0x090   /* PM Local Control A0 */
  60 #define PMRN_PMLCA1     0x091   /* PM Local Control A1 */
  61 #define PMRN_PMLCA2     0x092   /* PM Local Control A2 */
  62 #define PMRN_PMLCA3     0x093   /* PM Local Control A3 */
  63
  64 #define PMLCA_FC        0x80000000      /* Freeze Counter */
  65 #define PMLCA_FCS       0x40000000      /* Freeze in Supervisor */
  66 #define PMLCA_FCU       0x20000000      /* Freeze in User */
  67 #define PMLCA_FCM1      0x10000000      /* Freeze when PMM==1 */
  68 #define PMLCA_FCM0      0x08000000      /* Freeze when PMM==0 */
  69 #define PMLCA_CE        0x04000000      /* Condition Enable */
  70
  71 #define PMLCA_EVENT_MASK 0x007f0000     /* Event field */
  72 #define PMLCA_EVENT_SHIFT       16
  73
  74 #define PMRN_PMLCB0     0x110   /* PM Local Control B0 */
  75 #define PMRN_PMLCB1     0x111   /* PM Local Control B1 */
  76 #define PMRN_PMLCB2     0x112   /* PM Local Control B2 */
  77 #define PMRN_PMLCB3     0x113   /* PM Local Control B3 */
  78
  79 #define PMLCB_THRESHMUL_MASK    0x0700  /* Threshhold Multiple Field */
  80 #define PMLCB_THRESHMUL_SHIFT   8
  81
  82 #define PMLCB_THRESHOLD_MASK    0x003f  /* Threshold Field */
  83 #define PMLCB_THRESHOLD_SHIFT   0
  84
  85 #define PMRN_PMGC0      0x190   /* PM Global Control 0 */
  86
  87 #define PMGC0_FAC       0x80000000      /* Freeze all Counters */
  88 #define PMGC0_PMIE      0x40000000      /* Interrupt Enable */
  89 #define PMGC0_FCECE     0x20000000      /* Freeze countes on
  90                                            Enabled Condition or
  91                                            Event */
  92
  93 #define PMRN_UPMC0      0x000   /* User Performance Monitor Counter 0 */
  94 #define PMRN_UPMC1      0x001   /* User Performance Monitor Counter 1 */
  95 #define PMRN_UPMC2      0x002   /* User Performance Monitor Counter 1 */
  96 #define PMRN_UPMC3      0x003   /* User Performance Monitor Counter 1 */
  97 #define PMRN_UPMLCA0    0x080   /* User PM Local Control A0 */
  98 #define PMRN_UPMLCA1    0x081   /* User PM Local Control A1 */
  99 #define PMRN_UPMLCA2    0x082   /* User PM Local Control A2 */
 100 #define PMRN_UPMLCA3    0x083   /* User PM Local Control A3 */
 101 #define PMRN_UPMLCB0    0x100   /* User PM Local Control B0 */
 102 #define PMRN_UPMLCB1    0x101   /* User PM Local Control B1 */
 103 #define PMRN_UPMLCB2    0x102   /* User PM Local Control B2 */
 104 #define PMRN_UPMLCB3    0x103   /* User PM Local Control B3 */
 105 #define PMRN_UPMGC0     0x180   /* User PM Global Control 0 */
 106
 107
 108 /* Machine State Register (MSR) Fields */
 109 #define MSR_UCLE        (1<<26) /* User-mode cache lock enable */
 110 #define MSR_SPE         (1<<25) /* Enable SPE */
 111 #define MSR_DWE         (1<<10) /* Debug Wait Enable */
 112 #define MSR_UBLE        (1<<10) /* BTB lock enable (e500) */
 113 #define MSR_IS          MSR_IR  /* Instruction Space */
 114 #define MSR_DS          MSR_DR  /* Data Space */
 115 #define MSR_PMM         (1<<2)  /* Performance monitor mark bit */
 116
 117 /* Default MSR for kernel mode. */
 118 #if defined (CONFIG_40x)
 119 #define MSR_KERNEL      (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
 120 #elif defined(CONFIG_BOOKE)
 121 #define MSR_KERNEL      (MSR_ME|MSR_RI|MSR_CE)
 122 #endif
 123
 124 /* Special Purpose Registers (SPRNs)*/
 125 #define SPRN_DECAR      0x036   /* Decrementer Auto Reload Register */
 126 #define SPRN_IVPR       0x03F   /* Interrupt Vector Prefix Register */
 127 #define SPRN_USPRG0     0x100   /* User Special Purpose Register General 0 */
 128 #define SPRN_SPRG4R     0x104   /* Special Purpose Register General 4 Read */
 129 #define SPRN_SPRG5R     0x105   /* Special Purpose Register General 5 Read */
 130 #define SPRN_SPRG6R     0x106   /* Special Purpose Register General 6 Read */
 131 #define SPRN_SPRG7R     0x107   /* Special Purpose Register General 7 Read */
 132 #define SPRN_SPRG4W     0x114   /* Special Purpose Register General 4 Write */
 133 #define SPRN_SPRG5W     0x115   /* Special Purpose Register General 5 Write */
 134 #define SPRN_SPRG6W     0x116   /* Special Purpose Register General 6 Write */
 135 #define SPRN_SPRG7W     0x117   /* Special Purpose Register General 7 Write */
 136 #define SPRN_DBCR2      0x136   /* Debug Control Register 2 */
 137 #define SPRN_IAC3       0x13A   /* Instruction Address Compare 3 */
 138 #define SPRN_IAC4       0x13B   /* Instruction Address Compare 4 */
 139 #define SPRN_DVC1       0x13E   /* Data Value Compare Register 1 */
 140 #define SPRN_DVC2       0x13F   /* Data Value Compare Register 2 */
 141 #define SPRN_IVOR0      0x190   /* Interrupt Vector Offset Register 0 */
 142 #define SPRN_IVOR1      0x191   /* Interrupt Vector Offset Register 1 */
 143 #define SPRN_IVOR2      0x192   /* Interrupt Vector Offset Register 2 */
 144 #define SPRN_IVOR3      0x193   /* Interrupt Vector Offset Register 3 */
 145 #define SPRN_IVOR4      0x194   /* Interrupt Vector Offset Register 4 */
 146 #define SPRN_IVOR5      0x195   /* Interrupt Vector Offset Register 5 */
 147 #define SPRN_IVOR6      0x196   /* Interrupt Vector Offset Register 6 */
 148 #define SPRN_IVOR7      0x197   /* Interrupt Vector Offset Register 7 */
 149 #define SPRN_IVOR8      0x198   /* Interrupt Vector Offset Register 8 */
 150 #define SPRN_IVOR9      0x199   /* Interrupt Vector Offset Register 9 */
 151 #define SPRN_IVOR10     0x19A   /* Interrupt Vector Offset Register 10 */
 152 #define SPRN_IVOR11     0x19B   /* Interrupt Vector Offset Register 11 */
 153 #define SPRN_IVOR12     0x19C   /* Interrupt Vector Offset Register 12 */
 154 #define SPRN_IVOR13     0x19D   /* Interrupt Vector Offset Register 13 */
 155 #define SPRN_IVOR14     0x19E   /* Interrupt Vector Offset Register 14 */
 156 #define SPRN_IVOR15     0x19F   /* Interrupt Vector Offset Register 15 */
 157 #define SPRN_SPEFSCR    0x200   /* SPE & Embedded FP Status & Control */
 158 #define SPRN_BBEAR      0x201   /* Branch Buffer Entry Address Register */
 159 #define SPRN_BBTAR      0x202   /* Branch Buffer Target Address Register */
 160 #define SPRN_IVOR32     0x210   /* Interrupt Vector Offset Register 32 */
 161 #define SPRN_IVOR33     0x211   /* Interrupt Vector Offset Register 33 */
 162 #define SPRN_IVOR34     0x212   /* Interrupt Vector Offset Register 34 */
 163 #define SPRN_IVOR35     0x213   /* Interrupt Vector Offset Register 35 */
 164 #define SPRN_MCSRR0     0x23A   /* Machine Check Save and Restore Register 0 */
 165 #define SPRN_MCSRR1     0x23B   /* Machine Check Save and Restore Register 1 */
 166 #define SPRN_MCSR       0x23C   /* Machine Check Status Register */
 167 #define SPRN_MCAR       0x23D   /* Machine Check Address Register */
 168 #define SPRN_DSRR0      0x23E   /* Debug Save and Restore Register 0 */
 169 #define SPRN_DSRR1      0x23F   /* Debug Save and Restore Register 1 */
 170 #define SPRN_MAS0       0x270   /* MMU Assist Register 0 */
 171 #define SPRN_MAS1       0x271   /* MMU Assist Register 1 */
 172 #define SPRN_MAS2       0x272   /* MMU Assist Register 2 */
 173 #define SPRN_MAS3       0x273   /* MMU Assist Register 3 */
 174 #define SPRN_MAS4       0x274   /* MMU Assist Register 4 */
 175 #define SPRN_MAS5       0x275   /* MMU Assist Register 5 */
 176 #define SPRN_MAS6       0x276   /* MMU Assist Register 6 */
 177 #define SPRN_MAS7       0x3b0   /* MMU Assist Register 7 */
 178 #define SPRN_PID1       0x279   /* Process ID Register 1 */
 179 #define SPRN_PID2       0x27A   /* Process ID Register 2 */
 180 #define SPRN_TLB0CFG    0x2B0   /* TLB 0 Config Register */
 181 #define SPRN_TLB1CFG    0x2B1   /* TLB 1 Config Register */
 182 #define SPRN_CCR1       0x378   /* Core Configuration Register 1 */
 183 #define SPRN_ZPR        0x3B0   /* Zone Protection Register (40x) */
 184 #define SPRN_MMUCR      0x3B2   /* MMU Control Register */
 185 #define SPRN_CCR0       0x3B3   /* Core Configuration Register 0 */
 186 #define SPRN_SGR        0x3B9   /* Storage Guarded Register */
 187 #define SPRN_DCWR       0x3BA   /* Data Cache Write-thru Register */
 188 #define SPRN_SLER       0x3BB   /* Little-endian real mode */
 189 #define SPRN_SU0R       0x3BC   /* "User 0" real mode (40x) */
 190 #define SPRN_DCMP       0x3D1   /* Data TLB Compare Register */
 191 #define SPRN_ICDBDR     0x3D3   /* Instruction Cache Debug Data Register */
 192 #define SPRN_EVPR       0x3D6   /* Exception Vector Prefix Register */
 193 #define SPRN_L1CSR0     0x3F2   /* L1 Cache Control and Status Register 0 */
 194 #define SPRN_L1CSR1     0x3F3   /* L1 Cache Control and Status Register 1 */
 195 #define SPRN_PIT        0x3DB   /* Programmable Interval Timer */
 196 #define SPRN_DCCR       0x3FA   /* Data Cache Cacheability Register */
 197 #define SPRN_ICCR       0x3FB   /* Instruction Cache Cacheability Register */
 198 #define SPRN_SVR        0x3FF   /* System Version Register */
 199
 200 /*
 201  * SPRs which have conflicting definitions on true Book E versus classic,
 202  * or IBM 40x.
 203  */
 204 #ifdef CONFIG_BOOKE
 205 #define SPRN_PID        0x030   /* Process ID */
 206 #define SPRN_PID0       SPRN_PID/* Process ID Register 0 */
 207 #define SPRN_CSRR0      0x03A   /* Critical Save and Restore Register 0 */
 208 #define SPRN_CSRR1      0x03B   /* Critical Save and Restore Register 1 */
 209 #define SPRN_DEAR       0x03D   /* Data Error Address Register */
 210 #define SPRN_ESR        0x03E   /* Exception Syndrome Register */
 211 #define SPRN_PIR        0x11E   /* Processor Identification Register */
 212 #define SPRN_DBSR       0x130   /* Debug Status Register */
 213 #define SPRN_DBCR0      0x134   /* Debug Control Register 0 */
 214 #define SPRN_DBCR1      0x135   /* Debug Control Register 1 */
 215 #define SPRN_IAC1       0x138   /* Instruction Address Compare 1 */
 216 #define SPRN_IAC2       0x139   /* Instruction Address Compare 2 */
 217 #define SPRN_DAC1       0x13C   /* Data Address Compare 1 */
 218 #define SPRN_DAC2       0x13D   /* Data Address Compare 2 */
 219 #define SPRN_TSR        0x150   /* Timer Status Register */
 220 #define SPRN_TCR        0x154   /* Timer Control Register */
 221 #endif /* Book E */
 222 #ifdef CONFIG_40x
 223 #define SPRN_PID        0x3B1   /* Process ID */
 224 #define SPRN_DBCR1      0x3BD   /* Debug Control Register 1 */
 225 #define SPRN_ESR        0x3D4   /* Exception Syndrome Register */
 226 #define SPRN_DEAR       0x3D5   /* Data Error Address Register */
 227 #define SPRN_TSR        0x3D8   /* Timer Status Register */
 228 #define SPRN_TCR        0x3DA   /* Timer Control Register */
 229 #define SPRN_SRR2       0x3DE   /* Save/Restore Register 2 */
 230 #define SPRN_SRR3       0x3DF   /* Save/Restore Register 3 */
 231 #define SPRN_DBSR       0x3F0   /* Debug Status Register */
 232 #define SPRN_DBCR0      0x3F2   /* Debug Control Register 0 */
 233 #define SPRN_DAC1       0x3F6   /* Data Address Compare 1 */
 234 #define SPRN_DAC2       0x3F7   /* Data Address Compare 2 */
 235 #define SPRN_CSRR0      SPRN_SRR2 /* Critical Save and Restore Register 0 */
 236 #define SPRN_CSRR1      SPRN_SRR3 /* Critical Save and Restore Register 1 */
 237 #endif
 238
 239 /* Bit definitions for CCR1. */
 240 #define CCR1_TCS        0x00000080 /* Timer Clock Select */
 241
 242 /* Bit definitions for the MCSR. */
 243 #ifdef CONFIG_440A
 244 #define MCSR_MCS        0x80000000 /* Machine Check Summary */
 245 #define MCSR_IB         0x40000000 /* Instruction PLB Error */
 246 #define MCSR_DRB        0x20000000 /* Data Read PLB Error */
 247 #define MCSR_DWB        0x10000000 /* Data Write PLB Error */
 248 #define MCSR_TLBP       0x08000000 /* TLB Parity Error */
 249 #define MCSR_ICP        0x04000000 /* I-Cache Parity Error */
 250 #define MCSR_DCSP       0x02000000 /* D-Cache Search Parity Error */
 251 #define MCSR_DCFP       0x01000000 /* D-Cache Flush Parity Error */
 252 #define MCSR_IMPE       0x00800000 /* Imprecise Machine Check Exception */
 253 #endif
 254 #ifdef CONFIG_E500
 255 #define MCSR_MCP        0x80000000UL /* Machine Check Input Pin */
 256 #define MCSR_ICPERR     0x40000000UL /* I-Cache Parity Error */
 257 #define MCSR_DCP_PERR   0x20000000UL /* D-Cache Push Parity Error */
 258 #define MCSR_DCPERR     0x10000000UL /* D-Cache Parity Error */
 259 #define MCSR_GL_CI      0x00010000UL /* Guarded Load or Cache-Inhibited stwcx. */
 260 #define MCSR_BUS_IAERR  0x00000080UL /* Instruction Address Error */
 261 #define MCSR_BUS_RAERR  0x00000040UL /* Read Address Error */
 262 #define MCSR_BUS_WAERR  0x00000020UL /* Write Address Error */
 263 #define MCSR_BUS_IBERR  0x00000010UL /* Instruction Data Error */
 264 #define MCSR_BUS_RBERR  0x00000008UL /* Read Data Bus Error */
 265 #define MCSR_BUS_WBERR  0x00000004UL /* Write Data Bus Error */
 266 #define MCSR_BUS_IPERR  0x00000002UL /* Instruction parity Error */
 267 #define MCSR_BUS_RPERR  0x00000001UL /* Read parity Error */
 268 #endif
 269 #ifdef CONFIG_E200
 270 #define MCSR_MCP        0x80000000UL /* Machine Check Input Pin */
 271 #define MCSR_CP_PERR    0x20000000UL /* Cache Push Parity Error */
 272 #define MCSR_CPERR      0x10000000UL /* Cache Parity Error */
 273 #define MCSR_EXCP_ERR   0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn
 274                                         fetch for an exception handler */
 275 #define MCSR_BUS_IRERR  0x00000010UL /* Read Bus Error on instruction fetch*/
 276 #define MCSR_BUS_DRERR  0x00000008UL /* Read Bus Error on data load */
 277 #define MCSR_BUS_WRERR  0x00000004UL /* Write Bus Error on buffered
 278                                         store or cache line push */
 279 #endif
 280
 281 /* Bit definitions for the DBSR. */
 282 /*
 283  * DBSR bits which have conflicting definitions on true Book E versus IBM 40x.
 284  */
 285 #ifdef CONFIG_BOOKE
 286 #define DBSR_IC         0x08000000      /* Instruction Completion */
 287 #define DBSR_BT         0x04000000      /* Branch Taken */
 288 #define DBSR_TIE        0x01000000      /* Trap Instruction Event */
 289 #define DBSR_IAC1       0x00800000      /* Instr Address Compare 1 Event */
 290 #define DBSR_IAC2       0x00400000      /* Instr Address Compare 2 Event */
 291 #define DBSR_IAC3       0x00200000      /* Instr Address Compare 3 Event */
 292 #define DBSR_IAC4       0x00100000      /* Instr Address Compare 4 Event */
 293 #define DBSR_DAC1R      0x00080000      /* Data Addr Compare 1 Read Event */
 294 #define DBSR_DAC1W      0x00040000      /* Data Addr Compare 1 Write Event */
 295 #define DBSR_DAC2R      0x00020000      /* Data Addr Compare 2 Read Event */
 296 #define DBSR_DAC2W      0x00010000      /* Data Addr Compare 2 Write Event */
 297 #endif
 298 #ifdef CONFIG_40x
 299 #define DBSR_IC         0x80000000      /* Instruction Completion */
 300 #define DBSR_BT         0x40000000      /* Branch taken */
 301 #define DBSR_TIE        0x10000000      /* Trap Instruction debug Event */
 302 #define DBSR_IAC1       0x00800000      /* Instruction Address Compare 1 Event */
 303 #define DBSR_IAC2       0x00400000      /* Instruction Address Compare 2 Event */
 304 #define DBSR_IAC3       0x00200000      /* Instruction Address Compare 3 Event */
 305 #define DBSR_IAC4       0x00100000      /* Instruction Address Compare 4 Event */
 306 #define DBSR_DAC1R      0x00080000      /* Data Address Compare 1 Read Event */
 307 #define DBSR_DAC1W      0x00040000      /* Data Address Compare 1 Write Event */
 308 #define DBSR_DAC2R      0x00020000      /* Data Address Compare 2 Read Event */
 309 #define DBSR_DAC2W      0x00010000      /* Data Address Compare 2 Write Event */
 310 #endif
 311
 312 /* Bit definitions related to the ESR. */
 313 #define ESR_MCI         0x80000000      /* Machine Check - Instruction */
 314 #define ESR_IMCP        0x80000000      /* Instr. Machine Check - Protection */
 315 #define ESR_IMCN        0x40000000      /* Instr. Machine Check - Non-config */
 316 #define ESR_IMCB        0x20000000      /* Instr. Machine Check - Bus error */
 317 #define ESR_IMCT        0x10000000      /* Instr. Machine Check - Timeout */
 318 #define ESR_PIL         0x08000000      /* Program Exception - Illegal */
 319 #define ESR_PPR         0x04000000      /* Program Exception - Priveleged */
 320 #define ESR_PTR         0x02000000      /* Program Exception - Trap */
 321 #define ESR_FP          0x01000000      /* Floating Point Operation */
 322 #define ESR_DST         0x00800000      /* Storage Exception - Data miss */
 323 #define ESR_DIZ         0x00400000      /* Storage Exception - Zone fault */
 324 #define ESR_ST          0x00800000      /* Store Operation */
 325 #define ESR_DLK         0x00200000      /* Data Cache Locking */
 326 #define ESR_ILK         0x00100000      /* Instr. Cache Locking */
 327 #define ESR_PUO         0x00040000      /* Unimplemented Operation exception */
 328 #define ESR_BO          0x00020000      /* Byte Ordering */
 329
 330 /* Bit definitions related to the DBCR0. */
 331 #define DBCR0_EDM       0x80000000      /* External Debug Mode */
 332 #define DBCR0_IDM       0x40000000      /* Internal Debug Mode */
 333 #define DBCR0_RST       0x30000000      /* all the bits in the RST field */
 334 #define DBCR0_RST_SYSTEM 0x30000000     /* System Reset */
 335 #define DBCR0_RST_CHIP  0x20000000      /* Chip Reset */
 336 #define DBCR0_RST_CORE  0x10000000      /* Core Reset */
 337 #define DBCR0_RST_NONE  0x00000000      /* No Reset */
 338 #define DBCR0_IC        0x08000000      /* Instruction Completion */
 339 #define DBCR0_BT        0x04000000      /* Branch Taken */
 340 #define DBCR0_EDE       0x02000000      /* Exception Debug Event */
 341 #define DBCR0_TDE       0x01000000      /* TRAP Debug Event */
 342 #define DBCR0_IA1       0x00800000      /* Instr Addr compare 1 enable */
 343 #define DBCR0_IA2       0x00400000      /* Instr Addr compare 2 enable */
 344 #define DBCR0_IA12      0x00200000      /* Instr Addr 1-2 range enable */
 345 #define DBCR0_IA12X     0x00100000      /* Instr Addr 1-2 range eXclusive */
 346 #define DBCR0_IA3       0x00080000      /* Instr Addr compare 3 enable */
 347 #define DBCR0_IA4       0x00040000      /* Instr Addr compare 4 enable */
 348 #define DBCR0_IA34      0x00020000      /* Instr Addr 3-4 range Enable */
 349 #define DBCR0_IA34X     0x00010000      /* Instr Addr 3-4 range eXclusive */
 350 #define DBCR0_IA12T     0x00008000      /* Instr Addr 1-2 range Toggle */
 351 #define DBCR0_IA34T     0x00004000      /* Instr Addr 3-4 range Toggle */
 352 #define DBCR0_FT        0x00000001      /* Freeze Timers on debug event */
 353
 354 /* Bit definitions related to the TCR. */
 355 #define TCR_WP(x)       (((x)&0x3)<<30) /* WDT Period */
 356 #define TCR_WP_MASK     TCR_WP(3)
 357 #define WP_2_17         0               /* 2^17 clocks */
 358 #define WP_2_21         1               /* 2^21 clocks */
 359 #define WP_2_25         2               /* 2^25 clocks */
 360 #define WP_2_29         3               /* 2^29 clocks */
 361 #define TCR_WRC(x)      (((x)&0x3)<<28) /* WDT Reset Control */
 362 #define TCR_WRC_MASK    TCR_WRC(3)
 363 #define WRC_NONE        0               /* No reset will occur */
 364 #define WRC_CORE        1               /* Core reset will occur */
 365 #define WRC_CHIP        2               /* Chip reset will occur */
 366 #define WRC_SYSTEM      3               /* System reset will occur */
 367 #define TCR_WIE         0x08000000      /* WDT Interrupt Enable */
 368 #define TCR_PIE         0x04000000      /* PIT Interrupt Enable */
 369 #define TCR_DIE         TCR_PIE         /* DEC Interrupt Enable */
 370 #define TCR_FP(x)       (((x)&0x3)<<24) /* FIT Period */
 371 #define TCR_FP_MASK     TCR_FP(3)
 372 #define FP_2_9          0               /* 2^9 clocks */
 373 #define FP_2_13         1               /* 2^13 clocks */
 374 #define FP_2_17         2               /* 2^17 clocks */
 375 #define FP_2_21         3               /* 2^21 clocks */
 376 #define TCR_FIE         0x00800000      /* FIT Interrupt Enable */
 377 #define TCR_ARE         0x00400000      /* Auto Reload Enable */
 378
 379 /* Bit definitions for the TSR. */
 380 #define TSR_ENW         0x80000000      /* Enable Next Watchdog */
 381 #define TSR_WIS         0x40000000      /* WDT Interrupt Status */
 382 #define TSR_WRS(x)      (((x)&0x3)<<28) /* WDT Reset Status */
 383 #define WRS_NONE        0               /* No WDT reset occurred */
 384 #define WRS_CORE        1               /* WDT forced core reset */
 385 #define WRS_CHIP        2               /* WDT forced chip reset */
 386 #define WRS_SYSTEM      3               /* WDT forced system reset */
 387 #define TSR_PIS         0x08000000      /* PIT Interrupt Status */
 388 #define TSR_DIS         TSR_PIS         /* DEC Interrupt Status */
 389 #define TSR_FIS         0x04000000      /* FIT Interrupt Status */
 390
 391 /* Bit definitions for the DCCR. */
 392 #define DCCR_NOCACHE    0               /* Noncacheable */
 393 #define DCCR_CACHE      1               /* Cacheable */
 394
 395 /* Bit definitions for DCWR. */
 396 #define DCWR_COPY       0               /* Copy-back */
 397 #define DCWR_WRITE      1               /* Write-through */
 398
 399 /* Bit definitions for ICCR. */
 400 #define ICCR_NOCACHE    0               /* Noncacheable */
 401 #define ICCR_CACHE      1               /* Cacheable */
 402
 403 /* Bit definitions for L1CSR0. */
 404 #define L1CSR0_CLFC     0x00000100      /* Cache Lock Bits Flash Clear */
 405 #define L1CSR0_DCFI     0x00000002      /* Data Cache Flash Invalidate */
 406 #define L1CSR0_CFI      0x00000002      /* Cache Flash Invalidate */
 407 #define L1CSR0_DCE      0x00000001      /* Data Cache Enable */
 408
 409 /* Bit definitions for L1CSR1. */
 410 #define L1CSR1_ICLFR    0x00000100      /* Instr Cache Lock Bits Flash Reset */
 411 #define L1CSR1_ICFI     0x00000002      /* Instr Cache Flash Invalidate */
 412 #define L1CSR1_ICE      0x00000001      /* Instr Cache Enable */
 413
 414 /* Bit definitions for SGR. */
 415 #define SGR_NORMAL      0               /* Speculative fetching allowed. */
 416 #define SGR_GUARDED     1               /* Speculative fetching disallowed. */
 417
 418 /* Bit definitions for SPEFSCR. */
 419 #define SPEFSCR_SOVH    0x80000000      /* Summary integer overflow high */
 420 #define SPEFSCR_OVH     0x40000000      /* Integer overflow high */
 421 #define SPEFSCR_FGH     0x20000000      /* Embedded FP guard bit high */
 422 #define SPEFSCR_FXH     0x10000000      /* Embedded FP sticky bit high */
 423 #define SPEFSCR_FINVH   0x08000000      /* Embedded FP invalid operation high */
 424 #define SPEFSCR_FDBZH   0x04000000      /* Embedded FP div by zero high */
 425 #define SPEFSCR_FUNFH   0x02000000      /* Embedded FP underflow high */
 426 #define SPEFSCR_FOVFH   0x01000000      /* Embedded FP overflow high */
 427 #define SPEFSCR_FINXS   0x00200000      /* Embedded FP inexact sticky */
 428 #define SPEFSCR_FINVS   0x00100000      /* Embedded FP invalid op. sticky */
 429 #define SPEFSCR_FDBZS   0x00080000      /* Embedded FP div by zero sticky */
 430 #define SPEFSCR_FUNFS   0x00040000      /* Embedded FP underflow sticky */
 431 #define SPEFSCR_FOVFS   0x00020000      /* Embedded FP overflow sticky */
 432 #define SPEFSCR_MODE    0x00010000      /* Embedded FP mode */
 433 #define SPEFSCR_SOV     0x00008000      /* Integer summary overflow */
 434 #define SPEFSCR_OV      0x00004000      /* Integer overflow */
 435 #define SPEFSCR_FG      0x00002000      /* Embedded FP guard bit */
 436 #define SPEFSCR_FX      0x00001000      /* Embedded FP sticky bit */
 437 #define SPEFSCR_FINV    0x00000800      /* Embedded FP invalid operation */
 438 #define SPEFSCR_FDBZ    0x00000400      /* Embedded FP div by zero */
 439 #define SPEFSCR_FUNF    0x00000200      /* Embedded FP underflow */
 440 #define SPEFSCR_FOVF    0x00000100      /* Embedded FP overflow */
 441 #define SPEFSCR_FINXE   0x00000040      /* Embedded FP inexact enable */
 442 #define SPEFSCR_FINVE   0x00000020      /* Embedded FP invalid op. enable */
 443 #define SPEFSCR_FDBZE   0x00000010      /* Embedded FP div by zero enable */
 444 #define SPEFSCR_FUNFE   0x00000008      /* Embedded FP underflow enable */
 445 #define SPEFSCR_FOVFE   0x00000004      /* Embedded FP overflow enable */
 446 #define SPEFSCR_FRMC    0x00000003      /* Embedded FP rounding mode control */
 447
 448 /*
 449  * The IBM-403 is an even more odd special case, as it is much
 450  * older than the IBM-405 series.  We put these down here incase someone
 451  * wishes to support these machines again.
 452  */
 453 #ifdef CONFIG_403GCX
 454 /* Special Purpose Registers (SPRNs)*/
 455 #define SPRN_TBHU       0x3CC   /* Time Base High User-mode */
 456 #define SPRN_TBLU       0x3CD   /* Time Base Low User-mode */
 457 #define SPRN_CDBCR      0x3D7   /* Cache Debug Control Register */
 458 #define SPRN_TBHI       0x3DC   /* Time Base High */
 459 #define SPRN_TBLO       0x3DD   /* Time Base Low */
 460 #define SPRN_DBCR       0x3F2   /* Debug Control Regsiter */
 461 #define SPRN_PBL1       0x3FC   /* Protection Bound Lower 1 */
 462 #define SPRN_PBL2       0x3FE   /* Protection Bound Lower 2 */
 463 #define SPRN_PBU1       0x3FD   /* Protection Bound Upper 1 */
 464 #define SPRN_PBU2       0x3FF   /* Protection Bound Upper 2 */
 465
 466
 467 /* Bit definitions for the DBCR. */
 468 #define DBCR_EDM        DBCR0_EDM
 469 #define DBCR_IDM        DBCR0_IDM
 470 #define DBCR_RST(x)     (((x) & 0x3) << 28)
 471 #define DBCR_RST_NONE   0
 472 #define DBCR_RST_CORE   1
 473 #define DBCR_RST_CHIP   2
 474 #define DBCR_RST_SYSTEM 3
 475 #define DBCR_IC         DBCR0_IC        /* Instruction Completion Debug Evnt */
 476 #define DBCR_BT         DBCR0_BT        /* Branch Taken Debug Event */
 477 #define DBCR_EDE        DBCR0_EDE       /* Exception Debug Event */
 478 #define DBCR_TDE        DBCR0_TDE       /* TRAP Debug Event */
 479 #define DBCR_FER        0x00F80000      /* First Events Remaining Mask */
 480 #define DBCR_FT         0x00040000      /* Freeze Timers on Debug Event */
 481 #define DBCR_IA1        0x00020000      /* Instr. Addr. Compare 1 Enable */
 482 #define DBCR_IA2        0x00010000      /* Instr. Addr. Compare 2 Enable */
 483 #define DBCR_D1R        0x00008000      /* Data Addr. Compare 1 Read Enable */
 484 #define DBCR_D1W        0x00004000      /* Data Addr. Compare 1 Write Enable */
 485 #define DBCR_D1S(x)     (((x) & 0x3) << 12)     /* Data Adrr. Compare 1 Size */
 486 #define DAC_BYTE        0
 487 #define DAC_HALF        1
 488 #define DAC_WORD        2
 489 #define DAC_QUAD        3
 490 #define DBCR_D2R        0x00000800      /* Data Addr. Compare 2 Read Enable */
 491 #define DBCR_D2W        0x00000400      /* Data Addr. Compare 2 Write Enable */
 492 #define DBCR_D2S(x)     (((x) & 0x3) << 8)      /* Data Addr. Compare 2 Size */
 493 #define DBCR_SBT        0x00000040      /* Second Branch Taken Debug Event */
 494 #define DBCR_SED        0x00000020      /* Second Exception Debug Event */
 495 #define DBCR_STD        0x00000010      /* Second Trap Debug Event */
 496 #define DBCR_SIA        0x00000008      /* Second IAC Enable */
 497 #define DBCR_SDA        0x00000004      /* Second DAC Enable */
 498 #define DBCR_JOI        0x00000002      /* JTAG Serial Outbound Int. Enable */
 499 #define DBCR_JII        0x00000001      /* JTAG Serial Inbound Int. Enable */
 500 #endif /* 403GCX */
 501 #endif /* __ASM_PPC_REG_BOOKE_H__ */
 502 #endif /* __KERNEL__ */