drivers/net/wireless/rt2x00/rt2800.h

   1 /*
   2         Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
   3         Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   4         Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5         Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
   6         Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
   7         Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
   8         Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
   9         Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
  10         <http://rt2x00.serialmonkey.com>
  11
  12         This program is free software; you can redistribute it and/or modify
  13         it under the terms of the GNU General Public License as published by
  14         the Free Software Foundation; either version 2 of the License, or
  15         (at your option) any later version.
  16
  17         This program is distributed in the hope that it will be useful,
  18         but WITHOUT ANY WARRANTY; without even the implied warranty of
  19         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20         GNU General Public License for more details.
  21
  22         You should have received a copy of the GNU General Public License
  23         along with this program; if not, write to the
  24         Free Software Foundation, Inc.,
  25         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  26  */
  27
  28 /*
  29         Module: rt2800
  30         Abstract: Data structures and registers for the rt2800 modules.
  31         Supported chipsets: RT2800E, RT2800ED & RT2800U.
  32  */
  33
  34 #ifndef RT2800_H
  35 #define RT2800_H
  36
  37 /*
  38  * RF chip defines.
  39  *
  40  * RF2820 2.4G 2T3R
  41  * RF2850 2.4G/5G 2T3R
  42  * RF2720 2.4G 1T2R
  43  * RF2750 2.4G/5G 1T2R
  44  * RF3020 2.4G 1T1R
  45  * RF2020 2.4G B/G
  46  * RF3021 2.4G 1T2R
  47  * RF3022 2.4G 2T2R
  48  * RF3052 2.4G 2T2R
  49  */
  50 #define RF2820                          0x0001
  51 #define RF2850                          0x0002
  52 #define RF2720                          0x0003
  53 #define RF2750                          0x0004
  54 #define RF3020                          0x0005
  55 #define RF2020                          0x0006
  56 #define RF3021                          0x0007
  57 #define RF3022                          0x0008
  58 #define RF3052                          0x0009
  59 #define RF3320                          0x000b
  60
  61 /*
  62  * Chipset revisions.
  63  */
  64 #define REV_RT2860C                     0x0100
  65 #define REV_RT2860D                     0x0101
  66 #define REV_RT2872E                     0x0200
  67 #define REV_RT3070E                     0x0200
  68 #define REV_RT3070F                     0x0201
  69 #define REV_RT3071E                     0x0211
  70 #define REV_RT3090E                     0x0211
  71 #define REV_RT3390E                     0x0211
  72
  73 /*
  74  * Signal information.
  75  * Default offset is required for RSSI <-> dBm conversion.
  76  */
  77 #define DEFAULT_RSSI_OFFSET             120 /* FIXME */
  78
  79 /*
  80  * Register layout information.
  81  */
  82 #define CSR_REG_BASE                    0x1000
  83 #define CSR_REG_SIZE                    0x0800
  84 #define EEPROM_BASE                     0x0000
  85 #define EEPROM_SIZE                     0x0110
  86 #define BBP_BASE                        0x0000
  87 #define BBP_SIZE                        0x0080
  88 #define RF_BASE                         0x0004
  89 #define RF_SIZE                         0x0010
  90
  91 /*
  92  * Number of TX queues.
  93  */
  94 #define NUM_TX_QUEUES                   4
  95
  96 /*
  97  * Registers.
  98  */
  99
 100 /*
 101  * E2PROM_CSR: PCI EEPROM control register.
 102  * RELOAD: Write 1 to reload eeprom content.
 103  * TYPE: 0: 93c46, 1:93c66.
 104  * LOAD_STATUS: 1:loading, 0:done.
 105  */
 106 #define E2PROM_CSR                      0x0004
 107 #define E2PROM_CSR_DATA_CLOCK           FIELD32(0x00000001)
 108 #define E2PROM_CSR_CHIP_SELECT          FIELD32(0x00000002)
 109 #define E2PROM_CSR_DATA_IN              FIELD32(0x00000004)
 110 #define E2PROM_CSR_DATA_OUT             FIELD32(0x00000008)
 111 #define E2PROM_CSR_TYPE                 FIELD32(0x00000030)
 112 #define E2PROM_CSR_LOAD_STATUS          FIELD32(0x00000040)
 113 #define E2PROM_CSR_RELOAD               FIELD32(0x00000080)
 114
 115 /*
 116  * OPT_14: Unknown register used by rt3xxx devices.
 117  */
 118 #define OPT_14_CSR                      0x0114
 119 #define OPT_14_CSR_BIT0                 FIELD32(0x00000001)
 120
 121 /*
 122  * INT_SOURCE_CSR: Interrupt source register.
 123  * Write one to clear corresponding bit.
 124  * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO
 125  */
 126 #define INT_SOURCE_CSR                  0x0200
 127 #define INT_SOURCE_CSR_RXDELAYINT       FIELD32(0x00000001)
 128 #define INT_SOURCE_CSR_TXDELAYINT       FIELD32(0x00000002)
 129 #define INT_SOURCE_CSR_RX_DONE          FIELD32(0x00000004)
 130 #define INT_SOURCE_CSR_AC0_DMA_DONE     FIELD32(0x00000008)
 131 #define INT_SOURCE_CSR_AC1_DMA_DONE     FIELD32(0x00000010)
 132 #define INT_SOURCE_CSR_AC2_DMA_DONE     FIELD32(0x00000020)
 133 #define INT_SOURCE_CSR_AC3_DMA_DONE     FIELD32(0x00000040)
 134 #define INT_SOURCE_CSR_HCCA_DMA_DONE    FIELD32(0x00000080)
 135 #define INT_SOURCE_CSR_MGMT_DMA_DONE    FIELD32(0x00000100)
 136 #define INT_SOURCE_CSR_MCU_COMMAND      FIELD32(0x00000200)
 137 #define INT_SOURCE_CSR_RXTX_COHERENT    FIELD32(0x00000400)
 138 #define INT_SOURCE_CSR_TBTT             FIELD32(0x00000800)
 139 #define INT_SOURCE_CSR_PRE_TBTT         FIELD32(0x00001000)
 140 #define INT_SOURCE_CSR_TX_FIFO_STATUS   FIELD32(0x00002000)
 141 #define INT_SOURCE_CSR_AUTO_WAKEUP      FIELD32(0x00004000)
 142 #define INT_SOURCE_CSR_GPTIMER          FIELD32(0x00008000)
 143 #define INT_SOURCE_CSR_RX_COHERENT      FIELD32(0x00010000)
 144 #define INT_SOURCE_CSR_TX_COHERENT      FIELD32(0x00020000)
 145
 146 /*
 147  * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
 148  */
 149 #define INT_MASK_CSR                    0x0204
 150 #define INT_MASK_CSR_RXDELAYINT         FIELD32(0x00000001)
 151 #define INT_MASK_CSR_TXDELAYINT         FIELD32(0x00000002)
 152 #define INT_MASK_CSR_RX_DONE            FIELD32(0x00000004)
 153 #define INT_MASK_CSR_AC0_DMA_DONE       FIELD32(0x00000008)
 154 #define INT_MASK_CSR_AC1_DMA_DONE       FIELD32(0x00000010)
 155 #define INT_MASK_CSR_AC2_DMA_DONE       FIELD32(0x00000020)
 156 #define INT_MASK_CSR_AC3_DMA_DONE       FIELD32(0x00000040)
 157 #define INT_MASK_CSR_HCCA_DMA_DONE      FIELD32(0x00000080)
 158 #define INT_MASK_CSR_MGMT_DMA_DONE      FIELD32(0x00000100)
 159 #define INT_MASK_CSR_MCU_COMMAND        FIELD32(0x00000200)
 160 #define INT_MASK_CSR_RXTX_COHERENT      FIELD32(0x00000400)
 161 #define INT_MASK_CSR_TBTT               FIELD32(0x00000800)
 162 #define INT_MASK_CSR_PRE_TBTT           FIELD32(0x00001000)
 163 #define INT_MASK_CSR_TX_FIFO_STATUS     FIELD32(0x00002000)
 164 #define INT_MASK_CSR_AUTO_WAKEUP        FIELD32(0x00004000)
 165 #define INT_MASK_CSR_GPTIMER            FIELD32(0x00008000)
 166 #define INT_MASK_CSR_RX_COHERENT        FIELD32(0x00010000)
 167 #define INT_MASK_CSR_TX_COHERENT        FIELD32(0x00020000)
 168
 169 /*
 170  * WPDMA_GLO_CFG
 171  */
 172 #define WPDMA_GLO_CFG                   0x0208
 173 #define WPDMA_GLO_CFG_ENABLE_TX_DMA     FIELD32(0x00000001)
 174 #define WPDMA_GLO_CFG_TX_DMA_BUSY       FIELD32(0x00000002)
 175 #define WPDMA_GLO_CFG_ENABLE_RX_DMA     FIELD32(0x00000004)
 176 #define WPDMA_GLO_CFG_RX_DMA_BUSY       FIELD32(0x00000008)
 177 #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
 178 #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
 179 #define WPDMA_GLO_CFG_BIG_ENDIAN        FIELD32(0x00000080)
 180 #define WPDMA_GLO_CFG_RX_HDR_SCATTER    FIELD32(0x0000ff00)
 181 #define WPDMA_GLO_CFG_HDR_SEG_LEN       FIELD32(0xffff0000)
 182
 183 /*
 184  * WPDMA_RST_IDX
 185  */
 186 #define WPDMA_RST_IDX                   0x020c
 187 #define WPDMA_RST_IDX_DTX_IDX0          FIELD32(0x00000001)
 188 #define WPDMA_RST_IDX_DTX_IDX1          FIELD32(0x00000002)
 189 #define WPDMA_RST_IDX_DTX_IDX2          FIELD32(0x00000004)
 190 #define WPDMA_RST_IDX_DTX_IDX3          FIELD32(0x00000008)
 191 #define WPDMA_RST_IDX_DTX_IDX4          FIELD32(0x00000010)
 192 #define WPDMA_RST_IDX_DTX_IDX5          FIELD32(0x00000020)
 193 #define WPDMA_RST_IDX_DRX_IDX0          FIELD32(0x00010000)
 194
 195 /*
 196  * DELAY_INT_CFG
 197  */
 198 #define DELAY_INT_CFG                   0x0210
 199 #define DELAY_INT_CFG_RXMAX_PTIME       FIELD32(0x000000ff)
 200 #define DELAY_INT_CFG_RXMAX_PINT        FIELD32(0x00007f00)
 201 #define DELAY_INT_CFG_RXDLY_INT_EN      FIELD32(0x00008000)
 202 #define DELAY_INT_CFG_TXMAX_PTIME       FIELD32(0x00ff0000)
 203 #define DELAY_INT_CFG_TXMAX_PINT        FIELD32(0x7f000000)
 204 #define DELAY_INT_CFG_TXDLY_INT_EN      FIELD32(0x80000000)
 205
 206 /*
 207  * WMM_AIFSN_CFG: Aifsn for each EDCA AC
 208  * AIFSN0: AC_BE
 209  * AIFSN1: AC_BK
 210  * AIFSN2: AC_VI
 211  * AIFSN3: AC_VO
 212  */
 213 #define WMM_AIFSN_CFG                   0x0214
 214 #define WMM_AIFSN_CFG_AIFSN0            FIELD32(0x0000000f)
 215 #define WMM_AIFSN_CFG_AIFSN1            FIELD32(0x000000f0)
 216 #define WMM_AIFSN_CFG_AIFSN2            FIELD32(0x00000f00)
 217 #define WMM_AIFSN_CFG_AIFSN3            FIELD32(0x0000f000)
 218
 219 /*
 220  * WMM_CWMIN_CSR: CWmin for each EDCA AC
 221  * CWMIN0: AC_BE
 222  * CWMIN1: AC_BK
 223  * CWMIN2: AC_VI
 224  * CWMIN3: AC_VO
 225  */
 226 #define WMM_CWMIN_CFG                   0x0218
 227 #define WMM_CWMIN_CFG_CWMIN0            FIELD32(0x0000000f)
 228 #define WMM_CWMIN_CFG_CWMIN1            FIELD32(0x000000f0)
 229 #define WMM_CWMIN_CFG_CWMIN2            FIELD32(0x00000f00)
 230 #define WMM_CWMIN_CFG_CWMIN3            FIELD32(0x0000f000)
 231
 232 /*
 233  * WMM_CWMAX_CSR: CWmax for each EDCA AC
 234  * CWMAX0: AC_BE
 235  * CWMAX1: AC_BK
 236  * CWMAX2: AC_VI
 237  * CWMAX3: AC_VO
 238  */
 239 #define WMM_CWMAX_CFG                   0x021c
 240 #define WMM_CWMAX_CFG_CWMAX0            FIELD32(0x0000000f)
 241 #define WMM_CWMAX_CFG_CWMAX1            FIELD32(0x000000f0)
 242 #define WMM_CWMAX_CFG_CWMAX2            FIELD32(0x00000f00)
 243 #define WMM_CWMAX_CFG_CWMAX3            FIELD32(0x0000f000)
 244
 245 /*
 246  * AC_TXOP0: AC_BK/AC_BE TXOP register
 247  * AC0TXOP: AC_BK in unit of 32us
 248  * AC1TXOP: AC_BE in unit of 32us
 249  */
 250 #define WMM_TXOP0_CFG                   0x0220
 251 #define WMM_TXOP0_CFG_AC0TXOP           FIELD32(0x0000ffff)
 252 #define WMM_TXOP0_CFG_AC1TXOP           FIELD32(0xffff0000)
 253
 254 /*
 255  * AC_TXOP1: AC_VO/AC_VI TXOP register
 256  * AC2TXOP: AC_VI in unit of 32us
 257  * AC3TXOP: AC_VO in unit of 32us
 258  */
 259 #define WMM_TXOP1_CFG                   0x0224
 260 #define WMM_TXOP1_CFG_AC2TXOP           FIELD32(0x0000ffff)
 261 #define WMM_TXOP1_CFG_AC3TXOP           FIELD32(0xffff0000)
 262
 263 /*
 264  * GPIO_CTRL_CFG:
 265  */
 266 #define GPIO_CTRL_CFG                   0x0228
 267 #define GPIO_CTRL_CFG_BIT0              FIELD32(0x00000001)
 268 #define GPIO_CTRL_CFG_BIT1              FIELD32(0x00000002)
 269 #define GPIO_CTRL_CFG_BIT2              FIELD32(0x00000004)
 270 #define GPIO_CTRL_CFG_BIT3              FIELD32(0x00000008)
 271 #define GPIO_CTRL_CFG_BIT4              FIELD32(0x00000010)
 272 #define GPIO_CTRL_CFG_BIT5              FIELD32(0x00000020)
 273 #define GPIO_CTRL_CFG_BIT6              FIELD32(0x00000040)
 274 #define GPIO_CTRL_CFG_BIT7              FIELD32(0x00000080)
 275 #define GPIO_CTRL_CFG_BIT8              FIELD32(0x00000100)
 276
 277 /*
 278  * MCU_CMD_CFG
 279  */
 280 #define MCU_CMD_CFG                     0x022c
 281
 282 /*
 283  * AC_BK register offsets
 284  */
 285 #define TX_BASE_PTR0                    0x0230
 286 #define TX_MAX_CNT0                     0x0234
 287 #define TX_CTX_IDX0                     0x0238
 288 #define TX_DTX_IDX0                     0x023c
 289
 290 /*
 291  * AC_BE register offsets
 292  */
 293 #define TX_BASE_PTR1                    0x0240
 294 #define TX_MAX_CNT1                     0x0244
 295 #define TX_CTX_IDX1                     0x0248
 296 #define TX_DTX_IDX1                     0x024c
 297
 298 /*
 299  * AC_VI register offsets
 300  */
 301 #define TX_BASE_PTR2                    0x0250
 302 #define TX_MAX_CNT2                     0x0254
 303 #define TX_CTX_IDX2                     0x0258
 304 #define TX_DTX_IDX2                     0x025c
 305
 306 /*
 307  * AC_VO register offsets
 308  */
 309 #define TX_BASE_PTR3                    0x0260
 310 #define TX_MAX_CNT3                     0x0264
 311 #define TX_CTX_IDX3                     0x0268
 312 #define TX_DTX_IDX3                     0x026c
 313
 314 /*
 315  * HCCA register offsets
 316  */
 317 #define TX_BASE_PTR4                    0x0270
 318 #define TX_MAX_CNT4                     0x0274
 319 #define TX_CTX_IDX4                     0x0278
 320 #define TX_DTX_IDX4                     0x027c
 321
 322 /*
 323  * MGMT register offsets
 324  */
 325 #define TX_BASE_PTR5                    0x0280
 326 #define TX_MAX_CNT5                     0x0284
 327 #define TX_CTX_IDX5                     0x0288
 328 #define TX_DTX_IDX5                     0x028c
 329
 330 /*
 331  * RX register offsets
 332  */
 333 #define RX_BASE_PTR                     0x0290
 334 #define RX_MAX_CNT                      0x0294
 335 #define RX_CRX_IDX                      0x0298
 336 #define RX_DRX_IDX                      0x029c
 337
 338 /*
 339  * USB_DMA_CFG
 340  * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
 341  * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
 342  * PHY_CLEAR: phy watch dog enable.
 343  * TX_CLEAR: Clear USB DMA TX path.
 344  * TXOP_HALT: Halt TXOP count down when TX buffer is full.
 345  * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
 346  * RX_BULK_EN: Enable USB DMA Rx.
 347  * TX_BULK_EN: Enable USB DMA Tx.
 348  * EP_OUT_VALID: OUT endpoint data valid.
 349  * RX_BUSY: USB DMA RX FSM busy.
 350  * TX_BUSY: USB DMA TX FSM busy.
 351  */
 352 #define USB_DMA_CFG                     0x02a0
 353 #define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
 354 #define USB_DMA_CFG_RX_BULK_AGG_LIMIT   FIELD32(0x0000ff00)
 355 #define USB_DMA_CFG_PHY_CLEAR           FIELD32(0x00010000)
 356 #define USB_DMA_CFG_TX_CLEAR            FIELD32(0x00080000)
 357 #define USB_DMA_CFG_TXOP_HALT           FIELD32(0x00100000)
 358 #define USB_DMA_CFG_RX_BULK_AGG_EN      FIELD32(0x00200000)
 359 #define USB_DMA_CFG_RX_BULK_EN          FIELD32(0x00400000)
 360 #define USB_DMA_CFG_TX_BULK_EN          FIELD32(0x00800000)
 361 #define USB_DMA_CFG_EP_OUT_VALID        FIELD32(0x3f000000)
 362 #define USB_DMA_CFG_RX_BUSY             FIELD32(0x40000000)
 363 #define USB_DMA_CFG_TX_BUSY             FIELD32(0x80000000)
 364
 365 /*
 366  * US_CYC_CNT
 367  */
 368 #define US_CYC_CNT                      0x02a4
 369 #define US_CYC_CNT_CLOCK_CYCLE          FIELD32(0x000000ff)
 370
 371 /*
 372  * PBF_SYS_CTRL
 373  * HOST_RAM_WRITE: enable Host program ram write selection
 374  */
 375 #define PBF_SYS_CTRL                    0x0400
 376 #define PBF_SYS_CTRL_READY              FIELD32(0x00000080)
 377 #define PBF_SYS_CTRL_HOST_RAM_WRITE     FIELD32(0x00010000)
 378
 379 /*
 380  * HOST-MCU shared memory
 381  */
 382 #define HOST_CMD_CSR                    0x0404
 383 #define HOST_CMD_CSR_HOST_COMMAND       FIELD32(0x000000ff)
 384
 385 /*
 386  * PBF registers
 387  * Most are for debug. Driver doesn't touch PBF register.
 388  */
 389 #define PBF_CFG                         0x0408
 390 #define PBF_MAX_PCNT                    0x040c
 391 #define PBF_CTRL                        0x0410
 392 #define PBF_INT_STA                     0x0414
 393 #define PBF_INT_ENA                     0x0418
 394
 395 /*
 396  * BCN_OFFSET0:
 397  */
 398 #define BCN_OFFSET0                     0x042c
 399 #define BCN_OFFSET0_BCN0                FIELD32(0x000000ff)
 400 #define BCN_OFFSET0_BCN1                FIELD32(0x0000ff00)
 401 #define BCN_OFFSET0_BCN2                FIELD32(0x00ff0000)
 402 #define BCN_OFFSET0_BCN3                FIELD32(0xff000000)
 403
 404 /*
 405  * BCN_OFFSET1:
 406  */
 407 #define BCN_OFFSET1                     0x0430
 408 #define BCN_OFFSET1_BCN4                FIELD32(0x000000ff)
 409 #define BCN_OFFSET1_BCN5                FIELD32(0x0000ff00)
 410 #define BCN_OFFSET1_BCN6                FIELD32(0x00ff0000)
 411 #define BCN_OFFSET1_BCN7                FIELD32(0xff000000)
 412
 413 /*
 414  * PBF registers
 415  * Most are for debug. Driver doesn't touch PBF register.
 416  */
 417 #define TXRXQ_PCNT                      0x0438
 418 #define PBF_DBG                         0x043c
 419
 420 /*
 421  * RF registers
 422  */
 423 #define RF_CSR_CFG                      0x0500
 424 #define RF_CSR_CFG_DATA                 FIELD32(0x000000ff)
 425 #define RF_CSR_CFG_REGNUM               FIELD32(0x00001f00)
 426 #define RF_CSR_CFG_WRITE                FIELD32(0x00010000)
 427 #define RF_CSR_CFG_BUSY                 FIELD32(0x00020000)
 428
 429 /*
 430  * EFUSE_CSR: RT30x0 EEPROM
 431  */
 432 #define EFUSE_CTRL                      0x0580
 433 #define EFUSE_CTRL_ADDRESS_IN           FIELD32(0x03fe0000)
 434 #define EFUSE_CTRL_MODE                 FIELD32(0x000000c0)
 435 #define EFUSE_CTRL_KICK                 FIELD32(0x40000000)
 436 #define EFUSE_CTRL_PRESENT              FIELD32(0x80000000)
 437
 438 /*
 439  * EFUSE_DATA0
 440  */
 441 #define EFUSE_DATA0                     0x0590
 442
 443 /*
 444  * EFUSE_DATA1
 445  */
 446 #define EFUSE_DATA1                     0x0594
 447
 448 /*
 449  * EFUSE_DATA2
 450  */
 451 #define EFUSE_DATA2                     0x0598
 452
 453 /*
 454  * EFUSE_DATA3
 455  */
 456 #define EFUSE_DATA3                     0x059c
 457
 458 /*
 459  * LDO_CFG0
 460  */
 461 #define LDO_CFG0                        0x05d4
 462 #define LDO_CFG0_DELAY3                 FIELD32(0x000000ff)
 463 #define LDO_CFG0_DELAY2                 FIELD32(0x0000ff00)
 464 #define LDO_CFG0_DELAY1                 FIELD32(0x00ff0000)
 465 #define LDO_CFG0_BGSEL                  FIELD32(0x03000000)
 466 #define LDO_CFG0_LDO_CORE_VLEVEL        FIELD32(0x1c000000)
 467 #define LD0_CFG0_LDO25_LEVEL            FIELD32(0x60000000)
 468 #define LDO_CFG0_LDO25_LARGEA           FIELD32(0x80000000)
 469
 470 /*
 471  * GPIO_SWITCH
 472  */
 473 #define GPIO_SWITCH                     0x05dc
 474 #define GPIO_SWITCH_0                   FIELD32(0x00000001)
 475 #define GPIO_SWITCH_1                   FIELD32(0x00000002)
 476 #define GPIO_SWITCH_2                   FIELD32(0x00000004)
 477 #define GPIO_SWITCH_3                   FIELD32(0x00000008)
 478 #define GPIO_SWITCH_4                   FIELD32(0x00000010)
 479 #define GPIO_SWITCH_5                   FIELD32(0x00000020)
 480 #define GPIO_SWITCH_6                   FIELD32(0x00000040)
 481 #define GPIO_SWITCH_7                   FIELD32(0x00000080)
 482
 483 /*
 484  * MAC Control/Status Registers(CSR).
 485  * Some values are set in TU, whereas 1 TU == 1024 us.
 486  */
 487
 488 /*
 489  * MAC_CSR0: ASIC revision number.
 490  * ASIC_REV: 0
 491  * ASIC_VER: 2860 or 2870
 492  */
 493 #define MAC_CSR0                        0x1000
 494 #define MAC_CSR0_REVISION               FIELD32(0x0000ffff)
 495 #define MAC_CSR0_CHIPSET                FIELD32(0xffff0000)
 496
 497 /*
 498  * MAC_SYS_CTRL:
 499  */
 500 #define MAC_SYS_CTRL                    0x1004
 501 #define MAC_SYS_CTRL_RESET_CSR          FIELD32(0x00000001)
 502 #define MAC_SYS_CTRL_RESET_BBP          FIELD32(0x00000002)
 503 #define MAC_SYS_CTRL_ENABLE_TX          FIELD32(0x00000004)
 504 #define MAC_SYS_CTRL_ENABLE_RX          FIELD32(0x00000008)
 505 #define MAC_SYS_CTRL_CONTINUOUS_TX      FIELD32(0x00000010)
 506 #define MAC_SYS_CTRL_LOOPBACK           FIELD32(0x00000020)
 507 #define MAC_SYS_CTRL_WLAN_HALT          FIELD32(0x00000040)
 508 #define MAC_SYS_CTRL_RX_TIMESTAMP       FIELD32(0x00000080)
 509
 510 /*
 511  * MAC_ADDR_DW0: STA MAC register 0
 512  */
 513 #define MAC_ADDR_DW0                    0x1008
 514 #define MAC_ADDR_DW0_BYTE0              FIELD32(0x000000ff)
 515 #define MAC_ADDR_DW0_BYTE1              FIELD32(0x0000ff00)
 516 #define MAC_ADDR_DW0_BYTE2              FIELD32(0x00ff0000)
 517 #define MAC_ADDR_DW0_BYTE3              FIELD32(0xff000000)
 518
 519 /*
 520  * MAC_ADDR_DW1: STA MAC register 1
 521  * UNICAST_TO_ME_MASK:
 522  * Used to mask off bits from byte 5 of the MAC address
 523  * to determine the UNICAST_TO_ME bit for RX frames.
 524  * The full mask is complemented by BSS_ID_MASK:
 525  *    MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
 526  */
 527 #define MAC_ADDR_DW1                    0x100c
 528 #define MAC_ADDR_DW1_BYTE4              FIELD32(0x000000ff)
 529 #define MAC_ADDR_DW1_BYTE5              FIELD32(0x0000ff00)
 530 #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
 531
 532 /*
 533  * MAC_BSSID_DW0: BSSID register 0
 534  */
 535 #define MAC_BSSID_DW0                   0x1010
 536 #define MAC_BSSID_DW0_BYTE0             FIELD32(0x000000ff)
 537 #define MAC_BSSID_DW0_BYTE1             FIELD32(0x0000ff00)
 538 #define MAC_BSSID_DW0_BYTE2             FIELD32(0x00ff0000)
 539 #define MAC_BSSID_DW0_BYTE3             FIELD32(0xff000000)
 540
 541 /*
 542  * MAC_BSSID_DW1: BSSID register 1
 543  * BSS_ID_MASK:
 544  *     0: 1-BSSID mode (BSS index = 0)
 545  *     1: 2-BSSID mode (BSS index: Byte5, bit 0)
 546  *     2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
 547  *     3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
 548  * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
 549  * BSSID. This will make sure that those bits will be ignored
 550  * when determining the MY_BSS of RX frames.
 551  */
 552 #define MAC_BSSID_DW1                   0x1014
 553 #define MAC_BSSID_DW1_BYTE4             FIELD32(0x000000ff)
 554 #define MAC_BSSID_DW1_BYTE5             FIELD32(0x0000ff00)
 555 #define MAC_BSSID_DW1_BSS_ID_MASK       FIELD32(0x00030000)
 556 #define MAC_BSSID_DW1_BSS_BCN_NUM       FIELD32(0x001c0000)
 557
 558 /*
 559  * MAX_LEN_CFG: Maximum frame length register.
 560  * MAX_MPDU: rt2860b max 16k bytes
 561  * MAX_PSDU: Maximum PSDU length
 562  *      (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
 563  */
 564 #define MAX_LEN_CFG                     0x1018
 565 #define MAX_LEN_CFG_MAX_MPDU            FIELD32(0x00000fff)
 566 #define MAX_LEN_CFG_MAX_PSDU            FIELD32(0x00003000)
 567 #define MAX_LEN_CFG_MIN_PSDU            FIELD32(0x0000c000)
 568 #define MAX_LEN_CFG_MIN_MPDU            FIELD32(0x000f0000)
 569
 570 /*
 571  * BBP_CSR_CFG: BBP serial control register
 572  * VALUE: Register value to program into BBP
 573  * REG_NUM: Selected BBP register
 574  * READ_CONTROL: 0 write BBP, 1 read BBP
 575  * BUSY: ASIC is busy executing BBP commands
 576  * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
 577  * BBP_RW_MODE: 0 serial, 1 paralell
 578  */
 579 #define BBP_CSR_CFG                     0x101c
 580 #define BBP_CSR_CFG_VALUE               FIELD32(0x000000ff)
 581 #define BBP_CSR_CFG_REGNUM              FIELD32(0x0000ff00)
 582 #define BBP_CSR_CFG_READ_CONTROL        FIELD32(0x00010000)
 583 #define BBP_CSR_CFG_BUSY                FIELD32(0x00020000)
 584 #define BBP_CSR_CFG_BBP_PAR_DUR         FIELD32(0x00040000)
 585 #define BBP_CSR_CFG_BBP_RW_MODE         FIELD32(0x00080000)
 586
 587 /*
 588  * RF_CSR_CFG0: RF control register
 589  * REGID_AND_VALUE: Register value to program into RF
 590  * BITWIDTH: Selected RF register
 591  * STANDBYMODE: 0 high when standby, 1 low when standby
 592  * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
 593  * BUSY: ASIC is busy executing RF commands
 594  */
 595 #define RF_CSR_CFG0                     0x1020
 596 #define RF_CSR_CFG0_REGID_AND_VALUE     FIELD32(0x00ffffff)
 597 #define RF_CSR_CFG0_BITWIDTH            FIELD32(0x1f000000)
 598 #define RF_CSR_CFG0_REG_VALUE_BW        FIELD32(0x1fffffff)
 599 #define RF_CSR_CFG0_STANDBYMODE         FIELD32(0x20000000)
 600 #define RF_CSR_CFG0_SEL                 FIELD32(0x40000000)
 601 #define RF_CSR_CFG0_BUSY                FIELD32(0x80000000)
 602
 603 /*
 604  * RF_CSR_CFG1: RF control register
 605  * REGID_AND_VALUE: Register value to program into RF
 606  * RFGAP: Gap between BB_CONTROL_RF and RF_LE
 607  *        0: 3 system clock cycle (37.5usec)
 608  *        1: 5 system clock cycle (62.5usec)
 609  */
 610 #define RF_CSR_CFG1                     0x1024
 611 #define RF_CSR_CFG1_REGID_AND_VALUE     FIELD32(0x00ffffff)
 612 #define RF_CSR_CFG1_RFGAP               FIELD32(0x1f000000)
 613
 614 /*
 615  * RF_CSR_CFG2: RF control register
 616  * VALUE: Register value to program into RF
 617  */
 618 #define RF_CSR_CFG2                     0x1028
 619 #define RF_CSR_CFG2_VALUE               FIELD32(0x00ffffff)
 620
 621 /*
 622  * LED_CFG: LED control
 623  * color LED's:
 624  *   0: off
 625  *   1: blinking upon TX2
 626  *   2: periodic slow blinking
 627  *   3: always on
 628  * LED polarity:
 629  *   0: active low
 630  *   1: active high
 631  */
 632 #define LED_CFG                         0x102c
 633 #define LED_CFG_ON_PERIOD               FIELD32(0x000000ff)
 634 #define LED_CFG_OFF_PERIOD              FIELD32(0x0000ff00)
 635 #define LED_CFG_SLOW_BLINK_PERIOD       FIELD32(0x003f0000)
 636 #define LED_CFG_R_LED_MODE              FIELD32(0x03000000)
 637 #define LED_CFG_G_LED_MODE              FIELD32(0x0c000000)
 638 #define LED_CFG_Y_LED_MODE              FIELD32(0x30000000)
 639 #define LED_CFG_LED_POLAR               FIELD32(0x40000000)
 640
 641 /*
 642  * XIFS_TIME_CFG: MAC timing
 643  * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
 644  * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
 645  * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
 646  *      when MAC doesn't reference BBP signal BBRXEND
 647  * EIFS: unit 1us
 648  * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
 649  *
 650  */
 651 #define XIFS_TIME_CFG                   0x1100
 652 #define XIFS_TIME_CFG_CCKM_SIFS_TIME    FIELD32(0x000000ff)
 653 #define XIFS_TIME_CFG_OFDM_SIFS_TIME    FIELD32(0x0000ff00)
 654 #define XIFS_TIME_CFG_OFDM_XIFS_TIME    FIELD32(0x000f0000)
 655 #define XIFS_TIME_CFG_EIFS              FIELD32(0x1ff00000)
 656 #define XIFS_TIME_CFG_BB_RXEND_ENABLE   FIELD32(0x20000000)
 657
 658 /*
 659  * BKOFF_SLOT_CFG:
 660  */
 661 #define BKOFF_SLOT_CFG                  0x1104
 662 #define BKOFF_SLOT_CFG_SLOT_TIME        FIELD32(0x000000ff)
 663 #define BKOFF_SLOT_CFG_CC_DELAY_TIME    FIELD32(0x0000ff00)
 664
 665 /*
 666  * NAV_TIME_CFG:
 667  */
 668 #define NAV_TIME_CFG                    0x1108
 669 #define NAV_TIME_CFG_SIFS               FIELD32(0x000000ff)
 670 #define NAV_TIME_CFG_SLOT_TIME          FIELD32(0x0000ff00)
 671 #define NAV_TIME_CFG_EIFS               FIELD32(0x01ff0000)
 672 #define NAV_TIME_ZERO_SIFS              FIELD32(0x02000000)
 673
 674 /*
 675  * CH_TIME_CFG: count as channel busy
 676  */
 677 #define CH_TIME_CFG                     0x110c
 678
 679 /*
 680  * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
 681  */
 682 #define PBF_LIFE_TIMER                  0x1110
 683
 684 /*
 685  * BCN_TIME_CFG:
 686  * BEACON_INTERVAL: in unit of 1/16 TU
 687  * TSF_TICKING: Enable TSF auto counting
 688  * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
 689  * BEACON_GEN: Enable beacon generator
 690  */
 691 #define BCN_TIME_CFG                    0x1114
 692 #define BCN_TIME_CFG_BEACON_INTERVAL    FIELD32(0x0000ffff)
 693 #define BCN_TIME_CFG_TSF_TICKING        FIELD32(0x00010000)
 694 #define BCN_TIME_CFG_TSF_SYNC           FIELD32(0x00060000)
 695 #define BCN_TIME_CFG_TBTT_ENABLE        FIELD32(0x00080000)
 696 #define BCN_TIME_CFG_BEACON_GEN         FIELD32(0x00100000)
 697 #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
 698
 699 /*
 700  * TBTT_SYNC_CFG:
 701  */
 702 #define TBTT_SYNC_CFG                   0x1118
 703
 704 /*
 705  * TSF_TIMER_DW0: Local lsb TSF timer, read-only
 706  */
 707 #define TSF_TIMER_DW0                   0x111c
 708 #define TSF_TIMER_DW0_LOW_WORD          FIELD32(0xffffffff)
 709
 710 /*
 711  * TSF_TIMER_DW1: Local msb TSF timer, read-only
 712  */
 713 #define TSF_TIMER_DW1                   0x1120
 714 #define TSF_TIMER_DW1_HIGH_WORD         FIELD32(0xffffffff)
 715
 716 /*
 717  * TBTT_TIMER: TImer remains till next TBTT, read-only
 718  */
 719 #define TBTT_TIMER                      0x1124
 720
 721 /*
 722  * INT_TIMER_CFG:
 723  */
 724 #define INT_TIMER_CFG                   0x1128
 725
 726 /*
 727  * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
 728  */
 729 #define INT_TIMER_EN                    0x112c
 730
 731 /*
 732  * CH_IDLE_STA: channel idle time
 733  */
 734 #define CH_IDLE_STA                     0x1130
 735
 736 /*
 737  * CH_BUSY_STA: channel busy time
 738  */
 739 #define CH_BUSY_STA                     0x1134
 740
 741 /*
 742  * MAC_STATUS_CFG:
 743  * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
 744  *      if 1 or higher one of the 2 registers is busy.
 745  */
 746 #define MAC_STATUS_CFG                  0x1200
 747 #define MAC_STATUS_CFG_BBP_RF_BUSY      FIELD32(0x00000003)
 748
 749 /*
 750  * PWR_PIN_CFG:
 751  */
 752 #define PWR_PIN_CFG                     0x1204
 753
 754 /*
 755  * AUTOWAKEUP_CFG: Manual power control / status register
 756  * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
 757  * AUTOWAKE: 0:sleep, 1:awake
 758  */
 759 #define AUTOWAKEUP_CFG                  0x1208
 760 #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME   FIELD32(0x000000ff)
 761 #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
 762 #define AUTOWAKEUP_CFG_AUTOWAKE         FIELD32(0x00008000)
 763
 764 /*
 765  * EDCA_AC0_CFG:
 766  */
 767 #define EDCA_AC0_CFG                    0x1300
 768 #define EDCA_AC0_CFG_TX_OP              FIELD32(0x000000ff)
 769 #define EDCA_AC0_CFG_AIFSN              FIELD32(0x00000f00)
 770 #define EDCA_AC0_CFG_CWMIN              FIELD32(0x0000f000)
 771 #define EDCA_AC0_CFG_CWMAX              FIELD32(0x000f0000)
 772
 773 /*
 774  * EDCA_AC1_CFG:
 775  */
 776 #define EDCA_AC1_CFG                    0x1304
 777 #define EDCA_AC1_CFG_TX_OP              FIELD32(0x000000ff)
 778 #define EDCA_AC1_CFG_AIFSN              FIELD32(0x00000f00)
 779 #define EDCA_AC1_CFG_CWMIN              FIELD32(0x0000f000)
 780 #define EDCA_AC1_CFG_CWMAX              FIELD32(0x000f0000)
 781
 782 /*
 783  * EDCA_AC2_CFG:
 784  */
 785 #define EDCA_AC2_CFG                    0x1308
 786 #define EDCA_AC2_CFG_TX_OP              FIELD32(0x000000ff)
 787 #define EDCA_AC2_CFG_AIFSN              FIELD32(0x00000f00)
 788 #define EDCA_AC2_CFG_CWMIN              FIELD32(0x0000f000)
 789 #define EDCA_AC2_CFG_CWMAX              FIELD32(0x000f0000)
 790
 791 /*
 792  * EDCA_AC3_CFG:
 793  */
 794 #define EDCA_AC3_CFG                    0x130c
 795 #define EDCA_AC3_CFG_TX_OP              FIELD32(0x000000ff)
 796 #define EDCA_AC3_CFG_AIFSN              FIELD32(0x00000f00)
 797 #define EDCA_AC3_CFG_CWMIN              FIELD32(0x0000f000)
 798 #define EDCA_AC3_CFG_CWMAX              FIELD32(0x000f0000)
 799
 800 /*
 801  * EDCA_TID_AC_MAP:
 802  */
 803 #define EDCA_TID_AC_MAP                 0x1310
 804
 805 /*
 806  * TX_PWR_CFG_0:
 807  */
 808 #define TX_PWR_CFG_0                    0x1314
 809 #define TX_PWR_CFG_0_1MBS               FIELD32(0x0000000f)
 810 #define TX_PWR_CFG_0_2MBS               FIELD32(0x000000f0)
 811 #define TX_PWR_CFG_0_55MBS              FIELD32(0x00000f00)
 812 #define TX_PWR_CFG_0_11MBS              FIELD32(0x0000f000)
 813 #define TX_PWR_CFG_0_6MBS               FIELD32(0x000f0000)
 814 #define TX_PWR_CFG_0_9MBS               FIELD32(0x00f00000)
 815 #define TX_PWR_CFG_0_12MBS              FIELD32(0x0f000000)
 816 #define TX_PWR_CFG_0_18MBS              FIELD32(0xf0000000)
 817
 818 /*
 819  * TX_PWR_CFG_1:
 820  */
 821 #define TX_PWR_CFG_1                    0x1318
 822 #define TX_PWR_CFG_1_24MBS              FIELD32(0x0000000f)
 823 #define TX_PWR_CFG_1_36MBS              FIELD32(0x000000f0)
 824 #define TX_PWR_CFG_1_48MBS              FIELD32(0x00000f00)
 825 #define TX_PWR_CFG_1_54MBS              FIELD32(0x0000f000)
 826 #define TX_PWR_CFG_1_MCS0               FIELD32(0x000f0000)
 827 #define TX_PWR_CFG_1_MCS1               FIELD32(0x00f00000)
 828 #define TX_PWR_CFG_1_MCS2               FIELD32(0x0f000000)
 829 #define TX_PWR_CFG_1_MCS3               FIELD32(0xf0000000)
 830
 831 /*
 832  * TX_PWR_CFG_2:
 833  */
 834 #define TX_PWR_CFG_2                    0x131c
 835 #define TX_PWR_CFG_2_MCS4               FIELD32(0x0000000f)
 836 #define TX_PWR_CFG_2_MCS5               FIELD32(0x000000f0)
 837 #define TX_PWR_CFG_2_MCS6               FIELD32(0x00000f00)
 838 #define TX_PWR_CFG_2_MCS7               FIELD32(0x0000f000)
 839 #define TX_PWR_CFG_2_MCS8               FIELD32(0x000f0000)
 840 #define TX_PWR_CFG_2_MCS9               FIELD32(0x00f00000)
 841 #define TX_PWR_CFG_2_MCS10              FIELD32(0x0f000000)
 842 #define TX_PWR_CFG_2_MCS11              FIELD32(0xf0000000)
 843
 844 /*
 845  * TX_PWR_CFG_3:
 846  */
 847 #define TX_PWR_CFG_3                    0x1320
 848 #define TX_PWR_CFG_3_MCS12              FIELD32(0x0000000f)
 849 #define TX_PWR_CFG_3_MCS13              FIELD32(0x000000f0)
 850 #define TX_PWR_CFG_3_MCS14              FIELD32(0x00000f00)
 851 #define TX_PWR_CFG_3_MCS15              FIELD32(0x0000f000)
 852 #define TX_PWR_CFG_3_UKNOWN1            FIELD32(0x000f0000)
 853 #define TX_PWR_CFG_3_UKNOWN2            FIELD32(0x00f00000)
 854 #define TX_PWR_CFG_3_UKNOWN3            FIELD32(0x0f000000)
 855 #define TX_PWR_CFG_3_UKNOWN4            FIELD32(0xf0000000)
 856
 857 /*
 858  * TX_PWR_CFG_4:
 859  */
 860 #define TX_PWR_CFG_4                    0x1324
 861 #define TX_PWR_CFG_4_UKNOWN5            FIELD32(0x0000000f)
 862 #define TX_PWR_CFG_4_UKNOWN6            FIELD32(0x000000f0)
 863 #define TX_PWR_CFG_4_UKNOWN7            FIELD32(0x00000f00)
 864 #define TX_PWR_CFG_4_UKNOWN8            FIELD32(0x0000f000)
 865
 866 /*
 867  * TX_PIN_CFG:
 868  */
 869 #define TX_PIN_CFG                      0x1328
 870 #define TX_PIN_CFG_PA_PE_A0_EN          FIELD32(0x00000001)
 871 #define TX_PIN_CFG_PA_PE_G0_EN          FIELD32(0x00000002)
 872 #define TX_PIN_CFG_PA_PE_A1_EN          FIELD32(0x00000004)
 873 #define TX_PIN_CFG_PA_PE_G1_EN          FIELD32(0x00000008)
 874 #define TX_PIN_CFG_PA_PE_A0_POL         FIELD32(0x00000010)
 875 #define TX_PIN_CFG_PA_PE_G0_POL         FIELD32(0x00000020)
 876 #define TX_PIN_CFG_PA_PE_A1_POL         FIELD32(0x00000040)
 877 #define TX_PIN_CFG_PA_PE_G1_POL         FIELD32(0x00000080)
 878 #define TX_PIN_CFG_LNA_PE_A0_EN         FIELD32(0x00000100)
 879 #define TX_PIN_CFG_LNA_PE_G0_EN         FIELD32(0x00000200)
 880 #define TX_PIN_CFG_LNA_PE_A1_EN         FIELD32(0x00000400)
 881 #define TX_PIN_CFG_LNA_PE_G1_EN         FIELD32(0x00000800)
 882 #define TX_PIN_CFG_LNA_PE_A0_POL        FIELD32(0x00001000)
 883 #define TX_PIN_CFG_LNA_PE_G0_POL        FIELD32(0x00002000)
 884 #define TX_PIN_CFG_LNA_PE_A1_POL        FIELD32(0x00004000)
 885 #define TX_PIN_CFG_LNA_PE_G1_POL        FIELD32(0x00008000)
 886 #define TX_PIN_CFG_RFTR_EN              FIELD32(0x00010000)
 887 #define TX_PIN_CFG_RFTR_POL             FIELD32(0x00020000)
 888 #define TX_PIN_CFG_TRSW_EN              FIELD32(0x00040000)
 889 #define TX_PIN_CFG_TRSW_POL             FIELD32(0x00080000)
 890
 891 /*
 892  * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
 893  */
 894 #define TX_BAND_CFG                     0x132c
 895 #define TX_BAND_CFG_HT40_MINUS          FIELD32(0x00000001)
 896 #define TX_BAND_CFG_A                   FIELD32(0x00000002)
 897 #define TX_BAND_CFG_BG                  FIELD32(0x00000004)
 898
 899 /*
 900  * TX_SW_CFG0:
 901  */
 902 #define TX_SW_CFG0                      0x1330
 903
 904 /*
 905  * TX_SW_CFG1:
 906  */
 907 #define TX_SW_CFG1                      0x1334
 908
 909 /*
 910  * TX_SW_CFG2:
 911  */
 912 #define TX_SW_CFG2                      0x1338
 913
 914 /*
 915  * TXOP_THRES_CFG:
 916  */
 917 #define TXOP_THRES_CFG                  0x133c
 918
 919 /*
 920  * TXOP_CTRL_CFG:
 921  */
 922 #define TXOP_CTRL_CFG                   0x1340
 923
 924 /*
 925  * TX_RTS_CFG:
 926  * RTS_THRES: unit:byte
 927  * RTS_FBK_EN: enable rts rate fallback
 928  */
 929 #define TX_RTS_CFG                      0x1344
 930 #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
 931 #define TX_RTS_CFG_RTS_THRES            FIELD32(0x00ffff00)
 932 #define TX_RTS_CFG_RTS_FBK_EN           FIELD32(0x01000000)
 933
 934 /*
 935  * TX_TIMEOUT_CFG:
 936  * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
 937  * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
 938  * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
 939  *                it is recommended that:
 940  *                (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
 941  */
 942 #define TX_TIMEOUT_CFG                  0x1348
 943 #define TX_TIMEOUT_CFG_MPDU_LIFETIME    FIELD32(0x000000f0)
 944 #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT   FIELD32(0x0000ff00)
 945 #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT    FIELD32(0x00ff0000)
 946
 947 /*
 948  * TX_RTY_CFG:
 949  * SHORT_RTY_LIMIT: short retry limit
 950  * LONG_RTY_LIMIT: long retry limit
 951  * LONG_RTY_THRE: Long retry threshoold
 952  * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
 953  *                   0:expired by retry limit, 1: expired by mpdu life timer
 954  * AGG_RTY_MODE: Aggregate MPDU retry mode
 955  *               0:expired by retry limit, 1: expired by mpdu life timer
 956  * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
 957  */
 958 #define TX_RTY_CFG                      0x134c
 959 #define TX_RTY_CFG_SHORT_RTY_LIMIT      FIELD32(0x000000ff)
 960 #define TX_RTY_CFG_LONG_RTY_LIMIT       FIELD32(0x0000ff00)
 961 #define TX_RTY_CFG_LONG_RTY_THRE        FIELD32(0x0fff0000)
 962 #define TX_RTY_CFG_NON_AGG_RTY_MODE     FIELD32(0x10000000)
 963 #define TX_RTY_CFG_AGG_RTY_MODE         FIELD32(0x20000000)
 964 #define TX_RTY_CFG_TX_AUTO_FB_ENABLE    FIELD32(0x40000000)
 965
 966 /*
 967  * TX_LINK_CFG:
 968  * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
 969  * MFB_ENABLE: TX apply remote MFB 1:enable
 970  * REMOTE_UMFS_ENABLE: remote unsolicit  MFB enable
 971  *                     0: not apply remote remote unsolicit (MFS=7)
 972  * TX_MRQ_EN: MCS request TX enable
 973  * TX_RDG_EN: RDG TX enable
 974  * TX_CF_ACK_EN: Piggyback CF-ACK enable
 975  * REMOTE_MFB: remote MCS feedback
 976  * REMOTE_MFS: remote MCS feedback sequence number
 977  */
 978 #define TX_LINK_CFG                     0x1350
 979 #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
 980 #define TX_LINK_CFG_MFB_ENABLE          FIELD32(0x00000100)
 981 #define TX_LINK_CFG_REMOTE_UMFS_ENABLE  FIELD32(0x00000200)
 982 #define TX_LINK_CFG_TX_MRQ_EN           FIELD32(0x00000400)
 983 #define TX_LINK_CFG_TX_RDG_EN           FIELD32(0x00000800)
 984 #define TX_LINK_CFG_TX_CF_ACK_EN        FIELD32(0x00001000)
 985 #define TX_LINK_CFG_REMOTE_MFB          FIELD32(0x00ff0000)
 986 #define TX_LINK_CFG_REMOTE_MFS          FIELD32(0xff000000)
 987
 988 /*
 989  * HT_FBK_CFG0:
 990  */
 991 #define HT_FBK_CFG0                     0x1354
 992 #define HT_FBK_CFG0_HTMCS0FBK           FIELD32(0x0000000f)
 993 #define HT_FBK_CFG0_HTMCS1FBK           FIELD32(0x000000f0)
 994 #define HT_FBK_CFG0_HTMCS2FBK           FIELD32(0x00000f00)
 995 #define HT_FBK_CFG0_HTMCS3FBK           FIELD32(0x0000f000)
 996 #define HT_FBK_CFG0_HTMCS4FBK           FIELD32(0x000f0000)
 997 #define HT_FBK_CFG0_HTMCS5FBK           FIELD32(0x00f00000)
 998 #define HT_FBK_CFG0_HTMCS6FBK           FIELD32(0x0f000000)
 999 #define HT_FBK_CFG0_HTMCS7FBK           FIELD32(0xf0000000)
1000
1001 /*
1002  * HT_FBK_CFG1:
1003  */
1004 #define HT_FBK_CFG1                     0x1358
1005 #define HT_FBK_CFG1_HTMCS8FBK           FIELD32(0x0000000f)
1006 #define HT_FBK_CFG1_HTMCS9FBK           FIELD32(0x000000f0)
1007 #define HT_FBK_CFG1_HTMCS10FBK          FIELD32(0x00000f00)
1008 #define HT_FBK_CFG1_HTMCS11FBK          FIELD32(0x0000f000)
1009 #define HT_FBK_CFG1_HTMCS12FBK          FIELD32(0x000f0000)
1010 #define HT_FBK_CFG1_HTMCS13FBK          FIELD32(0x00f00000)
1011 #define HT_FBK_CFG1_HTMCS14FBK          FIELD32(0x0f000000)
1012 #define HT_FBK_CFG1_HTMCS15FBK          FIELD32(0xf0000000)
1013
1014 /*
1015  * LG_FBK_CFG0:
1016  */
1017 #define LG_FBK_CFG0                     0x135c
1018 #define LG_FBK_CFG0_OFDMMCS0FBK         FIELD32(0x0000000f)
1019 #define LG_FBK_CFG0_OFDMMCS1FBK         FIELD32(0x000000f0)
1020 #define LG_FBK_CFG0_OFDMMCS2FBK         FIELD32(0x00000f00)
1021 #define LG_FBK_CFG0_OFDMMCS3FBK         FIELD32(0x0000f000)
1022 #define LG_FBK_CFG0_OFDMMCS4FBK         FIELD32(0x000f0000)
1023 #define LG_FBK_CFG0_OFDMMCS5FBK         FIELD32(0x00f00000)
1024 #define LG_FBK_CFG0_OFDMMCS6FBK         FIELD32(0x0f000000)
1025 #define LG_FBK_CFG0_OFDMMCS7FBK         FIELD32(0xf0000000)
1026
1027 /*
1028  * LG_FBK_CFG1:
1029  */
1030 #define LG_FBK_CFG1                     0x1360
1031 #define LG_FBK_CFG0_CCKMCS0FBK          FIELD32(0x0000000f)
1032 #define LG_FBK_CFG0_CCKMCS1FBK          FIELD32(0x000000f0)
1033 #define LG_FBK_CFG0_CCKMCS2FBK          FIELD32(0x00000f00)
1034 #define LG_FBK_CFG0_CCKMCS3FBK          FIELD32(0x0000f000)
1035
1036 /*
1037  * CCK_PROT_CFG: CCK Protection
1038  * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
1039  * PROTECT_CTRL: Protection control frame type for CCK TX
1040  *               0:none, 1:RTS/CTS, 2:CTS-to-self
1041  * PROTECT_NAV: TXOP protection type for CCK TX
1042  *              0:none, 1:ShortNAVprotect, 2:LongNAVProtect
1043  * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
1044  * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
1045  * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
1046  * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
1047  * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
1048  * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
1049  * RTS_TH_EN: RTS threshold enable on CCK TX
1050  */
1051 #define CCK_PROT_CFG                    0x1364
1052 #define CCK_PROT_CFG_PROTECT_RATE       FIELD32(0x0000ffff)
1053 #define CCK_PROT_CFG_PROTECT_CTRL       FIELD32(0x00030000)
1054 #define CCK_PROT_CFG_PROTECT_NAV        FIELD32(0x000c0000)
1055 #define CCK_PROT_CFG_TX_OP_ALLOW_CCK    FIELD32(0x00100000)
1056 #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM   FIELD32(0x00200000)
1057 #define CCK_PROT_CFG_TX_OP_ALLOW_MM20   FIELD32(0x00400000)
1058 #define CCK_PROT_CFG_TX_OP_ALLOW_MM40   FIELD32(0x00800000)
1059 #define CCK_PROT_CFG_TX_OP_ALLOW_GF20   FIELD32(0x01000000)
1060 #define CCK_PROT_CFG_TX_OP_ALLOW_GF40   FIELD32(0x02000000)
1061 #define CCK_PROT_CFG_RTS_TH_EN          FIELD32(0x04000000)
1062
1063 /*
1064  * OFDM_PROT_CFG: OFDM Protection
1065  */
1066 #define OFDM_PROT_CFG                   0x1368
1067 #define OFDM_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
1068 #define OFDM_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
1069 #define OFDM_PROT_CFG_PROTECT_NAV       FIELD32(0x000c0000)
1070 #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
1071 #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
1072 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
1073 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
1074 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
1075 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
1076 #define OFDM_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
1077
1078 /*
1079  * MM20_PROT_CFG: MM20 Protection
1080  */
1081 #define MM20_PROT_CFG                   0x136c
1082 #define MM20_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
1083 #define MM20_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
1084 #define MM20_PROT_CFG_PROTECT_NAV       FIELD32(0x000c0000)
1085 #define MM20_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
1086 #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
1087 #define MM20_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
1088 #define MM20_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
1089 #define MM20_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
1090 #define MM20_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
1091 #define MM20_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
1092
1093 /*
1094  * MM40_PROT_CFG: MM40 Protection
1095  */
1096 #define MM40_PROT_CFG                   0x1370
1097 #define MM40_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
1098 #define MM40_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
1099 #define MM40_PROT_CFG_PROTECT_NAV       FIELD32(0x000c0000)
1100 #define MM40_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
1101 #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
1102 #define MM40_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
1103 #define MM40_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
1104 #define MM40_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
1105 #define MM40_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
1106 #define MM40_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
1107
1108 /*
1109  * GF20_PROT_CFG: GF20 Protection
1110  */
1111 #define GF20_PROT_CFG                   0x1374
1112 #define GF20_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
1113 #define GF20_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
1114 #define GF20_PROT_CFG_PROTECT_NAV       FIELD32(0x000c0000)
1115 #define GF20_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
1116 #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
1117 #define GF20_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
1118 #define GF20_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
1119 #define GF20_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
1120 #define GF20_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
1121 #define GF20_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
1122
1123 /*
1124  * GF40_PROT_CFG: GF40 Protection
1125  */
1126 #define GF40_PROT_CFG                   0x1378
1127 #define GF40_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
1128 #define GF40_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
1129 #define GF40_PROT_CFG_PROTECT_NAV       FIELD32(0x000c0000)
1130 #define GF40_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
1131 #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
1132 #define GF40_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
1133 #define GF40_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
1134 #define GF40_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
1135 #define GF40_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
1136 #define GF40_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
1137
1138 /*
1139  * EXP_CTS_TIME:
1140  */
1141 #define EXP_CTS_TIME                    0x137c
1142
1143 /*
1144  * EXP_ACK_TIME:
1145  */
1146 #define EXP_ACK_TIME                    0x1380
1147
1148 /*
1149  * RX_FILTER_CFG: RX configuration register.
1150  */
1151 #define RX_FILTER_CFG                   0x1400
1152 #define RX_FILTER_CFG_DROP_CRC_ERROR    FIELD32(0x00000001)
1153 #define RX_FILTER_CFG_DROP_PHY_ERROR    FIELD32(0x00000002)
1154 #define RX_FILTER_CFG_DROP_NOT_TO_ME    FIELD32(0x00000004)
1155 #define RX_FILTER_CFG_DROP_NOT_MY_BSSD  FIELD32(0x00000008)
1156 #define RX_FILTER_CFG_DROP_VER_ERROR    FIELD32(0x00000010)
1157 #define RX_FILTER_CFG_DROP_MULTICAST    FIELD32(0x00000020)
1158 #define RX_FILTER_CFG_DROP_BROADCAST    FIELD32(0x00000040)
1159 #define RX_FILTER_CFG_DROP_DUPLICATE    FIELD32(0x00000080)
1160 #define RX_FILTER_CFG_DROP_CF_END_ACK   FIELD32(0x00000100)
1161 #define RX_FILTER_CFG_DROP_CF_END       FIELD32(0x00000200)
1162 #define RX_FILTER_CFG_DROP_ACK          FIELD32(0x00000400)
1163 #define RX_FILTER_CFG_DROP_CTS          FIELD32(0x00000800)
1164 #define RX_FILTER_CFG_DROP_RTS          FIELD32(0x00001000)
1165 #define RX_FILTER_CFG_DROP_PSPOLL       FIELD32(0x00002000)
1166 #define RX_FILTER_CFG_DROP_BA           FIELD32(0x00004000)
1167 #define RX_FILTER_CFG_DROP_BAR          FIELD32(0x00008000)
1168 #define RX_FILTER_CFG_DROP_CNTL         FIELD32(0x00010000)
1169
1170 /*
1171  * AUTO_RSP_CFG:
1172  * AUTORESPONDER: 0: disable, 1: enable
1173  * BAC_ACK_POLICY: 0:long, 1:short preamble
1174  * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1175  * CTS_40_MREF: Response CTS 40MHz duplicate mode
1176  * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1177  * DUAL_CTS_EN: Power bit value in control frame
1178  * ACK_CTS_PSM_BIT:Power bit value in control frame
1179  */
1180 #define AUTO_RSP_CFG                    0x1404
1181 #define AUTO_RSP_CFG_AUTORESPONDER      FIELD32(0x00000001)
1182 #define AUTO_RSP_CFG_BAC_ACK_POLICY     FIELD32(0x00000002)
1183 #define AUTO_RSP_CFG_CTS_40_MMODE       FIELD32(0x00000004)
1184 #define AUTO_RSP_CFG_CTS_40_MREF        FIELD32(0x00000008)
1185 #define AUTO_RSP_CFG_AR_PREAMBLE        FIELD32(0x00000010)
1186 #define AUTO_RSP_CFG_DUAL_CTS_EN        FIELD32(0x00000040)
1187 #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT    FIELD32(0x00000080)
1188
1189 /*
1190  * LEGACY_BASIC_RATE:
1191  */
1192 #define LEGACY_BASIC_RATE               0x1408
1193
1194 /*
1195  * HT_BASIC_RATE:
1196  */
1197 #define HT_BASIC_RATE                   0x140c
1198
1199 /*
1200  * HT_CTRL_CFG:
1201  */
1202 #define HT_CTRL_CFG                     0x1410
1203
1204 /*
1205  * SIFS_COST_CFG:
1206  */
1207 #define SIFS_COST_CFG                   0x1414
1208
1209 /*
1210  * RX_PARSER_CFG:
1211  * Set NAV for all received frames
1212  */
1213 #define RX_PARSER_CFG                   0x1418
1214
1215 /*
1216  * TX_SEC_CNT0:
1217  */
1218 #define TX_SEC_CNT0                     0x1500
1219
1220 /*
1221  * RX_SEC_CNT0:
1222  */
1223 #define RX_SEC_CNT0                     0x1504
1224
1225 /*
1226  * CCMP_FC_MUTE:
1227  */
1228 #define CCMP_FC_MUTE                    0x1508
1229
1230 /*
1231  * TXOP_HLDR_ADDR0:
1232  */
1233 #define TXOP_HLDR_ADDR0                 0x1600
1234
1235 /*
1236  * TXOP_HLDR_ADDR1:
1237  */
1238 #define TXOP_HLDR_ADDR1                 0x1604
1239
1240 /*
1241  * TXOP_HLDR_ET:
1242  */
1243 #define TXOP_HLDR_ET                    0x1608
1244
1245 /*
1246  * QOS_CFPOLL_RA_DW0:
1247  */
1248 #define QOS_CFPOLL_RA_DW0               0x160c
1249
1250 /*
1251  * QOS_CFPOLL_RA_DW1:
1252  */
1253 #define QOS_CFPOLL_RA_DW1               0x1610
1254
1255 /*
1256  * QOS_CFPOLL_QC:
1257  */
1258 #define QOS_CFPOLL_QC                   0x1614
1259
1260 /*
1261  * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1262  */
1263 #define RX_STA_CNT0                     0x1700
1264 #define RX_STA_CNT0_CRC_ERR             FIELD32(0x0000ffff)
1265 #define RX_STA_CNT0_PHY_ERR             FIELD32(0xffff0000)
1266
1267 /*
1268  * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1269  */
1270 #define RX_STA_CNT1                     0x1704
1271 #define RX_STA_CNT1_FALSE_CCA           FIELD32(0x0000ffff)
1272 #define RX_STA_CNT1_PLCP_ERR            FIELD32(0xffff0000)
1273
1274 /*
1275  * RX_STA_CNT2:
1276  */
1277 #define RX_STA_CNT2                     0x1708
1278 #define RX_STA_CNT2_RX_DUPLI_COUNT      FIELD32(0x0000ffff)
1279 #define RX_STA_CNT2_RX_FIFO_OVERFLOW    FIELD32(0xffff0000)
1280
1281 /*
1282  * TX_STA_CNT0: TX Beacon count
1283  */
1284 #define TX_STA_CNT0                     0x170c
1285 #define TX_STA_CNT0_TX_FAIL_COUNT       FIELD32(0x0000ffff)
1286 #define TX_STA_CNT0_TX_BEACON_COUNT     FIELD32(0xffff0000)
1287
1288 /*
1289  * TX_STA_CNT1: TX tx count
1290  */
1291 #define TX_STA_CNT1                     0x1710
1292 #define TX_STA_CNT1_TX_SUCCESS          FIELD32(0x0000ffff)
1293 #define TX_STA_CNT1_TX_RETRANSMIT       FIELD32(0xffff0000)
1294
1295 /*
1296  * TX_STA_CNT2: TX tx count
1297  */
1298 #define TX_STA_CNT2                     0x1714
1299 #define TX_STA_CNT2_TX_ZERO_LEN_COUNT   FIELD32(0x0000ffff)
1300 #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1301
1302 /*
1303  * TX_STA_FIFO: TX Result for specific PID status fifo register
1304  */
1305 #define TX_STA_FIFO                     0x1718
1306 #define TX_STA_FIFO_VALID               FIELD32(0x00000001)
1307 #define TX_STA_FIFO_PID_TYPE            FIELD32(0x0000001e)
1308 #define TX_STA_FIFO_TX_SUCCESS          FIELD32(0x00000020)
1309 #define TX_STA_FIFO_TX_AGGRE            FIELD32(0x00000040)
1310 #define TX_STA_FIFO_TX_ACK_REQUIRED     FIELD32(0x00000080)
1311 #define TX_STA_FIFO_WCID                FIELD32(0x0000ff00)
1312 #define TX_STA_FIFO_SUCCESS_RATE        FIELD32(0xffff0000)
1313 #define TX_STA_FIFO_MCS                 FIELD32(0x007f0000)
1314 #define TX_STA_FIFO_PHYMODE             FIELD32(0xc0000000)
1315
1316 /*
1317  * TX_AGG_CNT: Debug counter
1318  */
1319 #define TX_AGG_CNT                      0x171c
1320 #define TX_AGG_CNT_NON_AGG_TX_COUNT     FIELD32(0x0000ffff)
1321 #define TX_AGG_CNT_AGG_TX_COUNT         FIELD32(0xffff0000)
1322
1323 /*
1324  * TX_AGG_CNT0:
1325  */
1326 #define TX_AGG_CNT0                     0x1720
1327 #define TX_AGG_CNT0_AGG_SIZE_1_COUNT    FIELD32(0x0000ffff)
1328 #define TX_AGG_CNT0_AGG_SIZE_2_COUNT    FIELD32(0xffff0000)
1329
1330 /*
1331  * TX_AGG_CNT1:
1332  */
1333 #define TX_AGG_CNT1                     0x1724
1334 #define TX_AGG_CNT1_AGG_SIZE_3_COUNT    FIELD32(0x0000ffff)
1335 #define TX_AGG_CNT1_AGG_SIZE_4_COUNT    FIELD32(0xffff0000)
1336
1337 /*
1338  * TX_AGG_CNT2:
1339  */
1340 #define TX_AGG_CNT2                     0x1728
1341 #define TX_AGG_CNT2_AGG_SIZE_5_COUNT    FIELD32(0x0000ffff)
1342 #define TX_AGG_CNT2_AGG_SIZE_6_COUNT    FIELD32(0xffff0000)
1343
1344 /*
1345  * TX_AGG_CNT3:
1346  */
1347 #define TX_AGG_CNT3                     0x172c
1348 #define TX_AGG_CNT3_AGG_SIZE_7_COUNT    FIELD32(0x0000ffff)
1349 #define TX_AGG_CNT3_AGG_SIZE_8_COUNT    FIELD32(0xffff0000)
1350
1351 /*
1352  * TX_AGG_CNT4:
1353  */
1354 #define TX_AGG_CNT4                     0x1730
1355 #define TX_AGG_CNT4_AGG_SIZE_9_COUNT    FIELD32(0x0000ffff)
1356 #define TX_AGG_CNT4_AGG_SIZE_10_COUNT   FIELD32(0xffff0000)
1357
1358 /*
1359  * TX_AGG_CNT5:
1360  */
1361 #define TX_AGG_CNT5                     0x1734
1362 #define TX_AGG_CNT5_AGG_SIZE_11_COUNT   FIELD32(0x0000ffff)
1363 #define TX_AGG_CNT5_AGG_SIZE_12_COUNT   FIELD32(0xffff0000)
1364
1365 /*
1366  * TX_AGG_CNT6:
1367  */
1368 #define TX_AGG_CNT6                     0x1738
1369 #define TX_AGG_CNT6_AGG_SIZE_13_COUNT   FIELD32(0x0000ffff)
1370 #define TX_AGG_CNT6_AGG_SIZE_14_COUNT   FIELD32(0xffff0000)
1371
1372 /*
1373  * TX_AGG_CNT7:
1374  */
1375 #define TX_AGG_CNT7                     0x173c
1376 #define TX_AGG_CNT7_AGG_SIZE_15_COUNT   FIELD32(0x0000ffff)
1377 #define TX_AGG_CNT7_AGG_SIZE_16_COUNT   FIELD32(0xffff0000)
1378
1379 /*
1380  * MPDU_DENSITY_CNT:
1381  * TX_ZERO_DEL: TX zero length delimiter count
1382  * RX_ZERO_DEL: RX zero length delimiter count
1383  */
1384 #define MPDU_DENSITY_CNT                0x1740
1385 #define MPDU_DENSITY_CNT_TX_ZERO_DEL    FIELD32(0x0000ffff)
1386 #define MPDU_DENSITY_CNT_RX_ZERO_DEL    FIELD32(0xffff0000)
1387
1388 /*
1389  * Security key table memory.
1390  * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1391  * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1392  * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1393  * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1394  * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
1395  * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
1396  */
1397 #define MAC_WCID_BASE                   0x1800
1398 #define PAIRWISE_KEY_TABLE_BASE         0x4000
1399 #define MAC_IVEIV_TABLE_BASE            0x6000
1400 #define MAC_WCID_ATTRIBUTE_BASE         0x6800
1401 #define SHARED_KEY_TABLE_BASE           0x6c00
1402 #define SHARED_KEY_MODE_BASE            0x7000
1403
1404 #define MAC_WCID_ENTRY(__idx) \
1405         ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
1406 #define PAIRWISE_KEY_ENTRY(__idx) \
1407         ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1408 #define MAC_IVEIV_ENTRY(__idx) \
1409         ( MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)) )
1410 #define MAC_WCID_ATTR_ENTRY(__idx) \
1411         ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
1412 #define SHARED_KEY_ENTRY(__idx) \
1413         ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1414 #define SHARED_KEY_MODE_ENTRY(__idx) \
1415         ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
1416
1417 struct mac_wcid_entry {
1418         u8 mac[6];
1419         u8 reserved[2];
1420 } __attribute__ ((packed));
1421
1422 struct hw_key_entry {
1423         u8 key[16];
1424         u8 tx_mic[8];
1425         u8 rx_mic[8];
1426 } __attribute__ ((packed));
1427
1428 struct mac_iveiv_entry {
1429         u8 iv[8];
1430 } __attribute__ ((packed));
1431
1432 /*
1433  * MAC_WCID_ATTRIBUTE:
1434  */
1435 #define MAC_WCID_ATTRIBUTE_KEYTAB       FIELD32(0x00000001)
1436 #define MAC_WCID_ATTRIBUTE_CIPHER       FIELD32(0x0000000e)
1437 #define MAC_WCID_ATTRIBUTE_BSS_IDX      FIELD32(0x00000070)
1438 #define MAC_WCID_ATTRIBUTE_RX_WIUDF     FIELD32(0x00000380)
1439 #define MAC_WCID_ATTRIBUTE_CIPHER_EXT   FIELD32(0x00000400)
1440 #define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT  FIELD32(0x00000800)
1441 #define MAC_WCID_ATTRIBUTE_WAPI_MCBC    FIELD32(0x00008000)
1442 #define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000)
1443
1444 /*
1445  * SHARED_KEY_MODE:
1446  */
1447 #define SHARED_KEY_MODE_BSS0_KEY0       FIELD32(0x00000007)
1448 #define SHARED_KEY_MODE_BSS0_KEY1       FIELD32(0x00000070)
1449 #define SHARED_KEY_MODE_BSS0_KEY2       FIELD32(0x00000700)
1450 #define SHARED_KEY_MODE_BSS0_KEY3       FIELD32(0x00007000)
1451 #define SHARED_KEY_MODE_BSS1_KEY0       FIELD32(0x00070000)
1452 #define SHARED_KEY_MODE_BSS1_KEY1       FIELD32(0x00700000)
1453 #define SHARED_KEY_MODE_BSS1_KEY2       FIELD32(0x07000000)
1454 #define SHARED_KEY_MODE_BSS1_KEY3       FIELD32(0x70000000)
1455
1456 /*
1457  * HOST-MCU communication
1458  */
1459
1460 /*
1461  * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1462  */
1463 #define H2M_MAILBOX_CSR                 0x7010
1464 #define H2M_MAILBOX_CSR_ARG0            FIELD32(0x000000ff)
1465 #define H2M_MAILBOX_CSR_ARG1            FIELD32(0x0000ff00)
1466 #define H2M_MAILBOX_CSR_CMD_TOKEN       FIELD32(0x00ff0000)
1467 #define H2M_MAILBOX_CSR_OWNER           FIELD32(0xff000000)
1468
1469 /*
1470  * H2M_MAILBOX_CID:
1471  */
1472 #define H2M_MAILBOX_CID                 0x7014
1473 #define H2M_MAILBOX_CID_CMD0            FIELD32(0x000000ff)
1474 #define H2M_MAILBOX_CID_CMD1            FIELD32(0x0000ff00)
1475 #define H2M_MAILBOX_CID_CMD2            FIELD32(0x00ff0000)
1476 #define H2M_MAILBOX_CID_CMD3            FIELD32(0xff000000)
1477
1478 /*
1479  * H2M_MAILBOX_STATUS:
1480  */
1481 #define H2M_MAILBOX_STATUS              0x701c
1482
1483 /*
1484  * H2M_INT_SRC:
1485  */
1486 #define H2M_INT_SRC                     0x7024
1487
1488 /*
1489  * H2M_BBP_AGENT:
1490  */
1491 #define H2M_BBP_AGENT                   0x7028
1492
1493 /*
1494  * MCU_LEDCS: LED control for MCU Mailbox.
1495  */
1496 #define MCU_LEDCS_LED_MODE              FIELD8(0x1f)
1497 #define MCU_LEDCS_POLARITY              FIELD8(0x01)
1498
1499 /*
1500  * HW_CS_CTS_BASE:
1501  * Carrier-sense CTS frame base address.
1502  * It's where mac stores carrier-sense frame for carrier-sense function.
1503  */
1504 #define HW_CS_CTS_BASE                  0x7700
1505
1506 /*
1507  * HW_DFS_CTS_BASE:
1508  * DFS CTS frame base address. It's where mac stores CTS frame for DFS.
1509  */
1510 #define HW_DFS_CTS_BASE                 0x7780
1511
1512 /*
1513  * TXRX control registers - base address 0x3000
1514  */
1515
1516 /*
1517  * TXRX_CSR1:
1518  * rt2860b  UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1519  */
1520 #define TXRX_CSR1                       0x77d0
1521
1522 /*
1523  * HW_DEBUG_SETTING_BASE:
1524  * since NULL frame won't be that long (256 byte)
1525  * We steal 16 tail bytes to save debugging settings
1526  */
1527 #define HW_DEBUG_SETTING_BASE           0x77f0
1528 #define HW_DEBUG_SETTING_BASE2          0x7770
1529
1530 /*
1531  * HW_BEACON_BASE
1532  * In order to support maximum 8 MBSS and its maximum length
1533  * is 512 bytes for each beacon
1534  * Three section discontinue memory segments will be used.
1535  * 1. The original region for BCN 0~3
1536  * 2. Extract memory from FCE table for BCN 4~5
1537  * 3. Extract memory from Pair-wise key table for BCN 6~7
1538  *    It occupied those memory of wcid 238~253 for BCN 6
1539  *    and wcid 222~237 for BCN 7
1540  *
1541  * IMPORTANT NOTE: Not sure why legacy driver does this,
1542  * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
1543  */
1544 #define HW_BEACON_BASE0                 0x7800
1545 #define HW_BEACON_BASE1                 0x7a00
1546 #define HW_BEACON_BASE2                 0x7c00
1547 #define HW_BEACON_BASE3                 0x7e00
1548 #define HW_BEACON_BASE4                 0x7200
1549 #define HW_BEACON_BASE5                 0x7400
1550 #define HW_BEACON_BASE6                 0x5dc0
1551 #define HW_BEACON_BASE7                 0x5bc0
1552
1553 #define HW_BEACON_OFFSET(__index) \
1554         ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
1555           (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
1556           (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
1557
1558 /*
1559  * BBP registers.
1560  * The wordsize of the BBP is 8 bits.
1561  */
1562
1563 /*
1564  * BBP 1: TX Antenna & Power
1565  * POWER: 0 - normal, 1 - drop tx power by 6dBm, 2 - drop tx power by 12dBm,
1566  *      3 - increase tx power by 6dBm
1567  */
1568 #define BBP1_TX_POWER                   FIELD8(0x07)
1569 #define BBP1_TX_ANTENNA                 FIELD8(0x18)
1570
1571 /*
1572  * BBP 3: RX Antenna
1573  */
1574 #define BBP3_RX_ANTENNA                 FIELD8(0x18)
1575 #define BBP3_HT40_MINUS                 FIELD8(0x20)
1576
1577 /*
1578  * BBP 4: Bandwidth
1579  */
1580 #define BBP4_TX_BF                      FIELD8(0x01)
1581 #define BBP4_BANDWIDTH                  FIELD8(0x18)
1582
1583 /*
1584  * BBP 138: Unknown
1585  */
1586 #define BBP138_RX_ADC1                  FIELD8(0x02)
1587 #define BBP138_RX_ADC2                  FIELD8(0x04)
1588 #define BBP138_TX_DAC1                  FIELD8(0x20)
1589 #define BBP138_TX_DAC2                  FIELD8(0x40)
1590
1591 /*
1592  * RFCSR registers
1593  * The wordsize of the RFCSR is 8 bits.
1594  */
1595
1596 /*
1597  * RFCSR 1:
1598  */
1599 #define RFCSR1_RF_BLOCK_EN              FIELD8(0x01)
1600 #define RFCSR1_RX0_PD                   FIELD8(0x04)
1601 #define RFCSR1_TX0_PD                   FIELD8(0x08)
1602 #define RFCSR1_RX1_PD                   FIELD8(0x10)
1603 #define RFCSR1_TX1_PD                   FIELD8(0x20)
1604
1605 /*
1606  * RFCSR 6:
1607  */
1608 #define RFCSR6_R1                       FIELD8(0x03)
1609 #define RFCSR6_R2                       FIELD8(0x40)
1610
1611 /*
1612  * RFCSR 7:
1613  */
1614 #define RFCSR7_RF_TUNING                FIELD8(0x01)
1615
1616 /*
1617  * RFCSR 12:
1618  */
1619 #define RFCSR12_TX_POWER                FIELD8(0x1f)
1620
1621 /*
1622  * RFCSR 13:
1623  */
1624 #define RFCSR13_TX_POWER                FIELD8(0x1f)
1625
1626 /*
1627  * RFCSR 15:
1628  */
1629 #define RFCSR15_TX_LO2_EN               FIELD8(0x08)
1630
1631 /*
1632  * RFCSR 17:
1633  */
1634 #define RFCSR17_TXMIXER_GAIN            FIELD8(0x07)
1635 #define RFCSR17_TX_LO1_EN               FIELD8(0x08)
1636 #define RFCSR17_R                       FIELD8(0x20)
1637
1638 /*
1639  * RFCSR 20:
1640  */
1641 #define RFCSR20_RX_LO1_EN               FIELD8(0x08)
1642
1643 /*
1644  * RFCSR 21:
1645  */
1646 #define RFCSR21_RX_LO2_EN               FIELD8(0x08)
1647
1648 /*
1649  * RFCSR 22:
1650  */
1651 #define RFCSR22_BASEBAND_LOOPBACK       FIELD8(0x01)
1652
1653 /*
1654  * RFCSR 23:
1655  */
1656 #define RFCSR23_FREQ_OFFSET             FIELD8(0x7f)
1657
1658 /*
1659  * RFCSR 27:
1660  */
1661 #define RFCSR27_R1                      FIELD8(0x03)
1662 #define RFCSR27_R2                      FIELD8(0x04)
1663 #define RFCSR27_R3                      FIELD8(0x30)
1664 #define RFCSR27_R4                      FIELD8(0x40)
1665
1666 /*
1667  * RFCSR 30:
1668  */
1669 #define RFCSR30_RF_CALIBRATION          FIELD8(0x80)
1670
1671 /*
1672  * RF registers
1673  */
1674
1675 /*
1676  * RF 2
1677  */
1678 #define RF2_ANTENNA_RX2                 FIELD32(0x00000040)
1679 #define RF2_ANTENNA_TX1                 FIELD32(0x00004000)
1680 #define RF2_ANTENNA_RX1                 FIELD32(0x00020000)
1681
1682 /*
1683  * RF 3
1684  */
1685 #define RF3_TXPOWER_G                   FIELD32(0x00003e00)
1686 #define RF3_TXPOWER_A_7DBM_BOOST        FIELD32(0x00000200)
1687 #define RF3_TXPOWER_A                   FIELD32(0x00003c00)
1688
1689 /*
1690  * RF 4
1691  */
1692 #define RF4_TXPOWER_G                   FIELD32(0x000007c0)
1693 #define RF4_TXPOWER_A_7DBM_BOOST        FIELD32(0x00000040)
1694 #define RF4_TXPOWER_A                   FIELD32(0x00000780)
1695 #define RF4_FREQ_OFFSET                 FIELD32(0x001f8000)
1696 #define RF4_HT40                        FIELD32(0x00200000)
1697
1698 /*
1699  * EEPROM content.
1700  * The wordsize of the EEPROM is 16 bits.
1701  */
1702
1703 /*
1704  * EEPROM Version
1705  */
1706 #define EEPROM_VERSION                  0x0001
1707 #define EEPROM_VERSION_FAE              FIELD16(0x00ff)
1708 #define EEPROM_VERSION_VERSION          FIELD16(0xff00)
1709
1710 /*
1711  * HW MAC address.
1712  */
1713 #define EEPROM_MAC_ADDR_0               0x0002
1714 #define EEPROM_MAC_ADDR_BYTE0           FIELD16(0x00ff)
1715 #define EEPROM_MAC_ADDR_BYTE1           FIELD16(0xff00)
1716 #define EEPROM_MAC_ADDR_1               0x0003
1717 #define EEPROM_MAC_ADDR_BYTE2           FIELD16(0x00ff)
1718 #define EEPROM_MAC_ADDR_BYTE3           FIELD16(0xff00)
1719 #define EEPROM_MAC_ADDR_2               0x0004
1720 #define EEPROM_MAC_ADDR_BYTE4           FIELD16(0x00ff)
1721 #define EEPROM_MAC_ADDR_BYTE5           FIELD16(0xff00)
1722
1723 /*
1724  * EEPROM ANTENNA config
1725  * RXPATH: 1: 1R, 2: 2R, 3: 3R
1726  * TXPATH: 1: 1T, 2: 2T
1727  */
1728 #define EEPROM_ANTENNA                  0x001a
1729 #define EEPROM_ANTENNA_RXPATH           FIELD16(0x000f)
1730 #define EEPROM_ANTENNA_TXPATH           FIELD16(0x00f0)
1731 #define EEPROM_ANTENNA_RF_TYPE          FIELD16(0x0f00)
1732
1733 /*
1734  * EEPROM NIC config
1735  * CARDBUS_ACCEL: 0 - enable, 1 - disable
1736  */
1737 #define EEPROM_NIC                      0x001b
1738 #define EEPROM_NIC_HW_RADIO             FIELD16(0x0001)
1739 #define EEPROM_NIC_DYNAMIC_TX_AGC       FIELD16(0x0002)
1740 #define EEPROM_NIC_EXTERNAL_LNA_BG      FIELD16(0x0004)
1741 #define EEPROM_NIC_EXTERNAL_LNA_A       FIELD16(0x0008)
1742 #define EEPROM_NIC_CARDBUS_ACCEL        FIELD16(0x0010)
1743 #define EEPROM_NIC_BW40M_SB_BG          FIELD16(0x0020)
1744 #define EEPROM_NIC_BW40M_SB_A           FIELD16(0x0040)
1745 #define EEPROM_NIC_WPS_PBC              FIELD16(0x0080)
1746 #define EEPROM_NIC_BW40M_BG             FIELD16(0x0100)
1747 #define EEPROM_NIC_BW40M_A              FIELD16(0x0200)
1748 #define EEPROM_NIC_ANT_DIVERSITY        FIELD16(0x0800)
1749 #define EEPROM_NIC_DAC_TEST             FIELD16(0x8000)
1750
1751 /*
1752  * EEPROM frequency
1753  */
1754 #define EEPROM_FREQ                     0x001d
1755 #define EEPROM_FREQ_OFFSET              FIELD16(0x00ff)
1756 #define EEPROM_FREQ_LED_MODE            FIELD16(0x7f00)
1757 #define EEPROM_FREQ_LED_POLARITY        FIELD16(0x1000)
1758
1759 /*
1760  * EEPROM LED
1761  * POLARITY_RDY_G: Polarity RDY_G setting.
1762  * POLARITY_RDY_A: Polarity RDY_A setting.
1763  * POLARITY_ACT: Polarity ACT setting.
1764  * POLARITY_GPIO_0: Polarity GPIO0 setting.
1765  * POLARITY_GPIO_1: Polarity GPIO1 setting.
1766  * POLARITY_GPIO_2: Polarity GPIO2 setting.
1767  * POLARITY_GPIO_3: Polarity GPIO3 setting.
1768  * POLARITY_GPIO_4: Polarity GPIO4 setting.
1769  * LED_MODE: Led mode.
1770  */
1771 #define EEPROM_LED1                     0x001e
1772 #define EEPROM_LED2                     0x001f
1773 #define EEPROM_LED3                     0x0020
1774 #define EEPROM_LED_POLARITY_RDY_BG      FIELD16(0x0001)
1775 #define EEPROM_LED_POLARITY_RDY_A       FIELD16(0x0002)
1776 #define EEPROM_LED_POLARITY_ACT         FIELD16(0x0004)
1777 #define EEPROM_LED_POLARITY_GPIO_0      FIELD16(0x0008)
1778 #define EEPROM_LED_POLARITY_GPIO_1      FIELD16(0x0010)
1779 #define EEPROM_LED_POLARITY_GPIO_2      FIELD16(0x0020)
1780 #define EEPROM_LED_POLARITY_GPIO_3      FIELD16(0x0040)
1781 #define EEPROM_LED_POLARITY_GPIO_4      FIELD16(0x0080)
1782 #define EEPROM_LED_LED_MODE             FIELD16(0x1f00)
1783
1784 /*
1785  * EEPROM LNA
1786  */
1787 #define EEPROM_LNA                      0x0022
1788 #define EEPROM_LNA_BG                   FIELD16(0x00ff)
1789 #define EEPROM_LNA_A0                   FIELD16(0xff00)
1790
1791 /*
1792  * EEPROM RSSI BG offset
1793  */
1794 #define EEPROM_RSSI_BG                  0x0023
1795 #define EEPROM_RSSI_BG_OFFSET0          FIELD16(0x00ff)
1796 #define EEPROM_RSSI_BG_OFFSET1          FIELD16(0xff00)
1797
1798 /*
1799  * EEPROM RSSI BG2 offset
1800  */
1801 #define EEPROM_RSSI_BG2                 0x0024
1802 #define EEPROM_RSSI_BG2_OFFSET2         FIELD16(0x00ff)
1803 #define EEPROM_RSSI_BG2_LNA_A1          FIELD16(0xff00)
1804
1805 /*
1806  * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2).
1807  */
1808 #define EEPROM_TXMIXER_GAIN_BG          0x0024
1809 #define EEPROM_TXMIXER_GAIN_BG_VAL      FIELD16(0x0007)
1810
1811 /*
1812  * EEPROM RSSI A offset
1813  */
1814 #define EEPROM_RSSI_A                   0x0025
1815 #define EEPROM_RSSI_A_OFFSET0           FIELD16(0x00ff)
1816 #define EEPROM_RSSI_A_OFFSET1           FIELD16(0xff00)
1817
1818 /*
1819  * EEPROM RSSI A2 offset
1820  */
1821 #define EEPROM_RSSI_A2                  0x0026
1822 #define EEPROM_RSSI_A2_OFFSET2          FIELD16(0x00ff)
1823 #define EEPROM_RSSI_A2_LNA_A2           FIELD16(0xff00)
1824
1825 /*
1826  * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
1827  *      This is delta in 40MHZ.
1828  * VALUE: Tx Power dalta value (MAX=4)
1829  * TYPE: 1: Plus the delta value, 0: minus the delta value
1830  * TXPOWER: Enable:
1831  */
1832 #define EEPROM_TXPOWER_DELTA            0x0028
1833 #define EEPROM_TXPOWER_DELTA_VALUE      FIELD16(0x003f)
1834 #define EEPROM_TXPOWER_DELTA_TYPE       FIELD16(0x0040)
1835 #define EEPROM_TXPOWER_DELTA_TXPOWER    FIELD16(0x0080)
1836
1837 /*
1838  * EEPROM TXPOWER 802.11BG
1839  */
1840 #define EEPROM_TXPOWER_BG1              0x0029
1841 #define EEPROM_TXPOWER_BG2              0x0030
1842 #define EEPROM_TXPOWER_BG_SIZE          7
1843 #define EEPROM_TXPOWER_BG_1             FIELD16(0x00ff)
1844 #define EEPROM_TXPOWER_BG_2             FIELD16(0xff00)
1845
1846 /*
1847  * EEPROM TXPOWER 802.11A
1848  */
1849 #define EEPROM_TXPOWER_A1               0x003c
1850 #define EEPROM_TXPOWER_A2               0x0053
1851 #define EEPROM_TXPOWER_A_SIZE           6
1852 #define EEPROM_TXPOWER_A_1              FIELD16(0x00ff)
1853 #define EEPROM_TXPOWER_A_2              FIELD16(0xff00)
1854
1855 /*
1856  * EEPROM TXpower byrate: 20MHZ power
1857  */
1858 #define EEPROM_TXPOWER_BYRATE           0x006f
1859
1860 /*
1861  * EEPROM BBP.
1862  */
1863 #define EEPROM_BBP_START                0x0078
1864 #define EEPROM_BBP_SIZE                 16
1865 #define EEPROM_BBP_VALUE                FIELD16(0x00ff)
1866 #define EEPROM_BBP_REG_ID               FIELD16(0xff00)
1867
1868 /*
1869  * MCU mailbox commands.
1870  */
1871 #define MCU_SLEEP                       0x30
1872 #define MCU_WAKEUP                      0x31
1873 #define MCU_RADIO_OFF                   0x35
1874 #define MCU_CURRENT                     0x36
1875 #define MCU_LED                         0x50
1876 #define MCU_LED_STRENGTH                0x51
1877 #define MCU_LED_1                       0x52
1878 #define MCU_LED_2                       0x53
1879 #define MCU_LED_3                       0x54
1880 #define MCU_RADAR                       0x60
1881 #define MCU_BOOT_SIGNAL                 0x72
1882 #define MCU_BBP_SIGNAL                  0x80
1883 #define MCU_POWER_SAVE                  0x83
1884
1885 /*
1886  * MCU mailbox tokens
1887  */
1888 #define TOKEN_WAKUP                     3
1889
1890 /*
1891  * DMA descriptor defines.
1892  */
1893 #define TXWI_DESC_SIZE                  ( 4 * sizeof(__le32) )
1894 #define RXWI_DESC_SIZE                  ( 4 * sizeof(__le32) )
1895
1896 /*
1897  * TX WI structure
1898  */
1899
1900 /*
1901  * Word0
1902  * FRAG: 1 To inform TKIP engine this is a fragment.
1903  * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
1904  * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
1905  * BW: Channel bandwidth 20MHz or 40 MHz
1906  * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
1907  */
1908 #define TXWI_W0_FRAG                    FIELD32(0x00000001)
1909 #define TXWI_W0_MIMO_PS                 FIELD32(0x00000002)
1910 #define TXWI_W0_CF_ACK                  FIELD32(0x00000004)
1911 #define TXWI_W0_TS                      FIELD32(0x00000008)
1912 #define TXWI_W0_AMPDU                   FIELD32(0x00000010)
1913 #define TXWI_W0_MPDU_DENSITY            FIELD32(0x000000e0)
1914 #define TXWI_W0_TX_OP                   FIELD32(0x00000300)
1915 #define TXWI_W0_MCS                     FIELD32(0x007f0000)
1916 #define TXWI_W0_BW                      FIELD32(0x00800000)
1917 #define TXWI_W0_SHORT_GI                FIELD32(0x01000000)
1918 #define TXWI_W0_STBC                    FIELD32(0x06000000)
1919 #define TXWI_W0_IFS                     FIELD32(0x08000000)
1920 #define TXWI_W0_PHYMODE                 FIELD32(0xc0000000)
1921
1922 /*
1923  * Word1
1924  */
1925 #define TXWI_W1_ACK                     FIELD32(0x00000001)
1926 #define TXWI_W1_NSEQ                    FIELD32(0x00000002)
1927 #define TXWI_W1_BW_WIN_SIZE             FIELD32(0x000000fc)
1928 #define TXWI_W1_WIRELESS_CLI_ID         FIELD32(0x0000ff00)
1929 #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT   FIELD32(0x0fff0000)
1930 #define TXWI_W1_PACKETID                FIELD32(0xf0000000)
1931
1932 /*
1933  * Word2
1934  */
1935 #define TXWI_W2_IV                      FIELD32(0xffffffff)
1936
1937 /*
1938  * Word3
1939  */
1940 #define TXWI_W3_EIV                     FIELD32(0xffffffff)
1941
1942 /*
1943  * RX WI structure
1944  */
1945
1946 /*
1947  * Word0
1948  */
1949 #define RXWI_W0_WIRELESS_CLI_ID         FIELD32(0x000000ff)
1950 #define RXWI_W0_KEY_INDEX               FIELD32(0x00000300)
1951 #define RXWI_W0_BSSID                   FIELD32(0x00001c00)
1952 #define RXWI_W0_UDF                     FIELD32(0x0000e000)
1953 #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT   FIELD32(0x0fff0000)
1954 #define RXWI_W0_TID                     FIELD32(0xf0000000)
1955
1956 /*
1957  * Word1
1958  */
1959 #define RXWI_W1_FRAG                    FIELD32(0x0000000f)
1960 #define RXWI_W1_SEQUENCE                FIELD32(0x0000fff0)
1961 #define RXWI_W1_MCS                     FIELD32(0x007f0000)
1962 #define RXWI_W1_BW                      FIELD32(0x00800000)
1963 #define RXWI_W1_SHORT_GI                FIELD32(0x01000000)
1964 #define RXWI_W1_STBC                    FIELD32(0x06000000)
1965 #define RXWI_W1_PHYMODE                 FIELD32(0xc0000000)
1966
1967 /*
1968  * Word2
1969  */
1970 #define RXWI_W2_RSSI0                   FIELD32(0x000000ff)
1971 #define RXWI_W2_RSSI1                   FIELD32(0x0000ff00)
1972 #define RXWI_W2_RSSI2                   FIELD32(0x00ff0000)
1973
1974 /*
1975  * Word3
1976  */
1977 #define RXWI_W3_SNR0                    FIELD32(0x000000ff)
1978 #define RXWI_W3_SNR1                    FIELD32(0x0000ff00)
1979
1980 /*
1981  * Macros for converting txpower from EEPROM to mac80211 value
1982  * and from mac80211 value to register value.
1983  */
1984 #define MIN_G_TXPOWER   0
1985 #define MIN_A_TXPOWER   -7
1986 #define MAX_G_TXPOWER   31
1987 #define MAX_A_TXPOWER   15
1988 #define DEFAULT_TXPOWER 5
1989
1990 #define TXPOWER_G_FROM_DEV(__txpower) \
1991         ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1992
1993 #define TXPOWER_G_TO_DEV(__txpower) \
1994         clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
1995
1996 #define TXPOWER_A_FROM_DEV(__txpower) \
1997         ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1998
1999 #define TXPOWER_A_TO_DEV(__txpower) \
2000         clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
2001
2002 #endif /* RT2800_H */