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rt2x00: use wiphy rfkill interface
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / rt2x00 / rt2500pci.c
blobc123e28396d03df3f073c12f97b09c69652f1804
1 /*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt2500pci
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
25 */
26
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
34
35 #include "rt2x00.h"
36 #include "rt2x00pci.h"
37 #include "rt2500pci.h"
38
39 /*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
52 #define WAIT_FOR_BBP(__dev, __reg) \
53 rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
54 #define WAIT_FOR_RF(__dev, __reg) \
55 rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
56
57 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
58 const unsigned int word, const u8 value)
59 {
60 u32 reg;
61
62 mutex_lock(&rt2x00dev->csr_mutex);
63
64 /*
65 * Wait until the BBP becomes available, afterwards we
66 * can safely write the new data into the register.
67 */
68 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
69 reg = 0;
70 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
71 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
72 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
73 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
74
75 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
76 }
77
78 mutex_unlock(&rt2x00dev->csr_mutex);
79 }
80
81 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
82 const unsigned int word, u8 *value)
83 {
84 u32 reg;
85
86 mutex_lock(&rt2x00dev->csr_mutex);
87
88 /*
89 * Wait until the BBP becomes available, afterwards we
90 * can safely write the read request into the register.
91 * After the data has been written, we wait until hardware
92 * returns the correct value, if at any time the register
93 * doesn't become available in time, reg will be 0xffffffff
94 * which means we return 0xff to the caller.
95 */
96 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
97 reg = 0;
98 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
99 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
100 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
101
102 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
103
104 WAIT_FOR_BBP(rt2x00dev, &reg);
105 }
106
107 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110 }
111
112 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, const u32 value)
114 {
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the RF becomes available, afterwards we
121 * can safely write the new data into the register.
122 */
123 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
124 reg = 0;
125 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
126 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
127 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
128 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
129
130 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
131 rt2x00_rf_write(rt2x00dev, word, value);
132 }
133
134 mutex_unlock(&rt2x00dev->csr_mutex);
135 }
136
137 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
138 {
139 struct rt2x00_dev *rt2x00dev = eeprom->data;
140 u32 reg;
141
142 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
143
144 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
145 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
146 eeprom->reg_data_clock =
147 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
148 eeprom->reg_chip_select =
149 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
150 }
151
152 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
153 {
154 struct rt2x00_dev *rt2x00dev = eeprom->data;
155 u32 reg = 0;
156
157 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
158 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
159 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
160 !!eeprom->reg_data_clock);
161 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
162 !!eeprom->reg_chip_select);
163
164 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
165 }
166
167 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
168 static const struct rt2x00debug rt2500pci_rt2x00debug = {
169 .owner = THIS_MODULE,
170 .csr = {
171 .read = rt2x00pci_register_read,
172 .write = rt2x00pci_register_write,
173 .flags = RT2X00DEBUGFS_OFFSET,
174 .word_base = CSR_REG_BASE,
175 .word_size = sizeof(u32),
176 .word_count = CSR_REG_SIZE / sizeof(u32),
177 },
178 .eeprom = {
179 .read = rt2x00_eeprom_read,
180 .write = rt2x00_eeprom_write,
181 .word_base = EEPROM_BASE,
182 .word_size = sizeof(u16),
183 .word_count = EEPROM_SIZE / sizeof(u16),
184 },
185 .bbp = {
186 .read = rt2500pci_bbp_read,
187 .write = rt2500pci_bbp_write,
188 .word_base = BBP_BASE,
189 .word_size = sizeof(u8),
190 .word_count = BBP_SIZE / sizeof(u8),
191 },
192 .rf = {
193 .read = rt2x00_rf_read,
194 .write = rt2500pci_rf_write,
195 .word_base = RF_BASE,
196 .word_size = sizeof(u32),
197 .word_count = RF_SIZE / sizeof(u32),
198 },
199 };
200 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
201
202 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
203 {
204 u32 reg;
205
206 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
207 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
208 }
209
210 #ifdef CONFIG_RT2X00_LIB_LEDS
211 static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
212 enum led_brightness brightness)
213 {
214 struct rt2x00_led *led =
215 container_of(led_cdev, struct rt2x00_led, led_dev);
216 unsigned int enabled = brightness != LED_OFF;
217 u32 reg;
218
219 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
220
221 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
222 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
223 else if (led->type == LED_TYPE_ACTIVITY)
224 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
225
226 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
227 }
228
229 static int rt2500pci_blink_set(struct led_classdev *led_cdev,
230 unsigned long *delay_on,
231 unsigned long *delay_off)
232 {
233 struct rt2x00_led *led =
234 container_of(led_cdev, struct rt2x00_led, led_dev);
235 u32 reg;
236
237 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
238 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
239 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
240 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
241
242 return 0;
243 }
244
245 static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
246 struct rt2x00_led *led,
247 enum led_type type)
248 {
249 led->rt2x00dev = rt2x00dev;
250 led->type = type;
251 led->led_dev.brightness_set = rt2500pci_brightness_set;
252 led->led_dev.blink_set = rt2500pci_blink_set;
253 led->flags = LED_INITIALIZED;
254 }
255 #endif /* CONFIG_RT2X00_LIB_LEDS */
256
257 /*
258 * Configuration handlers.
259 */
260 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
261 const unsigned int filter_flags)
262 {
263 u32 reg;
264
265 /*
266 * Start configuration steps.
267 * Note that the version error will always be dropped
268 * and broadcast frames will always be accepted since
269 * there is no filter for it at this time.
270 */
271 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
272 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
273 !(filter_flags & FIF_FCSFAIL));
274 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
275 !(filter_flags & FIF_PLCPFAIL));
276 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
277 !(filter_flags & FIF_CONTROL));
278 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
279 !(filter_flags & FIF_PROMISC_IN_BSS));
280 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
281 !(filter_flags & FIF_PROMISC_IN_BSS) &&
282 !rt2x00dev->intf_ap_count);
283 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
284 rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
285 !(filter_flags & FIF_ALLMULTI));
286 rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
287 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
288 }
289
290 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
291 struct rt2x00_intf *intf,
292 struct rt2x00intf_conf *conf,
293 const unsigned int flags)
294 {
295 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
296 unsigned int bcn_preload;
297 u32 reg;
298
299 if (flags & CONFIG_UPDATE_TYPE) {
300 /*
301 * Enable beacon config
302 */
303 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
304 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
305 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
306 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
307 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
308
309 /*
310 * Enable synchronisation.
311 */
312 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
313 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
314 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
315 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
316 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
317 }
318
319 if (flags & CONFIG_UPDATE_MAC)
320 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
321 conf->mac, sizeof(conf->mac));
322
323 if (flags & CONFIG_UPDATE_BSSID)
324 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
325 conf->bssid, sizeof(conf->bssid));
326 }
327
328 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
329 struct rt2x00lib_erp *erp)
330 {
331 int preamble_mask;
332 u32 reg;
333
334 /*
335 * When short preamble is enabled, we should set bit 0x08
336 */
337 preamble_mask = erp->short_preamble << 3;
338
339 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
340 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, erp->ack_timeout);
341 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
342 erp->ack_consume_time);
343 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
344 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
345 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
346
347 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
348 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
349 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
350 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
351 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
352
353 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
354 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
355 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
356 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
357 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
358
359 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
360 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
361 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
362 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
363 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
364
365 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
366 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
367 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
368 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
369 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
370
371 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
372
373 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
374 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
375 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
376
377 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
378 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, erp->beacon_int * 16);
379 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, erp->beacon_int * 16);
380 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
381
382 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
383 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
384 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
385 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
386
387 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
388 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
389 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
390 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
391 }
392
393 static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
394 struct antenna_setup *ant)
395 {
396 u32 reg;
397 u8 r14;
398 u8 r2;
399
400 /*
401 * We should never come here because rt2x00lib is supposed
402 * to catch this and send us the correct antenna explicitely.
403 */
404 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
405 ant->tx == ANTENNA_SW_DIVERSITY);
406
407 rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
408 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
409 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
410
411 /*
412 * Configure the TX antenna.
413 */
414 switch (ant->tx) {
415 case ANTENNA_A:
416 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
417 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
418 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
419 break;
420 case ANTENNA_B:
421 default:
422 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
423 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
424 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
425 break;
426 }
427
428 /*
429 * Configure the RX antenna.
430 */
431 switch (ant->rx) {
432 case ANTENNA_A:
433 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
434 break;
435 case ANTENNA_B:
436 default:
437 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
438 break;
439 }
440
441 /*
442 * RT2525E and RT5222 need to flip TX I/Q
443 */
444 if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
445 rt2x00_rf(&rt2x00dev->chip, RF5222)) {
446 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
447 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
448 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
449
450 /*
451 * RT2525E does not need RX I/Q Flip.
452 */
453 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
454 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
455 } else {
456 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
457 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
458 }
459
460 rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
461 rt2500pci_bbp_write(rt2x00dev, 14, r14);
462 rt2500pci_bbp_write(rt2x00dev, 2, r2);
463 }
464
465 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
466 struct rf_channel *rf, const int txpower)
467 {
468 u8 r70;
469
470 /*
471 * Set TXpower.
472 */
473 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
474
475 /*
476 * Switch on tuning bits.
477 * For RT2523 devices we do not need to update the R1 register.
478 */
479 if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
480 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
481 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
482
483 /*
484 * For RT2525 we should first set the channel to half band higher.
485 */
486 if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
487 static const u32 vals[] = {
488 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
489 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
490 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
491 0x00080d2e, 0x00080d3a
492 };
493
494 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
495 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
496 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
497 if (rf->rf4)
498 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
499 }
500
501 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
502 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
503 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
504 if (rf->rf4)
505 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
506
507 /*
508 * Channel 14 requires the Japan filter bit to be set.
509 */
510 r70 = 0x46;
511 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
512 rt2500pci_bbp_write(rt2x00dev, 70, r70);
513
514 msleep(1);
515
516 /*
517 * Switch off tuning bits.
518 * For RT2523 devices we do not need to update the R1 register.
519 */
520 if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
521 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
522 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
523 }
524
525 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
526 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
527
528 /*
529 * Clear false CRC during channel switch.
530 */
531 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
532 }
533
534 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
535 const int txpower)
536 {
537 u32 rf3;
538
539 rt2x00_rf_read(rt2x00dev, 3, &rf3);
540 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
541 rt2500pci_rf_write(rt2x00dev, 3, rf3);
542 }
543
544 static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
545 struct rt2x00lib_conf *libconf)
546 {
547 u32 reg;
548
549 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
550 rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
551 libconf->conf->long_frame_max_tx_count);
552 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
553 libconf->conf->short_frame_max_tx_count);
554 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
555 }
556
557 static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
558 struct rt2x00lib_conf *libconf)
559 {
560 enum dev_state state =
561 (libconf->conf->flags & IEEE80211_CONF_PS) ?
562 STATE_SLEEP : STATE_AWAKE;
563 u32 reg;
564
565 if (state == STATE_SLEEP) {
566 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
567 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
568 (rt2x00dev->beacon_int - 20) * 16);
569 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
570 libconf->conf->listen_interval - 1);
571
572 /* We must first disable autowake before it can be enabled */
573 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
574 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
575
576 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
577 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
578 }
579
580 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
581 }
582
583 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
584 struct rt2x00lib_conf *libconf,
585 const unsigned int flags)
586 {
587 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
588 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
589 libconf->conf->power_level);
590 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
591 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
592 rt2500pci_config_txpower(rt2x00dev,
593 libconf->conf->power_level);
594 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
595 rt2500pci_config_retry_limit(rt2x00dev, libconf);
596 if (flags & IEEE80211_CONF_CHANGE_PS)
597 rt2500pci_config_ps(rt2x00dev, libconf);
598 }
599
600 /*
601 * Link tuning
602 */
603 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
604 struct link_qual *qual)
605 {
606 u32 reg;
607
608 /*
609 * Update FCS error count from register.
610 */
611 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
612 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
613
614 /*
615 * Update False CCA count from register.
616 */
617 rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
618 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
619 }
620
621 static inline void rt2500pci_set_vgc(struct rt2x00_dev *rt2x00dev,
622 struct link_qual *qual, u8 vgc_level)
623 {
624 if (qual->vgc_level_reg != vgc_level) {
625 rt2500pci_bbp_write(rt2x00dev, 17, vgc_level);
626 qual->vgc_level_reg = vgc_level;
627 }
628 }
629
630 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
631 struct link_qual *qual)
632 {
633 rt2500pci_set_vgc(rt2x00dev, qual, 0x48);
634 }
635
636 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev,
637 struct link_qual *qual, const u32 count)
638 {
639 /*
640 * To prevent collisions with MAC ASIC on chipsets
641 * up to version C the link tuning should halt after 20
642 * seconds while being associated.
643 */
644 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
645 rt2x00dev->intf_associated && count > 20)
646 return;
647
648 /*
649 * Chipset versions C and lower should directly continue
650 * to the dynamic CCA tuning. Chipset version D and higher
651 * should go straight to dynamic CCA tuning when they
652 * are not associated.
653 */
654 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D ||
655 !rt2x00dev->intf_associated)
656 goto dynamic_cca_tune;
657
658 /*
659 * A too low RSSI will cause too much false CCA which will
660 * then corrupt the R17 tuning. To remidy this the tuning should
661 * be stopped (While making sure the R17 value will not exceed limits)
662 */
663 if (qual->rssi < -80 && count > 20) {
664 if (qual->vgc_level_reg >= 0x41)
665 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
666 return;
667 }
668
669 /*
670 * Special big-R17 for short distance
671 */
672 if (qual->rssi >= -58) {
673 rt2500pci_set_vgc(rt2x00dev, qual, 0x50);
674 return;
675 }
676
677 /*
678 * Special mid-R17 for middle distance
679 */
680 if (qual->rssi >= -74) {
681 rt2500pci_set_vgc(rt2x00dev, qual, 0x41);
682 return;
683 }
684
685 /*
686 * Leave short or middle distance condition, restore r17
687 * to the dynamic tuning range.
688 */
689 if (qual->vgc_level_reg >= 0x41) {
690 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
691 return;
692 }
693
694 dynamic_cca_tune:
695
696 /*
697 * R17 is inside the dynamic tuning range,
698 * start tuning the link based on the false cca counter.
699 */
700 if (qual->false_cca > 512 && qual->vgc_level_reg < 0x40) {
701 rt2500pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level_reg);
702 qual->vgc_level = qual->vgc_level_reg;
703 } else if (qual->false_cca < 100 && qual->vgc_level_reg > 0x32) {
704 rt2500pci_set_vgc(rt2x00dev, qual, --qual->vgc_level_reg);
705 qual->vgc_level = qual->vgc_level_reg;
706 }
707 }
708
709 /*
710 * Initialization functions.
711 */
712 static bool rt2500pci_get_entry_state(struct queue_entry *entry)
713 {
714 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
715 u32 word;
716
717 if (entry->queue->qid == QID_RX) {
718 rt2x00_desc_read(entry_priv->desc, 0, &word);
719
720 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
721 } else {
722 rt2x00_desc_read(entry_priv->desc, 0, &word);
723
724 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
725 rt2x00_get_field32(word, TXD_W0_VALID));
726 }
727 }
728
729 static void rt2500pci_clear_entry(struct queue_entry *entry)
730 {
731 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
732 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
733 u32 word;
734
735 if (entry->queue->qid == QID_RX) {
736 rt2x00_desc_read(entry_priv->desc, 1, &word);
737 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
738 rt2x00_desc_write(entry_priv->desc, 1, word);
739
740 rt2x00_desc_read(entry_priv->desc, 0, &word);
741 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
742 rt2x00_desc_write(entry_priv->desc, 0, word);
743 } else {
744 rt2x00_desc_read(entry_priv->desc, 0, &word);
745 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
746 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
747 rt2x00_desc_write(entry_priv->desc, 0, word);
748 }
749 }
750
751 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
752 {
753 struct queue_entry_priv_pci *entry_priv;
754 u32 reg;
755
756 /*
757 * Initialize registers.
758 */
759 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
760 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
761 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
762 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
763 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
764 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
765
766 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
767 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
768 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
769 entry_priv->desc_dma);
770 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
771
772 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
773 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
774 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
775 entry_priv->desc_dma);
776 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
777
778 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
779 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
780 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
781 entry_priv->desc_dma);
782 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
783
784 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
785 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
786 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
787 entry_priv->desc_dma);
788 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
789
790 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
791 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
792 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
793 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
794
795 entry_priv = rt2x00dev->rx->entries[0].priv_data;
796 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
797 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
798 entry_priv->desc_dma);
799 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
800
801 return 0;
802 }
803
804 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
805 {
806 u32 reg;
807
808 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
809 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
810 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
811 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
812
813 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
814 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
815 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
816 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
817 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
818
819 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
820 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
821 rt2x00dev->rx->data_size / 128);
822 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
823
824 /*
825 * Always use CWmin and CWmax set in descriptor.
826 */
827 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
828 rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
829 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
830
831 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
832 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
833 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
834 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
835 rt2x00_set_field32(&reg, CSR14_TCFP, 0);
836 rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
837 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
838 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
839 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
840 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
841
842 rt2x00pci_register_write(rt2x00dev, CNT3, 0);
843
844 rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
845 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
846 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
847 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
848 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
849 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
850 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
851 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
852 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
853 rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
854
855 rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
856 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
857 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
858 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
859 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
860 rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
861
862 rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
863 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
864 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
865 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
866 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
867 rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
868
869 rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
870 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
871 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
872 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
873 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
874 rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
875
876 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
877 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
878 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
879 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
880 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
881 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
882 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
883 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
884 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
885 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
886
887 rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
888 rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
889 rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
890 rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
891 rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
892 rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
893 rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
894 rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
895 rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
896
897 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
898
899 rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
900 rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
901
902 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
903 return -EBUSY;
904
905 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
906 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
907
908 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
909 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
910 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
911
912 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
913 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
914 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
915 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
916 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
917 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
918 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
919 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
920
921 rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
922
923 rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
924
925 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
926 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
927 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
928 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
929 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
930
931 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
932 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
933 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
934 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
935
936 /*
937 * We must clear the FCS and FIFO error count.
938 * These registers are cleared on read,
939 * so we may pass a useless variable to store the value.
940 */
941 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
942 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
943
944 return 0;
945 }
946
947 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
948 {
949 unsigned int i;
950 u8 value;
951
952 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
953 rt2500pci_bbp_read(rt2x00dev, 0, &value);
954 if ((value != 0xff) && (value != 0x00))
955 return 0;
956 udelay(REGISTER_BUSY_DELAY);
957 }
958
959 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
960 return -EACCES;
961 }
962
963 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
964 {
965 unsigned int i;
966 u16 eeprom;
967 u8 reg_id;
968 u8 value;
969
970 if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
971 return -EACCES;
972
973 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
974 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
975 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
976 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
977 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
978 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
979 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
980 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
981 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
982 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
983 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
984 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
985 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
986 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
987 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
988 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
989 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
990 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
991 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
992 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
993 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
994 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
995 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
996 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
997 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
998 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
999 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1000 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1001 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1002 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1003
1004 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1005 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1006
1007 if (eeprom != 0xffff && eeprom != 0x0000) {
1008 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1009 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1010 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1011 }
1012 }
1013
1014 return 0;
1015 }
1016
1017 /*
1018 * Device state switch handlers.
1019 */
1020 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1021 enum dev_state state)
1022 {
1023 u32 reg;
1024
1025 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1026 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1027 (state == STATE_RADIO_RX_OFF) ||
1028 (state == STATE_RADIO_RX_OFF_LINK));
1029 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1030 }
1031
1032 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1033 enum dev_state state)
1034 {
1035 int mask = (state == STATE_RADIO_IRQ_OFF);
1036 u32 reg;
1037
1038 /*
1039 * When interrupts are being enabled, the interrupt registers
1040 * should clear the register to assure a clean state.
1041 */
1042 if (state == STATE_RADIO_IRQ_ON) {
1043 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1044 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1045 }
1046
1047 /*
1048 * Only toggle the interrupts bits we are going to use.
1049 * Non-checked interrupt bits are disabled by default.
1050 */
1051 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1052 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1053 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1054 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1055 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1056 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1057 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1058 }
1059
1060 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1061 {
1062 /*
1063 * Initialize all registers.
1064 */
1065 if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1066 rt2500pci_init_registers(rt2x00dev) ||
1067 rt2500pci_init_bbp(rt2x00dev)))
1068 return -EIO;
1069
1070 return 0;
1071 }
1072
1073 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1074 {
1075 /*
1076 * Disable power
1077 */
1078 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1079 }
1080
1081 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1082 enum dev_state state)
1083 {
1084 u32 reg;
1085 unsigned int i;
1086 char put_to_sleep;
1087 char bbp_state;
1088 char rf_state;
1089
1090 put_to_sleep = (state != STATE_AWAKE);
1091
1092 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1093 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1094 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1095 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1096 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1097 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1098
1099 /*
1100 * Device is not guaranteed to be in the requested state yet.
1101 * We must wait until the register indicates that the
1102 * device has entered the correct state.
1103 */
1104 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1105 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1106 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1107 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1108 if (bbp_state == state && rf_state == state)
1109 return 0;
1110 msleep(10);
1111 }
1112
1113 return -EBUSY;
1114 }
1115
1116 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1117 enum dev_state state)
1118 {
1119 int retval = 0;
1120
1121 switch (state) {
1122 case STATE_RADIO_ON:
1123 retval = rt2500pci_enable_radio(rt2x00dev);
1124 break;
1125 case STATE_RADIO_OFF:
1126 rt2500pci_disable_radio(rt2x00dev);
1127 break;
1128 case STATE_RADIO_RX_ON:
1129 case STATE_RADIO_RX_ON_LINK:
1130 case STATE_RADIO_RX_OFF:
1131 case STATE_RADIO_RX_OFF_LINK:
1132 rt2500pci_toggle_rx(rt2x00dev, state);
1133 break;
1134 case STATE_RADIO_IRQ_ON:
1135 case STATE_RADIO_IRQ_OFF:
1136 rt2500pci_toggle_irq(rt2x00dev, state);
1137 break;
1138 case STATE_DEEP_SLEEP:
1139 case STATE_SLEEP:
1140 case STATE_STANDBY:
1141 case STATE_AWAKE:
1142 retval = rt2500pci_set_state(rt2x00dev, state);
1143 break;
1144 default:
1145 retval = -ENOTSUPP;
1146 break;
1147 }
1148
1149 if (unlikely(retval))
1150 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1151 state, retval);
1152
1153 return retval;
1154 }
1155
1156 /*
1157 * TX descriptor initialization
1158 */
1159 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1160 struct sk_buff *skb,
1161 struct txentry_desc *txdesc)
1162 {
1163 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1164 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1165 __le32 *txd = skbdesc->desc;
1166 u32 word;
1167
1168 /*
1169 * Start writing the descriptor words.
1170 */
1171 rt2x00_desc_read(entry_priv->desc, 1, &word);
1172 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1173 rt2x00_desc_write(entry_priv->desc, 1, word);
1174
1175 rt2x00_desc_read(txd, 2, &word);
1176 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1177 rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1178 rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1179 rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
1180 rt2x00_desc_write(txd, 2, word);
1181
1182 rt2x00_desc_read(txd, 3, &word);
1183 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1184 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1185 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1186 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
1187 rt2x00_desc_write(txd, 3, word);
1188
1189 rt2x00_desc_read(txd, 10, &word);
1190 rt2x00_set_field32(&word, TXD_W10_RTS,
1191 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1192 rt2x00_desc_write(txd, 10, word);
1193
1194 rt2x00_desc_read(txd, 0, &word);
1195 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1196 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1197 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1198 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1199 rt2x00_set_field32(&word, TXD_W0_ACK,
1200 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1201 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1202 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1203 rt2x00_set_field32(&word, TXD_W0_OFDM,
1204 (txdesc->rate_mode == RATE_MODE_OFDM));
1205 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1206 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1207 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1208 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1209 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1210 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1211 rt2x00_desc_write(txd, 0, word);
1212 }
1213
1214 /*
1215 * TX data initialization
1216 */
1217 static void rt2500pci_write_beacon(struct queue_entry *entry)
1218 {
1219 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1220 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1221 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1222 u32 word;
1223 u32 reg;
1224
1225 /*
1226 * Disable beaconing while we are reloading the beacon data,
1227 * otherwise we might be sending out invalid data.
1228 */
1229 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1230 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1231 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1232 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1233 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1234
1235 /*
1236 * Replace rt2x00lib allocated descriptor with the
1237 * pointer to the _real_ hardware descriptor.
1238 * After that, map the beacon to DMA and update the
1239 * descriptor.
1240 */
1241 memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1242 skbdesc->desc = entry_priv->desc;
1243
1244 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1245
1246 rt2x00_desc_read(entry_priv->desc, 1, &word);
1247 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1248 rt2x00_desc_write(entry_priv->desc, 1, word);
1249 }
1250
1251 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1252 const enum data_queue_qid queue)
1253 {
1254 u32 reg;
1255
1256 if (queue == QID_BEACON) {
1257 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1258 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1259 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1260 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1261 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1262 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1263 }
1264 return;
1265 }
1266
1267 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1268 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1269 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1270 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1271 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1272 }
1273
1274 static void rt2500pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1275 const enum data_queue_qid qid)
1276 {
1277 u32 reg;
1278
1279 if (qid == QID_BEACON) {
1280 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1281 } else {
1282 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1283 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1284 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1285 }
1286 }
1287
1288 /*
1289 * RX control handlers
1290 */
1291 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1292 struct rxdone_entry_desc *rxdesc)
1293 {
1294 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1295 u32 word0;
1296 u32 word2;
1297
1298 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1299 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1300
1301 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1302 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1303 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1304 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1305
1306 /*
1307 * Obtain the status about this packet.
1308 * When frame was received with an OFDM bitrate,
1309 * the signal is the PLCP value. If it was received with
1310 * a CCK bitrate the signal is the rate in 100kbit/s.
1311 */
1312 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1313 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1314 entry->queue->rt2x00dev->rssi_offset;
1315 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1316
1317 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1318 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1319 else
1320 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1321 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1322 rxdesc->dev_flags |= RXDONE_MY_BSS;
1323 }
1324
1325 /*
1326 * Interrupt functions.
1327 */
1328 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1329 const enum data_queue_qid queue_idx)
1330 {
1331 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1332 struct queue_entry_priv_pci *entry_priv;
1333 struct queue_entry *entry;
1334 struct txdone_entry_desc txdesc;
1335 u32 word;
1336
1337 while (!rt2x00queue_empty(queue)) {
1338 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1339 entry_priv = entry->priv_data;
1340 rt2x00_desc_read(entry_priv->desc, 0, &word);
1341
1342 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1343 !rt2x00_get_field32(word, TXD_W0_VALID))
1344 break;
1345
1346 /*
1347 * Obtain the status about this packet.
1348 */
1349 txdesc.flags = 0;
1350 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1351 case 0: /* Success */
1352 case 1: /* Success with retry */
1353 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1354 break;
1355 case 2: /* Failure, excessive retries */
1356 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1357 /* Don't break, this is a failed frame! */
1358 default: /* Failure */
1359 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1360 }
1361 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1362
1363 rt2x00lib_txdone(entry, &txdesc);
1364 }
1365 }
1366
1367 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1368 {
1369 struct rt2x00_dev *rt2x00dev = dev_instance;
1370 u32 reg;
1371
1372 /*
1373 * Get the interrupt sources & saved to local variable.
1374 * Write register value back to clear pending interrupts.
1375 */
1376 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1377 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1378
1379 if (!reg)
1380 return IRQ_NONE;
1381
1382 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1383 return IRQ_HANDLED;
1384
1385 /*
1386 * Handle interrupts, walk through all bits
1387 * and run the tasks, the bits are checked in order of
1388 * priority.
1389 */
1390
1391 /*
1392 * 1 - Beacon timer expired interrupt.
1393 */
1394 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1395 rt2x00lib_beacondone(rt2x00dev);
1396
1397 /*
1398 * 2 - Rx ring done interrupt.
1399 */
1400 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1401 rt2x00pci_rxdone(rt2x00dev);
1402
1403 /*
1404 * 3 - Atim ring transmit done interrupt.
1405 */
1406 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1407 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1408
1409 /*
1410 * 4 - Priority ring transmit done interrupt.
1411 */
1412 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1413 rt2500pci_txdone(rt2x00dev, QID_AC_BE);
1414
1415 /*
1416 * 5 - Tx ring transmit done interrupt.
1417 */
1418 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1419 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
1420
1421 return IRQ_HANDLED;
1422 }
1423
1424 /*
1425 * Device probe functions.
1426 */
1427 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1428 {
1429 struct eeprom_93cx6 eeprom;
1430 u32 reg;
1431 u16 word;
1432 u8 *mac;
1433
1434 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1435
1436 eeprom.data = rt2x00dev;
1437 eeprom.register_read = rt2500pci_eepromregister_read;
1438 eeprom.register_write = rt2500pci_eepromregister_write;
1439 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1440 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1441 eeprom.reg_data_in = 0;
1442 eeprom.reg_data_out = 0;
1443 eeprom.reg_data_clock = 0;
1444 eeprom.reg_chip_select = 0;
1445
1446 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1447 EEPROM_SIZE / sizeof(u16));
1448
1449 /*
1450 * Start validation of the data that has been read.
1451 */
1452 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1453 if (!is_valid_ether_addr(mac)) {
1454 random_ether_addr(mac);
1455 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1456 }
1457
1458 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1459 if (word == 0xffff) {
1460 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1461 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1462 ANTENNA_SW_DIVERSITY);
1463 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1464 ANTENNA_SW_DIVERSITY);
1465 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1466 LED_MODE_DEFAULT);
1467 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1468 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1469 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1470 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1471 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1472 }
1473
1474 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1475 if (word == 0xffff) {
1476 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1477 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1478 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1479 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1480 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1481 }
1482
1483 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1484 if (word == 0xffff) {
1485 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1486 DEFAULT_RSSI_OFFSET);
1487 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1488 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1489 }
1490
1491 return 0;
1492 }
1493
1494 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1495 {
1496 u32 reg;
1497 u16 value;
1498 u16 eeprom;
1499
1500 /*
1501 * Read EEPROM word for configuration.
1502 */
1503 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1504
1505 /*
1506 * Identify RF chipset.
1507 */
1508 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1509 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1510 rt2x00_set_chip_rf(rt2x00dev, value, reg);
1511
1512 if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1513 !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1514 !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1515 !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1516 !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1517 !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1518 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1519 return -ENODEV;
1520 }
1521
1522 /*
1523 * Identify default antenna configuration.
1524 */
1525 rt2x00dev->default_ant.tx =
1526 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1527 rt2x00dev->default_ant.rx =
1528 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1529
1530 /*
1531 * Store led mode, for correct led behaviour.
1532 */
1533 #ifdef CONFIG_RT2X00_LIB_LEDS
1534 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1535
1536 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1537 if (value == LED_MODE_TXRX_ACTIVITY ||
1538 value == LED_MODE_DEFAULT ||
1539 value == LED_MODE_ASUS)
1540 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1541 LED_TYPE_ACTIVITY);
1542 #endif /* CONFIG_RT2X00_LIB_LEDS */
1543
1544 /*
1545 * Detect if this device has an hardware controlled radio.
1546 */
1547 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1548 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1549
1550 /*
1551 * Check if the BBP tuning should be enabled.
1552 */
1553 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1554
1555 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1556 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1557
1558 /*
1559 * Read the RSSI <-> dBm offset information.
1560 */
1561 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1562 rt2x00dev->rssi_offset =
1563 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1564
1565 return 0;
1566 }
1567
1568 /*
1569 * RF value list for RF2522
1570 * Supports: 2.4 GHz
1571 */
1572 static const struct rf_channel rf_vals_bg_2522[] = {
1573 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1574 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1575 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1576 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1577 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1578 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1579 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1580 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1581 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1582 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1583 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1584 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1585 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1586 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1587 };
1588
1589 /*
1590 * RF value list for RF2523
1591 * Supports: 2.4 GHz
1592 */
1593 static const struct rf_channel rf_vals_bg_2523[] = {
1594 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1595 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1596 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1597 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1598 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1599 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1600 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1601 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1602 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1603 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1604 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1605 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1606 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1607 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1608 };
1609
1610 /*
1611 * RF value list for RF2524
1612 * Supports: 2.4 GHz
1613 */
1614 static const struct rf_channel rf_vals_bg_2524[] = {
1615 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1616 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1617 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1618 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1619 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1620 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1621 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1622 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1623 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1624 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1625 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1626 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1627 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1628 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1629 };
1630
1631 /*
1632 * RF value list for RF2525
1633 * Supports: 2.4 GHz
1634 */
1635 static const struct rf_channel rf_vals_bg_2525[] = {
1636 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1637 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1638 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1639 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1640 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1641 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1642 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1643 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1644 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1645 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1646 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1647 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1648 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1649 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1650 };
1651
1652 /*
1653 * RF value list for RF2525e
1654 * Supports: 2.4 GHz
1655 */
1656 static const struct rf_channel rf_vals_bg_2525e[] = {
1657 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1658 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1659 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1660 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1661 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1662 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1663 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1664 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1665 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1666 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1667 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1668 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1669 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1670 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1671 };
1672
1673 /*
1674 * RF value list for RF5222
1675 * Supports: 2.4 GHz & 5.2 GHz
1676 */
1677 static const struct rf_channel rf_vals_5222[] = {
1678 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1679 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1680 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1681 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1682 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1683 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1684 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1685 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1686 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1687 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1688 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1689 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1690 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1691 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1692
1693 /* 802.11 UNI / HyperLan 2 */
1694 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1695 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1696 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1697 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1698 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1699 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1700 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1701 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1702
1703 /* 802.11 HyperLan 2 */
1704 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1705 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1706 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1707 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1708 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1709 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1710 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1711 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1712 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1713 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1714
1715 /* 802.11 UNII */
1716 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1717 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1718 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1719 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1720 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1721 };
1722
1723 static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1724 {
1725 struct hw_mode_spec *spec = &rt2x00dev->spec;
1726 struct channel_info *info;
1727 char *tx_power;
1728 unsigned int i;
1729
1730 /*
1731 * Initialize all hw fields.
1732 */
1733 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1734 IEEE80211_HW_SIGNAL_DBM |
1735 IEEE80211_HW_SUPPORTS_PS |
1736 IEEE80211_HW_PS_NULLFUNC_STACK;
1737
1738 rt2x00dev->hw->extra_tx_headroom = 0;
1739
1740 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1741 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1742 rt2x00_eeprom_addr(rt2x00dev,
1743 EEPROM_MAC_ADDR_0));
1744
1745 /*
1746 * Initialize hw_mode information.
1747 */
1748 spec->supported_bands = SUPPORT_BAND_2GHZ;
1749 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1750
1751 if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1752 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1753 spec->channels = rf_vals_bg_2522;
1754 } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1755 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1756 spec->channels = rf_vals_bg_2523;
1757 } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1758 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1759 spec->channels = rf_vals_bg_2524;
1760 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1761 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1762 spec->channels = rf_vals_bg_2525;
1763 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1764 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1765 spec->channels = rf_vals_bg_2525e;
1766 } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1767 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1768 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1769 spec->channels = rf_vals_5222;
1770 }
1771
1772 /*
1773 * Create channel information array
1774 */
1775 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1776 if (!info)
1777 return -ENOMEM;
1778
1779 spec->channels_info = info;
1780
1781 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1782 for (i = 0; i < 14; i++)
1783 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1784
1785 if (spec->num_channels > 14) {
1786 for (i = 14; i < spec->num_channels; i++)
1787 info[i].tx_power1 = DEFAULT_TXPOWER;
1788 }
1789
1790 return 0;
1791 }
1792
1793 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1794 {
1795 int retval;
1796
1797 /*
1798 * Allocate eeprom data.
1799 */
1800 retval = rt2500pci_validate_eeprom(rt2x00dev);
1801 if (retval)
1802 return retval;
1803
1804 retval = rt2500pci_init_eeprom(rt2x00dev);
1805 if (retval)
1806 return retval;
1807
1808 /*
1809 * Initialize hw specifications.
1810 */
1811 retval = rt2500pci_probe_hw_mode(rt2x00dev);
1812 if (retval)
1813 return retval;
1814
1815 /*
1816 * This device requires the atim queue and DMA-mapped skbs.
1817 */
1818 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1819 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1820
1821 /*
1822 * Set the rssi offset.
1823 */
1824 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1825
1826 return 0;
1827 }
1828
1829 /*
1830 * IEEE80211 stack callback functions.
1831 */
1832 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1833 {
1834 struct rt2x00_dev *rt2x00dev = hw->priv;
1835 u64 tsf;
1836 u32 reg;
1837
1838 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1839 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1840 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1841 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1842
1843 return tsf;
1844 }
1845
1846 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1847 {
1848 struct rt2x00_dev *rt2x00dev = hw->priv;
1849 u32 reg;
1850
1851 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1852 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1853 }
1854
1855 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1856 .tx = rt2x00mac_tx,
1857 .start = rt2x00mac_start,
1858 .stop = rt2x00mac_stop,
1859 .add_interface = rt2x00mac_add_interface,
1860 .remove_interface = rt2x00mac_remove_interface,
1861 .config = rt2x00mac_config,
1862 .configure_filter = rt2x00mac_configure_filter,
1863 .get_stats = rt2x00mac_get_stats,
1864 .bss_info_changed = rt2x00mac_bss_info_changed,
1865 .conf_tx = rt2x00mac_conf_tx,
1866 .get_tx_stats = rt2x00mac_get_tx_stats,
1867 .get_tsf = rt2500pci_get_tsf,
1868 .tx_last_beacon = rt2500pci_tx_last_beacon,
1869 .rfkill_poll = rt2x00mac_rfkill_poll,
1870 };
1871
1872 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1873 .irq_handler = rt2500pci_interrupt,
1874 .probe_hw = rt2500pci_probe_hw,
1875 .initialize = rt2x00pci_initialize,
1876 .uninitialize = rt2x00pci_uninitialize,
1877 .get_entry_state = rt2500pci_get_entry_state,
1878 .clear_entry = rt2500pci_clear_entry,
1879 .set_device_state = rt2500pci_set_device_state,
1880 .rfkill_poll = rt2500pci_rfkill_poll,
1881 .link_stats = rt2500pci_link_stats,
1882 .reset_tuner = rt2500pci_reset_tuner,
1883 .link_tuner = rt2500pci_link_tuner,
1884 .write_tx_desc = rt2500pci_write_tx_desc,
1885 .write_tx_data = rt2x00pci_write_tx_data,
1886 .write_beacon = rt2500pci_write_beacon,
1887 .kick_tx_queue = rt2500pci_kick_tx_queue,
1888 .kill_tx_queue = rt2500pci_kill_tx_queue,
1889 .fill_rxdone = rt2500pci_fill_rxdone,
1890 .config_filter = rt2500pci_config_filter,
1891 .config_intf = rt2500pci_config_intf,
1892 .config_erp = rt2500pci_config_erp,
1893 .config_ant = rt2500pci_config_ant,
1894 .config = rt2500pci_config,
1895 };
1896
1897 static const struct data_queue_desc rt2500pci_queue_rx = {
1898 .entry_num = RX_ENTRIES,
1899 .data_size = DATA_FRAME_SIZE,
1900 .desc_size = RXD_DESC_SIZE,
1901 .priv_size = sizeof(struct queue_entry_priv_pci),
1902 };
1903
1904 static const struct data_queue_desc rt2500pci_queue_tx = {
1905 .entry_num = TX_ENTRIES,
1906 .data_size = DATA_FRAME_SIZE,
1907 .desc_size = TXD_DESC_SIZE,
1908 .priv_size = sizeof(struct queue_entry_priv_pci),
1909 };
1910
1911 static const struct data_queue_desc rt2500pci_queue_bcn = {
1912 .entry_num = BEACON_ENTRIES,
1913 .data_size = MGMT_FRAME_SIZE,
1914 .desc_size = TXD_DESC_SIZE,
1915 .priv_size = sizeof(struct queue_entry_priv_pci),
1916 };
1917
1918 static const struct data_queue_desc rt2500pci_queue_atim = {
1919 .entry_num = ATIM_ENTRIES,
1920 .data_size = DATA_FRAME_SIZE,
1921 .desc_size = TXD_DESC_SIZE,
1922 .priv_size = sizeof(struct queue_entry_priv_pci),
1923 };
1924
1925 static const struct rt2x00_ops rt2500pci_ops = {
1926 .name = KBUILD_MODNAME,
1927 .max_sta_intf = 1,
1928 .max_ap_intf = 1,
1929 .eeprom_size = EEPROM_SIZE,
1930 .rf_size = RF_SIZE,
1931 .tx_queues = NUM_TX_QUEUES,
1932 .rx = &rt2500pci_queue_rx,
1933 .tx = &rt2500pci_queue_tx,
1934 .bcn = &rt2500pci_queue_bcn,
1935 .atim = &rt2500pci_queue_atim,
1936 .lib = &rt2500pci_rt2x00_ops,
1937 .hw = &rt2500pci_mac80211_ops,
1938 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1939 .debugfs = &rt2500pci_rt2x00debug,
1940 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1941 };
1942
1943 /*
1944 * RT2500pci module information.
1945 */
1946 static struct pci_device_id rt2500pci_device_table[] = {
1947 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1948 { 0, }
1949 };
1950
1951 MODULE_AUTHOR(DRV_PROJECT);
1952 MODULE_VERSION(DRV_VERSION);
1953 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1954 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1955 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1956 MODULE_LICENSE("GPL");
1957
1958 static struct pci_driver rt2500pci_driver = {
1959 .name = KBUILD_MODNAME,
1960 .id_table = rt2500pci_device_table,
1961 .probe = rt2x00pci_probe,
1962 .remove = __devexit_p(rt2x00pci_remove),
1963 .suspend = rt2x00pci_suspend,
1964 .resume = rt2x00pci_resume,
1965 };
1966
1967 static int __init rt2500pci_init(void)
1968 {
1969 return pci_register_driver(&rt2500pci_driver);
1970 }
1971
1972 static void __exit rt2500pci_exit(void)
1973 {
1974 pci_unregister_driver(&rt2500pci_driver);
1975 }
1976
1977 module_init(rt2500pci_init);
1978 module_exit(rt2500pci_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree