drivers/pcmcia/m32r_cfc.c

   1 /*
   2  *  drivers/pcmcia/m32r_cfc.c
   3  *
   4  *  Device driver for the CFC functionality of M32R.
   5  *
   6  *  Copyright (c) 2001, 2002, 2003, 2004
   7  *    Hiroyuki Kondo, Naoto Sugai, Hayato Fujiwara
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/moduleparam.h>
  12 #include <linux/init.h>
  13 #include <linux/config.h>
  14 #include <linux/types.h>
  15 #include <linux/fcntl.h>
  16 #include <linux/string.h>
  17 #include <linux/kernel.h>
  18 #include <linux/errno.h>
  19 #include <linux/timer.h>
  20 #include <linux/sched.h>
  21 #include <linux/slab.h>
  22 #include <linux/ioport.h>
  23 #include <linux/delay.h>
  24 #include <linux/workqueue.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/bitops.h>
  28 #include <asm/irq.h>
  29 #include <asm/io.h>
  30 #include <asm/system.h>
  31
  32 #include <pcmcia/cs_types.h>
  33 #include <pcmcia/ss.h>
  34 #include <pcmcia/cs.h>
  35
  36 #undef MAX_IO_WIN       /* FIXME */
  37 #define MAX_IO_WIN 1
  38 #undef MAX_WIN          /* FIXME */
  39 #define MAX_WIN 1
  40
  41 #include "m32r_cfc.h"
  42
  43 #ifdef DEBUG
  44 static int m32r_cfc_debug;
  45 module_param(m32r_cfc_debug, int, 0644);
  46 #define debug(lvl, fmt, arg...) do {                            \
  47         if (m32r_cfc_debug > (lvl))                             \
  48                 printk(KERN_DEBUG "m32r_cfc: " fmt , ## arg);   \
  49 } while (0)
  50 #else
  51 #define debug(n, args...) do { } while (0)
  52 #endif
  53
  54 /* Poll status interval -- 0 means default to interrupt */
  55 static int poll_interval = 0;
  56
  57 typedef enum pcc_space { as_none = 0, as_comm, as_attr, as_io } pcc_as_t;
  58
  59 typedef struct pcc_socket {
  60         u_short                 type, flags;
  61         struct pcmcia_socket    socket;
  62         unsigned int            number;
  63         kio_addr_t              ioaddr;
  64         u_long                  mapaddr;
  65         u_long                  base;   /* PCC register base */
  66         u_char                  cs_irq1, cs_irq2, intr;
  67         pccard_io_map           io_map[MAX_IO_WIN];
  68         pccard_mem_map          mem_map[MAX_WIN];
  69         u_char                  io_win;
  70         u_char                  mem_win;
  71         pcc_as_t                current_space;
  72         u_char                  last_iodbex;
  73 #ifdef CONFIG_PROC_FS
  74         struct proc_dir_entry *proc;
  75 #endif
  76 } pcc_socket_t;
  77
  78 static int pcc_sockets = 0;
  79 static pcc_socket_t socket[M32R_MAX_PCC] = {
  80         { 0, }, /* ... */
  81 };
  82
  83 /*====================================================================*/
  84
  85 static unsigned int pcc_get(u_short, unsigned int);
  86 static void pcc_set(u_short, unsigned int , unsigned int );
  87
  88 static DEFINE_SPINLOCK(pcc_lock);
  89
  90 #if !defined(CONFIG_PLAT_USRV)
  91 static inline u_long pcc_port2addr(unsigned long port, int size) {
  92         u_long addr = 0;
  93         u_long odd;
  94
  95         if (size == 1) {        /* byte access */
  96                 odd = (port&1) << 11;
  97                 port -= port & 1;
  98                 addr = CFC_IO_MAPBASE_BYTE - CFC_IOPORT_BASE + odd + port;
  99         } else if (size == 2)
 100                 addr = CFC_IO_MAPBASE_WORD - CFC_IOPORT_BASE + port;
 101
 102         return addr;
 103 }
 104 #else   /* CONFIG_PLAT_USRV */
 105 static inline u_long pcc_port2addr(unsigned long port, int size) {
 106         u_long odd;
 107         u_long addr = ((port - CFC_IOPORT_BASE) & 0xf000) << 8;
 108
 109         if (size == 1) {        /* byte access */
 110                 odd = port & 1;
 111                 port -= odd;
 112                 odd <<= 11;
 113                 addr = (addr | CFC_IO_MAPBASE_BYTE) + odd + (port & 0xfff);
 114         } else if (size == 2)   /* word access */
 115                 addr = (addr | CFC_IO_MAPBASE_WORD) + (port & 0xfff);
 116
 117         return addr;
 118 }
 119 #endif  /* CONFIG_PLAT_USRV */
 120
 121 void pcc_ioread_byte(int sock, unsigned long port, void *buf, size_t size,
 122         size_t nmemb, int flag)
 123 {
 124         u_long addr;
 125         unsigned char *bp = (unsigned char *)buf;
 126         unsigned long flags;
 127
 128         debug(3, "m32r_cfc: pcc_ioread_byte: sock=%d, port=%#lx, buf=%p, "
 129                  "size=%u, nmemb=%d, flag=%d\n",
 130                   sock, port, buf, size, nmemb, flag);
 131
 132         addr = pcc_port2addr(port, 1);
 133         if (!addr) {
 134                 printk("m32r_cfc:ioread_byte null port :%#lx\n",port);
 135                 return;
 136         }
 137         debug(3, "m32r_cfc: pcc_ioread_byte: addr=%#lx\n", addr);
 138
 139         spin_lock_irqsave(&pcc_lock, flags);
 140         /* read Byte */
 141         while (nmemb--)
 142                 *bp++ = readb(addr);
 143         spin_unlock_irqrestore(&pcc_lock, flags);
 144 }
 145
 146 void pcc_ioread_word(int sock, unsigned long port, void *buf, size_t size,
 147         size_t nmemb, int flag)
 148 {
 149         u_long addr;
 150         unsigned short *bp = (unsigned short *)buf;
 151         unsigned long flags;
 152
 153         debug(3, "m32r_cfc: pcc_ioread_word: sock=%d, port=%#lx, "
 154                  "buf=%p, size=%u, nmemb=%d, flag=%d\n",
 155                  sock, port, buf, size, nmemb, flag);
 156
 157         if (size != 2)
 158                 printk("m32r_cfc: ioread_word :illigal size %u : %#lx\n", size,
 159                         port);
 160         if (size == 9)
 161                 printk("m32r_cfc: ioread_word :insw \n");
 162
 163         addr = pcc_port2addr(port, 2);
 164         if (!addr) {
 165                 printk("m32r_cfc:ioread_word null port :%#lx\n",port);
 166                 return;
 167         }
 168         debug(3, "m32r_cfc: pcc_ioread_word: addr=%#lx\n", addr);
 169
 170         spin_lock_irqsave(&pcc_lock, flags);
 171         /* read Word */
 172         while (nmemb--)
 173                 *bp++ = readw(addr);
 174         spin_unlock_irqrestore(&pcc_lock, flags);
 175 }
 176
 177 void pcc_iowrite_byte(int sock, unsigned long port, void *buf, size_t size,
 178         size_t nmemb, int flag)
 179 {
 180         u_long addr;
 181         unsigned char *bp = (unsigned char *)buf;
 182         unsigned long flags;
 183
 184         debug(3, "m32r_cfc: pcc_iowrite_byte: sock=%d, port=%#lx, "
 185                  "buf=%p, size=%u, nmemb=%d, flag=%d\n",
 186                  sock, port, buf, size, nmemb, flag);
 187
 188         /* write Byte */
 189         addr = pcc_port2addr(port, 1);
 190         if (!addr) {
 191                 printk("m32r_cfc:iowrite_byte null port:%#lx\n",port);
 192                 return;
 193         }
 194         debug(3, "m32r_cfc: pcc_iowrite_byte: addr=%#lx\n", addr);
 195
 196         spin_lock_irqsave(&pcc_lock, flags);
 197         while (nmemb--)
 198                 writeb(*bp++, addr);
 199         spin_unlock_irqrestore(&pcc_lock, flags);
 200 }
 201
 202 void pcc_iowrite_word(int sock, unsigned long port, void *buf, size_t size,
 203         size_t nmemb, int flag)
 204 {
 205         u_long addr;
 206         unsigned short *bp = (unsigned short *)buf;
 207         unsigned long flags;
 208
 209         debug(3, "m32r_cfc: pcc_iowrite_word: sock=%d, port=%#lx, "
 210                  "buf=%p, size=%u, nmemb=%d, flag=%d\n",
 211                  sock, port, buf, size, nmemb, flag);
 212
 213         if(size != 2)
 214                 printk("m32r_cfc: iowrite_word :illigal size %u : %#lx\n",
 215                         size, port);
 216         if(size == 9)
 217                 printk("m32r_cfc: iowrite_word :outsw \n");
 218
 219         addr = pcc_port2addr(port, 2);
 220         if (!addr) {
 221                 printk("m32r_cfc:iowrite_word null addr :%#lx\n",port);
 222                 return;
 223         }
 224 #if 1
 225         if (addr & 1) {
 226                 printk("m32r_cfc:iowrite_word port addr (%#lx):%#lx\n", port,
 227                         addr);
 228                 return;
 229         }
 230 #endif
 231         debug(3, "m32r_cfc: pcc_iowrite_word: addr=%#lx\n", addr);
 232
 233         spin_lock_irqsave(&pcc_lock, flags);
 234         while (nmemb--)
 235                 writew(*bp++, addr);
 236         spin_unlock_irqrestore(&pcc_lock, flags);
 237 }
 238
 239 /*====================================================================*/
 240
 241 #define IS_REGISTERED           0x2000
 242 #define IS_ALIVE                0x8000
 243
 244 typedef struct pcc_t {
 245         char                    *name;
 246         u_short                 flags;
 247 } pcc_t;
 248
 249 static pcc_t pcc[] = {
 250 #if !defined(CONFIG_PLAT_USRV)
 251         { "m32r_cfc", 0 }, { "", 0 },
 252 #else   /* CONFIG_PLAT_USRV */
 253         { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, { "m32r_cfc", 0 },
 254         { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, { "", 0 },
 255 #endif  /* CONFIG_PLAT_USRV */
 256 };
 257
 258 static irqreturn_t pcc_interrupt(int, void *, struct pt_regs *);
 259
 260 /*====================================================================*/
 261
 262 static struct timer_list poll_timer;
 263
 264 static unsigned int pcc_get(u_short sock, unsigned int reg)
 265 {
 266         unsigned int val = inw(reg);
 267         debug(3, "m32r_cfc: pcc_get: reg(0x%08x)=0x%04x\n", reg, val);
 268         return val;
 269 }
 270
 271
 272 static void pcc_set(u_short sock, unsigned int reg, unsigned int data)
 273 {
 274         outw(data, reg);
 275         debug(3, "m32r_cfc: pcc_set: reg(0x%08x)=0x%04x\n", reg, data);
 276 }
 277
 278 /*======================================================================
 279
 280         See if a card is present, powered up, in IO mode, and already
 281         bound to a (non PC Card) Linux driver.  We leave these alone.
 282
 283         We make an exception for cards that seem to be serial devices.
 284
 285 ======================================================================*/
 286
 287 static int __init is_alive(u_short sock)
 288 {
 289         unsigned int stat;
 290
 291         debug(3, "m32r_cfc: is_alive:\n");
 292
 293         printk("CF: ");
 294         stat = pcc_get(sock, (unsigned int)PLD_CFSTS);
 295         if (!stat)
 296                 printk("No ");
 297         printk("Card is detected at socket %d : stat = 0x%08x\n", sock, stat);
 298         debug(3, "m32r_cfc: is_alive: sock stat is 0x%04x\n", stat);
 299
 300         return 0;
 301 }
 302
 303 static void add_pcc_socket(ulong base, int irq, ulong mapaddr, kio_addr_t ioaddr)
 304 {
 305         pcc_socket_t *t = &socket[pcc_sockets];
 306
 307         debug(3, "m32r_cfc: add_pcc_socket: base=%#lx, irq=%d, "
 308                  "mapaddr=%#lx, ioaddr=%08x\n",
 309                  base, irq, mapaddr, ioaddr);
 310
 311         /* add sockets */
 312         t->ioaddr = ioaddr;
 313         t->mapaddr = mapaddr;
 314 #if !defined(CONFIG_PLAT_USRV)
 315         t->base = 0;
 316         t->flags = 0;
 317         t->cs_irq1 = irq;               // insert irq
 318         t->cs_irq2 = irq + 1;           // eject irq
 319 #else   /* CONFIG_PLAT_USRV */
 320         t->base = base;
 321         t->flags = 0;
 322         t->cs_irq1 = 0;                 // insert irq
 323         t->cs_irq2 = 0;                 // eject irq
 324 #endif  /* CONFIG_PLAT_USRV */
 325
 326         if (is_alive(pcc_sockets))
 327                 t->flags |= IS_ALIVE;
 328
 329         /* add pcc */
 330 #if !defined(CONFIG_PLAT_USRV)
 331         request_region((unsigned int)PLD_CFRSTCR, 0x20, "m32r_cfc");
 332 #else   /* CONFIG_PLAT_USRV */
 333         {
 334                 unsigned int reg_base;
 335
 336                 reg_base = (unsigned int)PLD_CFRSTCR;
 337                 reg_base |= pcc_sockets << 8;
 338                 request_region(reg_base, 0x20, "m32r_cfc");
 339         }
 340 #endif  /* CONFIG_PLAT_USRV */
 341         printk(KERN_INFO "  %s ", pcc[pcc_sockets].name);
 342         printk("pcc at 0x%08lx\n", t->base);
 343
 344         /* Update socket interrupt information, capabilities */
 345         t->socket.features |= (SS_CAP_PCCARD | SS_CAP_STATIC_MAP);
 346         t->socket.map_size = M32R_PCC_MAPSIZE;
 347         t->socket.io_offset = ioaddr;   /* use for io access offset */
 348         t->socket.irq_mask = 0;
 349 #if !defined(CONFIG_PLAT_USRV)
 350         t->socket.pci_irq = PLD_IRQ_CFIREQ ;    /* card interrupt */
 351 #else   /* CONFIG_PLAT_USRV */
 352         t->socket.pci_irq = PLD_IRQ_CF0 + pcc_sockets;
 353 #endif  /* CONFIG_PLAT_USRV */
 354
 355 #ifndef CONFIG_PLAT_USRV
 356         /* insert interrupt */
 357         request_irq(irq, pcc_interrupt, 0, "m32r_cfc", pcc_interrupt);
 358 #ifndef CONFIG_PLAT_MAPPI3
 359         /* eject interrupt */
 360         request_irq(irq+1, pcc_interrupt, 0, "m32r_cfc", pcc_interrupt);
 361 #endif
 362         debug(3, "m32r_cfc: enable CFMSK, RDYSEL\n");
 363         pcc_set(pcc_sockets, (unsigned int)PLD_CFIMASK, 0x01);
 364 #endif  /* CONFIG_PLAT_USRV */
 365 #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT)
 366         pcc_set(pcc_sockets, (unsigned int)PLD_CFCR1, 0x0200);
 367 #endif
 368         pcc_sockets++;
 369
 370         return;
 371 }
 372
 373
 374 /*====================================================================*/
 375
 376 static irqreturn_t pcc_interrupt(int irq, void *dev, struct pt_regs *regs)
 377 {
 378         int i;
 379         u_int events = 0;
 380         int handled = 0;
 381
 382         debug(3, "m32r_cfc: pcc_interrupt: irq=%d, dev=%p, regs=%p\n",
 383                 irq, dev, regs);
 384         for (i = 0; i < pcc_sockets; i++) {
 385                 if (socket[i].cs_irq1 != irq && socket[i].cs_irq2 != irq)
 386                         continue;
 387
 388                 handled = 1;
 389                 debug(3, "m32r_cfc: pcc_interrupt: socket %d irq 0x%02x ",
 390                         i, irq);
 391                 events |= SS_DETECT;    /* insert or eject */
 392                 if (events)
 393                         pcmcia_parse_events(&socket[i].socket, events);
 394         }
 395         debug(3, "m32r_cfc: pcc_interrupt: done\n");
 396
 397         return IRQ_RETVAL(handled);
 398 } /* pcc_interrupt */
 399
 400 static void pcc_interrupt_wrapper(u_long data)
 401 {
 402         debug(3, "m32r_cfc: pcc_interrupt_wrapper:\n");
 403         pcc_interrupt(0, NULL, NULL);
 404         init_timer(&poll_timer);
 405         poll_timer.expires = jiffies + poll_interval;
 406         add_timer(&poll_timer);
 407 }
 408
 409 /*====================================================================*/
 410
 411 static int _pcc_get_status(u_short sock, u_int *value)
 412 {
 413         u_int status;
 414
 415         debug(3, "m32r_cfc: _pcc_get_status:\n");
 416         status = pcc_get(sock, (unsigned int)PLD_CFSTS);
 417         *value = (status) ? SS_DETECT : 0;
 418         debug(3, "m32r_cfc: _pcc_get_status: status=0x%08x\n", status);
 419
 420 #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT)
 421         if ( status ) {
 422                 /* enable CF power */
 423                 status = inw((unsigned int)PLD_CPCR);
 424                 if (!(status & PLD_CPCR_CF)) {
 425                         debug(3, "m32r_cfc: _pcc_get_status: "
 426                                  "power on (CPCR=0x%08x)\n", status);
 427                         status |= PLD_CPCR_CF;
 428                         outw(status, (unsigned int)PLD_CPCR);
 429                         udelay(100);
 430                 }
 431                 *value |= SS_POWERON;
 432
 433                 pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);/* enable buffer */
 434                 udelay(100);
 435
 436                 *value |= SS_READY;             /* always ready */
 437                 *value |= SS_3VCARD;
 438         } else {
 439                 /* disable CF power */
 440                 status = inw((unsigned int)PLD_CPCR);
 441                 status &= ~PLD_CPCR_CF;
 442                 outw(status, (unsigned int)PLD_CPCR);
 443                 udelay(100);
 444                 debug(3, "m32r_cfc: _pcc_get_status: "
 445                          "power off (CPCR=0x%08x)\n", status);
 446         }
 447 #elif defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
 448         if ( status ) {
 449                 status = pcc_get(sock, (unsigned int)PLD_CPCR);
 450                 if (status == 0) { /* power off */
 451                         pcc_set(sock, (unsigned int)PLD_CPCR, 1);
 452                         pcc_set(sock, (unsigned int)PLD_CFBUFCR,0); /* force buffer off for ZA-36 */
 453                         udelay(50);
 454                 }
 455                 *value |= SS_POWERON;
 456
 457                 pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);
 458                 udelay(50);
 459                 pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0101);
 460                 udelay(25); /* for IDE reset */
 461                 pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0100);
 462                 mdelay(2);  /* for IDE reset */
 463
 464                 *value |= SS_READY;
 465                 *value |= SS_3VCARD;
 466         } else {
 467                 /* disable CF power */
 468                 pcc_set(sock, (unsigned int)PLD_CPCR, 0);
 469                 udelay(100);
 470                 debug(3, "m32r_cfc: _pcc_get_status: "
 471                          "power off (CPCR=0x%08x)\n", status);
 472         }
 473 #else
 474 #error no platform configuration
 475 #endif
 476         debug(3, "m32r_cfc: _pcc_get_status: GetStatus(%d) = %#4.4x\n",
 477                  sock, *value);
 478         return 0;
 479 } /* _get_status */
 480
 481 /*====================================================================*/
 482
 483 static int _pcc_set_socket(u_short sock, socket_state_t *state)
 484 {
 485         debug(3, "m32r_cfc: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
 486                   "io_irq %d, csc_mask %#2.2x)\n", sock, state->flags,
 487                   state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
 488
 489 #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
 490         if (state->Vcc) {
 491                 if ((state->Vcc != 50) && (state->Vcc != 33))
 492                         return -EINVAL;
 493                 /* accept 5V and 3.3V */
 494         }
 495 #endif
 496         if (state->flags & SS_RESET) {
 497                 debug(3, ":RESET\n");
 498                 pcc_set(sock,(unsigned int)PLD_CFRSTCR,0x101);
 499         }else{
 500                 pcc_set(sock,(unsigned int)PLD_CFRSTCR,0x100);
 501         }
 502         if (state->flags & SS_OUTPUT_ENA){
 503                 debug(3, ":OUTPUT_ENA\n");
 504                 /* bit clear */
 505                 pcc_set(sock,(unsigned int)PLD_CFBUFCR,0);
 506         } else {
 507                 pcc_set(sock,(unsigned int)PLD_CFBUFCR,1);
 508         }
 509
 510 #ifdef DEBUG
 511         if(state->flags & SS_IOCARD){
 512                 debug(3, ":IOCARD");
 513         }
 514         if (state->flags & SS_PWR_AUTO) {
 515                 debug(3, ":PWR_AUTO");
 516         }
 517         if (state->csc_mask & SS_DETECT)
 518                 debug(3, ":csc-SS_DETECT");
 519         if (state->flags & SS_IOCARD) {
 520                 if (state->csc_mask & SS_STSCHG)
 521                         debug(3, ":STSCHG");
 522         } else {
 523                 if (state->csc_mask & SS_BATDEAD)
 524                         debug(3, ":BATDEAD");
 525                 if (state->csc_mask & SS_BATWARN)
 526                         debug(3, ":BATWARN");
 527                 if (state->csc_mask & SS_READY)
 528                         debug(3, ":READY");
 529         }
 530         debug(3, "\n");
 531 #endif
 532         return 0;
 533 } /* _set_socket */
 534
 535 /*====================================================================*/
 536
 537 static int _pcc_set_io_map(u_short sock, struct pccard_io_map *io)
 538 {
 539         u_char map;
 540
 541         debug(3, "m32r_cfc: SetIOMap(%d, %d, %#2.2x, %d ns, "
 542                   "%#lx-%#lx)\n", sock, io->map, io->flags,
 543                   io->speed, io->start, io->stop);
 544         map = io->map;
 545
 546         return 0;
 547 } /* _set_io_map */
 548
 549 /*====================================================================*/
 550
 551 static int _pcc_set_mem_map(u_short sock, struct pccard_mem_map *mem)
 552 {
 553
 554         u_char map = mem->map;
 555         u_long addr;
 556         pcc_socket_t *t = &socket[sock];
 557
 558         debug(3, "m32r_cfc: SetMemMap(%d, %d, %#2.2x, %d ns, "
 559                  "%#lx, %#x)\n", sock, map, mem->flags,
 560                  mem->speed, mem->static_start, mem->card_start);
 561
 562         /*
 563          * sanity check
 564          */
 565         if ((map > MAX_WIN) || (mem->card_start > 0x3ffffff)){
 566                 return -EINVAL;
 567         }
 568
 569         /*
 570          * de-activate
 571          */
 572         if ((mem->flags & MAP_ACTIVE) == 0) {
 573                 t->current_space = as_none;
 574                 return 0;
 575         }
 576
 577         /*
 578          * Set mode
 579          */
 580         if (mem->flags & MAP_ATTRIB) {
 581                 t->current_space = as_attr;
 582         } else {
 583                 t->current_space = as_comm;
 584         }
 585
 586         /*
 587          * Set address
 588          */
 589         addr = t->mapaddr + (mem->card_start & M32R_PCC_MAPMASK);
 590         mem->static_start = addr + mem->card_start;
 591
 592         return 0;
 593
 594 } /* _set_mem_map */
 595
 596 #if 0 /* driver model ordering issue */
 597 /*======================================================================
 598
 599         Routines for accessing socket information and register dumps via
 600         /proc/bus/pccard/...
 601
 602 ======================================================================*/
 603
 604 static ssize_t show_info(struct class_device *class_dev, char *buf)
 605 {
 606         pcc_socket_t *s = container_of(class_dev, struct pcc_socket,
 607                 socket.dev);
 608
 609         return sprintf(buf, "type:     %s\nbase addr:    0x%08lx\n",
 610                 pcc[s->type].name, s->base);
 611 }
 612
 613 static ssize_t show_exca(struct class_device *class_dev, char *buf)
 614 {
 615         /* FIXME */
 616
 617         return 0;
 618 }
 619
 620 static CLASS_DEVICE_ATTR(info, S_IRUGO, show_info, NULL);
 621 static CLASS_DEVICE_ATTR(exca, S_IRUGO, show_exca, NULL);
 622 #endif
 623
 624 /*====================================================================*/
 625
 626 /* this is horribly ugly... proper locking needs to be done here at
 627  * some time... */
 628 #define LOCKED(x) do {                                  \
 629         int retval;                                     \
 630         unsigned long flags;                            \
 631         spin_lock_irqsave(&pcc_lock, flags);            \
 632         retval = x;                                     \
 633         spin_unlock_irqrestore(&pcc_lock, flags);       \
 634         return retval;                                  \
 635 } while (0)
 636
 637
 638 static int pcc_get_status(struct pcmcia_socket *s, u_int *value)
 639 {
 640         unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
 641
 642         if (socket[sock].flags & IS_ALIVE) {
 643                 debug(3, "m32r_cfc: pcc_get_status: sock(%d) -EINVAL\n", sock);
 644                 *value = 0;
 645                 return -EINVAL;
 646         }
 647         debug(3, "m32r_cfc: pcc_get_status: sock(%d)\n", sock);
 648         LOCKED(_pcc_get_status(sock, value));
 649 }
 650
 651 static int pcc_set_socket(struct pcmcia_socket *s, socket_state_t *state)
 652 {
 653         unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
 654
 655         if (socket[sock].flags & IS_ALIVE) {
 656                 debug(3, "m32r_cfc: pcc_set_socket: sock(%d) -EINVAL\n", sock);
 657                 return -EINVAL;
 658         }
 659         debug(3, "m32r_cfc: pcc_set_socket: sock(%d)\n", sock);
 660         LOCKED(_pcc_set_socket(sock, state));
 661 }
 662
 663 static int pcc_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
 664 {
 665         unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
 666
 667         if (socket[sock].flags & IS_ALIVE) {
 668                 debug(3, "m32r_cfc: pcc_set_io_map: sock(%d) -EINVAL\n", sock);
 669                 return -EINVAL;
 670         }
 671         debug(3, "m32r_cfc: pcc_set_io_map: sock(%d)\n", sock);
 672         LOCKED(_pcc_set_io_map(sock, io));
 673 }
 674
 675 static int pcc_set_mem_map(struct pcmcia_socket *s, struct pccard_mem_map *mem)
 676 {
 677         unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
 678
 679         if (socket[sock].flags & IS_ALIVE) {
 680                 debug(3, "m32r_cfc: pcc_set_mem_map: sock(%d) -EINVAL\n", sock);
 681                 return -EINVAL;
 682         }
 683         debug(3, "m32r_cfc: pcc_set_mem_map: sock(%d)\n", sock);
 684         LOCKED(_pcc_set_mem_map(sock, mem));
 685 }
 686
 687 static int pcc_init(struct pcmcia_socket *s)
 688 {
 689         debug(3, "m32r_cfc: pcc_init()\n");
 690         return 0;
 691 }
 692
 693 static struct pccard_operations pcc_operations = {
 694         .init                   = pcc_init,
 695         .get_status             = pcc_get_status,
 696         .set_socket             = pcc_set_socket,
 697         .set_io_map             = pcc_set_io_map,
 698         .set_mem_map            = pcc_set_mem_map,
 699 };
 700
 701 /*====================================================================*/
 702
 703 static struct device_driver pcc_driver = {
 704         .name = "cfc",
 705         .bus = &platform_bus_type,
 706         .suspend = pcmcia_socket_dev_suspend,
 707         .resume = pcmcia_socket_dev_resume,
 708 };
 709
 710 static struct platform_device pcc_device = {
 711         .name = "cfc",
 712         .id = 0,
 713 };
 714
 715 /*====================================================================*/
 716
 717 static int __init init_m32r_pcc(void)
 718 {
 719         int i, ret;
 720
 721         ret = driver_register(&pcc_driver);
 722         if (ret)
 723                 return ret;
 724
 725         ret = platform_device_register(&pcc_device);
 726         if (ret){
 727                 driver_unregister(&pcc_driver);
 728                 return ret;
 729         }
 730
 731 #if defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
 732         pcc_set(0, (unsigned int)PLD_CFCR0, 0x0f0f);
 733         pcc_set(0, (unsigned int)PLD_CFCR1, 0x0200);
 734 #endif
 735
 736         pcc_sockets = 0;
 737
 738 #if !defined(CONFIG_PLAT_USRV)
 739         add_pcc_socket(M32R_PCC0_BASE, PLD_IRQ_CFC_INSERT, CFC_ATTR_MAPBASE,
 740                        CFC_IOPORT_BASE);
 741 #else   /* CONFIG_PLAT_USRV */
 742         {
 743                 ulong base, mapaddr;
 744                 kio_addr_t ioaddr;
 745
 746                 for (i = 0 ; i < M32R_MAX_PCC ; i++) {
 747                         base = (ulong)PLD_CFRSTCR;
 748                         base = base | (i << 8);
 749                         ioaddr = (i + 1) << 12;
 750                         mapaddr = CFC_ATTR_MAPBASE | (i << 20);
 751                         add_pcc_socket(base, 0, mapaddr, ioaddr);
 752                 }
 753         }
 754 #endif  /* CONFIG_PLAT_USRV */
 755
 756         if (pcc_sockets == 0) {
 757                 printk("socket is not found.\n");
 758                 platform_device_unregister(&pcc_device);
 759                 driver_unregister(&pcc_driver);
 760                 return -ENODEV;
 761         }
 762
 763         /* Set up interrupt handler(s) */
 764
 765         for (i = 0 ; i < pcc_sockets ; i++) {
 766                 socket[i].socket.dev.dev = &pcc_device.dev;
 767                 socket[i].socket.ops = &pcc_operations;
 768                 socket[i].socket.resource_ops = &pccard_nonstatic_ops;
 769                 socket[i].socket.owner = THIS_MODULE;
 770                 socket[i].number = i;
 771                 ret = pcmcia_register_socket(&socket[i].socket);
 772                 if (!ret)
 773                         socket[i].flags |= IS_REGISTERED;
 774
 775 #if 0   /* driver model ordering issue */
 776                 class_device_create_file(&socket[i].socket.dev,
 777                                          &class_device_attr_info);
 778                 class_device_create_file(&socket[i].socket.dev,
 779                                          &class_device_attr_exca);
 780 #endif
 781         }
 782
 783         /* Finally, schedule a polling interrupt */
 784         if (poll_interval != 0) {
 785                 poll_timer.function = pcc_interrupt_wrapper;
 786                 poll_timer.data = 0;
 787                 init_timer(&poll_timer);
 788                 poll_timer.expires = jiffies + poll_interval;
 789                 add_timer(&poll_timer);
 790         }
 791
 792         return 0;
 793 } /* init_m32r_pcc */
 794
 795 static void __exit exit_m32r_pcc(void)
 796 {
 797         int i;
 798
 799         for (i = 0; i < pcc_sockets; i++)
 800                 if (socket[i].flags & IS_REGISTERED)
 801                         pcmcia_unregister_socket(&socket[i].socket);
 802
 803         platform_device_unregister(&pcc_device);
 804         if (poll_interval != 0)
 805                 del_timer_sync(&poll_timer);
 806
 807         driver_unregister(&pcc_driver);
 808 } /* exit_m32r_pcc */
 809
 810 module_init(init_m32r_pcc);
 811 module_exit(exit_m32r_pcc);
 812 MODULE_LICENSE("Dual MPL/GPL");
 813 /*====================================================================*/