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agp/intel: Use a non-reserved value for the cache field of the PTEs.
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / char / agp / intel-agp.c
blobc3c870bf567808005301483c2bab399659ec667a
1 /*
2 * Intel AGPGART routines.
3 */
4
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/init.h>
8 #include <linux/kernel.h>
9 #include <linux/pagemap.h>
10 #include <linux/agp_backend.h>
11 #include "agp.h"
12
13 /*
14 * If we have Intel graphics, we're not going to have anything other than
15 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
16 * on the Intel IOMMU support (CONFIG_DMAR).
17 * Only newer chipsets need to bother with this, of course.
18 */
19 #ifdef CONFIG_DMAR
20 #define USE_PCI_DMA_API 1
21 #endif
22
23 #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588
24 #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a
25 #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
26 #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
27 #define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980
28 #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982
29 #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
30 #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
31 #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
32 #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
33 #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
34 #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
35 #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
36 #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
37 #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
38 #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
39 #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB 0xA010
40 #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG 0xA011
41 #define PCI_DEVICE_ID_INTEL_PINEVIEW_HB 0xA000
42 #define PCI_DEVICE_ID_INTEL_PINEVIEW_IG 0xA001
43 #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
44 #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
45 #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
46 #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
47 #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
48 #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
49 #define PCI_DEVICE_ID_INTEL_B43_HB 0x2E40
50 #define PCI_DEVICE_ID_INTEL_B43_IG 0x2E42
51 #define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40
52 #define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42
53 #define PCI_DEVICE_ID_INTEL_EAGLELAKE_HB 0x2E00
54 #define PCI_DEVICE_ID_INTEL_EAGLELAKE_IG 0x2E02
55 #define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
56 #define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
57 #define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
58 #define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22
59 #define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30
60 #define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32
61 #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB 0x0040
62 #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG 0x0042
63 #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB 0x0044
64 #define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062
65 #define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB 0x006a
66 #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046
67 #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB 0x0100
68 #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG 0x0102
69
70 /* cover 915 and 945 variants */
71 #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
72 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \
73 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
74 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
75 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
76 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
77
78 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
79 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
80 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
81 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
82 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
83 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
84
85 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
86 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
87 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \
88 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \
89 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)
90
91 #define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \
92 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)
93
94 #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \
95 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
96 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
97 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
98 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \
99 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \
100 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB || \
101 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \
102 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \
103 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \
104 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB)
105
106 extern int agp_memory_reserved;
107
108
109 /* Intel 815 register */
110 #define INTEL_815_APCONT 0x51
111 #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
112
113 /* Intel i820 registers */
114 #define INTEL_I820_RDCR 0x51
115 #define INTEL_I820_ERRSTS 0xc8
116
117 /* Intel i840 registers */
118 #define INTEL_I840_MCHCFG 0x50
119 #define INTEL_I840_ERRSTS 0xc8
120
121 /* Intel i850 registers */
122 #define INTEL_I850_MCHCFG 0x50
123 #define INTEL_I850_ERRSTS 0xc8
124
125 /* intel 915G registers */
126 #define I915_GMADDR 0x18
127 #define I915_MMADDR 0x10
128 #define I915_PTEADDR 0x1C
129 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
130 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
131 #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
132 #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
133 #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
134 #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
135 #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
136 #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
137
138 #define I915_IFPADDR 0x60
139
140 /* Intel 965G registers */
141 #define I965_MSAC 0x62
142 #define I965_IFPADDR 0x70
143
144 /* Intel 7505 registers */
145 #define INTEL_I7505_APSIZE 0x74
146 #define INTEL_I7505_NCAPID 0x60
147 #define INTEL_I7505_NISTAT 0x6c
148 #define INTEL_I7505_ATTBASE 0x78
149 #define INTEL_I7505_ERRSTS 0x42
150 #define INTEL_I7505_AGPCTRL 0x70
151 #define INTEL_I7505_MCHCFG 0x50
152
153 static const struct aper_size_info_fixed intel_i810_sizes[] =
154 {
155 {64, 16384, 4},
156 /* The 32M mode still requires a 64k gatt */
157 {32, 8192, 4}
158 };
159
160 #define AGP_DCACHE_MEMORY 1
161 #define AGP_PHYS_MEMORY 2
162 #define INTEL_AGP_CACHED_MEMORY 3
163
164 static struct gatt_mask intel_i810_masks[] =
165 {
166 {.mask = I810_PTE_VALID, .type = 0},
167 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
168 {.mask = I810_PTE_VALID, .type = 0},
169 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
170 .type = INTEL_AGP_CACHED_MEMORY}
171 };
172
173 static struct _intel_private {
174 struct pci_dev *pcidev; /* device one */
175 u8 __iomem *registers;
176 u32 __iomem *gtt; /* I915G */
177 int num_dcache_entries;
178 /* gtt_entries is the number of gtt entries that are already mapped
179 * to stolen memory. Stolen memory is larger than the memory mapped
180 * through gtt_entries, as it includes some reserved space for the BIOS
181 * popup and for the GTT.
182 */
183 int gtt_entries; /* i830+ */
184 int gtt_total_size;
185 union {
186 void __iomem *i9xx_flush_page;
187 void *i8xx_flush_page;
188 };
189 struct page *i8xx_page;
190 struct resource ifp_resource;
191 int resource_valid;
192 } intel_private;
193
194 #ifdef USE_PCI_DMA_API
195 static int intel_agp_map_page(struct page *page, dma_addr_t *ret)
196 {
197 *ret = pci_map_page(intel_private.pcidev, page, 0,
198 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
199 if (pci_dma_mapping_error(intel_private.pcidev, *ret))
200 return -EINVAL;
201 return 0;
202 }
203
204 static void intel_agp_unmap_page(struct page *page, dma_addr_t dma)
205 {
206 pci_unmap_page(intel_private.pcidev, dma,
207 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
208 }
209
210 static void intel_agp_free_sglist(struct agp_memory *mem)
211 {
212 struct sg_table st;
213
214 st.sgl = mem->sg_list;
215 st.orig_nents = st.nents = mem->page_count;
216
217 sg_free_table(&st);
218
219 mem->sg_list = NULL;
220 mem->num_sg = 0;
221 }
222
223 static int intel_agp_map_memory(struct agp_memory *mem)
224 {
225 struct sg_table st;
226 struct scatterlist *sg;
227 int i;
228
229 DBG("try mapping %lu pages\n", (unsigned long)mem->page_count);
230
231 if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL))
232 return -ENOMEM;
233
234 mem->sg_list = sg = st.sgl;
235
236 for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg))
237 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0);
238
239 mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list,
240 mem->page_count, PCI_DMA_BIDIRECTIONAL);
241 if (unlikely(!mem->num_sg)) {
242 intel_agp_free_sglist(mem);
243 return -ENOMEM;
244 }
245 return 0;
246 }
247
248 static void intel_agp_unmap_memory(struct agp_memory *mem)
249 {
250 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
251
252 pci_unmap_sg(intel_private.pcidev, mem->sg_list,
253 mem->page_count, PCI_DMA_BIDIRECTIONAL);
254 intel_agp_free_sglist(mem);
255 }
256
257 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
258 off_t pg_start, int mask_type)
259 {
260 struct scatterlist *sg;
261 int i, j;
262
263 j = pg_start;
264
265 WARN_ON(!mem->num_sg);
266
267 if (mem->num_sg == mem->page_count) {
268 for_each_sg(mem->sg_list, sg, mem->page_count, i) {
269 writel(agp_bridge->driver->mask_memory(agp_bridge,
270 sg_dma_address(sg), mask_type),
271 intel_private.gtt+j);
272 j++;
273 }
274 } else {
275 /* sg may merge pages, but we have to seperate
276 * per-page addr for GTT */
277 unsigned int len, m;
278
279 for_each_sg(mem->sg_list, sg, mem->num_sg, i) {
280 len = sg_dma_len(sg) / PAGE_SIZE;
281 for (m = 0; m < len; m++) {
282 writel(agp_bridge->driver->mask_memory(agp_bridge,
283 sg_dma_address(sg) + m * PAGE_SIZE,
284 mask_type),
285 intel_private.gtt+j);
286 j++;
287 }
288 }
289 }
290 readl(intel_private.gtt+j-1);
291 }
292
293 #else
294
295 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
296 off_t pg_start, int mask_type)
297 {
298 int i, j;
299 u32 cache_bits = 0;
300
301 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB) {
302 cache_bits = I830_PTE_SYSTEM_CACHED;
303 }
304
305 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
306 writel(agp_bridge->driver->mask_memory(agp_bridge,
307 page_to_phys(mem->pages[i]), mask_type),
308 intel_private.gtt+j);
309 }
310
311 readl(intel_private.gtt+j-1);
312 }
313
314 #endif
315
316 static int intel_i810_fetch_size(void)
317 {
318 u32 smram_miscc;
319 struct aper_size_info_fixed *values;
320
321 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
322 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
323
324 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
325 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n");
326 return 0;
327 }
328 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
329 agp_bridge->previous_size =
330 agp_bridge->current_size = (void *) (values + 1);
331 agp_bridge->aperture_size_idx = 1;
332 return values[1].size;
333 } else {
334 agp_bridge->previous_size =
335 agp_bridge->current_size = (void *) (values);
336 agp_bridge->aperture_size_idx = 0;
337 return values[0].size;
338 }
339
340 return 0;
341 }
342
343 static int intel_i810_configure(void)
344 {
345 struct aper_size_info_fixed *current_size;
346 u32 temp;
347 int i;
348
349 current_size = A_SIZE_FIX(agp_bridge->current_size);
350
351 if (!intel_private.registers) {
352 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
353 temp &= 0xfff80000;
354
355 intel_private.registers = ioremap(temp, 128 * 4096);
356 if (!intel_private.registers) {
357 dev_err(&intel_private.pcidev->dev,
358 "can't remap memory\n");
359 return -ENOMEM;
360 }
361 }
362
363 if ((readl(intel_private.registers+I810_DRAM_CTL)
364 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
365 /* This will need to be dynamically assigned */
366 dev_info(&intel_private.pcidev->dev,
367 "detected 4MB dedicated video ram\n");
368 intel_private.num_dcache_entries = 1024;
369 }
370 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
371 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
372 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
373 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
374
375 if (agp_bridge->driver->needs_scratch_page) {
376 for (i = 0; i < current_size->num_entries; i++) {
377 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
378 }
379 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
380 }
381 global_cache_flush();
382 return 0;
383 }
384
385 static void intel_i810_cleanup(void)
386 {
387 writel(0, intel_private.registers+I810_PGETBL_CTL);
388 readl(intel_private.registers); /* PCI Posting. */
389 iounmap(intel_private.registers);
390 }
391
392 static void intel_i810_tlbflush(struct agp_memory *mem)
393 {
394 return;
395 }
396
397 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
398 {
399 return;
400 }
401
402 /* Exists to support ARGB cursors */
403 static struct page *i8xx_alloc_pages(void)
404 {
405 struct page *page;
406
407 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
408 if (page == NULL)
409 return NULL;
410
411 if (set_pages_uc(page, 4) < 0) {
412 set_pages_wb(page, 4);
413 __free_pages(page, 2);
414 return NULL;
415 }
416 get_page(page);
417 atomic_inc(&agp_bridge->current_memory_agp);
418 return page;
419 }
420
421 static void i8xx_destroy_pages(struct page *page)
422 {
423 if (page == NULL)
424 return;
425
426 set_pages_wb(page, 4);
427 put_page(page);
428 __free_pages(page, 2);
429 atomic_dec(&agp_bridge->current_memory_agp);
430 }
431
432 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
433 int type)
434 {
435 if (type < AGP_USER_TYPES)
436 return type;
437 else if (type == AGP_USER_CACHED_MEMORY)
438 return INTEL_AGP_CACHED_MEMORY;
439 else
440 return 0;
441 }
442
443 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
444 int type)
445 {
446 int i, j, num_entries;
447 void *temp;
448 int ret = -EINVAL;
449 int mask_type;
450
451 if (mem->page_count == 0)
452 goto out;
453
454 temp = agp_bridge->current_size;
455 num_entries = A_SIZE_FIX(temp)->num_entries;
456
457 if ((pg_start + mem->page_count) > num_entries)
458 goto out_err;
459
460
461 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
462 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
463 ret = -EBUSY;
464 goto out_err;
465 }
466 }
467
468 if (type != mem->type)
469 goto out_err;
470
471 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
472
473 switch (mask_type) {
474 case AGP_DCACHE_MEMORY:
475 if (!mem->is_flushed)
476 global_cache_flush();
477 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
478 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
479 intel_private.registers+I810_PTE_BASE+(i*4));
480 }
481 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
482 break;
483 case AGP_PHYS_MEMORY:
484 case AGP_NORMAL_MEMORY:
485 if (!mem->is_flushed)
486 global_cache_flush();
487 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
488 writel(agp_bridge->driver->mask_memory(agp_bridge,
489 page_to_phys(mem->pages[i]), mask_type),
490 intel_private.registers+I810_PTE_BASE+(j*4));
491 }
492 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
493 break;
494 default:
495 goto out_err;
496 }
497
498 agp_bridge->driver->tlb_flush(mem);
499 out:
500 ret = 0;
501 out_err:
502 mem->is_flushed = true;
503 return ret;
504 }
505
506 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
507 int type)
508 {
509 int i;
510
511 if (mem->page_count == 0)
512 return 0;
513
514 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
515 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
516 }
517 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
518
519 agp_bridge->driver->tlb_flush(mem);
520 return 0;
521 }
522
523 /*
524 * The i810/i830 requires a physical address to program its mouse
525 * pointer into hardware.
526 * However the Xserver still writes to it through the agp aperture.
527 */
528 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
529 {
530 struct agp_memory *new;
531 struct page *page;
532
533 switch (pg_count) {
534 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
535 break;
536 case 4:
537 /* kludge to get 4 physical pages for ARGB cursor */
538 page = i8xx_alloc_pages();
539 break;
540 default:
541 return NULL;
542 }
543
544 if (page == NULL)
545 return NULL;
546
547 new = agp_create_memory(pg_count);
548 if (new == NULL)
549 return NULL;
550
551 new->pages[0] = page;
552 if (pg_count == 4) {
553 /* kludge to get 4 physical pages for ARGB cursor */
554 new->pages[1] = new->pages[0] + 1;
555 new->pages[2] = new->pages[1] + 1;
556 new->pages[3] = new->pages[2] + 1;
557 }
558 new->page_count = pg_count;
559 new->num_scratch_pages = pg_count;
560 new->type = AGP_PHYS_MEMORY;
561 new->physical = page_to_phys(new->pages[0]);
562 return new;
563 }
564
565 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
566 {
567 struct agp_memory *new;
568
569 if (type == AGP_DCACHE_MEMORY) {
570 if (pg_count != intel_private.num_dcache_entries)
571 return NULL;
572
573 new = agp_create_memory(1);
574 if (new == NULL)
575 return NULL;
576
577 new->type = AGP_DCACHE_MEMORY;
578 new->page_count = pg_count;
579 new->num_scratch_pages = 0;
580 agp_free_page_array(new);
581 return new;
582 }
583 if (type == AGP_PHYS_MEMORY)
584 return alloc_agpphysmem_i8xx(pg_count, type);
585 return NULL;
586 }
587
588 static void intel_i810_free_by_type(struct agp_memory *curr)
589 {
590 agp_free_key(curr->key);
591 if (curr->type == AGP_PHYS_MEMORY) {
592 if (curr->page_count == 4)
593 i8xx_destroy_pages(curr->pages[0]);
594 else {
595 agp_bridge->driver->agp_destroy_page(curr->pages[0],
596 AGP_PAGE_DESTROY_UNMAP);
597 agp_bridge->driver->agp_destroy_page(curr->pages[0],
598 AGP_PAGE_DESTROY_FREE);
599 }
600 agp_free_page_array(curr);
601 }
602 kfree(curr);
603 }
604
605 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
606 dma_addr_t addr, int type)
607 {
608 /* Type checking must be done elsewhere */
609 return addr | bridge->driver->masks[type].mask;
610 }
611
612 static struct aper_size_info_fixed intel_i830_sizes[] =
613 {
614 {128, 32768, 5},
615 /* The 64M mode still requires a 128k gatt */
616 {64, 16384, 5},
617 {256, 65536, 6},
618 {512, 131072, 7},
619 };
620
621 static void intel_i830_init_gtt_entries(void)
622 {
623 u16 gmch_ctrl;
624 int gtt_entries;
625 u8 rdct;
626 int local = 0;
627 static const int ddt[4] = { 0, 16, 32, 64 };
628 int size; /* reserved space (in kb) at the top of stolen memory */
629
630 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
631
632 if (IS_I965) {
633 u32 pgetbl_ctl;
634 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
635
636 /* The 965 has a field telling us the size of the GTT,
637 * which may be larger than what is necessary to map the
638 * aperture.
639 */
640 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
641 case I965_PGETBL_SIZE_128KB:
642 size = 128;
643 break;
644 case I965_PGETBL_SIZE_256KB:
645 size = 256;
646 break;
647 case I965_PGETBL_SIZE_512KB:
648 size = 512;
649 break;
650 case I965_PGETBL_SIZE_1MB:
651 size = 1024;
652 break;
653 case I965_PGETBL_SIZE_2MB:
654 size = 2048;
655 break;
656 case I965_PGETBL_SIZE_1_5MB:
657 size = 1024 + 512;
658 break;
659 default:
660 dev_info(&intel_private.pcidev->dev,
661 "unknown page table size, assuming 512KB\n");
662 size = 512;
663 }
664 size += 4; /* add in BIOS popup space */
665 } else if (IS_G33 && !IS_PINEVIEW) {
666 /* G33's GTT size defined in gmch_ctrl */
667 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
668 case G33_PGETBL_SIZE_1M:
669 size = 1024;
670 break;
671 case G33_PGETBL_SIZE_2M:
672 size = 2048;
673 break;
674 default:
675 dev_info(&agp_bridge->dev->dev,
676 "unknown page table size 0x%x, assuming 512KB\n",
677 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
678 size = 512;
679 }
680 size += 4;
681 } else if (IS_G4X || IS_PINEVIEW) {
682 /* On 4 series hardware, GTT stolen is separate from graphics
683 * stolen, ignore it in stolen gtt entries counting. However,
684 * 4KB of the stolen memory doesn't get mapped to the GTT.
685 */
686 size = 4;
687 } else {
688 /* On previous hardware, the GTT size was just what was
689 * required to map the aperture.
690 */
691 size = agp_bridge->driver->fetch_size() + 4;
692 }
693
694 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
695 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
696 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
697 case I830_GMCH_GMS_STOLEN_512:
698 gtt_entries = KB(512) - KB(size);
699 break;
700 case I830_GMCH_GMS_STOLEN_1024:
701 gtt_entries = MB(1) - KB(size);
702 break;
703 case I830_GMCH_GMS_STOLEN_8192:
704 gtt_entries = MB(8) - KB(size);
705 break;
706 case I830_GMCH_GMS_LOCAL:
707 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
708 gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
709 MB(ddt[I830_RDRAM_DDT(rdct)]);
710 local = 1;
711 break;
712 default:
713 gtt_entries = 0;
714 break;
715 }
716 } else if (agp_bridge->dev->device ==
717 PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB) {
718 /* XXX: This is what my A1 silicon has. What's the right
719 * answer?
720 */
721 gtt_entries = MB(64) - KB(size);
722 } else {
723 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
724 case I855_GMCH_GMS_STOLEN_1M:
725 gtt_entries = MB(1) - KB(size);
726 break;
727 case I855_GMCH_GMS_STOLEN_4M:
728 gtt_entries = MB(4) - KB(size);
729 break;
730 case I855_GMCH_GMS_STOLEN_8M:
731 gtt_entries = MB(8) - KB(size);
732 break;
733 case I855_GMCH_GMS_STOLEN_16M:
734 gtt_entries = MB(16) - KB(size);
735 break;
736 case I855_GMCH_GMS_STOLEN_32M:
737 gtt_entries = MB(32) - KB(size);
738 break;
739 case I915_GMCH_GMS_STOLEN_48M:
740 /* Check it's really I915G */
741 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
742 gtt_entries = MB(48) - KB(size);
743 else
744 gtt_entries = 0;
745 break;
746 case I915_GMCH_GMS_STOLEN_64M:
747 /* Check it's really I915G */
748 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
749 gtt_entries = MB(64) - KB(size);
750 else
751 gtt_entries = 0;
752 break;
753 case G33_GMCH_GMS_STOLEN_128M:
754 if (IS_G33 || IS_I965 || IS_G4X)
755 gtt_entries = MB(128) - KB(size);
756 else
757 gtt_entries = 0;
758 break;
759 case G33_GMCH_GMS_STOLEN_256M:
760 if (IS_G33 || IS_I965 || IS_G4X)
761 gtt_entries = MB(256) - KB(size);
762 else
763 gtt_entries = 0;
764 break;
765 case INTEL_GMCH_GMS_STOLEN_96M:
766 if (IS_I965 || IS_G4X)
767 gtt_entries = MB(96) - KB(size);
768 else
769 gtt_entries = 0;
770 break;
771 case INTEL_GMCH_GMS_STOLEN_160M:
772 if (IS_I965 || IS_G4X)
773 gtt_entries = MB(160) - KB(size);
774 else
775 gtt_entries = 0;
776 break;
777 case INTEL_GMCH_GMS_STOLEN_224M:
778 if (IS_I965 || IS_G4X)
779 gtt_entries = MB(224) - KB(size);
780 else
781 gtt_entries = 0;
782 break;
783 case INTEL_GMCH_GMS_STOLEN_352M:
784 if (IS_I965 || IS_G4X)
785 gtt_entries = MB(352) - KB(size);
786 else
787 gtt_entries = 0;
788 break;
789 default:
790 gtt_entries = 0;
791 break;
792 }
793 }
794 if (gtt_entries > 0) {
795 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n",
796 gtt_entries / KB(1), local ? "local" : "stolen");
797 gtt_entries /= KB(4);
798 } else {
799 dev_info(&agp_bridge->dev->dev,
800 "no pre-allocated video memory detected\n");
801 gtt_entries = 0;
802 }
803
804 intel_private.gtt_entries = gtt_entries;
805 }
806
807 static void intel_i830_fini_flush(void)
808 {
809 kunmap(intel_private.i8xx_page);
810 intel_private.i8xx_flush_page = NULL;
811 unmap_page_from_agp(intel_private.i8xx_page);
812
813 __free_page(intel_private.i8xx_page);
814 intel_private.i8xx_page = NULL;
815 }
816
817 static void intel_i830_setup_flush(void)
818 {
819 /* return if we've already set the flush mechanism up */
820 if (intel_private.i8xx_page)
821 return;
822
823 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
824 if (!intel_private.i8xx_page)
825 return;
826
827 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
828 if (!intel_private.i8xx_flush_page)
829 intel_i830_fini_flush();
830 }
831
832 static void
833 do_wbinvd(void *null)
834 {
835 wbinvd();
836 }
837
838 /* The chipset_flush interface needs to get data that has already been
839 * flushed out of the CPU all the way out to main memory, because the GPU
840 * doesn't snoop those buffers.
841 *
842 * The 8xx series doesn't have the same lovely interface for flushing the
843 * chipset write buffers that the later chips do. According to the 865
844 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
845 * that buffer out, we just fill 1KB and clflush it out, on the assumption
846 * that it'll push whatever was in there out. It appears to work.
847 */
848 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
849 {
850 unsigned int *pg = intel_private.i8xx_flush_page;
851
852 memset(pg, 0, 1024);
853
854 if (cpu_has_clflush) {
855 clflush_cache_range(pg, 1024);
856 } else {
857 if (on_each_cpu(do_wbinvd, NULL, 1) != 0)
858 printk(KERN_ERR "Timed out waiting for cache flush.\n");
859 }
860 }
861
862 /* The intel i830 automatically initializes the agp aperture during POST.
863 * Use the memory already set aside for in the GTT.
864 */
865 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
866 {
867 int page_order;
868 struct aper_size_info_fixed *size;
869 int num_entries;
870 u32 temp;
871
872 size = agp_bridge->current_size;
873 page_order = size->page_order;
874 num_entries = size->num_entries;
875 agp_bridge->gatt_table_real = NULL;
876
877 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
878 temp &= 0xfff80000;
879
880 intel_private.registers = ioremap(temp, 128 * 4096);
881 if (!intel_private.registers)
882 return -ENOMEM;
883
884 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
885 global_cache_flush(); /* FIXME: ?? */
886
887 /* we have to call this as early as possible after the MMIO base address is known */
888 intel_i830_init_gtt_entries();
889
890 agp_bridge->gatt_table = NULL;
891
892 agp_bridge->gatt_bus_addr = temp;
893
894 return 0;
895 }
896
897 /* Return the gatt table to a sane state. Use the top of stolen
898 * memory for the GTT.
899 */
900 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
901 {
902 return 0;
903 }
904
905 static int intel_i830_fetch_size(void)
906 {
907 u16 gmch_ctrl;
908 struct aper_size_info_fixed *values;
909
910 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
911
912 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
913 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
914 /* 855GM/852GM/865G has 128MB aperture size */
915 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
916 agp_bridge->aperture_size_idx = 0;
917 return values[0].size;
918 }
919
920 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
921
922 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
923 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
924 agp_bridge->aperture_size_idx = 0;
925 return values[0].size;
926 } else {
927 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
928 agp_bridge->aperture_size_idx = 1;
929 return values[1].size;
930 }
931
932 return 0;
933 }
934
935 static int intel_i830_configure(void)
936 {
937 struct aper_size_info_fixed *current_size;
938 u32 temp;
939 u16 gmch_ctrl;
940 int i;
941
942 current_size = A_SIZE_FIX(agp_bridge->current_size);
943
944 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
945 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
946
947 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
948 gmch_ctrl |= I830_GMCH_ENABLED;
949 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
950
951 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
952 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
953
954 if (agp_bridge->driver->needs_scratch_page) {
955 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
956 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
957 }
958 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
959 }
960
961 global_cache_flush();
962
963 intel_i830_setup_flush();
964 return 0;
965 }
966
967 static void intel_i830_cleanup(void)
968 {
969 iounmap(intel_private.registers);
970 }
971
972 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
973 int type)
974 {
975 int i, j, num_entries;
976 void *temp;
977 int ret = -EINVAL;
978 int mask_type;
979
980 if (mem->page_count == 0)
981 goto out;
982
983 temp = agp_bridge->current_size;
984 num_entries = A_SIZE_FIX(temp)->num_entries;
985
986 if (pg_start < intel_private.gtt_entries) {
987 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
988 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
989 pg_start, intel_private.gtt_entries);
990
991 dev_info(&intel_private.pcidev->dev,
992 "trying to insert into local/stolen memory\n");
993 goto out_err;
994 }
995
996 if ((pg_start + mem->page_count) > num_entries)
997 goto out_err;
998
999 /* The i830 can't check the GTT for entries since its read only,
1000 * depend on the caller to make the correct offset decisions.
1001 */
1002
1003 if (type != mem->type)
1004 goto out_err;
1005
1006 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1007
1008 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1009 mask_type != INTEL_AGP_CACHED_MEMORY)
1010 goto out_err;
1011
1012 if (!mem->is_flushed)
1013 global_cache_flush();
1014
1015 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1016 writel(agp_bridge->driver->mask_memory(agp_bridge,
1017 page_to_phys(mem->pages[i]), mask_type),
1018 intel_private.registers+I810_PTE_BASE+(j*4));
1019 }
1020 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
1021 agp_bridge->driver->tlb_flush(mem);
1022
1023 out:
1024 ret = 0;
1025 out_err:
1026 mem->is_flushed = true;
1027 return ret;
1028 }
1029
1030 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
1031 int type)
1032 {
1033 int i;
1034
1035 if (mem->page_count == 0)
1036 return 0;
1037
1038 if (pg_start < intel_private.gtt_entries) {
1039 dev_info(&intel_private.pcidev->dev,
1040 "trying to disable local/stolen memory\n");
1041 return -EINVAL;
1042 }
1043
1044 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1045 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
1046 }
1047 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
1048
1049 agp_bridge->driver->tlb_flush(mem);
1050 return 0;
1051 }
1052
1053 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
1054 {
1055 if (type == AGP_PHYS_MEMORY)
1056 return alloc_agpphysmem_i8xx(pg_count, type);
1057 /* always return NULL for other allocation types for now */
1058 return NULL;
1059 }
1060
1061 static int intel_alloc_chipset_flush_resource(void)
1062 {
1063 int ret;
1064 ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1065 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1066 pcibios_align_resource, agp_bridge->dev);
1067
1068 return ret;
1069 }
1070
1071 static void intel_i915_setup_chipset_flush(void)
1072 {
1073 int ret;
1074 u32 temp;
1075
1076 pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
1077 if (!(temp & 0x1)) {
1078 intel_alloc_chipset_flush_resource();
1079 intel_private.resource_valid = 1;
1080 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1081 } else {
1082 temp &= ~1;
1083
1084 intel_private.resource_valid = 1;
1085 intel_private.ifp_resource.start = temp;
1086 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1087 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1088 /* some BIOSes reserve this area in a pnp some don't */
1089 if (ret)
1090 intel_private.resource_valid = 0;
1091 }
1092 }
1093
1094 static void intel_i965_g33_setup_chipset_flush(void)
1095 {
1096 u32 temp_hi, temp_lo;
1097 int ret;
1098
1099 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
1100 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
1101
1102 if (!(temp_lo & 0x1)) {
1103
1104 intel_alloc_chipset_flush_resource();
1105
1106 intel_private.resource_valid = 1;
1107 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
1108 upper_32_bits(intel_private.ifp_resource.start));
1109 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1110 } else {
1111 u64 l64;
1112
1113 temp_lo &= ~0x1;
1114 l64 = ((u64)temp_hi << 32) | temp_lo;
1115
1116 intel_private.resource_valid = 1;
1117 intel_private.ifp_resource.start = l64;
1118 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1119 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1120 /* some BIOSes reserve this area in a pnp some don't */
1121 if (ret)
1122 intel_private.resource_valid = 0;
1123 }
1124 }
1125
1126 static void intel_i9xx_setup_flush(void)
1127 {
1128 /* return if already configured */
1129 if (intel_private.ifp_resource.start)
1130 return;
1131
1132 /* setup a resource for this object */
1133 intel_private.ifp_resource.name = "Intel Flush Page";
1134 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1135
1136 /* Setup chipset flush for 915 */
1137 if (IS_I965 || IS_G33 || IS_G4X) {
1138 intel_i965_g33_setup_chipset_flush();
1139 } else {
1140 intel_i915_setup_chipset_flush();
1141 }
1142
1143 if (intel_private.ifp_resource.start) {
1144 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1145 if (!intel_private.i9xx_flush_page)
1146 dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing");
1147 }
1148 }
1149
1150 static int intel_i915_configure(void)
1151 {
1152 struct aper_size_info_fixed *current_size;
1153 u32 temp;
1154 u16 gmch_ctrl;
1155 int i;
1156
1157 current_size = A_SIZE_FIX(agp_bridge->current_size);
1158
1159 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
1160
1161 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1162
1163 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1164 gmch_ctrl |= I830_GMCH_ENABLED;
1165 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
1166
1167 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
1168 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1169
1170 if (agp_bridge->driver->needs_scratch_page) {
1171 for (i = intel_private.gtt_entries; i < intel_private.gtt_total_size; i++) {
1172 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1173 }
1174 readl(intel_private.gtt+i-1); /* PCI Posting. */
1175 }
1176
1177 global_cache_flush();
1178
1179 intel_i9xx_setup_flush();
1180
1181 return 0;
1182 }
1183
1184 static void intel_i915_cleanup(void)
1185 {
1186 if (intel_private.i9xx_flush_page)
1187 iounmap(intel_private.i9xx_flush_page);
1188 if (intel_private.resource_valid)
1189 release_resource(&intel_private.ifp_resource);
1190 intel_private.ifp_resource.start = 0;
1191 intel_private.resource_valid = 0;
1192 iounmap(intel_private.gtt);
1193 iounmap(intel_private.registers);
1194 }
1195
1196 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1197 {
1198 if (intel_private.i9xx_flush_page)
1199 writel(1, intel_private.i9xx_flush_page);
1200 }
1201
1202 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1203 int type)
1204 {
1205 int num_entries;
1206 void *temp;
1207 int ret = -EINVAL;
1208 int mask_type;
1209
1210 if (mem->page_count == 0)
1211 goto out;
1212
1213 temp = agp_bridge->current_size;
1214 num_entries = A_SIZE_FIX(temp)->num_entries;
1215
1216 if (pg_start < intel_private.gtt_entries) {
1217 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1218 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
1219 pg_start, intel_private.gtt_entries);
1220
1221 dev_info(&intel_private.pcidev->dev,
1222 "trying to insert into local/stolen memory\n");
1223 goto out_err;
1224 }
1225
1226 if ((pg_start + mem->page_count) > num_entries)
1227 goto out_err;
1228
1229 /* The i915 can't check the GTT for entries since it's read only;
1230 * depend on the caller to make the correct offset decisions.
1231 */
1232
1233 if (type != mem->type)
1234 goto out_err;
1235
1236 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1237
1238 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1239 mask_type != INTEL_AGP_CACHED_MEMORY)
1240 goto out_err;
1241
1242 if (!mem->is_flushed)
1243 global_cache_flush();
1244
1245 intel_agp_insert_sg_entries(mem, pg_start, mask_type);
1246 agp_bridge->driver->tlb_flush(mem);
1247
1248 out:
1249 ret = 0;
1250 out_err:
1251 mem->is_flushed = true;
1252 return ret;
1253 }
1254
1255 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1256 int type)
1257 {
1258 int i;
1259
1260 if (mem->page_count == 0)
1261 return 0;
1262
1263 if (pg_start < intel_private.gtt_entries) {
1264 dev_info(&intel_private.pcidev->dev,
1265 "trying to disable local/stolen memory\n");
1266 return -EINVAL;
1267 }
1268
1269 for (i = pg_start; i < (mem->page_count + pg_start); i++)
1270 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1271
1272 readl(intel_private.gtt+i-1);
1273
1274 agp_bridge->driver->tlb_flush(mem);
1275 return 0;
1276 }
1277
1278 /* Return the aperture size by just checking the resource length. The effect
1279 * described in the spec of the MSAC registers is just changing of the
1280 * resource size.
1281 */
1282 static int intel_i9xx_fetch_size(void)
1283 {
1284 int num_sizes = ARRAY_SIZE(intel_i830_sizes);
1285 int aper_size; /* size in megabytes */
1286 int i;
1287
1288 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1289
1290 for (i = 0; i < num_sizes; i++) {
1291 if (aper_size == intel_i830_sizes[i].size) {
1292 agp_bridge->current_size = intel_i830_sizes + i;
1293 agp_bridge->previous_size = agp_bridge->current_size;
1294 return aper_size;
1295 }
1296 }
1297
1298 return 0;
1299 }
1300
1301 /* The intel i915 automatically initializes the agp aperture during POST.
1302 * Use the memory already set aside for in the GTT.
1303 */
1304 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1305 {
1306 int page_order;
1307 struct aper_size_info_fixed *size;
1308 int num_entries;
1309 u32 temp, temp2;
1310 int gtt_map_size = 256 * 1024;
1311
1312 size = agp_bridge->current_size;
1313 page_order = size->page_order;
1314 num_entries = size->num_entries;
1315 agp_bridge->gatt_table_real = NULL;
1316
1317 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1318 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1319
1320 if (IS_G33)
1321 gtt_map_size = 1024 * 1024; /* 1M on G33 */
1322 intel_private.gtt = ioremap(temp2, gtt_map_size);
1323 if (!intel_private.gtt)
1324 return -ENOMEM;
1325
1326 intel_private.gtt_total_size = gtt_map_size / 4;
1327
1328 temp &= 0xfff80000;
1329
1330 intel_private.registers = ioremap(temp, 128 * 4096);
1331 if (!intel_private.registers) {
1332 iounmap(intel_private.gtt);
1333 return -ENOMEM;
1334 }
1335
1336 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1337 global_cache_flush(); /* FIXME: ? */
1338
1339 /* we have to call this as early as possible after the MMIO base address is known */
1340 intel_i830_init_gtt_entries();
1341
1342 agp_bridge->gatt_table = NULL;
1343
1344 agp_bridge->gatt_bus_addr = temp;
1345
1346 return 0;
1347 }
1348
1349 /*
1350 * The i965 supports 36-bit physical addresses, but to keep
1351 * the format of the GTT the same, the bits that don't fit
1352 * in a 32-bit word are shifted down to bits 4..7.
1353 *
1354 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1355 * is always zero on 32-bit architectures, so no need to make
1356 * this conditional.
1357 */
1358 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1359 dma_addr_t addr, int type)
1360 {
1361 /* Shift high bits down */
1362 addr |= (addr >> 28) & 0xf0;
1363
1364 /* Type checking must be done elsewhere */
1365 return addr | bridge->driver->masks[type].mask;
1366 }
1367
1368 static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1369 {
1370 switch (agp_bridge->dev->device) {
1371 case PCI_DEVICE_ID_INTEL_GM45_HB:
1372 case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB:
1373 case PCI_DEVICE_ID_INTEL_Q45_HB:
1374 case PCI_DEVICE_ID_INTEL_G45_HB:
1375 case PCI_DEVICE_ID_INTEL_G41_HB:
1376 case PCI_DEVICE_ID_INTEL_B43_HB:
1377 case PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB:
1378 case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB:
1379 case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB:
1380 case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB:
1381 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB:
1382 *gtt_offset = *gtt_size = MB(2);
1383 break;
1384 default:
1385 *gtt_offset = *gtt_size = KB(512);
1386 }
1387 }
1388
1389 /* The intel i965 automatically initializes the agp aperture during POST.
1390 * Use the memory already set aside for in the GTT.
1391 */
1392 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1393 {
1394 int page_order;
1395 struct aper_size_info_fixed *size;
1396 int num_entries;
1397 u32 temp;
1398 int gtt_offset, gtt_size;
1399
1400 size = agp_bridge->current_size;
1401 page_order = size->page_order;
1402 num_entries = size->num_entries;
1403 agp_bridge->gatt_table_real = NULL;
1404
1405 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1406
1407 temp &= 0xfff00000;
1408
1409 intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
1410
1411 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1412
1413 if (!intel_private.gtt)
1414 return -ENOMEM;
1415
1416 intel_private.gtt_total_size = gtt_size / 4;
1417
1418 intel_private.registers = ioremap(temp, 128 * 4096);
1419 if (!intel_private.registers) {
1420 iounmap(intel_private.gtt);
1421 return -ENOMEM;
1422 }
1423
1424 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1425 global_cache_flush(); /* FIXME: ? */
1426
1427 /* we have to call this as early as possible after the MMIO base address is known */
1428 intel_i830_init_gtt_entries();
1429
1430 agp_bridge->gatt_table = NULL;
1431
1432 agp_bridge->gatt_bus_addr = temp;
1433
1434 return 0;
1435 }
1436
1437
1438 static int intel_fetch_size(void)
1439 {
1440 int i;
1441 u16 temp;
1442 struct aper_size_info_16 *values;
1443
1444 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1445 values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1446
1447 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1448 if (temp == values[i].size_value) {
1449 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1450 agp_bridge->aperture_size_idx = i;
1451 return values[i].size;
1452 }
1453 }
1454
1455 return 0;
1456 }
1457
1458 static int __intel_8xx_fetch_size(u8 temp)
1459 {
1460 int i;
1461 struct aper_size_info_8 *values;
1462
1463 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1464
1465 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1466 if (temp == values[i].size_value) {
1467 agp_bridge->previous_size =
1468 agp_bridge->current_size = (void *) (values + i);
1469 agp_bridge->aperture_size_idx = i;
1470 return values[i].size;
1471 }
1472 }
1473 return 0;
1474 }
1475
1476 static int intel_8xx_fetch_size(void)
1477 {
1478 u8 temp;
1479
1480 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1481 return __intel_8xx_fetch_size(temp);
1482 }
1483
1484 static int intel_815_fetch_size(void)
1485 {
1486 u8 temp;
1487
1488 /* Intel 815 chipsets have a _weird_ APSIZE register with only
1489 * one non-reserved bit, so mask the others out ... */
1490 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1491 temp &= (1 << 3);
1492
1493 return __intel_8xx_fetch_size(temp);
1494 }
1495
1496 static void intel_tlbflush(struct agp_memory *mem)
1497 {
1498 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1499 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1500 }
1501
1502
1503 static void intel_8xx_tlbflush(struct agp_memory *mem)
1504 {
1505 u32 temp;
1506 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1507 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1508 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1509 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1510 }
1511
1512
1513 static void intel_cleanup(void)
1514 {
1515 u16 temp;
1516 struct aper_size_info_16 *previous_size;
1517
1518 previous_size = A_SIZE_16(agp_bridge->previous_size);
1519 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1520 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1521 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1522 }
1523
1524
1525 static void intel_8xx_cleanup(void)
1526 {
1527 u16 temp;
1528 struct aper_size_info_8 *previous_size;
1529
1530 previous_size = A_SIZE_8(agp_bridge->previous_size);
1531 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1532 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1533 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1534 }
1535
1536
1537 static int intel_configure(void)
1538 {
1539 u32 temp;
1540 u16 temp2;
1541 struct aper_size_info_16 *current_size;
1542
1543 current_size = A_SIZE_16(agp_bridge->current_size);
1544
1545 /* aperture size */
1546 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1547
1548 /* address to map to */
1549 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1550 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1551
1552 /* attbase - aperture base */
1553 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1554
1555 /* agpctrl */
1556 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1557
1558 /* paccfg/nbxcfg */
1559 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1560 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1561 (temp2 & ~(1 << 10)) | (1 << 9));
1562 /* clear any possible error conditions */
1563 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1564 return 0;
1565 }
1566
1567 static int intel_815_configure(void)
1568 {
1569 u32 temp, addr;
1570 u8 temp2;
1571 struct aper_size_info_8 *current_size;
1572
1573 /* attbase - aperture base */
1574 /* the Intel 815 chipset spec. says that bits 29-31 in the
1575 * ATTBASE register are reserved -> try not to write them */
1576 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1577 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high");
1578 return -EINVAL;
1579 }
1580
1581 current_size = A_SIZE_8(agp_bridge->current_size);
1582
1583 /* aperture size */
1584 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1585 current_size->size_value);
1586
1587 /* address to map to */
1588 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1589 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1590
1591 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1592 addr &= INTEL_815_ATTBASE_MASK;
1593 addr |= agp_bridge->gatt_bus_addr;
1594 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1595
1596 /* agpctrl */
1597 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1598
1599 /* apcont */
1600 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1601 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1602
1603 /* clear any possible error conditions */
1604 /* Oddness : this chipset seems to have no ERRSTS register ! */
1605 return 0;
1606 }
1607
1608 static void intel_820_tlbflush(struct agp_memory *mem)
1609 {
1610 return;
1611 }
1612
1613 static void intel_820_cleanup(void)
1614 {
1615 u8 temp;
1616 struct aper_size_info_8 *previous_size;
1617
1618 previous_size = A_SIZE_8(agp_bridge->previous_size);
1619 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1620 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1621 temp & ~(1 << 1));
1622 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1623 previous_size->size_value);
1624 }
1625
1626
1627 static int intel_820_configure(void)
1628 {
1629 u32 temp;
1630 u8 temp2;
1631 struct aper_size_info_8 *current_size;
1632
1633 current_size = A_SIZE_8(agp_bridge->current_size);
1634
1635 /* aperture size */
1636 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1637
1638 /* address to map to */
1639 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1640 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1641
1642 /* attbase - aperture base */
1643 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1644
1645 /* agpctrl */
1646 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1647
1648 /* global enable aperture access */
1649 /* This flag is not accessed through MCHCFG register as in */
1650 /* i850 chipset. */
1651 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1652 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1653 /* clear any possible AGP-related error conditions */
1654 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1655 return 0;
1656 }
1657
1658 static int intel_840_configure(void)
1659 {
1660 u32 temp;
1661 u16 temp2;
1662 struct aper_size_info_8 *current_size;
1663
1664 current_size = A_SIZE_8(agp_bridge->current_size);
1665
1666 /* aperture size */
1667 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1668
1669 /* address to map to */
1670 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1671 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1672
1673 /* attbase - aperture base */
1674 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1675
1676 /* agpctrl */
1677 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1678
1679 /* mcgcfg */
1680 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1681 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1682 /* clear any possible error conditions */
1683 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1684 return 0;
1685 }
1686
1687 static int intel_845_configure(void)
1688 {
1689 u32 temp;
1690 u8 temp2;
1691 struct aper_size_info_8 *current_size;
1692
1693 current_size = A_SIZE_8(agp_bridge->current_size);
1694
1695 /* aperture size */
1696 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1697
1698 if (agp_bridge->apbase_config != 0) {
1699 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1700 agp_bridge->apbase_config);
1701 } else {
1702 /* address to map to */
1703 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1704 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1705 agp_bridge->apbase_config = temp;
1706 }
1707
1708 /* attbase - aperture base */
1709 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1710
1711 /* agpctrl */
1712 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1713
1714 /* agpm */
1715 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1716 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1717 /* clear any possible error conditions */
1718 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1719
1720 intel_i830_setup_flush();
1721 return 0;
1722 }
1723
1724 static int intel_850_configure(void)
1725 {
1726 u32 temp;
1727 u16 temp2;
1728 struct aper_size_info_8 *current_size;
1729
1730 current_size = A_SIZE_8(agp_bridge->current_size);
1731
1732 /* aperture size */
1733 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1734
1735 /* address to map to */
1736 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1737 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1738
1739 /* attbase - aperture base */
1740 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1741
1742 /* agpctrl */
1743 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1744
1745 /* mcgcfg */
1746 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1747 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1748 /* clear any possible AGP-related error conditions */
1749 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1750 return 0;
1751 }
1752
1753 static int intel_860_configure(void)
1754 {
1755 u32 temp;
1756 u16 temp2;
1757 struct aper_size_info_8 *current_size;
1758
1759 current_size = A_SIZE_8(agp_bridge->current_size);
1760
1761 /* aperture size */
1762 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1763
1764 /* address to map to */
1765 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1766 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1767
1768 /* attbase - aperture base */
1769 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1770
1771 /* agpctrl */
1772 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1773
1774 /* mcgcfg */
1775 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1776 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1777 /* clear any possible AGP-related error conditions */
1778 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1779 return 0;
1780 }
1781
1782 static int intel_830mp_configure(void)
1783 {
1784 u32 temp;
1785 u16 temp2;
1786 struct aper_size_info_8 *current_size;
1787
1788 current_size = A_SIZE_8(agp_bridge->current_size);
1789
1790 /* aperture size */
1791 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1792
1793 /* address to map to */
1794 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1795 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1796
1797 /* attbase - aperture base */
1798 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1799
1800 /* agpctrl */
1801 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1802
1803 /* gmch */
1804 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1805 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1806 /* clear any possible AGP-related error conditions */
1807 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1808 return 0;
1809 }
1810
1811 static int intel_7505_configure(void)
1812 {
1813 u32 temp;
1814 u16 temp2;
1815 struct aper_size_info_8 *current_size;
1816
1817 current_size = A_SIZE_8(agp_bridge->current_size);
1818
1819 /* aperture size */
1820 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1821
1822 /* address to map to */
1823 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1824 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1825
1826 /* attbase - aperture base */
1827 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1828
1829 /* agpctrl */
1830 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1831
1832 /* mchcfg */
1833 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1834 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1835
1836 return 0;
1837 }
1838
1839 /* Setup function */
1840 static const struct gatt_mask intel_generic_masks[] =
1841 {
1842 {.mask = 0x00000017, .type = 0}
1843 };
1844
1845 static const struct aper_size_info_8 intel_815_sizes[2] =
1846 {
1847 {64, 16384, 4, 0},
1848 {32, 8192, 3, 8},
1849 };
1850
1851 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1852 {
1853 {256, 65536, 6, 0},
1854 {128, 32768, 5, 32},
1855 {64, 16384, 4, 48},
1856 {32, 8192, 3, 56},
1857 {16, 4096, 2, 60},
1858 {8, 2048, 1, 62},
1859 {4, 1024, 0, 63}
1860 };
1861
1862 static const struct aper_size_info_16 intel_generic_sizes[7] =
1863 {
1864 {256, 65536, 6, 0},
1865 {128, 32768, 5, 32},
1866 {64, 16384, 4, 48},
1867 {32, 8192, 3, 56},
1868 {16, 4096, 2, 60},
1869 {8, 2048, 1, 62},
1870 {4, 1024, 0, 63}
1871 };
1872
1873 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1874 {
1875 {256, 65536, 6, 0},
1876 {128, 32768, 5, 32},
1877 {64, 16384, 4, 48},
1878 {32, 8192, 3, 56}
1879 };
1880
1881 static const struct agp_bridge_driver intel_generic_driver = {
1882 .owner = THIS_MODULE,
1883 .aperture_sizes = intel_generic_sizes,
1884 .size_type = U16_APER_SIZE,
1885 .num_aperture_sizes = 7,
1886 .configure = intel_configure,
1887 .fetch_size = intel_fetch_size,
1888 .cleanup = intel_cleanup,
1889 .tlb_flush = intel_tlbflush,
1890 .mask_memory = agp_generic_mask_memory,
1891 .masks = intel_generic_masks,
1892 .agp_enable = agp_generic_enable,
1893 .cache_flush = global_cache_flush,
1894 .create_gatt_table = agp_generic_create_gatt_table,
1895 .free_gatt_table = agp_generic_free_gatt_table,
1896 .insert_memory = agp_generic_insert_memory,
1897 .remove_memory = agp_generic_remove_memory,
1898 .alloc_by_type = agp_generic_alloc_by_type,
1899 .free_by_type = agp_generic_free_by_type,
1900 .agp_alloc_page = agp_generic_alloc_page,
1901 .agp_alloc_pages = agp_generic_alloc_pages,
1902 .agp_destroy_page = agp_generic_destroy_page,
1903 .agp_destroy_pages = agp_generic_destroy_pages,
1904 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1905 };
1906
1907 static const struct agp_bridge_driver intel_810_driver = {
1908 .owner = THIS_MODULE,
1909 .aperture_sizes = intel_i810_sizes,
1910 .size_type = FIXED_APER_SIZE,
1911 .num_aperture_sizes = 2,
1912 .needs_scratch_page = true,
1913 .configure = intel_i810_configure,
1914 .fetch_size = intel_i810_fetch_size,
1915 .cleanup = intel_i810_cleanup,
1916 .tlb_flush = intel_i810_tlbflush,
1917 .mask_memory = intel_i810_mask_memory,
1918 .masks = intel_i810_masks,
1919 .agp_enable = intel_i810_agp_enable,
1920 .cache_flush = global_cache_flush,
1921 .create_gatt_table = agp_generic_create_gatt_table,
1922 .free_gatt_table = agp_generic_free_gatt_table,
1923 .insert_memory = intel_i810_insert_entries,
1924 .remove_memory = intel_i810_remove_entries,
1925 .alloc_by_type = intel_i810_alloc_by_type,
1926 .free_by_type = intel_i810_free_by_type,
1927 .agp_alloc_page = agp_generic_alloc_page,
1928 .agp_alloc_pages = agp_generic_alloc_pages,
1929 .agp_destroy_page = agp_generic_destroy_page,
1930 .agp_destroy_pages = agp_generic_destroy_pages,
1931 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1932 };
1933
1934 static const struct agp_bridge_driver intel_815_driver = {
1935 .owner = THIS_MODULE,
1936 .aperture_sizes = intel_815_sizes,
1937 .size_type = U8_APER_SIZE,
1938 .num_aperture_sizes = 2,
1939 .configure = intel_815_configure,
1940 .fetch_size = intel_815_fetch_size,
1941 .cleanup = intel_8xx_cleanup,
1942 .tlb_flush = intel_8xx_tlbflush,
1943 .mask_memory = agp_generic_mask_memory,
1944 .masks = intel_generic_masks,
1945 .agp_enable = agp_generic_enable,
1946 .cache_flush = global_cache_flush,
1947 .create_gatt_table = agp_generic_create_gatt_table,
1948 .free_gatt_table = agp_generic_free_gatt_table,
1949 .insert_memory = agp_generic_insert_memory,
1950 .remove_memory = agp_generic_remove_memory,
1951 .alloc_by_type = agp_generic_alloc_by_type,
1952 .free_by_type = agp_generic_free_by_type,
1953 .agp_alloc_page = agp_generic_alloc_page,
1954 .agp_alloc_pages = agp_generic_alloc_pages,
1955 .agp_destroy_page = agp_generic_destroy_page,
1956 .agp_destroy_pages = agp_generic_destroy_pages,
1957 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1958 };
1959
1960 static const struct agp_bridge_driver intel_830_driver = {
1961 .owner = THIS_MODULE,
1962 .aperture_sizes = intel_i830_sizes,
1963 .size_type = FIXED_APER_SIZE,
1964 .num_aperture_sizes = 4,
1965 .needs_scratch_page = true,
1966 .configure = intel_i830_configure,
1967 .fetch_size = intel_i830_fetch_size,
1968 .cleanup = intel_i830_cleanup,
1969 .tlb_flush = intel_i810_tlbflush,
1970 .mask_memory = intel_i810_mask_memory,
1971 .masks = intel_i810_masks,
1972 .agp_enable = intel_i810_agp_enable,
1973 .cache_flush = global_cache_flush,
1974 .create_gatt_table = intel_i830_create_gatt_table,
1975 .free_gatt_table = intel_i830_free_gatt_table,
1976 .insert_memory = intel_i830_insert_entries,
1977 .remove_memory = intel_i830_remove_entries,
1978 .alloc_by_type = intel_i830_alloc_by_type,
1979 .free_by_type = intel_i810_free_by_type,
1980 .agp_alloc_page = agp_generic_alloc_page,
1981 .agp_alloc_pages = agp_generic_alloc_pages,
1982 .agp_destroy_page = agp_generic_destroy_page,
1983 .agp_destroy_pages = agp_generic_destroy_pages,
1984 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1985 .chipset_flush = intel_i830_chipset_flush,
1986 };
1987
1988 static const struct agp_bridge_driver intel_820_driver = {
1989 .owner = THIS_MODULE,
1990 .aperture_sizes = intel_8xx_sizes,
1991 .size_type = U8_APER_SIZE,
1992 .num_aperture_sizes = 7,
1993 .configure = intel_820_configure,
1994 .fetch_size = intel_8xx_fetch_size,
1995 .cleanup = intel_820_cleanup,
1996 .tlb_flush = intel_820_tlbflush,
1997 .mask_memory = agp_generic_mask_memory,
1998 .masks = intel_generic_masks,
1999 .agp_enable = agp_generic_enable,
2000 .cache_flush = global_cache_flush,
2001 .create_gatt_table = agp_generic_create_gatt_table,
2002 .free_gatt_table = agp_generic_free_gatt_table,
2003 .insert_memory = agp_generic_insert_memory,
2004 .remove_memory = agp_generic_remove_memory,
2005 .alloc_by_type = agp_generic_alloc_by_type,
2006 .free_by_type = agp_generic_free_by_type,
2007 .agp_alloc_page = agp_generic_alloc_page,
2008 .agp_alloc_pages = agp_generic_alloc_pages,
2009 .agp_destroy_page = agp_generic_destroy_page,
2010 .agp_destroy_pages = agp_generic_destroy_pages,
2011 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2012 };
2013
2014 static const struct agp_bridge_driver intel_830mp_driver = {
2015 .owner = THIS_MODULE,
2016 .aperture_sizes = intel_830mp_sizes,
2017 .size_type = U8_APER_SIZE,
2018 .num_aperture_sizes = 4,
2019 .configure = intel_830mp_configure,
2020 .fetch_size = intel_8xx_fetch_size,
2021 .cleanup = intel_8xx_cleanup,
2022 .tlb_flush = intel_8xx_tlbflush,
2023 .mask_memory = agp_generic_mask_memory,
2024 .masks = intel_generic_masks,
2025 .agp_enable = agp_generic_enable,
2026 .cache_flush = global_cache_flush,
2027 .create_gatt_table = agp_generic_create_gatt_table,
2028 .free_gatt_table = agp_generic_free_gatt_table,
2029 .insert_memory = agp_generic_insert_memory,
2030 .remove_memory = agp_generic_remove_memory,
2031 .alloc_by_type = agp_generic_alloc_by_type,
2032 .free_by_type = agp_generic_free_by_type,
2033 .agp_alloc_page = agp_generic_alloc_page,
2034 .agp_alloc_pages = agp_generic_alloc_pages,
2035 .agp_destroy_page = agp_generic_destroy_page,
2036 .agp_destroy_pages = agp_generic_destroy_pages,
2037 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2038 };
2039
2040 static const struct agp_bridge_driver intel_840_driver = {
2041 .owner = THIS_MODULE,
2042 .aperture_sizes = intel_8xx_sizes,
2043 .size_type = U8_APER_SIZE,
2044 .num_aperture_sizes = 7,
2045 .configure = intel_840_configure,
2046 .fetch_size = intel_8xx_fetch_size,
2047 .cleanup = intel_8xx_cleanup,
2048 .tlb_flush = intel_8xx_tlbflush,
2049 .mask_memory = agp_generic_mask_memory,
2050 .masks = intel_generic_masks,
2051 .agp_enable = agp_generic_enable,
2052 .cache_flush = global_cache_flush,
2053 .create_gatt_table = agp_generic_create_gatt_table,
2054 .free_gatt_table = agp_generic_free_gatt_table,
2055 .insert_memory = agp_generic_insert_memory,
2056 .remove_memory = agp_generic_remove_memory,
2057 .alloc_by_type = agp_generic_alloc_by_type,
2058 .free_by_type = agp_generic_free_by_type,
2059 .agp_alloc_page = agp_generic_alloc_page,
2060 .agp_alloc_pages = agp_generic_alloc_pages,
2061 .agp_destroy_page = agp_generic_destroy_page,
2062 .agp_destroy_pages = agp_generic_destroy_pages,
2063 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2064 };
2065
2066 static const struct agp_bridge_driver intel_845_driver = {
2067 .owner = THIS_MODULE,
2068 .aperture_sizes = intel_8xx_sizes,
2069 .size_type = U8_APER_SIZE,
2070 .num_aperture_sizes = 7,
2071 .configure = intel_845_configure,
2072 .fetch_size = intel_8xx_fetch_size,
2073 .cleanup = intel_8xx_cleanup,
2074 .tlb_flush = intel_8xx_tlbflush,
2075 .mask_memory = agp_generic_mask_memory,
2076 .masks = intel_generic_masks,
2077 .agp_enable = agp_generic_enable,
2078 .cache_flush = global_cache_flush,
2079 .create_gatt_table = agp_generic_create_gatt_table,
2080 .free_gatt_table = agp_generic_free_gatt_table,
2081 .insert_memory = agp_generic_insert_memory,
2082 .remove_memory = agp_generic_remove_memory,
2083 .alloc_by_type = agp_generic_alloc_by_type,
2084 .free_by_type = agp_generic_free_by_type,
2085 .agp_alloc_page = agp_generic_alloc_page,
2086 .agp_alloc_pages = agp_generic_alloc_pages,
2087 .agp_destroy_page = agp_generic_destroy_page,
2088 .agp_destroy_pages = agp_generic_destroy_pages,
2089 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2090 .chipset_flush = intel_i830_chipset_flush,
2091 };
2092
2093 static const struct agp_bridge_driver intel_850_driver = {
2094 .owner = THIS_MODULE,
2095 .aperture_sizes = intel_8xx_sizes,
2096 .size_type = U8_APER_SIZE,
2097 .num_aperture_sizes = 7,
2098 .configure = intel_850_configure,
2099 .fetch_size = intel_8xx_fetch_size,
2100 .cleanup = intel_8xx_cleanup,
2101 .tlb_flush = intel_8xx_tlbflush,
2102 .mask_memory = agp_generic_mask_memory,
2103 .masks = intel_generic_masks,
2104 .agp_enable = agp_generic_enable,
2105 .cache_flush = global_cache_flush,
2106 .create_gatt_table = agp_generic_create_gatt_table,
2107 .free_gatt_table = agp_generic_free_gatt_table,
2108 .insert_memory = agp_generic_insert_memory,
2109 .remove_memory = agp_generic_remove_memory,
2110 .alloc_by_type = agp_generic_alloc_by_type,
2111 .free_by_type = agp_generic_free_by_type,
2112 .agp_alloc_page = agp_generic_alloc_page,
2113 .agp_alloc_pages = agp_generic_alloc_pages,
2114 .agp_destroy_page = agp_generic_destroy_page,
2115 .agp_destroy_pages = agp_generic_destroy_pages,
2116 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2117 };
2118
2119 static const struct agp_bridge_driver intel_860_driver = {
2120 .owner = THIS_MODULE,
2121 .aperture_sizes = intel_8xx_sizes,
2122 .size_type = U8_APER_SIZE,
2123 .num_aperture_sizes = 7,
2124 .configure = intel_860_configure,
2125 .fetch_size = intel_8xx_fetch_size,
2126 .cleanup = intel_8xx_cleanup,
2127 .tlb_flush = intel_8xx_tlbflush,
2128 .mask_memory = agp_generic_mask_memory,
2129 .masks = intel_generic_masks,
2130 .agp_enable = agp_generic_enable,
2131 .cache_flush = global_cache_flush,
2132 .create_gatt_table = agp_generic_create_gatt_table,
2133 .free_gatt_table = agp_generic_free_gatt_table,
2134 .insert_memory = agp_generic_insert_memory,
2135 .remove_memory = agp_generic_remove_memory,
2136 .alloc_by_type = agp_generic_alloc_by_type,
2137 .free_by_type = agp_generic_free_by_type,
2138 .agp_alloc_page = agp_generic_alloc_page,
2139 .agp_alloc_pages = agp_generic_alloc_pages,
2140 .agp_destroy_page = agp_generic_destroy_page,
2141 .agp_destroy_pages = agp_generic_destroy_pages,
2142 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2143 };
2144
2145 static const struct agp_bridge_driver intel_915_driver = {
2146 .owner = THIS_MODULE,
2147 .aperture_sizes = intel_i830_sizes,
2148 .size_type = FIXED_APER_SIZE,
2149 .num_aperture_sizes = 4,
2150 .needs_scratch_page = true,
2151 .configure = intel_i915_configure,
2152 .fetch_size = intel_i9xx_fetch_size,
2153 .cleanup = intel_i915_cleanup,
2154 .tlb_flush = intel_i810_tlbflush,
2155 .mask_memory = intel_i810_mask_memory,
2156 .masks = intel_i810_masks,
2157 .agp_enable = intel_i810_agp_enable,
2158 .cache_flush = global_cache_flush,
2159 .create_gatt_table = intel_i915_create_gatt_table,
2160 .free_gatt_table = intel_i830_free_gatt_table,
2161 .insert_memory = intel_i915_insert_entries,
2162 .remove_memory = intel_i915_remove_entries,
2163 .alloc_by_type = intel_i830_alloc_by_type,
2164 .free_by_type = intel_i810_free_by_type,
2165 .agp_alloc_page = agp_generic_alloc_page,
2166 .agp_alloc_pages = agp_generic_alloc_pages,
2167 .agp_destroy_page = agp_generic_destroy_page,
2168 .agp_destroy_pages = agp_generic_destroy_pages,
2169 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
2170 .chipset_flush = intel_i915_chipset_flush,
2171 #ifdef USE_PCI_DMA_API
2172 .agp_map_page = intel_agp_map_page,
2173 .agp_unmap_page = intel_agp_unmap_page,
2174 .agp_map_memory = intel_agp_map_memory,
2175 .agp_unmap_memory = intel_agp_unmap_memory,
2176 #endif
2177 };
2178
2179 static const struct agp_bridge_driver intel_i965_driver = {
2180 .owner = THIS_MODULE,
2181 .aperture_sizes = intel_i830_sizes,
2182 .size_type = FIXED_APER_SIZE,
2183 .num_aperture_sizes = 4,
2184 .needs_scratch_page = true,
2185 .configure = intel_i915_configure,
2186 .fetch_size = intel_i9xx_fetch_size,
2187 .cleanup = intel_i915_cleanup,
2188 .tlb_flush = intel_i810_tlbflush,
2189 .mask_memory = intel_i965_mask_memory,
2190 .masks = intel_i810_masks,
2191 .agp_enable = intel_i810_agp_enable,
2192 .cache_flush = global_cache_flush,
2193 .create_gatt_table = intel_i965_create_gatt_table,
2194 .free_gatt_table = intel_i830_free_gatt_table,
2195 .insert_memory = intel_i915_insert_entries,
2196 .remove_memory = intel_i915_remove_entries,
2197 .alloc_by_type = intel_i830_alloc_by_type,
2198 .free_by_type = intel_i810_free_by_type,
2199 .agp_alloc_page = agp_generic_alloc_page,
2200 .agp_alloc_pages = agp_generic_alloc_pages,
2201 .agp_destroy_page = agp_generic_destroy_page,
2202 .agp_destroy_pages = agp_generic_destroy_pages,
2203 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
2204 .chipset_flush = intel_i915_chipset_flush,
2205 #ifdef USE_PCI_DMA_API
2206 .agp_map_page = intel_agp_map_page,
2207 .agp_unmap_page = intel_agp_unmap_page,
2208 .agp_map_memory = intel_agp_map_memory,
2209 .agp_unmap_memory = intel_agp_unmap_memory,
2210 #endif
2211 };
2212
2213 static const struct agp_bridge_driver intel_7505_driver = {
2214 .owner = THIS_MODULE,
2215 .aperture_sizes = intel_8xx_sizes,
2216 .size_type = U8_APER_SIZE,
2217 .num_aperture_sizes = 7,
2218 .configure = intel_7505_configure,
2219 .fetch_size = intel_8xx_fetch_size,
2220 .cleanup = intel_8xx_cleanup,
2221 .tlb_flush = intel_8xx_tlbflush,
2222 .mask_memory = agp_generic_mask_memory,
2223 .masks = intel_generic_masks,
2224 .agp_enable = agp_generic_enable,
2225 .cache_flush = global_cache_flush,
2226 .create_gatt_table = agp_generic_create_gatt_table,
2227 .free_gatt_table = agp_generic_free_gatt_table,
2228 .insert_memory = agp_generic_insert_memory,
2229 .remove_memory = agp_generic_remove_memory,
2230 .alloc_by_type = agp_generic_alloc_by_type,
2231 .free_by_type = agp_generic_free_by_type,
2232 .agp_alloc_page = agp_generic_alloc_page,
2233 .agp_alloc_pages = agp_generic_alloc_pages,
2234 .agp_destroy_page = agp_generic_destroy_page,
2235 .agp_destroy_pages = agp_generic_destroy_pages,
2236 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2237 };
2238
2239 static const struct agp_bridge_driver intel_g33_driver = {
2240 .owner = THIS_MODULE,
2241 .aperture_sizes = intel_i830_sizes,
2242 .size_type = FIXED_APER_SIZE,
2243 .num_aperture_sizes = 4,
2244 .needs_scratch_page = true,
2245 .configure = intel_i915_configure,
2246 .fetch_size = intel_i9xx_fetch_size,
2247 .cleanup = intel_i915_cleanup,
2248 .tlb_flush = intel_i810_tlbflush,
2249 .mask_memory = intel_i965_mask_memory,
2250 .masks = intel_i810_masks,
2251 .agp_enable = intel_i810_agp_enable,
2252 .cache_flush = global_cache_flush,
2253 .create_gatt_table = intel_i915_create_gatt_table,
2254 .free_gatt_table = intel_i830_free_gatt_table,
2255 .insert_memory = intel_i915_insert_entries,
2256 .remove_memory = intel_i915_remove_entries,
2257 .alloc_by_type = intel_i830_alloc_by_type,
2258 .free_by_type = intel_i810_free_by_type,
2259 .agp_alloc_page = agp_generic_alloc_page,
2260 .agp_alloc_pages = agp_generic_alloc_pages,
2261 .agp_destroy_page = agp_generic_destroy_page,
2262 .agp_destroy_pages = agp_generic_destroy_pages,
2263 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
2264 .chipset_flush = intel_i915_chipset_flush,
2265 #ifdef USE_PCI_DMA_API
2266 .agp_map_page = intel_agp_map_page,
2267 .agp_unmap_page = intel_agp_unmap_page,
2268 .agp_map_memory = intel_agp_map_memory,
2269 .agp_unmap_memory = intel_agp_unmap_memory,
2270 #endif
2271 };
2272
2273 static int find_gmch(u16 device)
2274 {
2275 struct pci_dev *gmch_device;
2276
2277 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
2278 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
2279 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
2280 device, gmch_device);
2281 }
2282
2283 if (!gmch_device)
2284 return 0;
2285
2286 intel_private.pcidev = gmch_device;
2287 return 1;
2288 }
2289
2290 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
2291 * driver and gmch_driver must be non-null, and find_gmch will determine
2292 * which one should be used if a gmch_chip_id is present.
2293 */
2294 static const struct intel_driver_description {
2295 unsigned int chip_id;
2296 unsigned int gmch_chip_id;
2297 unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
2298 char *name;
2299 const struct agp_bridge_driver *driver;
2300 const struct agp_bridge_driver *gmch_driver;
2301 } intel_agp_chipsets[] = {
2302 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
2303 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
2304 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
2305 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
2306 NULL, &intel_810_driver },
2307 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
2308 NULL, &intel_810_driver },
2309 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
2310 NULL, &intel_810_driver },
2311 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
2312 &intel_815_driver, &intel_810_driver },
2313 { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
2314 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
2315 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
2316 &intel_830mp_driver, &intel_830_driver },
2317 { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
2318 { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
2319 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
2320 &intel_845_driver, &intel_830_driver },
2321 { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
2322 { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854",
2323 &intel_845_driver, &intel_830_driver },
2324 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2325 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
2326 &intel_845_driver, &intel_830_driver },
2327 { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2328 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
2329 &intel_845_driver, &intel_830_driver },
2330 { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
2331 { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2332 NULL, &intel_915_driver },
2333 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
2334 NULL, &intel_915_driver },
2335 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
2336 NULL, &intel_915_driver },
2337 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
2338 NULL, &intel_915_driver },
2339 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
2340 NULL, &intel_915_driver },
2341 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
2342 NULL, &intel_915_driver },
2343 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
2344 NULL, &intel_i965_driver },
2345 { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35",
2346 NULL, &intel_i965_driver },
2347 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
2348 NULL, &intel_i965_driver },
2349 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
2350 NULL, &intel_i965_driver },
2351 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
2352 NULL, &intel_i965_driver },
2353 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
2354 NULL, &intel_i965_driver },
2355 { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2356 { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2357 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
2358 NULL, &intel_g33_driver },
2359 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
2360 NULL, &intel_g33_driver },
2361 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
2362 NULL, &intel_g33_driver },
2363 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, 0, "GMA3150",
2364 NULL, &intel_g33_driver },
2365 { PCI_DEVICE_ID_INTEL_PINEVIEW_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_IG, 0, "GMA3150",
2366 NULL, &intel_g33_driver },
2367 { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0,
2368 "GM45", NULL, &intel_i965_driver },
2369 { PCI_DEVICE_ID_INTEL_EAGLELAKE_HB, PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, 0,
2370 "Eaglelake", NULL, &intel_i965_driver },
2371 { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
2372 "Q45/Q43", NULL, &intel_i965_driver },
2373 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
2374 "G45/G43", NULL, &intel_i965_driver },
2375 { PCI_DEVICE_ID_INTEL_B43_HB, PCI_DEVICE_ID_INTEL_B43_IG, 0,
2376 "B43", NULL, &intel_i965_driver },
2377 { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0,
2378 "G41", NULL, &intel_i965_driver },
2379 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, 0,
2380 "HD Graphics", NULL, &intel_i965_driver },
2381 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0,
2382 "HD Graphics", NULL, &intel_i965_driver },
2383 { PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0,
2384 "HD Graphics", NULL, &intel_i965_driver },
2385 { PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0,
2386 "HD Graphics", NULL, &intel_i965_driver },
2387 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG, 0,
2388 "Sandybridge", NULL, &intel_i965_driver },
2389 { 0, 0, 0, NULL, NULL, NULL }
2390 };
2391
2392 static int __devinit agp_intel_probe(struct pci_dev *pdev,
2393 const struct pci_device_id *ent)
2394 {
2395 struct agp_bridge_data *bridge;
2396 u8 cap_ptr = 0;
2397 struct resource *r;
2398 int i;
2399
2400 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2401
2402 bridge = agp_alloc_bridge();
2403 if (!bridge)
2404 return -ENOMEM;
2405
2406 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2407 /* In case that multiple models of gfx chip may
2408 stand on same host bridge type, this can be
2409 sure we detect the right IGD. */
2410 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2411 if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2412 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2413 bridge->driver =
2414 intel_agp_chipsets[i].gmch_driver;
2415 break;
2416 } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2417 continue;
2418 } else {
2419 bridge->driver = intel_agp_chipsets[i].driver;
2420 break;
2421 }
2422 }
2423 }
2424
2425 if (intel_agp_chipsets[i].name == NULL) {
2426 if (cap_ptr)
2427 dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
2428 pdev->vendor, pdev->device);
2429 agp_put_bridge(bridge);
2430 return -ENODEV;
2431 }
2432
2433 if (bridge->driver == NULL) {
2434 /* bridge has no AGP and no IGD detected */
2435 if (cap_ptr)
2436 dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n",
2437 intel_agp_chipsets[i].gmch_chip_id);
2438 agp_put_bridge(bridge);
2439 return -ENODEV;
2440 }
2441
2442 bridge->dev = pdev;
2443 bridge->capndx = cap_ptr;
2444 bridge->dev_private_data = &intel_private;
2445
2446 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
2447
2448 /*
2449 * The following fixes the case where the BIOS has "forgotten" to
2450 * provide an address range for the GART.
2451 * 20030610 - hamish@zot.org
2452 */
2453 r = &pdev->resource[0];
2454 if (!r->start && r->end) {
2455 if (pci_assign_resource(pdev, 0)) {
2456 dev_err(&pdev->dev, "can't assign resource 0\n");
2457 agp_put_bridge(bridge);
2458 return -ENODEV;
2459 }
2460 }
2461
2462 /*
2463 * If the device has not been properly setup, the following will catch
2464 * the problem and should stop the system from crashing.
2465 * 20030610 - hamish@zot.org
2466 */
2467 if (pci_enable_device(pdev)) {
2468 dev_err(&pdev->dev, "can't enable PCI device\n");
2469 agp_put_bridge(bridge);
2470 return -ENODEV;
2471 }
2472
2473 /* Fill in the mode register */
2474 if (cap_ptr) {
2475 pci_read_config_dword(pdev,
2476 bridge->capndx+PCI_AGP_STATUS,
2477 &bridge->mode);
2478 }
2479
2480 if (bridge->driver->mask_memory == intel_i965_mask_memory) {
2481 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(36)))
2482 dev_err(&intel_private.pcidev->dev,
2483 "set gfx device dma mask 36bit failed!\n");
2484 else
2485 pci_set_consistent_dma_mask(intel_private.pcidev,
2486 DMA_BIT_MASK(36));
2487 }
2488
2489 pci_set_drvdata(pdev, bridge);
2490 return agp_add_bridge(bridge);
2491 }
2492
2493 static void __devexit agp_intel_remove(struct pci_dev *pdev)
2494 {
2495 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2496
2497 agp_remove_bridge(bridge);
2498
2499 if (intel_private.pcidev)
2500 pci_dev_put(intel_private.pcidev);
2501
2502 agp_put_bridge(bridge);
2503 }
2504
2505 #ifdef CONFIG_PM
2506 static int agp_intel_resume(struct pci_dev *pdev)
2507 {
2508 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2509 int ret_val;
2510
2511 if (bridge->driver == &intel_generic_driver)
2512 intel_configure();
2513 else if (bridge->driver == &intel_850_driver)
2514 intel_850_configure();
2515 else if (bridge->driver == &intel_845_driver)
2516 intel_845_configure();
2517 else if (bridge->driver == &intel_830mp_driver)
2518 intel_830mp_configure();
2519 else if (bridge->driver == &intel_915_driver)
2520 intel_i915_configure();
2521 else if (bridge->driver == &intel_830_driver)
2522 intel_i830_configure();
2523 else if (bridge->driver == &intel_810_driver)
2524 intel_i810_configure();
2525 else if (bridge->driver == &intel_i965_driver)
2526 intel_i915_configure();
2527
2528 ret_val = agp_rebind_memory();
2529 if (ret_val != 0)
2530 return ret_val;
2531
2532 return 0;
2533 }
2534 #endif
2535
2536 static struct pci_device_id agp_intel_pci_table[] = {
2537 #define ID(x) \
2538 { \
2539 .class = (PCI_CLASS_BRIDGE_HOST << 8), \
2540 .class_mask = ~0, \
2541 .vendor = PCI_VENDOR_ID_INTEL, \
2542 .device = x, \
2543 .subvendor = PCI_ANY_ID, \
2544 .subdevice = PCI_ANY_ID, \
2545 }
2546 ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2547 ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2548 ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2549 ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2550 ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2551 ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2552 ID(PCI_DEVICE_ID_INTEL_82815_MC),
2553 ID(PCI_DEVICE_ID_INTEL_82820_HB),
2554 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2555 ID(PCI_DEVICE_ID_INTEL_82830_HB),
2556 ID(PCI_DEVICE_ID_INTEL_82840_HB),
2557 ID(PCI_DEVICE_ID_INTEL_82845_HB),
2558 ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2559 ID(PCI_DEVICE_ID_INTEL_82850_HB),
2560 ID(PCI_DEVICE_ID_INTEL_82854_HB),
2561 ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2562 ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2563 ID(PCI_DEVICE_ID_INTEL_82860_HB),
2564 ID(PCI_DEVICE_ID_INTEL_82865_HB),
2565 ID(PCI_DEVICE_ID_INTEL_82875_HB),
2566 ID(PCI_DEVICE_ID_INTEL_7505_0),
2567 ID(PCI_DEVICE_ID_INTEL_7205_0),
2568 ID(PCI_DEVICE_ID_INTEL_E7221_HB),
2569 ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2570 ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2571 ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2572 ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2573 ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2574 ID(PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB),
2575 ID(PCI_DEVICE_ID_INTEL_PINEVIEW_HB),
2576 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2577 ID(PCI_DEVICE_ID_INTEL_82G35_HB),
2578 ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2579 ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2580 ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2581 ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2582 ID(PCI_DEVICE_ID_INTEL_G33_HB),
2583 ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2584 ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2585 ID(PCI_DEVICE_ID_INTEL_GM45_HB),
2586 ID(PCI_DEVICE_ID_INTEL_EAGLELAKE_HB),
2587 ID(PCI_DEVICE_ID_INTEL_Q45_HB),
2588 ID(PCI_DEVICE_ID_INTEL_G45_HB),
2589 ID(PCI_DEVICE_ID_INTEL_G41_HB),
2590 ID(PCI_DEVICE_ID_INTEL_B43_HB),
2591 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB),
2592 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB),
2593 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB),
2594 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB),
2595 ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB),
2596 { }
2597 };
2598
2599 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2600
2601 static struct pci_driver agp_intel_pci_driver = {
2602 .name = "agpgart-intel",
2603 .id_table = agp_intel_pci_table,
2604 .probe = agp_intel_probe,
2605 .remove = __devexit_p(agp_intel_remove),
2606 #ifdef CONFIG_PM
2607 .resume = agp_intel_resume,
2608 #endif
2609 };
2610
2611 static int __init agp_intel_init(void)
2612 {
2613 if (agp_off)
2614 return -EINVAL;
2615 return pci_register_driver(&agp_intel_pci_driver);
2616 }
2617
2618 static void __exit agp_intel_cleanup(void)
2619 {
2620 pci_unregister_driver(&agp_intel_pci_driver);
2621 }
2622
2623 module_init(agp_intel_init);
2624 module_exit(agp_intel_cleanup);
2625
2626 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
2627 MODULE_LICENSE("GPL and additional rights");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree