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drm/radeon/kms: add new NI pci ids
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / mfd / max8997-irq.c
blob638bf7e4d3b38b613a188d08e655d09389516626
1 /*
2 * max8997-irq.c - Interrupt controller support for MAX8997
3 *
4 * Copyright (C) 2011 Samsung Electronics Co.Ltd
5 * MyungJoo Ham <myungjoo.ham@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 * This driver is based on max8998-irq.c
22 */
23
24 #include <linux/err.h>
25 #include <linux/irq.h>
26 #include <linux/interrupt.h>
27 #include <linux/mfd/max8997.h>
28 #include <linux/mfd/max8997-private.h>
29
30 static const u8 max8997_mask_reg[] = {
31 [PMIC_INT1] = MAX8997_REG_INT1MSK,
32 [PMIC_INT2] = MAX8997_REG_INT2MSK,
33 [PMIC_INT3] = MAX8997_REG_INT3MSK,
34 [PMIC_INT4] = MAX8997_REG_INT4MSK,
35 [FUEL_GAUGE] = MAX8997_REG_INVALID,
36 [MUIC_INT1] = MAX8997_MUIC_REG_INTMASK1,
37 [MUIC_INT2] = MAX8997_MUIC_REG_INTMASK2,
38 [MUIC_INT3] = MAX8997_MUIC_REG_INTMASK3,
39 [GPIO_LOW] = MAX8997_REG_INVALID,
40 [GPIO_HI] = MAX8997_REG_INVALID,
41 [FLASH_STATUS] = MAX8997_REG_INVALID,
42 };
43
44 static struct i2c_client *get_i2c(struct max8997_dev *max8997,
45 enum max8997_irq_source src)
46 {
47 switch (src) {
48 case PMIC_INT1 ... PMIC_INT4:
49 return max8997->i2c;
50 case FUEL_GAUGE:
51 return NULL;
52 case MUIC_INT1 ... MUIC_INT3:
53 return max8997->muic;
54 case GPIO_LOW ... GPIO_HI:
55 return max8997->i2c;
56 case FLASH_STATUS:
57 return max8997->i2c;
58 default:
59 return ERR_PTR(-EINVAL);
60 }
61
62 return ERR_PTR(-EINVAL);
63 }
64
65 struct max8997_irq_data {
66 int mask;
67 enum max8997_irq_source group;
68 };
69
70 #define DECLARE_IRQ(idx, _group, _mask) \
71 [(idx)] = { .group = (_group), .mask = (_mask) }
72 static const struct max8997_irq_data max8997_irqs[] = {
73 DECLARE_IRQ(MAX8997_PMICIRQ_PWRONR, PMIC_INT1, 1 << 0),
74 DECLARE_IRQ(MAX8997_PMICIRQ_PWRONF, PMIC_INT1, 1 << 1),
75 DECLARE_IRQ(MAX8997_PMICIRQ_PWRON1SEC, PMIC_INT1, 1 << 3),
76 DECLARE_IRQ(MAX8997_PMICIRQ_JIGONR, PMIC_INT1, 1 << 4),
77 DECLARE_IRQ(MAX8997_PMICIRQ_JIGONF, PMIC_INT1, 1 << 5),
78 DECLARE_IRQ(MAX8997_PMICIRQ_LOWBAT2, PMIC_INT1, 1 << 6),
79 DECLARE_IRQ(MAX8997_PMICIRQ_LOWBAT1, PMIC_INT1, 1 << 7),
80
81 DECLARE_IRQ(MAX8997_PMICIRQ_JIGR, PMIC_INT2, 1 << 0),
82 DECLARE_IRQ(MAX8997_PMICIRQ_JIGF, PMIC_INT2, 1 << 1),
83 DECLARE_IRQ(MAX8997_PMICIRQ_MR, PMIC_INT2, 1 << 2),
84 DECLARE_IRQ(MAX8997_PMICIRQ_DVS1OK, PMIC_INT2, 1 << 3),
85 DECLARE_IRQ(MAX8997_PMICIRQ_DVS2OK, PMIC_INT2, 1 << 4),
86 DECLARE_IRQ(MAX8997_PMICIRQ_DVS3OK, PMIC_INT2, 1 << 5),
87 DECLARE_IRQ(MAX8997_PMICIRQ_DVS4OK, PMIC_INT2, 1 << 6),
88
89 DECLARE_IRQ(MAX8997_PMICIRQ_CHGINS, PMIC_INT3, 1 << 0),
90 DECLARE_IRQ(MAX8997_PMICIRQ_CHGRM, PMIC_INT3, 1 << 1),
91 DECLARE_IRQ(MAX8997_PMICIRQ_DCINOVP, PMIC_INT3, 1 << 2),
92 DECLARE_IRQ(MAX8997_PMICIRQ_TOPOFFR, PMIC_INT3, 1 << 3),
93 DECLARE_IRQ(MAX8997_PMICIRQ_CHGRSTF, PMIC_INT3, 1 << 5),
94 DECLARE_IRQ(MAX8997_PMICIRQ_MBCHGTMEXPD, PMIC_INT3, 1 << 7),
95
96 DECLARE_IRQ(MAX8997_PMICIRQ_RTC60S, PMIC_INT4, 1 << 0),
97 DECLARE_IRQ(MAX8997_PMICIRQ_RTCA1, PMIC_INT4, 1 << 1),
98 DECLARE_IRQ(MAX8997_PMICIRQ_RTCA2, PMIC_INT4, 1 << 2),
99 DECLARE_IRQ(MAX8997_PMICIRQ_SMPL_INT, PMIC_INT4, 1 << 3),
100 DECLARE_IRQ(MAX8997_PMICIRQ_RTC1S, PMIC_INT4, 1 << 4),
101 DECLARE_IRQ(MAX8997_PMICIRQ_WTSR, PMIC_INT4, 1 << 5),
102
103 DECLARE_IRQ(MAX8997_MUICIRQ_ADCError, MUIC_INT1, 1 << 2),
104 DECLARE_IRQ(MAX8997_MUICIRQ_ADCLow, MUIC_INT1, 1 << 1),
105 DECLARE_IRQ(MAX8997_MUICIRQ_ADC, MUIC_INT1, 1 << 0),
106
107 DECLARE_IRQ(MAX8997_MUICIRQ_VBVolt, MUIC_INT2, 1 << 4),
108 DECLARE_IRQ(MAX8997_MUICIRQ_DBChg, MUIC_INT2, 1 << 3),
109 DECLARE_IRQ(MAX8997_MUICIRQ_DCDTmr, MUIC_INT2, 1 << 2),
110 DECLARE_IRQ(MAX8997_MUICIRQ_ChgDetRun, MUIC_INT2, 1 << 1),
111 DECLARE_IRQ(MAX8997_MUICIRQ_ChgTyp, MUIC_INT2, 1 << 0),
112
113 DECLARE_IRQ(MAX8997_MUICIRQ_OVP, MUIC_INT3, 1 << 2),
114 };
115
116 static void max8997_irq_lock(struct irq_data *data)
117 {
118 struct max8997_dev *max8997 = irq_get_chip_data(data->irq);
119
120 mutex_lock(&max8997->irqlock);
121 }
122
123 static void max8997_irq_sync_unlock(struct irq_data *data)
124 {
125 struct max8997_dev *max8997 = irq_get_chip_data(data->irq);
126 int i;
127
128 for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++) {
129 u8 mask_reg = max8997_mask_reg[i];
130 struct i2c_client *i2c = get_i2c(max8997, i);
131
132 if (mask_reg == MAX8997_REG_INVALID ||
133 IS_ERR_OR_NULL(i2c))
134 continue;
135 max8997->irq_masks_cache[i] = max8997->irq_masks_cur[i];
136
137 max8997_write_reg(i2c, max8997_mask_reg[i],
138 max8997->irq_masks_cur[i]);
139 }
140
141 mutex_unlock(&max8997->irqlock);
142 }
143
144 static const inline struct max8997_irq_data *
145 irq_to_max8997_irq(struct max8997_dev *max8997, int irq)
146 {
147 return &max8997_irqs[irq - max8997->irq_base];
148 }
149
150 static void max8997_irq_mask(struct irq_data *data)
151 {
152 struct max8997_dev *max8997 = irq_get_chip_data(data->irq);
153 const struct max8997_irq_data *irq_data = irq_to_max8997_irq(max8997,
154 data->irq);
155
156 max8997->irq_masks_cur[irq_data->group] |= irq_data->mask;
157 }
158
159 static void max8997_irq_unmask(struct irq_data *data)
160 {
161 struct max8997_dev *max8997 = irq_get_chip_data(data->irq);
162 const struct max8997_irq_data *irq_data = irq_to_max8997_irq(max8997,
163 data->irq);
164
165 max8997->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
166 }
167
168 static struct irq_chip max8997_irq_chip = {
169 .name = "max8997",
170 .irq_bus_lock = max8997_irq_lock,
171 .irq_bus_sync_unlock = max8997_irq_sync_unlock,
172 .irq_mask = max8997_irq_mask,
173 .irq_unmask = max8997_irq_unmask,
174 };
175
176 #define MAX8997_IRQSRC_PMIC (1 << 1)
177 #define MAX8997_IRQSRC_FUELGAUGE (1 << 2)
178 #define MAX8997_IRQSRC_MUIC (1 << 3)
179 #define MAX8997_IRQSRC_GPIO (1 << 4)
180 #define MAX8997_IRQSRC_FLASH (1 << 5)
181 static irqreturn_t max8997_irq_thread(int irq, void *data)
182 {
183 struct max8997_dev *max8997 = data;
184 u8 irq_reg[MAX8997_IRQ_GROUP_NR] = {};
185 u8 irq_src;
186 int ret;
187 int i;
188
189 ret = max8997_read_reg(max8997->i2c, MAX8997_REG_INTSRC, &irq_src);
190 if (ret < 0) {
191 dev_err(max8997->dev, "Failed to read interrupt source: %d\n",
192 ret);
193 return IRQ_NONE;
194 }
195
196 if (irq_src & MAX8997_IRQSRC_PMIC) {
197 /* PMIC INT1 ~ INT4 */
198 max8997_bulk_read(max8997->i2c, MAX8997_REG_INT1, 4,
199 &irq_reg[PMIC_INT1]);
200 }
201 if (irq_src & MAX8997_IRQSRC_FUELGAUGE) {
202 /*
203 * TODO: FUEL GAUGE
204 *
205 * This is to be supported by Max17042 driver. When
206 * an interrupt incurs here, it should be relayed to a
207 * Max17042 device that is connected (probably by
208 * platform-data). However, we do not have interrupt
209 * handling in Max17042 driver currently. The Max17042 IRQ
210 * driver should be ready to be used as a stand-alone device and
211 * a Max8997-dependent device. Because it is not ready in
212 * Max17042-side and it is not too critical in operating
213 * Max8997, we do not implement this in initial releases.
214 */
215 irq_reg[FUEL_GAUGE] = 0;
216 }
217 if (irq_src & MAX8997_IRQSRC_MUIC) {
218 /* MUIC INT1 ~ INT3 */
219 max8997_bulk_read(max8997->muic, MAX8997_MUIC_REG_INT1, 3,
220 &irq_reg[MUIC_INT1]);
221 }
222 if (irq_src & MAX8997_IRQSRC_GPIO) {
223 /* GPIO Interrupt */
224 u8 gpio_info[MAX8997_NUM_GPIO];
225
226 irq_reg[GPIO_LOW] = 0;
227 irq_reg[GPIO_HI] = 0;
228
229 max8997_bulk_read(max8997->i2c, MAX8997_REG_GPIOCNTL1,
230 MAX8997_NUM_GPIO, gpio_info);
231 for (i = 0; i < MAX8997_NUM_GPIO; i++) {
232 bool interrupt = false;
233
234 switch (gpio_info[i] & MAX8997_GPIO_INT_MASK) {
235 case MAX8997_GPIO_INT_BOTH:
236 if (max8997->gpio_status[i] != gpio_info[i])
237 interrupt = true;
238 break;
239 case MAX8997_GPIO_INT_RISE:
240 if ((max8997->gpio_status[i] != gpio_info[i]) &&
241 (gpio_info[i] & MAX8997_GPIO_DATA_MASK))
242 interrupt = true;
243 break;
244 case MAX8997_GPIO_INT_FALL:
245 if ((max8997->gpio_status[i] != gpio_info[i]) &&
246 !(gpio_info[i] & MAX8997_GPIO_DATA_MASK))
247 interrupt = true;
248 break;
249 default:
250 break;
251 }
252
253 if (interrupt) {
254 if (i < 8)
255 irq_reg[GPIO_LOW] |= (1 << i);
256 else
257 irq_reg[GPIO_HI] |= (1 << (i - 8));
258 }
259
260 }
261 }
262 if (irq_src & MAX8997_IRQSRC_FLASH) {
263 /* Flash Status Interrupt */
264 ret = max8997_read_reg(max8997->i2c, MAX8997_REG_FLASHSTATUS,
265 &irq_reg[FLASH_STATUS]);
266 }
267
268 /* Apply masking */
269 for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++)
270 irq_reg[i] &= ~max8997->irq_masks_cur[i];
271
272 /* Report */
273 for (i = 0; i < MAX8997_IRQ_NR; i++) {
274 if (irq_reg[max8997_irqs[i].group] & max8997_irqs[i].mask)
275 handle_nested_irq(max8997->irq_base + i);
276 }
277
278 return IRQ_HANDLED;
279 }
280
281 int max8997_irq_resume(struct max8997_dev *max8997)
282 {
283 if (max8997->irq && max8997->irq_base)
284 max8997_irq_thread(max8997->irq_base, max8997);
285 return 0;
286 }
287
288 int max8997_irq_init(struct max8997_dev *max8997)
289 {
290 int i;
291 int cur_irq;
292 int ret;
293 u8 val;
294
295 if (!max8997->irq) {
296 dev_warn(max8997->dev, "No interrupt specified.\n");
297 max8997->irq_base = 0;
298 return 0;
299 }
300
301 if (!max8997->irq_base) {
302 dev_err(max8997->dev, "No interrupt base specified.\n");
303 return 0;
304 }
305
306 mutex_init(&max8997->irqlock);
307
308 /* Mask individual interrupt sources */
309 for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++) {
310 struct i2c_client *i2c;
311
312 max8997->irq_masks_cur[i] = 0xff;
313 max8997->irq_masks_cache[i] = 0xff;
314 i2c = get_i2c(max8997, i);
315
316 if (IS_ERR_OR_NULL(i2c))
317 continue;
318 if (max8997_mask_reg[i] == MAX8997_REG_INVALID)
319 continue;
320
321 max8997_write_reg(i2c, max8997_mask_reg[i], 0xff);
322 }
323
324 for (i = 0; i < MAX8997_NUM_GPIO; i++) {
325 max8997->gpio_status[i] = (max8997_read_reg(max8997->i2c,
326 MAX8997_REG_GPIOCNTL1 + i,
327 &val)
328 & MAX8997_GPIO_DATA_MASK) ?
329 true : false;
330 }
331
332 /* Register with genirq */
333 for (i = 0; i < MAX8997_IRQ_NR; i++) {
334 cur_irq = i + max8997->irq_base;
335 irq_set_chip_data(cur_irq, max8997);
336 irq_set_chip_and_handler(cur_irq, &max8997_irq_chip,
337 handle_edge_irq);
338 irq_set_nested_thread(cur_irq, 1);
339 #ifdef CONFIG_ARM
340 set_irq_flags(cur_irq, IRQF_VALID);
341 #else
342 irq_set_noprobe(cur_irq);
343 #endif
344 }
345
346 ret = request_threaded_irq(max8997->irq, NULL, max8997_irq_thread,
347 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
348 "max8997-irq", max8997);
349
350 if (ret) {
351 dev_err(max8997->dev, "Failed to request IRQ %d: %d\n",
352 max8997->irq, ret);
353 return ret;
354 }
355
356 if (!max8997->ono)
357 return 0;
358
359 ret = request_threaded_irq(max8997->ono, NULL, max8997_irq_thread,
360 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
361 IRQF_ONESHOT, "max8997-ono", max8997);
362
363 if (ret)
364 dev_err(max8997->dev, "Failed to request ono-IRQ %d: %d\n",
365 max8997->ono, ret);
366
367 return 0;
368 }
369
370 void max8997_irq_exit(struct max8997_dev *max8997)
371 {
372 if (max8997->ono)
373 free_irq(max8997->ono, max8997);
374
375 if (max8997->irq)
376 free_irq(max8997->irq, max8997);
377 }
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