2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 #define NV_DEBUG_NOTRACE
27 #include "nouveau_drv.h"
28 #include "nouveau_hw.h"
29 #include "nouveau_encoder.h"
31 #include <linux/io-mapping.h>
33 /* these defines are made up */
34 #define NV_CIO_CRE_44_HEADA 0x0
35 #define NV_CIO_CRE_44_HEADB 0x3
36 #define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
37 #define LEGACY_I2C_CRT 0x80
38 #define LEGACY_I2C_PANEL 0x81
39 #define LEGACY_I2C_TV 0x82
43 #define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
44 #define LOG_OLD_VALUE(x)
46 #define ROM16(x) le16_to_cpu(*(uint16_t *)&(x))
47 #define ROM32(x) le32_to_cpu(*(uint32_t *)&(x))
54 static bool nv_cksum(const uint8_t *data
, unsigned int length
)
57 * There's a few checksums in the BIOS, so here's a generic checking
63 for (i
= 0; i
< length
; i
++)
73 score_vbios(struct drm_device
*dev
, const uint8_t *data
, const bool writeable
)
75 if (!(data
[0] == 0x55 && data
[1] == 0xAA)) {
76 NV_TRACEWARN(dev
, "... BIOS signature not found\n");
80 if (nv_cksum(data
, data
[2] * 512)) {
81 NV_TRACEWARN(dev
, "... BIOS checksum invalid\n");
82 /* if a ro image is somewhat bad, it's probably all rubbish */
83 return writeable
? 2 : 1;
85 NV_TRACE(dev
, "... appears to be valid\n");
90 static void load_vbios_prom(struct drm_device
*dev
, uint8_t *data
)
92 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
93 uint32_t pci_nv_20
, save_pci_nv_20
;
97 if (dev_priv
->card_type
>= NV_50
)
100 pci_nv_20
= NV_PBUS_PCI_NV_20
;
102 /* enable ROM access */
103 save_pci_nv_20
= nvReadMC(dev
, pci_nv_20
);
104 nvWriteMC(dev
, pci_nv_20
,
105 save_pci_nv_20
& ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED
);
107 /* bail if no rom signature */
108 if (nv_rd08(dev
, NV_PROM_OFFSET
) != 0x55 ||
109 nv_rd08(dev
, NV_PROM_OFFSET
+ 1) != 0xaa)
112 /* additional check (see note below) - read PCI record header */
113 pcir_ptr
= nv_rd08(dev
, NV_PROM_OFFSET
+ 0x18) |
114 nv_rd08(dev
, NV_PROM_OFFSET
+ 0x19) << 8;
115 if (nv_rd08(dev
, NV_PROM_OFFSET
+ pcir_ptr
) != 'P' ||
116 nv_rd08(dev
, NV_PROM_OFFSET
+ pcir_ptr
+ 1) != 'C' ||
117 nv_rd08(dev
, NV_PROM_OFFSET
+ pcir_ptr
+ 2) != 'I' ||
118 nv_rd08(dev
, NV_PROM_OFFSET
+ pcir_ptr
+ 3) != 'R')
121 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a
122 * a good read may be obtained by waiting or re-reading (cargocult: 5x)
123 * each byte. we'll hope pramin has something usable instead
125 for (i
= 0; i
< NV_PROM_SIZE
; i
++)
126 data
[i
] = nv_rd08(dev
, NV_PROM_OFFSET
+ i
);
129 /* disable ROM access */
130 nvWriteMC(dev
, pci_nv_20
,
131 save_pci_nv_20
| NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED
);
134 static void load_vbios_pramin(struct drm_device
*dev
, uint8_t *data
)
136 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
137 uint32_t old_bar0_pramin
= 0;
140 if (dev_priv
->card_type
>= NV_50
) {
141 uint32_t vbios_vram
= (nv_rd32(dev
, 0x619f04) & ~0xff) << 8;
144 vbios_vram
= (nv_rd32(dev
, 0x1700) << 16) + 0xf0000;
146 old_bar0_pramin
= nv_rd32(dev
, 0x1700);
147 nv_wr32(dev
, 0x1700, vbios_vram
>> 16);
150 /* bail if no rom signature */
151 if (nv_rd08(dev
, NV_PRAMIN_OFFSET
) != 0x55 ||
152 nv_rd08(dev
, NV_PRAMIN_OFFSET
+ 1) != 0xaa)
155 for (i
= 0; i
< NV_PROM_SIZE
; i
++)
156 data
[i
] = nv_rd08(dev
, NV_PRAMIN_OFFSET
+ i
);
159 if (dev_priv
->card_type
>= NV_50
)
160 nv_wr32(dev
, 0x1700, old_bar0_pramin
);
163 static void load_vbios_pci(struct drm_device
*dev
, uint8_t *data
)
165 void __iomem
*rom
= NULL
;
169 ret
= pci_enable_rom(dev
->pdev
);
173 rom
= pci_map_rom(dev
->pdev
, &rom_len
);
176 memcpy_fromio(data
, rom
, rom_len
);
177 pci_unmap_rom(dev
->pdev
, rom
);
180 pci_disable_rom(dev
->pdev
);
183 static void load_vbios_acpi(struct drm_device
*dev
, uint8_t *data
)
187 int size
= 64 * 1024;
189 if (!nouveau_acpi_rom_supported(dev
->pdev
))
192 for (i
= 0; i
< (size
/ ROM_BIOS_PAGE
); i
++) {
193 ret
= nouveau_acpi_get_bios_chunk(data
,
204 void (*loadbios
)(struct drm_device
*, uint8_t *);
208 static struct methods shadow_methods
[] = {
209 { "PRAMIN", load_vbios_pramin
, true },
210 { "PROM", load_vbios_prom
, false },
211 { "PCIROM", load_vbios_pci
, true },
212 { "ACPI", load_vbios_acpi
, true },
214 #define NUM_SHADOW_METHODS ARRAY_SIZE(shadow_methods)
216 static bool NVShadowVBIOS(struct drm_device
*dev
, uint8_t *data
)
218 struct methods
*methods
= shadow_methods
;
220 int scores
[NUM_SHADOW_METHODS
], i
;
223 for (i
= 0; i
< NUM_SHADOW_METHODS
; i
++)
224 if (!strcasecmp(nouveau_vbios
, methods
[i
].desc
))
227 if (i
< NUM_SHADOW_METHODS
) {
228 NV_INFO(dev
, "Attempting to use BIOS image from %s\n",
231 methods
[i
].loadbios(dev
, data
);
232 if (score_vbios(dev
, data
, methods
[i
].rw
))
236 NV_ERROR(dev
, "VBIOS source \'%s\' invalid\n", nouveau_vbios
);
239 for (i
= 0; i
< NUM_SHADOW_METHODS
; i
++) {
240 NV_TRACE(dev
, "Attempting to load BIOS image from %s\n",
242 data
[0] = data
[1] = 0; /* avoid reuse of previous image */
243 methods
[i
].loadbios(dev
, data
);
244 scores
[i
] = score_vbios(dev
, data
, methods
[i
].rw
);
245 if (scores
[i
] == testscore
)
249 while (--testscore
> 0) {
250 for (i
= 0; i
< NUM_SHADOW_METHODS
; i
++) {
251 if (scores
[i
] == testscore
) {
252 NV_TRACE(dev
, "Using BIOS image from %s\n",
254 methods
[i
].loadbios(dev
, data
);
260 NV_ERROR(dev
, "No valid BIOS image found\n");
264 struct init_tbl_entry
{
268 * > 0: success, length of opcode
269 * 0: success, but abort further parsing of table (INIT_DONE etc)
270 * < 0: failure, table parsing will be aborted
272 int (*handler
)(struct nvbios
*, uint16_t, struct init_exec
*);
281 static int parse_init_table(struct nvbios
*, unsigned int, struct init_exec
*);
283 #define MACRO_INDEX_SIZE 2
285 #define CONDITION_SIZE 12
286 #define IO_FLAG_CONDITION_SIZE 9
287 #define IO_CONDITION_SIZE 5
288 #define MEM_INIT_SIZE 66
290 static void still_alive(void)
299 munge_reg(struct nvbios
*bios
, uint32_t reg
)
301 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
302 struct dcb_entry
*dcbent
= bios
->display
.output
;
304 if (dev_priv
->card_type
< NV_50
)
307 if (reg
& 0x40000000) {
310 reg
+= (ffs(dcbent
->or) - 1) * 0x800;
311 if ((reg
& 0x20000000) && !(dcbent
->sorconf
.link
& 1))
320 valid_reg(struct nvbios
*bios
, uint32_t reg
)
322 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
323 struct drm_device
*dev
= bios
->dev
;
325 /* C51 has misaligned regs on purpose. Marvellous */
327 (reg
& 0x1 && dev_priv
->vbios
.chip_version
!= 0x51))
328 NV_ERROR(dev
, "======= misaligned reg 0x%08X =======\n", reg
);
330 /* warn on C51 regs that haven't been verified accessible in tracing */
331 if (reg
& 0x1 && dev_priv
->vbios
.chip_version
== 0x51 &&
332 reg
!= 0x130d && reg
!= 0x1311 && reg
!= 0x60081d)
333 NV_WARN(dev
, "=== C51 misaligned reg 0x%08X not verified ===\n",
336 if (reg
>= (8*1024*1024)) {
337 NV_ERROR(dev
, "=== reg 0x%08x out of mapped bounds ===\n", reg
);
345 valid_idx_port(struct nvbios
*bios
, uint16_t port
)
347 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
348 struct drm_device
*dev
= bios
->dev
;
351 * If adding more ports here, the read/write functions below will need
352 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
353 * used for the port in question
355 if (dev_priv
->card_type
< NV_50
) {
356 if (port
== NV_CIO_CRX__COLOR
)
358 if (port
== NV_VIO_SRX
)
361 if (port
== NV_CIO_CRX__COLOR
)
365 NV_ERROR(dev
, "========== unknown indexed io port 0x%04X ==========\n",
372 valid_port(struct nvbios
*bios
, uint16_t port
)
374 struct drm_device
*dev
= bios
->dev
;
377 * If adding more ports here, the read/write functions below will need
378 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
379 * used for the port in question
381 if (port
== NV_VIO_VSE2
)
384 NV_ERROR(dev
, "========== unknown io port 0x%04X ==========\n", port
);
390 bios_rd32(struct nvbios
*bios
, uint32_t reg
)
394 reg
= munge_reg(bios
, reg
);
395 if (!valid_reg(bios
, reg
))
399 * C51 sometimes uses regs with bit0 set in the address. For these
400 * cases there should exist a translation in a BIOS table to an IO
401 * port address which the BIOS uses for accessing the reg
403 * These only seem to appear for the power control regs to a flat panel,
404 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
405 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
406 * suspend-resume mmio trace from a C51 will be required to see if this
407 * is true for the power microcode in 0x14.., or whether the direct IO
408 * port access method is needed
413 data
= nv_rd32(bios
->dev
, reg
);
415 BIOSLOG(bios
, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg
, data
);
421 bios_wr32(struct nvbios
*bios
, uint32_t reg
, uint32_t data
)
423 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
425 reg
= munge_reg(bios
, reg
);
426 if (!valid_reg(bios
, reg
))
429 /* see note in bios_rd32 */
433 LOG_OLD_VALUE(bios_rd32(bios
, reg
));
434 BIOSLOG(bios
, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg
, data
);
436 if (dev_priv
->vbios
.execute
) {
438 nv_wr32(bios
->dev
, reg
, data
);
443 bios_idxprt_rd(struct nvbios
*bios
, uint16_t port
, uint8_t index
)
445 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
446 struct drm_device
*dev
= bios
->dev
;
449 if (!valid_idx_port(bios
, port
))
452 if (dev_priv
->card_type
< NV_50
) {
453 if (port
== NV_VIO_SRX
)
454 data
= NVReadVgaSeq(dev
, bios
->state
.crtchead
, index
);
455 else /* assume NV_CIO_CRX__COLOR */
456 data
= NVReadVgaCrtc(dev
, bios
->state
.crtchead
, index
);
460 data32
= bios_rd32(bios
, NV50_PDISPLAY_VGACRTC(index
& ~3));
461 data
= (data32
>> ((index
& 3) << 3)) & 0xff;
464 BIOSLOG(bios
, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
465 "Head: 0x%02X, Data: 0x%02X\n",
466 port
, index
, bios
->state
.crtchead
, data
);
471 bios_idxprt_wr(struct nvbios
*bios
, uint16_t port
, uint8_t index
, uint8_t data
)
473 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
474 struct drm_device
*dev
= bios
->dev
;
476 if (!valid_idx_port(bios
, port
))
480 * The current head is maintained in the nvbios member state.crtchead.
481 * We trap changes to CR44 and update the head variable and hence the
482 * register set written.
483 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
484 * of the write, and to head1 after the write
486 if (port
== NV_CIO_CRX__COLOR
&& index
== NV_CIO_CRE_44
&&
487 data
!= NV_CIO_CRE_44_HEADB
)
488 bios
->state
.crtchead
= 0;
490 LOG_OLD_VALUE(bios_idxprt_rd(bios
, port
, index
));
491 BIOSLOG(bios
, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
492 "Head: 0x%02X, Data: 0x%02X\n",
493 port
, index
, bios
->state
.crtchead
, data
);
495 if (bios
->execute
&& dev_priv
->card_type
< NV_50
) {
497 if (port
== NV_VIO_SRX
)
498 NVWriteVgaSeq(dev
, bios
->state
.crtchead
, index
, data
);
499 else /* assume NV_CIO_CRX__COLOR */
500 NVWriteVgaCrtc(dev
, bios
->state
.crtchead
, index
, data
);
503 uint32_t data32
, shift
= (index
& 3) << 3;
507 data32
= bios_rd32(bios
, NV50_PDISPLAY_VGACRTC(index
& ~3));
508 data32
&= ~(0xff << shift
);
509 data32
|= (data
<< shift
);
510 bios_wr32(bios
, NV50_PDISPLAY_VGACRTC(index
& ~3), data32
);
513 if (port
== NV_CIO_CRX__COLOR
&&
514 index
== NV_CIO_CRE_44
&& data
== NV_CIO_CRE_44_HEADB
)
515 bios
->state
.crtchead
= 1;
519 bios_port_rd(struct nvbios
*bios
, uint16_t port
)
521 uint8_t data
, head
= bios
->state
.crtchead
;
523 if (!valid_port(bios
, port
))
526 data
= NVReadPRMVIO(bios
->dev
, head
, NV_PRMVIO0_OFFSET
+ port
);
528 BIOSLOG(bios
, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
535 bios_port_wr(struct nvbios
*bios
, uint16_t port
, uint8_t data
)
537 int head
= bios
->state
.crtchead
;
539 if (!valid_port(bios
, port
))
542 LOG_OLD_VALUE(bios_port_rd(bios
, port
));
543 BIOSLOG(bios
, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
550 NVWritePRMVIO(bios
->dev
, head
, NV_PRMVIO0_OFFSET
+ port
, data
);
554 io_flag_condition_met(struct nvbios
*bios
, uint16_t offset
, uint8_t cond
)
557 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
558 * for the CRTC index; 1 byte for the mask to apply to the value
559 * retrieved from the CRTC; 1 byte for the shift right to apply to the
560 * masked CRTC value; 2 bytes for the offset to the flag array, to
561 * which the shifted value is added; 1 byte for the mask applied to the
562 * value read from the flag array; and 1 byte for the value to compare
563 * against the masked byte from the flag table.
566 uint16_t condptr
= bios
->io_flag_condition_tbl_ptr
+ cond
* IO_FLAG_CONDITION_SIZE
;
567 uint16_t crtcport
= ROM16(bios
->data
[condptr
]);
568 uint8_t crtcindex
= bios
->data
[condptr
+ 2];
569 uint8_t mask
= bios
->data
[condptr
+ 3];
570 uint8_t shift
= bios
->data
[condptr
+ 4];
571 uint16_t flagarray
= ROM16(bios
->data
[condptr
+ 5]);
572 uint8_t flagarraymask
= bios
->data
[condptr
+ 7];
573 uint8_t cmpval
= bios
->data
[condptr
+ 8];
576 BIOSLOG(bios
, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
577 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
579 offset
, crtcport
, crtcindex
, mask
, shift
, flagarray
, flagarraymask
, cmpval
);
581 data
= bios_idxprt_rd(bios
, crtcport
, crtcindex
);
583 data
= bios
->data
[flagarray
+ ((data
& mask
) >> shift
)];
584 data
&= flagarraymask
;
586 BIOSLOG(bios
, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
587 offset
, data
, cmpval
);
589 return (data
== cmpval
);
593 bios_condition_met(struct nvbios
*bios
, uint16_t offset
, uint8_t cond
)
596 * The condition table entry has 4 bytes for the address of the
597 * register to check, 4 bytes for a mask to apply to the register and
598 * 4 for a test comparison value
601 uint16_t condptr
= bios
->condition_tbl_ptr
+ cond
* CONDITION_SIZE
;
602 uint32_t reg
= ROM32(bios
->data
[condptr
]);
603 uint32_t mask
= ROM32(bios
->data
[condptr
+ 4]);
604 uint32_t cmpval
= ROM32(bios
->data
[condptr
+ 8]);
607 BIOSLOG(bios
, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
608 offset
, cond
, reg
, mask
);
610 data
= bios_rd32(bios
, reg
) & mask
;
612 BIOSLOG(bios
, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
613 offset
, data
, cmpval
);
615 return (data
== cmpval
);
619 io_condition_met(struct nvbios
*bios
, uint16_t offset
, uint8_t cond
)
622 * The IO condition entry has 2 bytes for the IO port address; 1 byte
623 * for the index to write to io_port; 1 byte for the mask to apply to
624 * the byte read from io_port+1; and 1 byte for the value to compare
625 * against the masked byte.
628 uint16_t condptr
= bios
->io_condition_tbl_ptr
+ cond
* IO_CONDITION_SIZE
;
629 uint16_t io_port
= ROM16(bios
->data
[condptr
]);
630 uint8_t port_index
= bios
->data
[condptr
+ 2];
631 uint8_t mask
= bios
->data
[condptr
+ 3];
632 uint8_t cmpval
= bios
->data
[condptr
+ 4];
634 uint8_t data
= bios_idxprt_rd(bios
, io_port
, port_index
) & mask
;
636 BIOSLOG(bios
, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
637 offset
, data
, cmpval
);
639 return (data
== cmpval
);
643 nv50_pll_set(struct drm_device
*dev
, uint32_t reg
, uint32_t clk
)
645 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
646 uint32_t reg0
= nv_rd32(dev
, reg
+ 0);
647 uint32_t reg1
= nv_rd32(dev
, reg
+ 4);
648 struct nouveau_pll_vals pll
;
649 struct pll_lims pll_limits
;
652 ret
= get_pll_limits(dev
, reg
, &pll_limits
);
656 clk
= nouveau_calc_pll_mnp(dev
, &pll_limits
, clk
, &pll
);
660 reg0
= (reg0
& 0xfff8ffff) | (pll
.log2P
<< 16);
661 reg1
= (reg1
& 0xffff0000) | (pll
.N1
<< 8) | pll
.M1
;
663 if (dev_priv
->vbios
.execute
) {
665 nv_wr32(dev
, reg
+ 4, reg1
);
666 nv_wr32(dev
, reg
+ 0, reg0
);
673 setPLL(struct nvbios
*bios
, uint32_t reg
, uint32_t clk
)
675 struct drm_device
*dev
= bios
->dev
;
676 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
678 struct pll_lims pll_lim
;
679 struct nouveau_pll_vals pllvals
;
682 if (dev_priv
->card_type
>= NV_50
)
683 return nv50_pll_set(dev
, reg
, clk
);
685 /* high regs (such as in the mac g5 table) are not -= 4 */
686 ret
= get_pll_limits(dev
, reg
> 0x405c ? reg
: reg
- 4, &pll_lim
);
690 clk
= nouveau_calc_pll_mnp(dev
, &pll_lim
, clk
, &pllvals
);
696 nouveau_hw_setpll(dev
, reg
, &pllvals
);
702 static int dcb_entry_idx_from_crtchead(struct drm_device
*dev
)
704 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
705 struct nvbios
*bios
= &dev_priv
->vbios
;
708 * For the results of this function to be correct, CR44 must have been
709 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
710 * and the DCB table parsed, before the script calling the function is
711 * run. run_digital_op_script is example of how to do such setup
714 uint8_t dcb_entry
= NVReadVgaCrtc5758(dev
, bios
->state
.crtchead
, 0);
716 if (dcb_entry
> bios
->dcb
.entries
) {
717 NV_ERROR(dev
, "CR58 doesn't have a valid DCB entry currently "
718 "(%02X)\n", dcb_entry
);
719 dcb_entry
= 0x7f; /* unused / invalid marker */
726 read_dcb_i2c_entry(struct drm_device
*dev
, int dcb_version
, uint8_t *i2ctable
, int index
, struct dcb_i2c_entry
*i2c
)
728 uint8_t dcb_i2c_ver
= dcb_version
, headerlen
= 0, entry_len
= 4;
729 int i2c_entries
= DCB_MAX_NUM_I2C_ENTRIES
;
730 int recordoffset
= 0, rdofs
= 1, wrofs
= 0;
731 uint8_t port_type
= 0;
736 if (dcb_version
>= 0x30) {
737 if (i2ctable
[0] != dcb_version
) /* necessary? */
739 "DCB I2C table version mismatch (%02X vs %02X)\n",
740 i2ctable
[0], dcb_version
);
741 dcb_i2c_ver
= i2ctable
[0];
742 headerlen
= i2ctable
[1];
743 if (i2ctable
[2] <= DCB_MAX_NUM_I2C_ENTRIES
)
744 i2c_entries
= i2ctable
[2];
747 "DCB I2C table has more entries than indexable "
748 "(%d entries, max %d)\n", i2ctable
[2],
749 DCB_MAX_NUM_I2C_ENTRIES
);
750 entry_len
= i2ctable
[3];
751 /* [4] is i2c_default_indices, read in parse_dcb_table() */
754 * It's your own fault if you call this function on a DCB 1.1 BIOS --
755 * the test below is for DCB 1.2
757 if (dcb_version
< 0x14) {
765 if (index
>= i2c_entries
) {
766 NV_ERROR(dev
, "DCB I2C index too big (%d >= %d)\n",
770 if (i2ctable
[headerlen
+ entry_len
* index
+ 3] == 0xff) {
771 NV_ERROR(dev
, "DCB I2C entry invalid\n");
775 if (dcb_i2c_ver
>= 0x30) {
776 port_type
= i2ctable
[headerlen
+ recordoffset
+ 3 + entry_len
* index
];
779 * Fixup for chips using same address offset for read and
782 if (port_type
== 4) /* seen on C51 */
784 if (port_type
>= 5) /* G80+ */
788 if (dcb_i2c_ver
>= 0x40) {
789 if (port_type
!= 5 && port_type
!= 6)
790 NV_WARN(dev
, "DCB I2C table has port type %d\n", port_type
);
792 i2c
->entry
= ROM32(i2ctable
[headerlen
+ recordoffset
+ entry_len
* index
]);
795 i2c
->port_type
= port_type
;
796 i2c
->read
= i2ctable
[headerlen
+ recordoffset
+ rdofs
+ entry_len
* index
];
797 i2c
->write
= i2ctable
[headerlen
+ recordoffset
+ wrofs
+ entry_len
* index
];
802 static struct nouveau_i2c_chan
*
803 init_i2c_device_find(struct drm_device
*dev
, int i2c_index
)
805 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
806 struct dcb_table
*dcb
= &dev_priv
->vbios
.dcb
;
808 if (i2c_index
== 0xff) {
809 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
810 int idx
= dcb_entry_idx_from_crtchead(dev
), shift
= 0;
811 int default_indices
= dcb
->i2c_default_indices
;
813 if (idx
!= 0x7f && dcb
->entry
[idx
].i2c_upper_default
)
816 i2c_index
= (default_indices
>> shift
) & 0xf;
818 if (i2c_index
== 0x80) /* g80+ */
819 i2c_index
= dcb
->i2c_default_indices
& 0xf;
821 if (i2c_index
== 0x81)
822 i2c_index
= (dcb
->i2c_default_indices
& 0xf0) >> 4;
824 if (i2c_index
>= DCB_MAX_NUM_I2C_ENTRIES
) {
825 NV_ERROR(dev
, "invalid i2c_index 0x%x\n", i2c_index
);
829 /* Make sure i2c table entry has been parsed, it may not
830 * have been if this is a bus not referenced by a DCB encoder
832 read_dcb_i2c_entry(dev
, dcb
->version
, dcb
->i2c_table
,
833 i2c_index
, &dcb
->i2c
[i2c_index
]);
835 return nouveau_i2c_find(dev
, i2c_index
);
839 get_tmds_index_reg(struct drm_device
*dev
, uint8_t mlv
)
842 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
843 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
844 * CR58 for CR57 = 0 to index a table of offsets to the basic
846 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
847 * CR58 for CR57 = 0 to index a table of offsets to the basic
848 * 0x6808b0 address, and then flip the offset by 8.
851 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
852 struct nvbios
*bios
= &dev_priv
->vbios
;
853 const int pramdac_offset
[13] = {
854 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
855 const uint32_t pramdac_table
[4] = {
856 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
859 int dcb_entry
, dacoffset
;
861 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
862 dcb_entry
= dcb_entry_idx_from_crtchead(dev
);
863 if (dcb_entry
== 0x7f)
865 dacoffset
= pramdac_offset
[bios
->dcb
.entry
[dcb_entry
].or];
868 return 0x6808b0 + dacoffset
;
870 if (mlv
>= ARRAY_SIZE(pramdac_table
)) {
871 NV_ERROR(dev
, "Magic Lookup Value too big (%02X)\n",
875 return pramdac_table
[mlv
];
880 init_io_restrict_prog(struct nvbios
*bios
, uint16_t offset
,
881 struct init_exec
*iexec
)
884 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
886 * offset (8 bit): opcode
887 * offset + 1 (16 bit): CRTC port
888 * offset + 3 (8 bit): CRTC index
889 * offset + 4 (8 bit): mask
890 * offset + 5 (8 bit): shift
891 * offset + 6 (8 bit): count
892 * offset + 7 (32 bit): register
893 * offset + 11 (32 bit): configuration 1
896 * Starting at offset + 11 there are "count" 32 bit values.
897 * To find out which value to use read index "CRTC index" on "CRTC
898 * port", AND this value with "mask" and then bit shift right "shift"
899 * bits. Read the appropriate value using this index and write to
903 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 1]);
904 uint8_t crtcindex
= bios
->data
[offset
+ 3];
905 uint8_t mask
= bios
->data
[offset
+ 4];
906 uint8_t shift
= bios
->data
[offset
+ 5];
907 uint8_t count
= bios
->data
[offset
+ 6];
908 uint32_t reg
= ROM32(bios
->data
[offset
+ 7]);
911 int len
= 11 + count
* 4;
916 BIOSLOG(bios
, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
917 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
918 offset
, crtcport
, crtcindex
, mask
, shift
, count
, reg
);
920 config
= (bios_idxprt_rd(bios
, crtcport
, crtcindex
) & mask
) >> shift
;
921 if (config
> count
) {
923 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
924 offset
, config
, count
);
928 configval
= ROM32(bios
->data
[offset
+ 11 + config
* 4]);
930 BIOSLOG(bios
, "0x%04X: Writing config %02X\n", offset
, config
);
932 bios_wr32(bios
, reg
, configval
);
938 init_repeat(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
941 * INIT_REPEAT opcode: 0x33 ('3')
943 * offset (8 bit): opcode
944 * offset + 1 (8 bit): count
946 * Execute script following this opcode up to INIT_REPEAT_END
950 uint8_t count
= bios
->data
[offset
+ 1];
953 /* no iexec->execute check by design */
955 BIOSLOG(bios
, "0x%04X: Repeating following segment %d times\n",
958 iexec
->repeat
= true;
961 * count - 1, as the script block will execute once when we leave this
962 * opcode -- this is compatible with bios behaviour as:
963 * a) the block is always executed at least once, even if count == 0
964 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
967 for (i
= 0; i
< count
- 1; i
++)
968 parse_init_table(bios
, offset
+ 2, iexec
);
970 iexec
->repeat
= false;
976 init_io_restrict_pll(struct nvbios
*bios
, uint16_t offset
,
977 struct init_exec
*iexec
)
980 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
982 * offset (8 bit): opcode
983 * offset + 1 (16 bit): CRTC port
984 * offset + 3 (8 bit): CRTC index
985 * offset + 4 (8 bit): mask
986 * offset + 5 (8 bit): shift
987 * offset + 6 (8 bit): IO flag condition index
988 * offset + 7 (8 bit): count
989 * offset + 8 (32 bit): register
990 * offset + 12 (16 bit): frequency 1
993 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
994 * Set PLL register "register" to coefficients for frequency n,
995 * selected by reading index "CRTC index" of "CRTC port" ANDed with
996 * "mask" and shifted right by "shift".
998 * If "IO flag condition index" > 0, and condition met, double
999 * frequency before setting it.
1002 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 1]);
1003 uint8_t crtcindex
= bios
->data
[offset
+ 3];
1004 uint8_t mask
= bios
->data
[offset
+ 4];
1005 uint8_t shift
= bios
->data
[offset
+ 5];
1006 int8_t io_flag_condition_idx
= bios
->data
[offset
+ 6];
1007 uint8_t count
= bios
->data
[offset
+ 7];
1008 uint32_t reg
= ROM32(bios
->data
[offset
+ 8]);
1011 int len
= 12 + count
* 2;
1013 if (!iexec
->execute
)
1016 BIOSLOG(bios
, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1017 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
1018 "Count: 0x%02X, Reg: 0x%08X\n",
1019 offset
, crtcport
, crtcindex
, mask
, shift
,
1020 io_flag_condition_idx
, count
, reg
);
1022 config
= (bios_idxprt_rd(bios
, crtcport
, crtcindex
) & mask
) >> shift
;
1023 if (config
> count
) {
1025 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1026 offset
, config
, count
);
1030 freq
= ROM16(bios
->data
[offset
+ 12 + config
* 2]);
1032 if (io_flag_condition_idx
> 0) {
1033 if (io_flag_condition_met(bios
, offset
, io_flag_condition_idx
)) {
1034 BIOSLOG(bios
, "0x%04X: Condition fulfilled -- "
1035 "frequency doubled\n", offset
);
1038 BIOSLOG(bios
, "0x%04X: Condition not fulfilled -- "
1039 "frequency unchanged\n", offset
);
1042 BIOSLOG(bios
, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
1043 offset
, reg
, config
, freq
);
1045 setPLL(bios
, reg
, freq
* 10);
1051 init_end_repeat(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1054 * INIT_END_REPEAT opcode: 0x36 ('6')
1056 * offset (8 bit): opcode
1058 * Marks the end of the block for INIT_REPEAT to repeat
1061 /* no iexec->execute check by design */
1064 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
1065 * we're not in repeat mode
1074 init_copy(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1077 * INIT_COPY opcode: 0x37 ('7')
1079 * offset (8 bit): opcode
1080 * offset + 1 (32 bit): register
1081 * offset + 5 (8 bit): shift
1082 * offset + 6 (8 bit): srcmask
1083 * offset + 7 (16 bit): CRTC port
1084 * offset + 9 (8 bit): CRTC index
1085 * offset + 10 (8 bit): mask
1087 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
1088 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
1092 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
1093 uint8_t shift
= bios
->data
[offset
+ 5];
1094 uint8_t srcmask
= bios
->data
[offset
+ 6];
1095 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 7]);
1096 uint8_t crtcindex
= bios
->data
[offset
+ 9];
1097 uint8_t mask
= bios
->data
[offset
+ 10];
1101 if (!iexec
->execute
)
1104 BIOSLOG(bios
, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1105 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1106 offset
, reg
, shift
, srcmask
, crtcport
, crtcindex
, mask
);
1108 data
= bios_rd32(bios
, reg
);
1113 data
<<= (0x100 - shift
);
1117 crtcdata
= bios_idxprt_rd(bios
, crtcport
, crtcindex
) & mask
;
1118 crtcdata
|= (uint8_t)data
;
1119 bios_idxprt_wr(bios
, crtcport
, crtcindex
, crtcdata
);
1125 init_not(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1128 * INIT_NOT opcode: 0x38 ('8')
1130 * offset (8 bit): opcode
1132 * Invert the current execute / no-execute condition (i.e. "else")
1135 BIOSLOG(bios
, "0x%04X: ------ Skipping following commands ------\n", offset
);
1137 BIOSLOG(bios
, "0x%04X: ------ Executing following commands ------\n", offset
);
1139 iexec
->execute
= !iexec
->execute
;
1144 init_io_flag_condition(struct nvbios
*bios
, uint16_t offset
,
1145 struct init_exec
*iexec
)
1148 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1150 * offset (8 bit): opcode
1151 * offset + 1 (8 bit): condition number
1153 * Check condition "condition number" in the IO flag condition table.
1154 * If condition not met skip subsequent opcodes until condition is
1155 * inverted (INIT_NOT), or we hit INIT_RESUME
1158 uint8_t cond
= bios
->data
[offset
+ 1];
1160 if (!iexec
->execute
)
1163 if (io_flag_condition_met(bios
, offset
, cond
))
1164 BIOSLOG(bios
, "0x%04X: Condition fulfilled -- continuing to execute\n", offset
);
1166 BIOSLOG(bios
, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset
);
1167 iexec
->execute
= false;
1174 init_dp_condition(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1177 * INIT_DP_CONDITION opcode: 0x3A ('')
1179 * offset (8 bit): opcode
1180 * offset + 1 (8 bit): "sub" opcode
1181 * offset + 2 (8 bit): unknown
1185 struct bit_displayport_encoder_table
*dpe
= NULL
;
1186 struct dcb_entry
*dcb
= bios
->display
.output
;
1187 struct drm_device
*dev
= bios
->dev
;
1188 uint8_t cond
= bios
->data
[offset
+ 1];
1191 BIOSLOG(bios
, "0x%04X: subop 0x%02X\n", offset
, cond
);
1193 if (!iexec
->execute
)
1196 dpe
= nouveau_bios_dp_table(dev
, dcb
, &dummy
);
1198 NV_ERROR(dev
, "0x%04X: INIT_3A: no encoder table!!\n", offset
);
1205 struct dcb_connector_table_entry
*ent
=
1206 &bios
->dcb
.connector
.entry
[dcb
->connector
];
1208 if (ent
->type
!= DCB_CONNECTOR_eDP
)
1209 iexec
->execute
= false;
1214 if (!(dpe
->unknown
& cond
))
1215 iexec
->execute
= false;
1219 struct nouveau_i2c_chan
*auxch
;
1222 auxch
= nouveau_i2c_find(dev
, bios
->display
.output
->i2c_index
);
1224 NV_ERROR(dev
, "0x%04X: couldn't get auxch\n", offset
);
1228 ret
= nouveau_dp_auxch(auxch
, 9, 0xd, &cond
, 1);
1230 NV_ERROR(dev
, "0x%04X: auxch rd fail: %d\n", offset
, ret
);
1235 iexec
->execute
= false;
1239 NV_WARN(dev
, "0x%04X: unknown INIT_3A op: %d\n", offset
, cond
);
1244 BIOSLOG(bios
, "0x%04X: continuing to execute\n", offset
);
1246 BIOSLOG(bios
, "0x%04X: skipping following commands\n", offset
);
1252 init_op_3b(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1255 * INIT_3B opcode: 0x3B ('')
1257 * offset (8 bit): opcode
1258 * offset + 1 (8 bit): crtc index
1262 uint8_t or = ffs(bios
->display
.output
->or) - 1;
1263 uint8_t index
= bios
->data
[offset
+ 1];
1266 if (!iexec
->execute
)
1269 data
= bios_idxprt_rd(bios
, 0x3d4, index
);
1270 bios_idxprt_wr(bios
, 0x3d4, index
, data
& ~(1 << or));
1275 init_op_3c(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1278 * INIT_3C opcode: 0x3C ('')
1280 * offset (8 bit): opcode
1281 * offset + 1 (8 bit): crtc index
1285 uint8_t or = ffs(bios
->display
.output
->or) - 1;
1286 uint8_t index
= bios
->data
[offset
+ 1];
1289 if (!iexec
->execute
)
1292 data
= bios_idxprt_rd(bios
, 0x3d4, index
);
1293 bios_idxprt_wr(bios
, 0x3d4, index
, data
| (1 << or));
1298 init_idx_addr_latched(struct nvbios
*bios
, uint16_t offset
,
1299 struct init_exec
*iexec
)
1302 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1304 * offset (8 bit): opcode
1305 * offset + 1 (32 bit): control register
1306 * offset + 5 (32 bit): data register
1307 * offset + 9 (32 bit): mask
1308 * offset + 13 (32 bit): data
1309 * offset + 17 (8 bit): count
1310 * offset + 18 (8 bit): address 1
1311 * offset + 19 (8 bit): data 1
1314 * For each of "count" address and data pairs, write "data n" to
1315 * "data register", read the current value of "control register",
1316 * and write it back once ANDed with "mask", ORed with "data",
1317 * and ORed with "address n"
1320 uint32_t controlreg
= ROM32(bios
->data
[offset
+ 1]);
1321 uint32_t datareg
= ROM32(bios
->data
[offset
+ 5]);
1322 uint32_t mask
= ROM32(bios
->data
[offset
+ 9]);
1323 uint32_t data
= ROM32(bios
->data
[offset
+ 13]);
1324 uint8_t count
= bios
->data
[offset
+ 17];
1325 int len
= 18 + count
* 2;
1329 if (!iexec
->execute
)
1332 BIOSLOG(bios
, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1333 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1334 offset
, controlreg
, datareg
, mask
, data
, count
);
1336 for (i
= 0; i
< count
; i
++) {
1337 uint8_t instaddress
= bios
->data
[offset
+ 18 + i
* 2];
1338 uint8_t instdata
= bios
->data
[offset
+ 19 + i
* 2];
1340 BIOSLOG(bios
, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
1341 offset
, instaddress
, instdata
);
1343 bios_wr32(bios
, datareg
, instdata
);
1344 value
= bios_rd32(bios
, controlreg
) & mask
;
1346 value
|= instaddress
;
1347 bios_wr32(bios
, controlreg
, value
);
1354 init_io_restrict_pll2(struct nvbios
*bios
, uint16_t offset
,
1355 struct init_exec
*iexec
)
1358 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1360 * offset (8 bit): opcode
1361 * offset + 1 (16 bit): CRTC port
1362 * offset + 3 (8 bit): CRTC index
1363 * offset + 4 (8 bit): mask
1364 * offset + 5 (8 bit): shift
1365 * offset + 6 (8 bit): count
1366 * offset + 7 (32 bit): register
1367 * offset + 11 (32 bit): frequency 1
1370 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1371 * Set PLL register "register" to coefficients for frequency n,
1372 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1373 * "mask" and shifted right by "shift".
1376 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 1]);
1377 uint8_t crtcindex
= bios
->data
[offset
+ 3];
1378 uint8_t mask
= bios
->data
[offset
+ 4];
1379 uint8_t shift
= bios
->data
[offset
+ 5];
1380 uint8_t count
= bios
->data
[offset
+ 6];
1381 uint32_t reg
= ROM32(bios
->data
[offset
+ 7]);
1382 int len
= 11 + count
* 4;
1386 if (!iexec
->execute
)
1389 BIOSLOG(bios
, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1390 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1391 offset
, crtcport
, crtcindex
, mask
, shift
, count
, reg
);
1396 config
= (bios_idxprt_rd(bios
, crtcport
, crtcindex
) & mask
) >> shift
;
1397 if (config
> count
) {
1399 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1400 offset
, config
, count
);
1404 freq
= ROM32(bios
->data
[offset
+ 11 + config
* 4]);
1406 BIOSLOG(bios
, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1407 offset
, reg
, config
, freq
);
1409 setPLL(bios
, reg
, freq
);
1415 init_pll2(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1418 * INIT_PLL2 opcode: 0x4B ('K')
1420 * offset (8 bit): opcode
1421 * offset + 1 (32 bit): register
1422 * offset + 5 (32 bit): freq
1424 * Set PLL register "register" to coefficients for frequency "freq"
1427 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
1428 uint32_t freq
= ROM32(bios
->data
[offset
+ 5]);
1430 if (!iexec
->execute
)
1433 BIOSLOG(bios
, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1436 setPLL(bios
, reg
, freq
);
1441 init_i2c_byte(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1444 * INIT_I2C_BYTE opcode: 0x4C ('L')
1446 * offset (8 bit): opcode
1447 * offset + 1 (8 bit): DCB I2C table entry index
1448 * offset + 2 (8 bit): I2C slave address
1449 * offset + 3 (8 bit): count
1450 * offset + 4 (8 bit): I2C register 1
1451 * offset + 5 (8 bit): mask 1
1452 * offset + 6 (8 bit): data 1
1455 * For each of "count" registers given by "I2C register n" on the device
1456 * addressed by "I2C slave address" on the I2C bus given by
1457 * "DCB I2C table entry index", read the register, AND the result with
1458 * "mask n" and OR it with "data n" before writing it back to the device
1461 struct drm_device
*dev
= bios
->dev
;
1462 uint8_t i2c_index
= bios
->data
[offset
+ 1];
1463 uint8_t i2c_address
= bios
->data
[offset
+ 2] >> 1;
1464 uint8_t count
= bios
->data
[offset
+ 3];
1465 struct nouveau_i2c_chan
*chan
;
1466 int len
= 4 + count
* 3;
1469 if (!iexec
->execute
)
1472 BIOSLOG(bios
, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1474 offset
, i2c_index
, i2c_address
, count
);
1476 chan
= init_i2c_device_find(dev
, i2c_index
);
1478 NV_ERROR(dev
, "0x%04X: i2c bus not found\n", offset
);
1482 for (i
= 0; i
< count
; i
++) {
1483 uint8_t reg
= bios
->data
[offset
+ 4 + i
* 3];
1484 uint8_t mask
= bios
->data
[offset
+ 5 + i
* 3];
1485 uint8_t data
= bios
->data
[offset
+ 6 + i
* 3];
1486 union i2c_smbus_data val
;
1488 ret
= i2c_smbus_xfer(&chan
->adapter
, i2c_address
, 0,
1489 I2C_SMBUS_READ
, reg
,
1490 I2C_SMBUS_BYTE_DATA
, &val
);
1492 NV_ERROR(dev
, "0x%04X: i2c rd fail: %d\n", offset
, ret
);
1496 BIOSLOG(bios
, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1497 "Mask: 0x%02X, Data: 0x%02X\n",
1498 offset
, reg
, val
.byte
, mask
, data
);
1505 ret
= i2c_smbus_xfer(&chan
->adapter
, i2c_address
, 0,
1506 I2C_SMBUS_WRITE
, reg
,
1507 I2C_SMBUS_BYTE_DATA
, &val
);
1509 NV_ERROR(dev
, "0x%04X: i2c wr fail: %d\n", offset
, ret
);
1518 init_zm_i2c_byte(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1521 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1523 * offset (8 bit): opcode
1524 * offset + 1 (8 bit): DCB I2C table entry index
1525 * offset + 2 (8 bit): I2C slave address
1526 * offset + 3 (8 bit): count
1527 * offset + 4 (8 bit): I2C register 1
1528 * offset + 5 (8 bit): data 1
1531 * For each of "count" registers given by "I2C register n" on the device
1532 * addressed by "I2C slave address" on the I2C bus given by
1533 * "DCB I2C table entry index", set the register to "data n"
1536 struct drm_device
*dev
= bios
->dev
;
1537 uint8_t i2c_index
= bios
->data
[offset
+ 1];
1538 uint8_t i2c_address
= bios
->data
[offset
+ 2] >> 1;
1539 uint8_t count
= bios
->data
[offset
+ 3];
1540 struct nouveau_i2c_chan
*chan
;
1541 int len
= 4 + count
* 2;
1544 if (!iexec
->execute
)
1547 BIOSLOG(bios
, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1549 offset
, i2c_index
, i2c_address
, count
);
1551 chan
= init_i2c_device_find(dev
, i2c_index
);
1553 NV_ERROR(dev
, "0x%04X: i2c bus not found\n", offset
);
1557 for (i
= 0; i
< count
; i
++) {
1558 uint8_t reg
= bios
->data
[offset
+ 4 + i
* 2];
1559 union i2c_smbus_data val
;
1561 val
.byte
= bios
->data
[offset
+ 5 + i
* 2];
1563 BIOSLOG(bios
, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
1564 offset
, reg
, val
.byte
);
1569 ret
= i2c_smbus_xfer(&chan
->adapter
, i2c_address
, 0,
1570 I2C_SMBUS_WRITE
, reg
,
1571 I2C_SMBUS_BYTE_DATA
, &val
);
1573 NV_ERROR(dev
, "0x%04X: i2c wr fail: %d\n", offset
, ret
);
1582 init_zm_i2c(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1585 * INIT_ZM_I2C opcode: 0x4E ('N')
1587 * offset (8 bit): opcode
1588 * offset + 1 (8 bit): DCB I2C table entry index
1589 * offset + 2 (8 bit): I2C slave address
1590 * offset + 3 (8 bit): count
1591 * offset + 4 (8 bit): data 1
1594 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1595 * address" on the I2C bus given by "DCB I2C table entry index"
1598 struct drm_device
*dev
= bios
->dev
;
1599 uint8_t i2c_index
= bios
->data
[offset
+ 1];
1600 uint8_t i2c_address
= bios
->data
[offset
+ 2] >> 1;
1601 uint8_t count
= bios
->data
[offset
+ 3];
1602 int len
= 4 + count
;
1603 struct nouveau_i2c_chan
*chan
;
1608 if (!iexec
->execute
)
1611 BIOSLOG(bios
, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1613 offset
, i2c_index
, i2c_address
, count
);
1615 chan
= init_i2c_device_find(dev
, i2c_index
);
1617 NV_ERROR(dev
, "0x%04X: i2c bus not found\n", offset
);
1621 for (i
= 0; i
< count
; i
++) {
1622 data
[i
] = bios
->data
[offset
+ 4 + i
];
1624 BIOSLOG(bios
, "0x%04X: Data: 0x%02X\n", offset
, data
[i
]);
1627 if (bios
->execute
) {
1628 msg
.addr
= i2c_address
;
1632 ret
= i2c_transfer(&chan
->adapter
, &msg
, 1);
1634 NV_ERROR(dev
, "0x%04X: i2c wr fail: %d\n", offset
, ret
);
1643 init_tmds(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1646 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1648 * offset (8 bit): opcode
1649 * offset + 1 (8 bit): magic lookup value
1650 * offset + 2 (8 bit): TMDS address
1651 * offset + 3 (8 bit): mask
1652 * offset + 4 (8 bit): data
1654 * Read the data reg for TMDS address "TMDS address", AND it with mask
1655 * and OR it with data, then write it back
1656 * "magic lookup value" determines which TMDS base address register is
1657 * used -- see get_tmds_index_reg()
1660 struct drm_device
*dev
= bios
->dev
;
1661 uint8_t mlv
= bios
->data
[offset
+ 1];
1662 uint32_t tmdsaddr
= bios
->data
[offset
+ 2];
1663 uint8_t mask
= bios
->data
[offset
+ 3];
1664 uint8_t data
= bios
->data
[offset
+ 4];
1665 uint32_t reg
, value
;
1667 if (!iexec
->execute
)
1670 BIOSLOG(bios
, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1671 "Mask: 0x%02X, Data: 0x%02X\n",
1672 offset
, mlv
, tmdsaddr
, mask
, data
);
1674 reg
= get_tmds_index_reg(bios
->dev
, mlv
);
1676 NV_ERROR(dev
, "0x%04X: no tmds_index_reg\n", offset
);
1680 bios_wr32(bios
, reg
,
1681 tmdsaddr
| NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE
);
1682 value
= (bios_rd32(bios
, reg
+ 4) & mask
) | data
;
1683 bios_wr32(bios
, reg
+ 4, value
);
1684 bios_wr32(bios
, reg
, tmdsaddr
);
1690 init_zm_tmds_group(struct nvbios
*bios
, uint16_t offset
,
1691 struct init_exec
*iexec
)
1694 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1696 * offset (8 bit): opcode
1697 * offset + 1 (8 bit): magic lookup value
1698 * offset + 2 (8 bit): count
1699 * offset + 3 (8 bit): addr 1
1700 * offset + 4 (8 bit): data 1
1703 * For each of "count" TMDS address and data pairs write "data n" to
1704 * "addr n". "magic lookup value" determines which TMDS base address
1705 * register is used -- see get_tmds_index_reg()
1708 struct drm_device
*dev
= bios
->dev
;
1709 uint8_t mlv
= bios
->data
[offset
+ 1];
1710 uint8_t count
= bios
->data
[offset
+ 2];
1711 int len
= 3 + count
* 2;
1715 if (!iexec
->execute
)
1718 BIOSLOG(bios
, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1719 offset
, mlv
, count
);
1721 reg
= get_tmds_index_reg(bios
->dev
, mlv
);
1723 NV_ERROR(dev
, "0x%04X: no tmds_index_reg\n", offset
);
1727 for (i
= 0; i
< count
; i
++) {
1728 uint8_t tmdsaddr
= bios
->data
[offset
+ 3 + i
* 2];
1729 uint8_t tmdsdata
= bios
->data
[offset
+ 4 + i
* 2];
1731 bios_wr32(bios
, reg
+ 4, tmdsdata
);
1732 bios_wr32(bios
, reg
, tmdsaddr
);
1739 init_cr_idx_adr_latch(struct nvbios
*bios
, uint16_t offset
,
1740 struct init_exec
*iexec
)
1743 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1745 * offset (8 bit): opcode
1746 * offset + 1 (8 bit): CRTC index1
1747 * offset + 2 (8 bit): CRTC index2
1748 * offset + 3 (8 bit): baseaddr
1749 * offset + 4 (8 bit): count
1750 * offset + 5 (8 bit): data 1
1753 * For each of "count" address and data pairs, write "baseaddr + n" to
1754 * "CRTC index1" and "data n" to "CRTC index2"
1755 * Once complete, restore initial value read from "CRTC index1"
1757 uint8_t crtcindex1
= bios
->data
[offset
+ 1];
1758 uint8_t crtcindex2
= bios
->data
[offset
+ 2];
1759 uint8_t baseaddr
= bios
->data
[offset
+ 3];
1760 uint8_t count
= bios
->data
[offset
+ 4];
1761 int len
= 5 + count
;
1762 uint8_t oldaddr
, data
;
1765 if (!iexec
->execute
)
1768 BIOSLOG(bios
, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1769 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1770 offset
, crtcindex1
, crtcindex2
, baseaddr
, count
);
1772 oldaddr
= bios_idxprt_rd(bios
, NV_CIO_CRX__COLOR
, crtcindex1
);
1774 for (i
= 0; i
< count
; i
++) {
1775 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
, crtcindex1
,
1777 data
= bios
->data
[offset
+ 5 + i
];
1778 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
, crtcindex2
, data
);
1781 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
, crtcindex1
, oldaddr
);
1787 init_cr(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1790 * INIT_CR opcode: 0x52 ('R')
1792 * offset (8 bit): opcode
1793 * offset + 1 (8 bit): CRTC index
1794 * offset + 2 (8 bit): mask
1795 * offset + 3 (8 bit): data
1797 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1798 * data back to "CRTC index"
1801 uint8_t crtcindex
= bios
->data
[offset
+ 1];
1802 uint8_t mask
= bios
->data
[offset
+ 2];
1803 uint8_t data
= bios
->data
[offset
+ 3];
1806 if (!iexec
->execute
)
1809 BIOSLOG(bios
, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1810 offset
, crtcindex
, mask
, data
);
1812 value
= bios_idxprt_rd(bios
, NV_CIO_CRX__COLOR
, crtcindex
) & mask
;
1814 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
, crtcindex
, value
);
1820 init_zm_cr(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1823 * INIT_ZM_CR opcode: 0x53 ('S')
1825 * offset (8 bit): opcode
1826 * offset + 1 (8 bit): CRTC index
1827 * offset + 2 (8 bit): value
1829 * Assign "value" to CRTC register with index "CRTC index".
1832 uint8_t crtcindex
= ROM32(bios
->data
[offset
+ 1]);
1833 uint8_t data
= bios
->data
[offset
+ 2];
1835 if (!iexec
->execute
)
1838 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
, crtcindex
, data
);
1844 init_zm_cr_group(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1847 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1849 * offset (8 bit): opcode
1850 * offset + 1 (8 bit): count
1851 * offset + 2 (8 bit): CRTC index 1
1852 * offset + 3 (8 bit): value 1
1855 * For "count", assign "value n" to CRTC register with index
1859 uint8_t count
= bios
->data
[offset
+ 1];
1860 int len
= 2 + count
* 2;
1863 if (!iexec
->execute
)
1866 for (i
= 0; i
< count
; i
++)
1867 init_zm_cr(bios
, offset
+ 2 + 2 * i
- 1, iexec
);
1873 init_condition_time(struct nvbios
*bios
, uint16_t offset
,
1874 struct init_exec
*iexec
)
1877 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1879 * offset (8 bit): opcode
1880 * offset + 1 (8 bit): condition number
1881 * offset + 2 (8 bit): retries / 50
1883 * Check condition "condition number" in the condition table.
1884 * Bios code then sleeps for 2ms if the condition is not met, and
1885 * repeats up to "retries" times, but on one C51 this has proved
1886 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1887 * this, and bail after "retries" times, or 2s, whichever is less.
1888 * If still not met after retries, clear execution flag for this table.
1891 uint8_t cond
= bios
->data
[offset
+ 1];
1892 uint16_t retries
= bios
->data
[offset
+ 2] * 50;
1895 if (!iexec
->execute
)
1901 BIOSLOG(bios
, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1902 offset
, cond
, retries
);
1904 if (!bios
->execute
) /* avoid 2s delays when "faking" execution */
1907 for (cnt
= 0; cnt
< retries
; cnt
++) {
1908 if (bios_condition_met(bios
, offset
, cond
)) {
1909 BIOSLOG(bios
, "0x%04X: Condition met, continuing\n",
1913 BIOSLOG(bios
, "0x%04X: "
1914 "Condition not met, sleeping for 20ms\n",
1920 if (!bios_condition_met(bios
, offset
, cond
)) {
1922 "0x%04X: Condition still not met after %dms, "
1923 "skipping following opcodes\n", offset
, 20 * retries
);
1924 iexec
->execute
= false;
1931 init_ltime(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1934 * INIT_LTIME opcode: 0x57 ('V')
1936 * offset (8 bit): opcode
1937 * offset + 1 (16 bit): time
1939 * Sleep for "time" miliseconds.
1942 unsigned time
= ROM16(bios
->data
[offset
+ 1]);
1944 if (!iexec
->execute
)
1947 BIOSLOG(bios
, "0x%04X: Sleeping for 0x%04X miliseconds\n",
1956 init_zm_reg_sequence(struct nvbios
*bios
, uint16_t offset
,
1957 struct init_exec
*iexec
)
1960 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1962 * offset (8 bit): opcode
1963 * offset + 1 (32 bit): base register
1964 * offset + 5 (8 bit): count
1965 * offset + 6 (32 bit): value 1
1968 * Starting at offset + 6 there are "count" 32 bit values.
1969 * For "count" iterations set "base register" + 4 * current_iteration
1970 * to "value current_iteration"
1973 uint32_t basereg
= ROM32(bios
->data
[offset
+ 1]);
1974 uint32_t count
= bios
->data
[offset
+ 5];
1975 int len
= 6 + count
* 4;
1978 if (!iexec
->execute
)
1981 BIOSLOG(bios
, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1982 offset
, basereg
, count
);
1984 for (i
= 0; i
< count
; i
++) {
1985 uint32_t reg
= basereg
+ i
* 4;
1986 uint32_t data
= ROM32(bios
->data
[offset
+ 6 + i
* 4]);
1988 bios_wr32(bios
, reg
, data
);
1995 init_sub_direct(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1998 * INIT_SUB_DIRECT opcode: 0x5B ('[')
2000 * offset (8 bit): opcode
2001 * offset + 1 (16 bit): subroutine offset (in bios)
2003 * Calls a subroutine that will execute commands until INIT_DONE
2007 uint16_t sub_offset
= ROM16(bios
->data
[offset
+ 1]);
2009 if (!iexec
->execute
)
2012 BIOSLOG(bios
, "0x%04X: Executing subroutine at 0x%04X\n",
2013 offset
, sub_offset
);
2015 parse_init_table(bios
, sub_offset
, iexec
);
2017 BIOSLOG(bios
, "0x%04X: End of 0x%04X subroutine\n", offset
, sub_offset
);
2023 init_copy_nv_reg(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2026 * INIT_COPY_NV_REG opcode: 0x5F ('_')
2028 * offset (8 bit): opcode
2029 * offset + 1 (32 bit): src reg
2030 * offset + 5 (8 bit): shift
2031 * offset + 6 (32 bit): src mask
2032 * offset + 10 (32 bit): xor
2033 * offset + 14 (32 bit): dst reg
2034 * offset + 18 (32 bit): dst mask
2036 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
2037 * "src mask", then XOR with "xor". Write this OR'd with
2038 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
2041 uint32_t srcreg
= *((uint32_t *)(&bios
->data
[offset
+ 1]));
2042 uint8_t shift
= bios
->data
[offset
+ 5];
2043 uint32_t srcmask
= *((uint32_t *)(&bios
->data
[offset
+ 6]));
2044 uint32_t xor = *((uint32_t *)(&bios
->data
[offset
+ 10]));
2045 uint32_t dstreg
= *((uint32_t *)(&bios
->data
[offset
+ 14]));
2046 uint32_t dstmask
= *((uint32_t *)(&bios
->data
[offset
+ 18]));
2047 uint32_t srcvalue
, dstvalue
;
2049 if (!iexec
->execute
)
2052 BIOSLOG(bios
, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
2053 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
2054 offset
, srcreg
, shift
, srcmask
, xor, dstreg
, dstmask
);
2056 srcvalue
= bios_rd32(bios
, srcreg
);
2061 srcvalue
<<= (0x100 - shift
);
2063 srcvalue
= (srcvalue
& srcmask
) ^ xor;
2065 dstvalue
= bios_rd32(bios
, dstreg
) & dstmask
;
2067 bios_wr32(bios
, dstreg
, dstvalue
| srcvalue
);
2073 init_zm_index_io(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2076 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
2078 * offset (8 bit): opcode
2079 * offset + 1 (16 bit): CRTC port
2080 * offset + 3 (8 bit): CRTC index
2081 * offset + 4 (8 bit): data
2083 * Write "data" to index "CRTC index" of "CRTC port"
2085 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 1]);
2086 uint8_t crtcindex
= bios
->data
[offset
+ 3];
2087 uint8_t data
= bios
->data
[offset
+ 4];
2089 if (!iexec
->execute
)
2092 bios_idxprt_wr(bios
, crtcport
, crtcindex
, data
);
2098 bios_md32(struct nvbios
*bios
, uint32_t reg
,
2099 uint32_t mask
, uint32_t val
)
2101 bios_wr32(bios
, reg
, (bios_rd32(bios
, reg
) & ~mask
) | val
);
2105 peek_fb(struct drm_device
*dev
, struct io_mapping
*fb
,
2110 if (off
< pci_resource_len(dev
->pdev
, 1)) {
2111 uint32_t __iomem
*p
=
2112 io_mapping_map_atomic_wc(fb
, off
& PAGE_MASK
, KM_USER0
);
2114 val
= ioread32(p
+ (off
& ~PAGE_MASK
));
2116 io_mapping_unmap_atomic(p
, KM_USER0
);
2123 poke_fb(struct drm_device
*dev
, struct io_mapping
*fb
,
2124 uint32_t off
, uint32_t val
)
2126 if (off
< pci_resource_len(dev
->pdev
, 1)) {
2127 uint32_t __iomem
*p
=
2128 io_mapping_map_atomic_wc(fb
, off
& PAGE_MASK
, KM_USER0
);
2130 iowrite32(val
, p
+ (off
& ~PAGE_MASK
));
2133 io_mapping_unmap_atomic(p
, KM_USER0
);
2138 read_back_fb(struct drm_device
*dev
, struct io_mapping
*fb
,
2139 uint32_t off
, uint32_t val
)
2141 poke_fb(dev
, fb
, off
, val
);
2142 return val
== peek_fb(dev
, fb
, off
);
2146 nv04_init_compute_mem(struct nvbios
*bios
)
2148 struct drm_device
*dev
= bios
->dev
;
2149 uint32_t patt
= 0xdeadbeef;
2150 struct io_mapping
*fb
;
2153 /* Map the framebuffer aperture */
2154 fb
= io_mapping_create_wc(pci_resource_start(dev
->pdev
, 1),
2155 pci_resource_len(dev
->pdev
, 1));
2159 /* Sequencer and refresh off */
2160 NVWriteVgaSeq(dev
, 0, 1, NVReadVgaSeq(dev
, 0, 1) | 0x20);
2161 bios_md32(bios
, NV04_PFB_DEBUG_0
, 0, NV04_PFB_DEBUG_0_REFRESH_OFF
);
2163 bios_md32(bios
, NV04_PFB_BOOT_0
, ~0,
2164 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB
|
2165 NV04_PFB_BOOT_0_RAM_WIDTH_128
|
2166 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT
);
2168 for (i
= 0; i
< 4; i
++)
2169 poke_fb(dev
, fb
, 4 * i
, patt
);
2171 poke_fb(dev
, fb
, 0x400000, patt
+ 1);
2173 if (peek_fb(dev
, fb
, 0) == patt
+ 1) {
2174 bios_md32(bios
, NV04_PFB_BOOT_0
, NV04_PFB_BOOT_0_RAM_TYPE
,
2175 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT
);
2176 bios_md32(bios
, NV04_PFB_DEBUG_0
,
2177 NV04_PFB_DEBUG_0_REFRESH_OFF
, 0);
2179 for (i
= 0; i
< 4; i
++)
2180 poke_fb(dev
, fb
, 4 * i
, patt
);
2182 if ((peek_fb(dev
, fb
, 0xc) & 0xffff) != (patt
& 0xffff))
2183 bios_md32(bios
, NV04_PFB_BOOT_0
,
2184 NV04_PFB_BOOT_0_RAM_WIDTH_128
|
2185 NV04_PFB_BOOT_0_RAM_AMOUNT
,
2186 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB
);
2188 } else if ((peek_fb(dev
, fb
, 0xc) & 0xffff0000) !=
2189 (patt
& 0xffff0000)) {
2190 bios_md32(bios
, NV04_PFB_BOOT_0
,
2191 NV04_PFB_BOOT_0_RAM_WIDTH_128
|
2192 NV04_PFB_BOOT_0_RAM_AMOUNT
,
2193 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB
);
2195 } else if (peek_fb(dev
, fb
, 0) == patt
) {
2196 if (read_back_fb(dev
, fb
, 0x800000, patt
))
2197 bios_md32(bios
, NV04_PFB_BOOT_0
,
2198 NV04_PFB_BOOT_0_RAM_AMOUNT
,
2199 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB
);
2201 bios_md32(bios
, NV04_PFB_BOOT_0
,
2202 NV04_PFB_BOOT_0_RAM_AMOUNT
,
2203 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB
);
2205 bios_md32(bios
, NV04_PFB_BOOT_0
, NV04_PFB_BOOT_0_RAM_TYPE
,
2206 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT
);
2208 } else if (!read_back_fb(dev
, fb
, 0x800000, patt
)) {
2209 bios_md32(bios
, NV04_PFB_BOOT_0
, NV04_PFB_BOOT_0_RAM_AMOUNT
,
2210 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB
);
2214 /* Refresh on, sequencer on */
2215 bios_md32(bios
, NV04_PFB_DEBUG_0
, NV04_PFB_DEBUG_0_REFRESH_OFF
, 0);
2216 NVWriteVgaSeq(dev
, 0, 1, NVReadVgaSeq(dev
, 0, 1) & ~0x20);
2218 io_mapping_free(fb
);
2222 static const uint8_t *
2223 nv05_memory_config(struct nvbios
*bios
)
2225 /* Defaults for BIOSes lacking a memory config table */
2226 static const uint8_t default_config_tab
[][2] = {
2236 int i
= (bios_rd32(bios
, NV_PEXTDEV_BOOT_0
) &
2237 NV_PEXTDEV_BOOT_0_RAMCFG
) >> 2;
2239 if (bios
->legacy
.mem_init_tbl_ptr
)
2240 return &bios
->data
[bios
->legacy
.mem_init_tbl_ptr
+ 2 * i
];
2242 return default_config_tab
[i
];
2246 nv05_init_compute_mem(struct nvbios
*bios
)
2248 struct drm_device
*dev
= bios
->dev
;
2249 const uint8_t *ramcfg
= nv05_memory_config(bios
);
2250 uint32_t patt
= 0xdeadbeef;
2251 struct io_mapping
*fb
;
2254 /* Map the framebuffer aperture */
2255 fb
= io_mapping_create_wc(pci_resource_start(dev
->pdev
, 1),
2256 pci_resource_len(dev
->pdev
, 1));
2261 NVWriteVgaSeq(dev
, 0, 1, NVReadVgaSeq(dev
, 0, 1) | 0x20);
2263 if (bios_rd32(bios
, NV04_PFB_BOOT_0
) & NV04_PFB_BOOT_0_UMA_ENABLE
)
2266 bios_md32(bios
, NV04_PFB_DEBUG_0
, NV04_PFB_DEBUG_0_REFRESH_OFF
, 0);
2268 /* If present load the hardcoded scrambling table */
2269 if (bios
->legacy
.mem_init_tbl_ptr
) {
2270 uint32_t *scramble_tab
= (uint32_t *)&bios
->data
[
2271 bios
->legacy
.mem_init_tbl_ptr
+ 0x10];
2273 for (i
= 0; i
< 8; i
++)
2274 bios_wr32(bios
, NV04_PFB_SCRAMBLE(i
),
2275 ROM32(scramble_tab
[i
]));
2278 /* Set memory type/width/length defaults depending on the straps */
2279 bios_md32(bios
, NV04_PFB_BOOT_0
, 0x3f, ramcfg
[0]);
2281 if (ramcfg
[1] & 0x80)
2282 bios_md32(bios
, NV04_PFB_CFG0
, 0, NV04_PFB_CFG0_SCRAMBLE
);
2284 bios_md32(bios
, NV04_PFB_CFG1
, 0x700001, (ramcfg
[1] & 1) << 20);
2285 bios_md32(bios
, NV04_PFB_CFG1
, 0, 1);
2287 /* Probe memory bus width */
2288 for (i
= 0; i
< 4; i
++)
2289 poke_fb(dev
, fb
, 4 * i
, patt
);
2291 if (peek_fb(dev
, fb
, 0xc) != patt
)
2292 bios_md32(bios
, NV04_PFB_BOOT_0
,
2293 NV04_PFB_BOOT_0_RAM_WIDTH_128
, 0);
2295 /* Probe memory length */
2296 v
= bios_rd32(bios
, NV04_PFB_BOOT_0
) & NV04_PFB_BOOT_0_RAM_AMOUNT
;
2298 if (v
== NV04_PFB_BOOT_0_RAM_AMOUNT_32MB
&&
2299 (!read_back_fb(dev
, fb
, 0x1000000, ++patt
) ||
2300 !read_back_fb(dev
, fb
, 0, ++patt
)))
2301 bios_md32(bios
, NV04_PFB_BOOT_0
, NV04_PFB_BOOT_0_RAM_AMOUNT
,
2302 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB
);
2304 if (v
== NV04_PFB_BOOT_0_RAM_AMOUNT_16MB
&&
2305 !read_back_fb(dev
, fb
, 0x800000, ++patt
))
2306 bios_md32(bios
, NV04_PFB_BOOT_0
, NV04_PFB_BOOT_0_RAM_AMOUNT
,
2307 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB
);
2309 if (!read_back_fb(dev
, fb
, 0x400000, ++patt
))
2310 bios_md32(bios
, NV04_PFB_BOOT_0
, NV04_PFB_BOOT_0_RAM_AMOUNT
,
2311 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB
);
2315 NVWriteVgaSeq(dev
, 0, 1, NVReadVgaSeq(dev
, 0, 1) & ~0x20);
2317 io_mapping_free(fb
);
2322 nv10_init_compute_mem(struct nvbios
*bios
)
2324 struct drm_device
*dev
= bios
->dev
;
2325 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
2326 const int mem_width
[] = { 0x10, 0x00, 0x20 };
2327 const int mem_width_count
= (dev_priv
->chipset
>= 0x17 ? 3 : 2);
2328 uint32_t patt
= 0xdeadbeef;
2329 struct io_mapping
*fb
;
2332 /* Map the framebuffer aperture */
2333 fb
= io_mapping_create_wc(pci_resource_start(dev
->pdev
, 1),
2334 pci_resource_len(dev
->pdev
, 1));
2338 bios_wr32(bios
, NV10_PFB_REFCTRL
, NV10_PFB_REFCTRL_VALID_1
);
2340 /* Probe memory bus width */
2341 for (i
= 0; i
< mem_width_count
; i
++) {
2342 bios_md32(bios
, NV04_PFB_CFG0
, 0x30, mem_width
[i
]);
2344 for (j
= 0; j
< 4; j
++) {
2345 for (k
= 0; k
< 4; k
++)
2346 poke_fb(dev
, fb
, 0x1c, 0);
2348 poke_fb(dev
, fb
, 0x1c, patt
);
2349 poke_fb(dev
, fb
, 0x3c, 0);
2351 if (peek_fb(dev
, fb
, 0x1c) == patt
)
2352 goto mem_width_found
;
2359 /* Probe amount of installed memory */
2360 for (i
= 0; i
< 4; i
++) {
2361 int off
= bios_rd32(bios
, NV04_PFB_FIFO_DATA
) - 0x100000;
2363 poke_fb(dev
, fb
, off
, patt
);
2364 poke_fb(dev
, fb
, 0, 0);
2366 peek_fb(dev
, fb
, 0);
2367 peek_fb(dev
, fb
, 0);
2368 peek_fb(dev
, fb
, 0);
2369 peek_fb(dev
, fb
, 0);
2371 if (peek_fb(dev
, fb
, off
) == patt
)
2375 /* IC missing - disable the upper half memory space. */
2376 bios_md32(bios
, NV04_PFB_CFG0
, 0x1000, 0);
2379 io_mapping_free(fb
);
2384 nv20_init_compute_mem(struct nvbios
*bios
)
2386 struct drm_device
*dev
= bios
->dev
;
2387 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
2388 uint32_t mask
= (dev_priv
->chipset
>= 0x25 ? 0x300 : 0x900);
2389 uint32_t amount
, off
;
2390 struct io_mapping
*fb
;
2392 /* Map the framebuffer aperture */
2393 fb
= io_mapping_create_wc(pci_resource_start(dev
->pdev
, 1),
2394 pci_resource_len(dev
->pdev
, 1));
2398 bios_wr32(bios
, NV10_PFB_REFCTRL
, NV10_PFB_REFCTRL_VALID_1
);
2400 /* Allow full addressing */
2401 bios_md32(bios
, NV04_PFB_CFG0
, 0, mask
);
2403 amount
= bios_rd32(bios
, NV04_PFB_FIFO_DATA
);
2404 for (off
= amount
; off
> 0x2000000; off
-= 0x2000000)
2405 poke_fb(dev
, fb
, off
- 4, off
);
2407 amount
= bios_rd32(bios
, NV04_PFB_FIFO_DATA
);
2408 if (amount
!= peek_fb(dev
, fb
, amount
- 4))
2409 /* IC missing - disable the upper half memory space. */
2410 bios_md32(bios
, NV04_PFB_CFG0
, mask
, 0);
2412 io_mapping_free(fb
);
2417 init_compute_mem(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2420 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
2422 * offset (8 bit): opcode
2424 * This opcode is meant to set the PFB memory config registers
2425 * appropriately so that we can correctly calculate how much VRAM it
2426 * has (on nv10 and better chipsets the amount of installed VRAM is
2427 * subsequently reported in NV_PFB_CSTATUS (0x10020C)).
2429 * The implementation of this opcode in general consists of several
2432 * 1) Determination of memory type and density. Only necessary for
2433 * really old chipsets, the memory type reported by the strap bits
2434 * (0x101000) is assumed to be accurate on nv05 and newer.
2436 * 2) Determination of the memory bus width. Usually done by a cunning
2437 * combination of writes to offsets 0x1c and 0x3c in the fb, and
2438 * seeing whether the written values are read back correctly.
2440 * Only necessary on nv0x-nv1x and nv34, on the other cards we can
2443 * 3) Determination of how many of the card's RAM pads have ICs
2444 * attached, usually done by a cunning combination of writes to an
2445 * offset slightly less than the maximum memory reported by
2446 * NV_PFB_CSTATUS, then seeing if the test pattern can be read back.
2448 * This appears to be a NOP on IGPs and NV4x or newer chipsets, both io
2449 * logs of the VBIOS and kmmio traces of the binary driver POSTing the
2450 * card show nothing being done for this opcode. Why is it still listed
2454 /* no iexec->execute check by design */
2456 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
2459 if (dev_priv
->chipset
>= 0x40 ||
2460 dev_priv
->chipset
== 0x1a ||
2461 dev_priv
->chipset
== 0x1f)
2463 else if (dev_priv
->chipset
>= 0x20 &&
2464 dev_priv
->chipset
!= 0x34)
2465 ret
= nv20_init_compute_mem(bios
);
2466 else if (dev_priv
->chipset
>= 0x10)
2467 ret
= nv10_init_compute_mem(bios
);
2468 else if (dev_priv
->chipset
>= 0x5)
2469 ret
= nv05_init_compute_mem(bios
);
2471 ret
= nv04_init_compute_mem(bios
);
2480 init_reset(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2483 * INIT_RESET opcode: 0x65 ('e')
2485 * offset (8 bit): opcode
2486 * offset + 1 (32 bit): register
2487 * offset + 5 (32 bit): value1
2488 * offset + 9 (32 bit): value2
2490 * Assign "value1" to "register", then assign "value2" to "register"
2493 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
2494 uint32_t value1
= ROM32(bios
->data
[offset
+ 5]);
2495 uint32_t value2
= ROM32(bios
->data
[offset
+ 9]);
2496 uint32_t pci_nv_19
, pci_nv_20
;
2498 /* no iexec->execute check by design */
2500 pci_nv_19
= bios_rd32(bios
, NV_PBUS_PCI_NV_19
);
2501 bios_wr32(bios
, NV_PBUS_PCI_NV_19
, pci_nv_19
& ~0xf00);
2503 bios_wr32(bios
, reg
, value1
);
2507 bios_wr32(bios
, reg
, value2
);
2508 bios_wr32(bios
, NV_PBUS_PCI_NV_19
, pci_nv_19
);
2510 pci_nv_20
= bios_rd32(bios
, NV_PBUS_PCI_NV_20
);
2511 pci_nv_20
&= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED
; /* 0xfffffffe */
2512 bios_wr32(bios
, NV_PBUS_PCI_NV_20
, pci_nv_20
);
2518 init_configure_mem(struct nvbios
*bios
, uint16_t offset
,
2519 struct init_exec
*iexec
)
2522 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
2524 * offset (8 bit): opcode
2526 * Equivalent to INIT_DONE on bios version 3 or greater.
2527 * For early bios versions, sets up the memory registers, using values
2528 * taken from the memory init table
2531 /* no iexec->execute check by design */
2533 uint16_t meminitoffs
= bios
->legacy
.mem_init_tbl_ptr
+ MEM_INIT_SIZE
* (bios_idxprt_rd(bios
, NV_CIO_CRX__COLOR
, NV_CIO_CRE_SCRATCH4__INDEX
) >> 4);
2534 uint16_t seqtbloffs
= bios
->legacy
.sdr_seq_tbl_ptr
, meminitdata
= meminitoffs
+ 6;
2537 if (bios
->major_version
> 2)
2540 bios_idxprt_wr(bios
, NV_VIO_SRX
, NV_VIO_SR_CLOCK_INDEX
, bios_idxprt_rd(
2541 bios
, NV_VIO_SRX
, NV_VIO_SR_CLOCK_INDEX
) | 0x20);
2543 if (bios
->data
[meminitoffs
] & 1)
2544 seqtbloffs
= bios
->legacy
.ddr_seq_tbl_ptr
;
2546 for (reg
= ROM32(bios
->data
[seqtbloffs
]);
2548 reg
= ROM32(bios
->data
[seqtbloffs
+= 4])) {
2552 data
= NV04_PFB_PRE_CMD_PRECHARGE
;
2555 data
= NV04_PFB_PAD_CKE_NORMAL
;
2558 data
= NV04_PFB_REF_CMD_REFRESH
;
2561 data
= ROM32(bios
->data
[meminitdata
]);
2563 if (data
== 0xffffffff)
2567 bios_wr32(bios
, reg
, data
);
2574 init_configure_clk(struct nvbios
*bios
, uint16_t offset
,
2575 struct init_exec
*iexec
)
2578 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2580 * offset (8 bit): opcode
2582 * Equivalent to INIT_DONE on bios version 3 or greater.
2583 * For early bios versions, sets up the NVClk and MClk PLLs, using
2584 * values taken from the memory init table
2587 /* no iexec->execute check by design */
2589 uint16_t meminitoffs
= bios
->legacy
.mem_init_tbl_ptr
+ MEM_INIT_SIZE
* (bios_idxprt_rd(bios
, NV_CIO_CRX__COLOR
, NV_CIO_CRE_SCRATCH4__INDEX
) >> 4);
2592 if (bios
->major_version
> 2)
2595 clock
= ROM16(bios
->data
[meminitoffs
+ 4]) * 10;
2596 setPLL(bios
, NV_PRAMDAC_NVPLL_COEFF
, clock
);
2598 clock
= ROM16(bios
->data
[meminitoffs
+ 2]) * 10;
2599 if (bios
->data
[meminitoffs
] & 1) /* DDR */
2601 setPLL(bios
, NV_PRAMDAC_MPLL_COEFF
, clock
);
2607 init_configure_preinit(struct nvbios
*bios
, uint16_t offset
,
2608 struct init_exec
*iexec
)
2611 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2613 * offset (8 bit): opcode
2615 * Equivalent to INIT_DONE on bios version 3 or greater.
2616 * For early bios versions, does early init, loading ram and crystal
2617 * configuration from straps into CR3C
2620 /* no iexec->execute check by design */
2622 uint32_t straps
= bios_rd32(bios
, NV_PEXTDEV_BOOT_0
);
2623 uint8_t cr3c
= ((straps
<< 2) & 0xf0) | (straps
& 0x40) >> 6;
2625 if (bios
->major_version
> 2)
2628 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
,
2629 NV_CIO_CRE_SCRATCH4__INDEX
, cr3c
);
2635 init_io(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2638 * INIT_IO opcode: 0x69 ('i')
2640 * offset (8 bit): opcode
2641 * offset + 1 (16 bit): CRTC port
2642 * offset + 3 (8 bit): mask
2643 * offset + 4 (8 bit): data
2645 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2648 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
2649 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 1]);
2650 uint8_t mask
= bios
->data
[offset
+ 3];
2651 uint8_t data
= bios
->data
[offset
+ 4];
2653 if (!iexec
->execute
)
2656 BIOSLOG(bios
, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2657 offset
, crtcport
, mask
, data
);
2660 * I have no idea what this does, but NVIDIA do this magic sequence
2661 * in the places where this INIT_IO happens..
2663 if (dev_priv
->card_type
>= NV_50
&& crtcport
== 0x3c3 && data
== 1) {
2666 bios_wr32(bios
, 0x614100, (bios_rd32(
2667 bios
, 0x614100) & 0x0fffffff) | 0x00800000);
2669 bios_wr32(bios
, 0x00e18c, bios_rd32(
2670 bios
, 0x00e18c) | 0x00020000);
2672 bios_wr32(bios
, 0x614900, (bios_rd32(
2673 bios
, 0x614900) & 0x0fffffff) | 0x00800000);
2675 bios_wr32(bios
, 0x000200, bios_rd32(
2676 bios
, 0x000200) & ~0x40000000);
2680 bios_wr32(bios
, 0x00e18c, bios_rd32(
2681 bios
, 0x00e18c) & ~0x00020000);
2683 bios_wr32(bios
, 0x000200, bios_rd32(
2684 bios
, 0x000200) | 0x40000000);
2686 bios_wr32(bios
, 0x614100, 0x00800018);
2687 bios_wr32(bios
, 0x614900, 0x00800018);
2691 bios_wr32(bios
, 0x614100, 0x10000018);
2692 bios_wr32(bios
, 0x614900, 0x10000018);
2694 for (i
= 0; i
< 3; i
++)
2695 bios_wr32(bios
, 0x614280 + (i
*0x800), bios_rd32(
2696 bios
, 0x614280 + (i
*0x800)) & 0xf0f0f0f0);
2698 for (i
= 0; i
< 2; i
++)
2699 bios_wr32(bios
, 0x614300 + (i
*0x800), bios_rd32(
2700 bios
, 0x614300 + (i
*0x800)) & 0xfffff0f0);
2702 for (i
= 0; i
< 3; i
++)
2703 bios_wr32(bios
, 0x614380 + (i
*0x800), bios_rd32(
2704 bios
, 0x614380 + (i
*0x800)) & 0xfffff0f0);
2706 for (i
= 0; i
< 2; i
++)
2707 bios_wr32(bios
, 0x614200 + (i
*0x800), bios_rd32(
2708 bios
, 0x614200 + (i
*0x800)) & 0xfffffff0);
2710 for (i
= 0; i
< 2; i
++)
2711 bios_wr32(bios
, 0x614108 + (i
*0x800), bios_rd32(
2712 bios
, 0x614108 + (i
*0x800)) & 0x0fffffff);
2716 bios_port_wr(bios
, crtcport
, (bios_port_rd(bios
, crtcport
) & mask
) |
2722 init_sub(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2725 * INIT_SUB opcode: 0x6B ('k')
2727 * offset (8 bit): opcode
2728 * offset + 1 (8 bit): script number
2730 * Execute script number "script number", as a subroutine
2733 uint8_t sub
= bios
->data
[offset
+ 1];
2735 if (!iexec
->execute
)
2738 BIOSLOG(bios
, "0x%04X: Calling script %d\n", offset
, sub
);
2740 parse_init_table(bios
,
2741 ROM16(bios
->data
[bios
->init_script_tbls_ptr
+ sub
* 2]),
2744 BIOSLOG(bios
, "0x%04X: End of script %d\n", offset
, sub
);
2750 init_ram_condition(struct nvbios
*bios
, uint16_t offset
,
2751 struct init_exec
*iexec
)
2754 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2756 * offset (8 bit): opcode
2757 * offset + 1 (8 bit): mask
2758 * offset + 2 (8 bit): cmpval
2760 * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval".
2761 * If condition not met skip subsequent opcodes until condition is
2762 * inverted (INIT_NOT), or we hit INIT_RESUME
2765 uint8_t mask
= bios
->data
[offset
+ 1];
2766 uint8_t cmpval
= bios
->data
[offset
+ 2];
2769 if (!iexec
->execute
)
2772 data
= bios_rd32(bios
, NV04_PFB_BOOT_0
) & mask
;
2774 BIOSLOG(bios
, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2775 offset
, data
, cmpval
);
2778 BIOSLOG(bios
, "0x%04X: Condition fulfilled -- continuing to execute\n", offset
);
2780 BIOSLOG(bios
, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset
);
2781 iexec
->execute
= false;
2788 init_nv_reg(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2791 * INIT_NV_REG opcode: 0x6E ('n')
2793 * offset (8 bit): opcode
2794 * offset + 1 (32 bit): register
2795 * offset + 5 (32 bit): mask
2796 * offset + 9 (32 bit): data
2798 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2801 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
2802 uint32_t mask
= ROM32(bios
->data
[offset
+ 5]);
2803 uint32_t data
= ROM32(bios
->data
[offset
+ 9]);
2805 if (!iexec
->execute
)
2808 BIOSLOG(bios
, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2809 offset
, reg
, mask
, data
);
2811 bios_wr32(bios
, reg
, (bios_rd32(bios
, reg
) & mask
) | data
);
2817 init_macro(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2820 * INIT_MACRO opcode: 0x6F ('o')
2822 * offset (8 bit): opcode
2823 * offset + 1 (8 bit): macro number
2825 * Look up macro index "macro number" in the macro index table.
2826 * The macro index table entry has 1 byte for the index in the macro
2827 * table, and 1 byte for the number of times to repeat the macro.
2828 * The macro table entry has 4 bytes for the register address and
2829 * 4 bytes for the value to write to that register
2832 uint8_t macro_index_tbl_idx
= bios
->data
[offset
+ 1];
2833 uint16_t tmp
= bios
->macro_index_tbl_ptr
+ (macro_index_tbl_idx
* MACRO_INDEX_SIZE
);
2834 uint8_t macro_tbl_idx
= bios
->data
[tmp
];
2835 uint8_t count
= bios
->data
[tmp
+ 1];
2839 if (!iexec
->execute
)
2842 BIOSLOG(bios
, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2844 offset
, macro_index_tbl_idx
, macro_tbl_idx
, count
);
2846 for (i
= 0; i
< count
; i
++) {
2847 uint16_t macroentryptr
= bios
->macro_tbl_ptr
+ (macro_tbl_idx
+ i
) * MACRO_SIZE
;
2849 reg
= ROM32(bios
->data
[macroentryptr
]);
2850 data
= ROM32(bios
->data
[macroentryptr
+ 4]);
2852 bios_wr32(bios
, reg
, data
);
2859 init_done(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2862 * INIT_DONE opcode: 0x71 ('q')
2864 * offset (8 bit): opcode
2866 * End the current script
2869 /* mild retval abuse to stop parsing this table */
2874 init_resume(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2877 * INIT_RESUME opcode: 0x72 ('r')
2879 * offset (8 bit): opcode
2881 * End the current execute / no-execute condition
2887 iexec
->execute
= true;
2888 BIOSLOG(bios
, "0x%04X: ---- Executing following commands ----\n", offset
);
2894 init_time(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2897 * INIT_TIME opcode: 0x74 ('t')
2899 * offset (8 bit): opcode
2900 * offset + 1 (16 bit): time
2902 * Sleep for "time" microseconds.
2905 unsigned time
= ROM16(bios
->data
[offset
+ 1]);
2907 if (!iexec
->execute
)
2910 BIOSLOG(bios
, "0x%04X: Sleeping for 0x%04X microseconds\n",
2916 msleep((time
+ 900) / 1000);
2922 init_condition(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2925 * INIT_CONDITION opcode: 0x75 ('u')
2927 * offset (8 bit): opcode
2928 * offset + 1 (8 bit): condition number
2930 * Check condition "condition number" in the condition table.
2931 * If condition not met skip subsequent opcodes until condition is
2932 * inverted (INIT_NOT), or we hit INIT_RESUME
2935 uint8_t cond
= bios
->data
[offset
+ 1];
2937 if (!iexec
->execute
)
2940 BIOSLOG(bios
, "0x%04X: Condition: 0x%02X\n", offset
, cond
);
2942 if (bios_condition_met(bios
, offset
, cond
))
2943 BIOSLOG(bios
, "0x%04X: Condition fulfilled -- continuing to execute\n", offset
);
2945 BIOSLOG(bios
, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset
);
2946 iexec
->execute
= false;
2953 init_io_condition(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2956 * INIT_IO_CONDITION opcode: 0x76
2958 * offset (8 bit): opcode
2959 * offset + 1 (8 bit): condition number
2961 * Check condition "condition number" in the io condition table.
2962 * If condition not met skip subsequent opcodes until condition is
2963 * inverted (INIT_NOT), or we hit INIT_RESUME
2966 uint8_t cond
= bios
->data
[offset
+ 1];
2968 if (!iexec
->execute
)
2971 BIOSLOG(bios
, "0x%04X: IO condition: 0x%02X\n", offset
, cond
);
2973 if (io_condition_met(bios
, offset
, cond
))
2974 BIOSLOG(bios
, "0x%04X: Condition fulfilled -- continuing to execute\n", offset
);
2976 BIOSLOG(bios
, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset
);
2977 iexec
->execute
= false;
2984 init_index_io(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2987 * INIT_INDEX_IO opcode: 0x78 ('x')
2989 * offset (8 bit): opcode
2990 * offset + 1 (16 bit): CRTC port
2991 * offset + 3 (8 bit): CRTC index
2992 * offset + 4 (8 bit): mask
2993 * offset + 5 (8 bit): data
2995 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
2996 * OR with "data", write-back
2999 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 1]);
3000 uint8_t crtcindex
= bios
->data
[offset
+ 3];
3001 uint8_t mask
= bios
->data
[offset
+ 4];
3002 uint8_t data
= bios
->data
[offset
+ 5];
3005 if (!iexec
->execute
)
3008 BIOSLOG(bios
, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
3010 offset
, crtcport
, crtcindex
, mask
, data
);
3012 value
= (bios_idxprt_rd(bios
, crtcport
, crtcindex
) & mask
) | data
;
3013 bios_idxprt_wr(bios
, crtcport
, crtcindex
, value
);
3019 init_pll(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
3022 * INIT_PLL opcode: 0x79 ('y')
3024 * offset (8 bit): opcode
3025 * offset + 1 (32 bit): register
3026 * offset + 5 (16 bit): freq
3028 * Set PLL register "register" to coefficients for frequency (10kHz)
3032 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
3033 uint16_t freq
= ROM16(bios
->data
[offset
+ 5]);
3035 if (!iexec
->execute
)
3038 BIOSLOG(bios
, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset
, reg
, freq
);
3040 setPLL(bios
, reg
, freq
* 10);
3046 init_zm_reg(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
3049 * INIT_ZM_REG opcode: 0x7A ('z')
3051 * offset (8 bit): opcode
3052 * offset + 1 (32 bit): register
3053 * offset + 5 (32 bit): value
3055 * Assign "value" to "register"
3058 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
3059 uint32_t value
= ROM32(bios
->data
[offset
+ 5]);
3061 if (!iexec
->execute
)
3064 if (reg
== 0x000200)
3067 bios_wr32(bios
, reg
, value
);
3073 init_ram_restrict_pll(struct nvbios
*bios
, uint16_t offset
,
3074 struct init_exec
*iexec
)
3077 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
3079 * offset (8 bit): opcode
3080 * offset + 1 (8 bit): PLL type
3081 * offset + 2 (32 bit): frequency 0
3083 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3084 * ram_restrict_table_ptr. The value read from there is used to select
3085 * a frequency from the table starting at 'frequency 0' to be
3086 * programmed into the PLL corresponding to 'type'.
3088 * The PLL limits table on cards using this opcode has a mapping of
3089 * 'type' to the relevant registers.
3092 struct drm_device
*dev
= bios
->dev
;
3093 uint32_t strap
= (bios_rd32(bios
, NV_PEXTDEV_BOOT_0
) & 0x0000003c) >> 2;
3094 uint8_t index
= bios
->data
[bios
->ram_restrict_tbl_ptr
+ strap
];
3095 uint8_t type
= bios
->data
[offset
+ 1];
3096 uint32_t freq
= ROM32(bios
->data
[offset
+ 2 + (index
* 4)]);
3097 uint8_t *pll_limits
= &bios
->data
[bios
->pll_limit_tbl_ptr
], *entry
;
3098 int len
= 2 + bios
->ram_restrict_group_count
* 4;
3101 if (!iexec
->execute
)
3104 if (!bios
->pll_limit_tbl_ptr
|| (pll_limits
[0] & 0xf0) != 0x30) {
3105 NV_ERROR(dev
, "PLL limits table not version 3.x\n");
3106 return len
; /* deliberate, allow default clocks to remain */
3109 entry
= pll_limits
+ pll_limits
[1];
3110 for (i
= 0; i
< pll_limits
[3]; i
++, entry
+= pll_limits
[2]) {
3111 if (entry
[0] == type
) {
3112 uint32_t reg
= ROM32(entry
[3]);
3114 BIOSLOG(bios
, "0x%04X: "
3115 "Type %02x Reg 0x%08x Freq %dKHz\n",
3116 offset
, type
, reg
, freq
);
3118 setPLL(bios
, reg
, freq
);
3123 NV_ERROR(dev
, "PLL type 0x%02x not found in PLL limits table", type
);
3128 init_8c(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
3131 * INIT_8C opcode: 0x8C ('')
3141 init_8d(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
3144 * INIT_8D opcode: 0x8D ('')
3154 init_gpio(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
3157 * INIT_GPIO opcode: 0x8E ('')
3159 * offset (8 bit): opcode
3161 * Loop over all entries in the DCB GPIO table, and initialise
3162 * each GPIO according to various values listed in each entry
3165 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
3166 struct nouveau_gpio_engine
*pgpio
= &dev_priv
->engine
.gpio
;
3167 const uint32_t nv50_gpio_ctl
[2] = { 0xe100, 0xe28c };
3170 if (dev_priv
->card_type
< NV_50
) {
3171 NV_ERROR(bios
->dev
, "INIT_GPIO on unsupported chipset\n");
3175 if (!iexec
->execute
)
3178 for (i
= 0; i
< bios
->dcb
.gpio
.entries
; i
++) {
3179 struct dcb_gpio_entry
*gpio
= &bios
->dcb
.gpio
.entry
[i
];
3182 BIOSLOG(bios
, "0x%04X: Entry: 0x%08X\n", offset
, gpio
->entry
);
3184 BIOSLOG(bios
, "0x%04X: set gpio 0x%02x, state %d\n",
3185 offset
, gpio
->tag
, gpio
->state_default
);
3187 pgpio
->set(bios
->dev
, gpio
->tag
, gpio
->state_default
);
3189 /* The NVIDIA binary driver doesn't appear to actually do
3190 * any of this, my VBIOS does however.
3192 /* Not a clue, needs de-magicing */
3193 r
= nv50_gpio_ctl
[gpio
->line
>> 4];
3194 s
= (gpio
->line
& 0x0f);
3195 v
= bios_rd32(bios
, r
) & ~(0x00010001 << s
);
3196 switch ((gpio
->entry
& 0x06000000) >> 25) {
3198 v
|= (0x00000001 << s
);
3201 v
|= (0x00010000 << s
);
3206 bios_wr32(bios
, r
, v
);
3213 init_ram_restrict_zm_reg_group(struct nvbios
*bios
, uint16_t offset
,
3214 struct init_exec
*iexec
)
3217 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
3219 * offset (8 bit): opcode
3220 * offset + 1 (32 bit): reg
3221 * offset + 5 (8 bit): regincrement
3222 * offset + 6 (8 bit): count
3223 * offset + 7 (32 bit): value 1,1
3226 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3227 * ram_restrict_table_ptr. The value read from here is 'n', and
3228 * "value 1,n" gets written to "reg". This repeats "count" times and on
3229 * each iteration 'm', "reg" increases by "regincrement" and
3230 * "value m,n" is used. The extent of n is limited by a number read
3231 * from the 'M' BIT table, herein called "blocklen"
3234 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
3235 uint8_t regincrement
= bios
->data
[offset
+ 5];
3236 uint8_t count
= bios
->data
[offset
+ 6];
3237 uint32_t strap_ramcfg
, data
;
3238 /* previously set by 'M' BIT table */
3239 uint16_t blocklen
= bios
->ram_restrict_group_count
* 4;
3240 int len
= 7 + count
* blocklen
;
3244 /* critical! to know the length of the opcode */;
3247 "0x%04X: Zero block length - has the M table "
3248 "been parsed?\n", offset
);
3252 if (!iexec
->execute
)
3255 strap_ramcfg
= (bios_rd32(bios
, NV_PEXTDEV_BOOT_0
) >> 2) & 0xf;
3256 index
= bios
->data
[bios
->ram_restrict_tbl_ptr
+ strap_ramcfg
];
3258 BIOSLOG(bios
, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
3259 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
3260 offset
, reg
, regincrement
, count
, strap_ramcfg
, index
);
3262 for (i
= 0; i
< count
; i
++) {
3263 data
= ROM32(bios
->data
[offset
+ 7 + index
* 4 + blocklen
* i
]);
3265 bios_wr32(bios
, reg
, data
);
3267 reg
+= regincrement
;
3274 init_copy_zm_reg(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
3277 * INIT_COPY_ZM_REG opcode: 0x90 ('')
3279 * offset (8 bit): opcode
3280 * offset + 1 (32 bit): src reg
3281 * offset + 5 (32 bit): dst reg
3283 * Put contents of "src reg" into "dst reg"
3286 uint32_t srcreg
= ROM32(bios
->data
[offset
+ 1]);
3287 uint32_t dstreg
= ROM32(bios
->data
[offset
+ 5]);
3289 if (!iexec
->execute
)
3292 bios_wr32(bios
, dstreg
, bios_rd32(bios
, srcreg
));
3298 init_zm_reg_group_addr_latched(struct nvbios
*bios
, uint16_t offset
,
3299 struct init_exec
*iexec
)
3302 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
3304 * offset (8 bit): opcode
3305 * offset + 1 (32 bit): dst reg
3306 * offset + 5 (8 bit): count
3307 * offset + 6 (32 bit): data 1
3310 * For each of "count" values write "data n" to "dst reg"
3313 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
3314 uint8_t count
= bios
->data
[offset
+ 5];
3315 int len
= 6 + count
* 4;
3318 if (!iexec
->execute
)
3321 for (i
= 0; i
< count
; i
++) {
3322 uint32_t data
= ROM32(bios
->data
[offset
+ 6 + 4 * i
]);
3323 bios_wr32(bios
, reg
, data
);
3330 init_reserved(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
3333 * INIT_RESERVED opcode: 0x92 ('')
3335 * offset (8 bit): opcode
3337 * Seemingly does nothing
3344 init_96(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
3347 * INIT_96 opcode: 0x96 ('')
3349 * offset (8 bit): opcode
3350 * offset + 1 (32 bit): sreg
3351 * offset + 5 (8 bit): sshift
3352 * offset + 6 (8 bit): smask
3353 * offset + 7 (8 bit): index
3354 * offset + 8 (32 bit): reg
3355 * offset + 12 (32 bit): mask
3356 * offset + 16 (8 bit): shift
3360 uint16_t xlatptr
= bios
->init96_tbl_ptr
+ (bios
->data
[offset
+ 7] * 2);
3361 uint32_t reg
= ROM32(bios
->data
[offset
+ 8]);
3362 uint32_t mask
= ROM32(bios
->data
[offset
+ 12]);
3365 val
= bios_rd32(bios
, ROM32(bios
->data
[offset
+ 1]));
3366 if (bios
->data
[offset
+ 5] < 0x80)
3367 val
>>= bios
->data
[offset
+ 5];
3369 val
<<= (0x100 - bios
->data
[offset
+ 5]);
3370 val
&= bios
->data
[offset
+ 6];
3372 val
= bios
->data
[ROM16(bios
->data
[xlatptr
]) + val
];
3373 val
<<= bios
->data
[offset
+ 16];
3375 if (!iexec
->execute
)
3378 bios_wr32(bios
, reg
, (bios_rd32(bios
, reg
) & mask
) | val
);
3383 init_97(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
3386 * INIT_97 opcode: 0x97 ('')
3388 * offset (8 bit): opcode
3389 * offset + 1 (32 bit): register
3390 * offset + 5 (32 bit): mask
3391 * offset + 9 (32 bit): value
3393 * Adds "value" to "register" preserving the fields specified
3397 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
3398 uint32_t mask
= ROM32(bios
->data
[offset
+ 5]);
3399 uint32_t add
= ROM32(bios
->data
[offset
+ 9]);
3402 val
= bios_rd32(bios
, reg
);
3403 val
= (val
& mask
) | ((val
+ add
) & ~mask
);
3405 if (!iexec
->execute
)
3408 bios_wr32(bios
, reg
, val
);
3413 init_auxch(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
3416 * INIT_AUXCH opcode: 0x98 ('')
3418 * offset (8 bit): opcode
3419 * offset + 1 (32 bit): address
3420 * offset + 5 (8 bit): count
3421 * offset + 6 (8 bit): mask 0
3422 * offset + 7 (8 bit): data 0
3427 struct drm_device
*dev
= bios
->dev
;
3428 struct nouveau_i2c_chan
*auxch
;
3429 uint32_t addr
= ROM32(bios
->data
[offset
+ 1]);
3430 uint8_t count
= bios
->data
[offset
+ 5];
3431 int len
= 6 + count
* 2;
3434 if (!bios
->display
.output
) {
3435 NV_ERROR(dev
, "INIT_AUXCH: no active output\n");
3439 auxch
= init_i2c_device_find(dev
, bios
->display
.output
->i2c_index
);
3441 NV_ERROR(dev
, "INIT_AUXCH: couldn't get auxch %d\n",
3442 bios
->display
.output
->i2c_index
);
3446 if (!iexec
->execute
)
3450 for (i
= 0; i
< count
; i
++, offset
+= 2) {
3453 ret
= nouveau_dp_auxch(auxch
, 9, addr
, &data
, 1);
3455 NV_ERROR(dev
, "INIT_AUXCH: rd auxch fail %d\n", ret
);
3459 data
&= bios
->data
[offset
+ 0];
3460 data
|= bios
->data
[offset
+ 1];
3462 ret
= nouveau_dp_auxch(auxch
, 8, addr
, &data
, 1);
3464 NV_ERROR(dev
, "INIT_AUXCH: wr auxch fail %d\n", ret
);
3473 init_zm_auxch(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
3476 * INIT_ZM_AUXCH opcode: 0x99 ('')
3478 * offset (8 bit): opcode
3479 * offset + 1 (32 bit): address
3480 * offset + 5 (8 bit): count
3481 * offset + 6 (8 bit): data 0
3486 struct drm_device
*dev
= bios
->dev
;
3487 struct nouveau_i2c_chan
*auxch
;
3488 uint32_t addr
= ROM32(bios
->data
[offset
+ 1]);
3489 uint8_t count
= bios
->data
[offset
+ 5];
3490 int len
= 6 + count
;
3493 if (!bios
->display
.output
) {
3494 NV_ERROR(dev
, "INIT_ZM_AUXCH: no active output\n");
3498 auxch
= init_i2c_device_find(dev
, bios
->display
.output
->i2c_index
);
3500 NV_ERROR(dev
, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
3501 bios
->display
.output
->i2c_index
);
3505 if (!iexec
->execute
)
3509 for (i
= 0; i
< count
; i
++, offset
++) {
3510 ret
= nouveau_dp_auxch(auxch
, 8, addr
, &bios
->data
[offset
], 1);
3512 NV_ERROR(dev
, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret
);
3520 static struct init_tbl_entry itbl_entry
[] = {
3521 /* command name , id , length , offset , mult , command handler */
3522 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
3523 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog
},
3524 { "INIT_REPEAT" , 0x33, init_repeat
},
3525 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll
},
3526 { "INIT_END_REPEAT" , 0x36, init_end_repeat
},
3527 { "INIT_COPY" , 0x37, init_copy
},
3528 { "INIT_NOT" , 0x38, init_not
},
3529 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition
},
3530 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition
},
3531 { "INIT_OP_3B" , 0x3B, init_op_3b
},
3532 { "INIT_OP_3C" , 0x3C, init_op_3c
},
3533 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched
},
3534 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2
},
3535 { "INIT_PLL2" , 0x4B, init_pll2
},
3536 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte
},
3537 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte
},
3538 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c
},
3539 { "INIT_TMDS" , 0x4F, init_tmds
},
3540 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group
},
3541 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch
},
3542 { "INIT_CR" , 0x52, init_cr
},
3543 { "INIT_ZM_CR" , 0x53, init_zm_cr
},
3544 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group
},
3545 { "INIT_CONDITION_TIME" , 0x56, init_condition_time
},
3546 { "INIT_LTIME" , 0x57, init_ltime
},
3547 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence
},
3548 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
3549 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct
},
3550 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg
},
3551 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io
},
3552 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem
},
3553 { "INIT_RESET" , 0x65, init_reset
},
3554 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem
},
3555 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk
},
3556 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit
},
3557 { "INIT_IO" , 0x69, init_io
},
3558 { "INIT_SUB" , 0x6B, init_sub
},
3559 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition
},
3560 { "INIT_NV_REG" , 0x6E, init_nv_reg
},
3561 { "INIT_MACRO" , 0x6F, init_macro
},
3562 { "INIT_DONE" , 0x71, init_done
},
3563 { "INIT_RESUME" , 0x72, init_resume
},
3564 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
3565 { "INIT_TIME" , 0x74, init_time
},
3566 { "INIT_CONDITION" , 0x75, init_condition
},
3567 { "INIT_IO_CONDITION" , 0x76, init_io_condition
},
3568 { "INIT_INDEX_IO" , 0x78, init_index_io
},
3569 { "INIT_PLL" , 0x79, init_pll
},
3570 { "INIT_ZM_REG" , 0x7A, init_zm_reg
},
3571 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll
},
3572 { "INIT_8C" , 0x8C, init_8c
},
3573 { "INIT_8D" , 0x8D, init_8d
},
3574 { "INIT_GPIO" , 0x8E, init_gpio
},
3575 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group
},
3576 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg
},
3577 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched
},
3578 { "INIT_RESERVED" , 0x92, init_reserved
},
3579 { "INIT_96" , 0x96, init_96
},
3580 { "INIT_97" , 0x97, init_97
},
3581 { "INIT_AUXCH" , 0x98, init_auxch
},
3582 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch
},
3586 #define MAX_TABLE_OPS 1000
3589 parse_init_table(struct nvbios
*bios
, unsigned int offset
,
3590 struct init_exec
*iexec
)
3593 * Parses all commands in an init table.
3595 * We start out executing all commands found in the init table. Some
3596 * opcodes may change the status of iexec->execute to SKIP, which will
3597 * cause the following opcodes to perform no operation until the value
3598 * is changed back to EXECUTE.
3601 int count
= 0, i
, ret
;
3605 * Loop until INIT_DONE causes us to break out of the loop
3606 * (or until offset > bios length just in case... )
3607 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3609 while ((offset
< bios
->length
) && (count
++ < MAX_TABLE_OPS
)) {
3610 id
= bios
->data
[offset
];
3612 /* Find matching id in itbl_entry */
3613 for (i
= 0; itbl_entry
[i
].name
&& (itbl_entry
[i
].id
!= id
); i
++)
3616 if (!itbl_entry
[i
].name
) {
3618 "0x%04X: Init table command not found: "
3619 "0x%02X\n", offset
, id
);
3623 BIOSLOG(bios
, "0x%04X: [ (0x%02X) - %s ]\n", offset
,
3624 itbl_entry
[i
].id
, itbl_entry
[i
].name
);
3626 /* execute eventual command handler */
3627 ret
= (*itbl_entry
[i
].handler
)(bios
, offset
, iexec
);
3629 NV_ERROR(bios
->dev
, "0x%04X: Failed parsing init "
3630 "table opcode: %s %d\n", offset
,
3631 itbl_entry
[i
].name
, ret
);
3638 * Add the offset of the current command including all data
3639 * of that command. The offset will then be pointing on the
3645 if (offset
>= bios
->length
)
3647 "Offset 0x%04X greater than known bios image length. "
3648 "Corrupt image?\n", offset
);
3649 if (count
>= MAX_TABLE_OPS
)
3651 "More than %d opcodes to a table is unlikely, "
3652 "is the bios image corrupt?\n", MAX_TABLE_OPS
);
3658 parse_init_tables(struct nvbios
*bios
)
3660 /* Loops and calls parse_init_table() for each present table. */
3664 struct init_exec iexec
= {true, false};
3666 if (bios
->old_style_init
) {
3667 if (bios
->init_script_tbls_ptr
)
3668 parse_init_table(bios
, bios
->init_script_tbls_ptr
, &iexec
);
3669 if (bios
->extra_init_script_tbl_ptr
)
3670 parse_init_table(bios
, bios
->extra_init_script_tbl_ptr
, &iexec
);
3675 while ((table
= ROM16(bios
->data
[bios
->init_script_tbls_ptr
+ i
]))) {
3677 "Parsing VBIOS init table %d at offset 0x%04X\n",
3679 BIOSLOG(bios
, "0x%04X: ------ Executing following commands ------\n", table
);
3681 parse_init_table(bios
, table
, &iexec
);
3686 static uint16_t clkcmptable(struct nvbios
*bios
, uint16_t clktable
, int pxclk
)
3688 int compare_record_len
, i
= 0;
3689 uint16_t compareclk
, scriptptr
= 0;
3691 if (bios
->major_version
< 5) /* pre BIT */
3692 compare_record_len
= 3;
3694 compare_record_len
= 4;
3697 compareclk
= ROM16(bios
->data
[clktable
+ compare_record_len
* i
]);
3698 if (pxclk
>= compareclk
* 10) {
3699 if (bios
->major_version
< 5) {
3700 uint8_t tmdssub
= bios
->data
[clktable
+ 2 + compare_record_len
* i
];
3701 scriptptr
= ROM16(bios
->data
[bios
->init_script_tbls_ptr
+ tmdssub
* 2]);
3703 scriptptr
= ROM16(bios
->data
[clktable
+ 2 + compare_record_len
* i
]);
3707 } while (compareclk
);
3713 run_digital_op_script(struct drm_device
*dev
, uint16_t scriptptr
,
3714 struct dcb_entry
*dcbent
, int head
, bool dl
)
3716 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3717 struct nvbios
*bios
= &dev_priv
->vbios
;
3718 struct init_exec iexec
= {true, false};
3720 NV_TRACE(dev
, "0x%04X: Parsing digital output script table\n",
3722 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
, NV_CIO_CRE_44
,
3723 head
? NV_CIO_CRE_44_HEADB
: NV_CIO_CRE_44_HEADA
);
3724 /* note: if dcb entries have been merged, index may be misleading */
3725 NVWriteVgaCrtc5758(dev
, head
, 0, dcbent
->index
);
3726 parse_init_table(bios
, scriptptr
, &iexec
);
3728 nv04_dfp_bind_head(dev
, dcbent
, head
, dl
);
3731 static int call_lvds_manufacturer_script(struct drm_device
*dev
, struct dcb_entry
*dcbent
, int head
, enum LVDS_script script
)
3733 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3734 struct nvbios
*bios
= &dev_priv
->vbios
;
3735 uint8_t sub
= bios
->data
[bios
->fp
.xlated_entry
+ script
] + (bios
->fp
.link_c_increment
&& dcbent
->or & OUTPUT_C
? 1 : 0);
3736 uint16_t scriptofs
= ROM16(bios
->data
[bios
->init_script_tbls_ptr
+ sub
* 2]);
3738 if (!bios
->fp
.xlated_entry
|| !sub
|| !scriptofs
)
3741 run_digital_op_script(dev
, scriptofs
, dcbent
, head
, bios
->fp
.dual_link
);
3743 if (script
== LVDS_PANEL_OFF
) {
3744 /* off-on delay in ms */
3745 msleep(ROM16(bios
->data
[bios
->fp
.xlated_entry
+ 7]));
3748 /* Powerbook specific quirks */
3749 if ((dev
->pci_device
& 0xffff) == 0x0179 ||
3750 (dev
->pci_device
& 0xffff) == 0x0189 ||
3751 (dev
->pci_device
& 0xffff) == 0x0329) {
3752 if (script
== LVDS_RESET
) {
3753 nv_write_tmds(dev
, dcbent
->or, 0, 0x02, 0x72);
3755 } else if (script
== LVDS_PANEL_ON
) {
3756 bios_wr32(bios
, NV_PBUS_DEBUG_DUALHEAD_CTL
,
3757 bios_rd32(bios
, NV_PBUS_DEBUG_DUALHEAD_CTL
)
3759 bios_wr32(bios
, NV_PCRTC_GPIO_EXT
,
3760 bios_rd32(bios
, NV_PCRTC_GPIO_EXT
) | 1);
3762 } else if (script
== LVDS_PANEL_OFF
) {
3763 bios_wr32(bios
, NV_PBUS_DEBUG_DUALHEAD_CTL
,
3764 bios_rd32(bios
, NV_PBUS_DEBUG_DUALHEAD_CTL
)
3766 bios_wr32(bios
, NV_PCRTC_GPIO_EXT
,
3767 bios_rd32(bios
, NV_PCRTC_GPIO_EXT
) & ~3);
3775 static int run_lvds_table(struct drm_device
*dev
, struct dcb_entry
*dcbent
, int head
, enum LVDS_script script
, int pxclk
)
3778 * The BIT LVDS table's header has the information to setup the
3779 * necessary registers. Following the standard 4 byte header are:
3780 * A bitmask byte and a dual-link transition pxclk value for use in
3781 * selecting the init script when not using straps; 4 script pointers
3782 * for panel power, selected by output and on/off; and 8 table pointers
3783 * for panel init, the needed one determined by output, and bits in the
3784 * conf byte. These tables are similar to the TMDS tables, consisting
3785 * of a list of pxclks and script pointers.
3787 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3788 struct nvbios
*bios
= &dev_priv
->vbios
;
3789 unsigned int outputset
= (dcbent
->or == 4) ? 1 : 0;
3790 uint16_t scriptptr
= 0, clktable
;
3793 * For now we assume version 3.0 table - g80 support will need some
3800 case LVDS_BACKLIGHT_ON
:
3802 scriptptr
= ROM16(bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 7 + outputset
* 2]);
3804 case LVDS_BACKLIGHT_OFF
:
3805 case LVDS_PANEL_OFF
:
3806 scriptptr
= ROM16(bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 11 + outputset
* 2]);
3809 clktable
= bios
->fp
.lvdsmanufacturerpointer
+ 15;
3810 if (dcbent
->or == 4)
3813 if (dcbent
->lvdsconf
.use_straps_for_mode
) {
3814 if (bios
->fp
.dual_link
)
3816 if (bios
->fp
.if_is_24bit
)
3820 int cmpval_24bit
= (dcbent
->or == 4) ? 4 : 1;
3822 if (bios
->fp
.dual_link
) {
3827 if (bios
->fp
.strapless_is_24bit
& cmpval_24bit
)
3831 clktable
= ROM16(bios
->data
[clktable
]);
3833 NV_ERROR(dev
, "Pixel clock comparison table not found\n");
3836 scriptptr
= clkcmptable(bios
, clktable
, pxclk
);
3840 NV_ERROR(dev
, "LVDS output init script not found\n");
3843 run_digital_op_script(dev
, scriptptr
, dcbent
, head
, bios
->fp
.dual_link
);
3848 int call_lvds_script(struct drm_device
*dev
, struct dcb_entry
*dcbent
, int head
, enum LVDS_script script
, int pxclk
)
3851 * LVDS operations are multiplexed in an effort to present a single API
3852 * which works with two vastly differing underlying structures.
3853 * This acts as the demux
3856 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3857 struct nvbios
*bios
= &dev_priv
->vbios
;
3858 uint8_t lvds_ver
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
];
3859 uint32_t sel_clk_binding
, sel_clk
;
3862 if (bios
->fp
.last_script_invoc
== (script
<< 1 | head
) || !lvds_ver
||
3863 (lvds_ver
>= 0x30 && script
== LVDS_INIT
))
3866 if (!bios
->fp
.lvds_init_run
) {
3867 bios
->fp
.lvds_init_run
= true;
3868 call_lvds_script(dev
, dcbent
, head
, LVDS_INIT
, pxclk
);
3871 if (script
== LVDS_PANEL_ON
&& bios
->fp
.reset_after_pclk_change
)
3872 call_lvds_script(dev
, dcbent
, head
, LVDS_RESET
, pxclk
);
3873 if (script
== LVDS_RESET
&& bios
->fp
.power_off_for_reset
)
3874 call_lvds_script(dev
, dcbent
, head
, LVDS_PANEL_OFF
, pxclk
);
3876 NV_TRACE(dev
, "Calling LVDS script %d:\n", script
);
3878 /* don't let script change pll->head binding */
3879 sel_clk_binding
= bios_rd32(bios
, NV_PRAMDAC_SEL_CLK
) & 0x50000;
3881 if (lvds_ver
< 0x30)
3882 ret
= call_lvds_manufacturer_script(dev
, dcbent
, head
, script
);
3884 ret
= run_lvds_table(dev
, dcbent
, head
, script
, pxclk
);
3886 bios
->fp
.last_script_invoc
= (script
<< 1 | head
);
3888 sel_clk
= NVReadRAMDAC(dev
, 0, NV_PRAMDAC_SEL_CLK
) & ~0x50000;
3889 NVWriteRAMDAC(dev
, 0, NV_PRAMDAC_SEL_CLK
, sel_clk
| sel_clk_binding
);
3890 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
3891 nvWriteMC(dev
, NV_PBUS_POWERCTRL_2
, 0);
3896 struct lvdstableheader
{
3897 uint8_t lvds_ver
, headerlen
, recordlen
;
3900 static int parse_lvds_manufacturer_table_header(struct drm_device
*dev
, struct nvbios
*bios
, struct lvdstableheader
*lth
)
3903 * BMP version (0xa) LVDS table has a simple header of version and
3904 * record length. The BIT LVDS table has the typical BIT table header:
3905 * version byte, header length byte, record length byte, and a byte for
3906 * the maximum number of records that can be held in the table.
3909 uint8_t lvds_ver
, headerlen
, recordlen
;
3911 memset(lth
, 0, sizeof(struct lvdstableheader
));
3913 if (bios
->fp
.lvdsmanufacturerpointer
== 0x0) {
3914 NV_ERROR(dev
, "Pointer to LVDS manufacturer table invalid\n");
3918 lvds_ver
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
];
3921 case 0x0a: /* pre NV40 */
3923 recordlen
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 1];
3925 case 0x30: /* NV4x */
3926 headerlen
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 1];
3927 if (headerlen
< 0x1f) {
3928 NV_ERROR(dev
, "LVDS table header not understood\n");
3931 recordlen
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 2];
3933 case 0x40: /* G80/G90 */
3934 headerlen
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 1];
3935 if (headerlen
< 0x7) {
3936 NV_ERROR(dev
, "LVDS table header not understood\n");
3939 recordlen
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 2];
3943 "LVDS table revision %d.%d not currently supported\n",
3944 lvds_ver
>> 4, lvds_ver
& 0xf);
3948 lth
->lvds_ver
= lvds_ver
;
3949 lth
->headerlen
= headerlen
;
3950 lth
->recordlen
= recordlen
;
3956 get_fp_strap(struct drm_device
*dev
, struct nvbios
*bios
)
3958 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3961 * The fp strap is normally dictated by the "User Strap" in
3962 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
3963 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
3964 * by the PCI subsystem ID during POST, but not before the previous user
3965 * strap has been committed to CR58 for CR57=0xf on head A, which may be
3966 * read and used instead
3969 if (bios
->major_version
< 5 && bios
->data
[0x48] & 0x4)
3970 return NVReadVgaCrtc5758(dev
, 0, 0xf) & 0xf;
3972 if (dev_priv
->card_type
>= NV_50
)
3973 return (bios_rd32(bios
, NV_PEXTDEV_BOOT_0
) >> 24) & 0xf;
3975 return (bios_rd32(bios
, NV_PEXTDEV_BOOT_0
) >> 16) & 0xf;
3978 static int parse_fp_mode_table(struct drm_device
*dev
, struct nvbios
*bios
)
3981 uint8_t fptable_ver
, headerlen
= 0, recordlen
, fpentries
= 0xf, fpindex
;
3982 int ret
, ofs
, fpstrapping
;
3983 struct lvdstableheader lth
;
3985 if (bios
->fp
.fptablepointer
== 0x0) {
3986 /* Apple cards don't have the fp table; the laptops use DDC */
3987 /* The table is also missing on some x86 IGPs */
3989 NV_ERROR(dev
, "Pointer to flat panel table invalid\n");
3991 bios
->digital_min_front_porch
= 0x4b;
3995 fptable
= &bios
->data
[bios
->fp
.fptablepointer
];
3996 fptable_ver
= fptable
[0];
3998 switch (fptable_ver
) {
4000 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
4001 * version field, and miss one of the spread spectrum/PWM bytes.
4002 * This could affect early GF2Go parts (not seen any appropriate ROMs
4003 * though). Here we assume that a version of 0x05 matches this case
4004 * (combining with a BMP version check would be better), as the
4005 * common case for the panel type field is 0x0005, and that is in
4006 * fact what we are reading the first byte of.
4008 case 0x05: /* some NV10, 11, 15, 16 */
4012 case 0x10: /* some NV15/16, and NV11+ */
4016 case 0x20: /* NV40+ */
4017 headerlen
= fptable
[1];
4018 recordlen
= fptable
[2];
4019 fpentries
= fptable
[3];
4021 * fptable[4] is the minimum
4022 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
4024 bios
->digital_min_front_porch
= fptable
[4];
4029 "FP table revision %d.%d not currently supported\n",
4030 fptable_ver
>> 4, fptable_ver
& 0xf);
4034 if (!bios
->is_mobile
) /* !mobile only needs digital_min_front_porch */
4037 ret
= parse_lvds_manufacturer_table_header(dev
, bios
, <h
);
4041 if (lth
.lvds_ver
== 0x30 || lth
.lvds_ver
== 0x40) {
4042 bios
->fp
.fpxlatetableptr
= bios
->fp
.lvdsmanufacturerpointer
+
4044 bios
->fp
.xlatwidth
= lth
.recordlen
;
4046 if (bios
->fp
.fpxlatetableptr
== 0x0) {
4047 NV_ERROR(dev
, "Pointer to flat panel xlat table invalid\n");
4051 fpstrapping
= get_fp_strap(dev
, bios
);
4053 fpindex
= bios
->data
[bios
->fp
.fpxlatetableptr
+
4054 fpstrapping
* bios
->fp
.xlatwidth
];
4056 if (fpindex
> fpentries
) {
4057 NV_ERROR(dev
, "Bad flat panel table index\n");
4061 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
4062 if (lth
.lvds_ver
> 0x10)
4063 bios
->fp_no_ddc
= fpstrapping
!= 0xf || fpindex
!= 0xf;
4066 * If either the strap or xlated fpindex value are 0xf there is no
4067 * panel using a strap-derived bios mode present. this condition
4068 * includes, but is different from, the DDC panel indicator above
4070 if (fpstrapping
== 0xf || fpindex
== 0xf)
4073 bios
->fp
.mode_ptr
= bios
->fp
.fptablepointer
+ headerlen
+
4074 recordlen
* fpindex
+ ofs
;
4076 NV_TRACE(dev
, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
4077 ROM16(bios
->data
[bios
->fp
.mode_ptr
+ 11]) + 1,
4078 ROM16(bios
->data
[bios
->fp
.mode_ptr
+ 25]) + 1,
4079 ROM16(bios
->data
[bios
->fp
.mode_ptr
+ 7]) * 10);
4084 bool nouveau_bios_fp_mode(struct drm_device
*dev
, struct drm_display_mode
*mode
)
4086 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
4087 struct nvbios
*bios
= &dev_priv
->vbios
;
4088 uint8_t *mode_entry
= &bios
->data
[bios
->fp
.mode_ptr
];
4090 if (!mode
) /* just checking whether we can produce a mode */
4091 return bios
->fp
.mode_ptr
;
4093 memset(mode
, 0, sizeof(struct drm_display_mode
));
4095 * For version 1.0 (version in byte 0):
4096 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
4097 * single/dual link, and type (TFT etc.)
4098 * bytes 3-6 are bits per colour in RGBX
4100 mode
->clock
= ROM16(mode_entry
[7]) * 10;
4101 /* bytes 9-10 is HActive */
4102 mode
->hdisplay
= ROM16(mode_entry
[11]) + 1;
4104 * bytes 13-14 is HValid Start
4105 * bytes 15-16 is HValid End
4107 mode
->hsync_start
= ROM16(mode_entry
[17]) + 1;
4108 mode
->hsync_end
= ROM16(mode_entry
[19]) + 1;
4109 mode
->htotal
= ROM16(mode_entry
[21]) + 1;
4110 /* bytes 23-24, 27-30 similarly, but vertical */
4111 mode
->vdisplay
= ROM16(mode_entry
[25]) + 1;
4112 mode
->vsync_start
= ROM16(mode_entry
[31]) + 1;
4113 mode
->vsync_end
= ROM16(mode_entry
[33]) + 1;
4114 mode
->vtotal
= ROM16(mode_entry
[35]) + 1;
4115 mode
->flags
|= (mode_entry
[37] & 0x10) ?
4116 DRM_MODE_FLAG_PHSYNC
: DRM_MODE_FLAG_NHSYNC
;
4117 mode
->flags
|= (mode_entry
[37] & 0x1) ?
4118 DRM_MODE_FLAG_PVSYNC
: DRM_MODE_FLAG_NVSYNC
;
4120 * bytes 38-39 relate to spread spectrum settings
4121 * bytes 40-43 are something to do with PWM
4124 mode
->status
= MODE_OK
;
4125 mode
->type
= DRM_MODE_TYPE_DRIVER
| DRM_MODE_TYPE_PREFERRED
;
4126 drm_mode_set_name(mode
);
4127 return bios
->fp
.mode_ptr
;
4130 int nouveau_bios_parse_lvds_table(struct drm_device
*dev
, int pxclk
, bool *dl
, bool *if_is_24bit
)
4133 * The LVDS table header is (mostly) described in
4134 * parse_lvds_manufacturer_table_header(): the BIT header additionally
4135 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
4136 * straps are not being used for the panel, this specifies the frequency
4137 * at which modes should be set up in the dual link style.
4139 * Following the header, the BMP (ver 0xa) table has several records,
4140 * indexed by a separate xlat table, indexed in turn by the fp strap in
4141 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
4142 * numbers for use by INIT_SUB which controlled panel init and power,
4143 * and finally a dword of ms to sleep between power off and on
4146 * In the BIT versions, the table following the header serves as an
4147 * integrated config and xlat table: the records in the table are
4148 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
4149 * two bytes - the first as a config byte, the second for indexing the
4150 * fp mode table pointed to by the BIT 'D' table
4152 * DDC is not used until after card init, so selecting the correct table
4153 * entry and setting the dual link flag for EDID equipped panels,
4154 * requiring tests against the native-mode pixel clock, cannot be done
4155 * until later, when this function should be called with non-zero pxclk
4157 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
4158 struct nvbios
*bios
= &dev_priv
->vbios
;
4159 int fpstrapping
= get_fp_strap(dev
, bios
), lvdsmanufacturerindex
= 0;
4160 struct lvdstableheader lth
;
4162 int ret
, chip_version
= bios
->chip_version
;
4164 ret
= parse_lvds_manufacturer_table_header(dev
, bios
, <h
);
4168 switch (lth
.lvds_ver
) {
4169 case 0x0a: /* pre NV40 */
4170 lvdsmanufacturerindex
= bios
->data
[
4171 bios
->fp
.fpxlatemanufacturertableptr
+
4174 /* we're done if this isn't the EDID panel case */
4178 if (chip_version
< 0x25) {
4181 * It seems the old style lvds script pointer is reused
4182 * to select 18/24 bit colour depth for EDID panels.
4184 lvdsmanufacturerindex
=
4185 (bios
->legacy
.lvds_single_a_script_ptr
& 1) ?
4187 if (pxclk
>= bios
->fp
.duallink_transition_clk
)
4188 lvdsmanufacturerindex
++;
4189 } else if (chip_version
< 0x30) {
4190 /* nv28 behaviour (off-chip encoder)
4192 * nv28 does a complex dance of first using byte 121 of
4193 * the EDID to choose the lvdsmanufacturerindex, then
4194 * later attempting to match the EDID manufacturer and
4195 * product IDs in a table (signature 'pidt' (panel id
4196 * table?)), setting an lvdsmanufacturerindex of 0 and
4197 * an fp strap of the match index (or 0xf if none)
4199 lvdsmanufacturerindex
= 0;
4201 /* nv31, nv34 behaviour */
4202 lvdsmanufacturerindex
= 0;
4203 if (pxclk
>= bios
->fp
.duallink_transition_clk
)
4204 lvdsmanufacturerindex
= 2;
4205 if (pxclk
>= 140000)
4206 lvdsmanufacturerindex
= 3;
4210 * nvidia set the high nibble of (cr57=f, cr58) to
4211 * lvdsmanufacturerindex in this case; we don't
4214 case 0x30: /* NV4x */
4215 case 0x40: /* G80/G90 */
4216 lvdsmanufacturerindex
= fpstrapping
;
4219 NV_ERROR(dev
, "LVDS table revision not currently supported\n");
4223 lvdsofs
= bios
->fp
.xlated_entry
= bios
->fp
.lvdsmanufacturerpointer
+ lth
.headerlen
+ lth
.recordlen
* lvdsmanufacturerindex
;
4224 switch (lth
.lvds_ver
) {
4226 bios
->fp
.power_off_for_reset
= bios
->data
[lvdsofs
] & 1;
4227 bios
->fp
.reset_after_pclk_change
= bios
->data
[lvdsofs
] & 2;
4228 bios
->fp
.dual_link
= bios
->data
[lvdsofs
] & 4;
4229 bios
->fp
.link_c_increment
= bios
->data
[lvdsofs
] & 8;
4230 *if_is_24bit
= bios
->data
[lvdsofs
] & 16;
4235 * No sign of the "power off for reset" or "reset for panel
4236 * on" bits, but it's safer to assume we should
4238 bios
->fp
.power_off_for_reset
= true;
4239 bios
->fp
.reset_after_pclk_change
= true;
4242 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
4243 * over-written, and if_is_24bit isn't used
4245 bios
->fp
.dual_link
= bios
->data
[lvdsofs
] & 1;
4246 bios
->fp
.if_is_24bit
= bios
->data
[lvdsofs
] & 2;
4247 bios
->fp
.strapless_is_24bit
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 4];
4248 bios
->fp
.duallink_transition_clk
= ROM16(bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 5]) * 10;
4252 /* Dell Latitude D620 reports a too-high value for the dual-link
4253 * transition freq, causing us to program the panel incorrectly.
4255 * It doesn't appear the VBIOS actually uses its transition freq
4256 * (90000kHz), instead it uses the "Number of LVDS channels" field
4257 * out of the panel ID structure (http://www.spwg.org/).
4259 * For the moment, a quirk will do :)
4261 if ((dev
->pdev
->device
== 0x01d7) &&
4262 (dev
->pdev
->subsystem_vendor
== 0x1028) &&
4263 (dev
->pdev
->subsystem_device
== 0x01c2)) {
4264 bios
->fp
.duallink_transition_clk
= 80000;
4267 /* set dual_link flag for EDID case */
4268 if (pxclk
&& (chip_version
< 0x25 || chip_version
> 0x28))
4269 bios
->fp
.dual_link
= (pxclk
>= bios
->fp
.duallink_transition_clk
);
4271 *dl
= bios
->fp
.dual_link
;
4277 bios_output_config_match(struct drm_device
*dev
, struct dcb_entry
*dcbent
,
4278 uint16_t record
, int record_len
, int record_nr
,
4281 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
4282 struct nvbios
*bios
= &dev_priv
->vbios
;
4287 switch (dcbent
->type
) {
4297 for (i
= 0; i
< record_nr
; i
++, record
+= record_len
) {
4298 table
= ROM16(bios
->data
[record
]);
4301 entry
= ROM32(bios
->data
[table
]);
4304 v
= (entry
& 0x00c00000) >> 22;
4305 if (!(v
& dcbent
->sorconf
.link
))
4309 v
= (entry
& 0x000f0000) >> 16;
4310 if (!(v
& dcbent
->or))
4313 v
= (entry
& 0x000000f0) >> 4;
4314 if (v
!= dcbent
->location
)
4317 v
= (entry
& 0x0000000f);
4318 if (v
!= dcbent
->type
)
4321 return &bios
->data
[table
];
4328 nouveau_bios_dp_table(struct drm_device
*dev
, struct dcb_entry
*dcbent
,
4331 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
4332 struct nvbios
*bios
= &dev_priv
->vbios
;
4335 if (!bios
->display
.dp_table_ptr
) {
4336 NV_ERROR(dev
, "No pointer to DisplayPort table\n");
4339 table
= &bios
->data
[bios
->display
.dp_table_ptr
];
4341 if (table
[0] != 0x20 && table
[0] != 0x21) {
4342 NV_ERROR(dev
, "DisplayPort table version 0x%02x unknown\n",
4348 return bios_output_config_match(dev
, dcbent
,
4349 bios
->display
.dp_table_ptr
+ table
[1],
4350 table
[2], table
[3], table
[0] >= 0x21);
4354 nouveau_bios_run_display_table(struct drm_device
*dev
, struct dcb_entry
*dcbent
,
4355 uint32_t sub
, int pxclk
)
4358 * The display script table is located by the BIT 'U' table.
4360 * It contains an array of pointers to various tables describing
4361 * a particular output type. The first 32-bits of the output
4362 * tables contains similar information to a DCB entry, and is
4363 * used to decide whether that particular table is suitable for
4364 * the output you want to access.
4366 * The "record header length" field here seems to indicate the
4367 * offset of the first configuration entry in the output tables.
4368 * This is 10 on most cards I've seen, but 12 has been witnessed
4369 * on DP cards, and there's another script pointer within the
4372 * offset + 0 ( 8 bits): version
4373 * offset + 1 ( 8 bits): header length
4374 * offset + 2 ( 8 bits): record length
4375 * offset + 3 ( 8 bits): number of records
4376 * offset + 4 ( 8 bits): record header length
4377 * offset + 5 (16 bits): pointer to first output script table
4380 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
4381 struct nvbios
*bios
= &dev_priv
->vbios
;
4382 uint8_t *table
= &bios
->data
[bios
->display
.script_table_ptr
];
4383 uint8_t *otable
= NULL
;
4387 if (!bios
->display
.script_table_ptr
) {
4388 NV_ERROR(dev
, "No pointer to output script table\n");
4393 * Nothing useful has been in any of the pre-2.0 tables I've seen,
4394 * so until they are, we really don't need to care.
4396 if (table
[0] < 0x20)
4399 if (table
[0] != 0x20 && table
[0] != 0x21) {
4400 NV_ERROR(dev
, "Output script table version 0x%02x unknown\n",
4406 * The output script tables describing a particular output type
4409 * offset + 0 (32 bits): output this table matches (hash of DCB)
4410 * offset + 4 ( 8 bits): unknown
4411 * offset + 5 ( 8 bits): number of configurations
4412 * offset + 6 (16 bits): pointer to some script
4413 * offset + 8 (16 bits): pointer to some script
4416 * offset + 10 : configuration 0
4419 * offset + 10 : pointer to some script
4420 * offset + 12 : configuration 0
4422 * Each config entry is as follows:
4424 * offset + 0 (16 bits): unknown, assumed to be a match value
4425 * offset + 2 (16 bits): pointer to script table (clock set?)
4426 * offset + 4 (16 bits): pointer to script table (reset?)
4428 * There doesn't appear to be a count value to say how many
4429 * entries exist in each script table, instead, a 0 value in
4430 * the first 16-bit word seems to indicate both the end of the
4431 * list and the default entry. The second 16-bit word in the
4432 * script tables is a pointer to the script to execute.
4435 NV_DEBUG_KMS(dev
, "Searching for output entry for %d %d %d\n",
4436 dcbent
->type
, dcbent
->location
, dcbent
->or);
4437 otable
= bios_output_config_match(dev
, dcbent
, table
[1] +
4438 bios
->display
.script_table_ptr
,
4439 table
[2], table
[3], table
[0] >= 0x21);
4441 NV_ERROR(dev
, "Couldn't find matching output script table\n");
4445 if (pxclk
< -2 || pxclk
> 0) {
4446 /* Try to find matching script table entry */
4447 for (i
= 0; i
< otable
[5]; i
++) {
4448 if (ROM16(otable
[table
[4] + i
*6]) == sub
)
4452 if (i
== otable
[5]) {
4453 NV_ERROR(dev
, "Table 0x%04x not found for %d/%d, "
4455 sub
, dcbent
->type
, dcbent
->or);
4461 script
= ROM16(otable
[6]);
4463 NV_DEBUG_KMS(dev
, "output script 0 not found\n");
4467 NV_TRACE(dev
, "0x%04X: parsing output script 0\n", script
);
4468 nouveau_bios_run_init_table(dev
, script
, dcbent
);
4471 script
= ROM16(otable
[8]);
4473 NV_DEBUG_KMS(dev
, "output script 1 not found\n");
4477 NV_TRACE(dev
, "0x%04X: parsing output script 1\n", script
);
4478 nouveau_bios_run_init_table(dev
, script
, dcbent
);
4482 script
= ROM16(otable
[10]);
4486 NV_DEBUG_KMS(dev
, "output script 2 not found\n");
4490 NV_TRACE(dev
, "0x%04X: parsing output script 2\n", script
);
4491 nouveau_bios_run_init_table(dev
, script
, dcbent
);
4494 script
= ROM16(otable
[table
[4] + i
*6 + 2]);
4496 script
= clkcmptable(bios
, script
, pxclk
);
4498 NV_ERROR(dev
, "clock script 0 not found\n");
4502 NV_TRACE(dev
, "0x%04X: parsing clock script 0\n", script
);
4503 nouveau_bios_run_init_table(dev
, script
, dcbent
);
4506 script
= ROM16(otable
[table
[4] + i
*6 + 4]);
4508 script
= clkcmptable(bios
, script
, -pxclk
);
4510 NV_DEBUG_KMS(dev
, "clock script 1 not found\n");
4514 NV_TRACE(dev
, "0x%04X: parsing clock script 1\n", script
);
4515 nouveau_bios_run_init_table(dev
, script
, dcbent
);
4522 int run_tmds_table(struct drm_device
*dev
, struct dcb_entry
*dcbent
, int head
, int pxclk
)
4525 * the pxclk parameter is in kHz
4527 * This runs the TMDS regs setting code found on BIT bios cards
4529 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
4530 * ffs(or) == 3, use the second.
4533 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
4534 struct nvbios
*bios
= &dev_priv
->vbios
;
4535 int cv
= bios
->chip_version
;
4536 uint16_t clktable
= 0, scriptptr
;
4537 uint32_t sel_clk_binding
, sel_clk
;
4539 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
4540 if (cv
>= 0x17 && cv
!= 0x1a && cv
!= 0x20 &&
4541 dcbent
->location
!= DCB_LOC_ON_CHIP
)
4544 switch (ffs(dcbent
->or)) {
4546 clktable
= bios
->tmds
.output0_script_ptr
;
4550 clktable
= bios
->tmds
.output1_script_ptr
;
4555 NV_ERROR(dev
, "Pixel clock comparison table not found\n");
4559 scriptptr
= clkcmptable(bios
, clktable
, pxclk
);
4562 NV_ERROR(dev
, "TMDS output init script not found\n");
4566 /* don't let script change pll->head binding */
4567 sel_clk_binding
= bios_rd32(bios
, NV_PRAMDAC_SEL_CLK
) & 0x50000;
4568 run_digital_op_script(dev
, scriptptr
, dcbent
, head
, pxclk
>= 165000);
4569 sel_clk
= NVReadRAMDAC(dev
, 0, NV_PRAMDAC_SEL_CLK
) & ~0x50000;
4570 NVWriteRAMDAC(dev
, 0, NV_PRAMDAC_SEL_CLK
, sel_clk
| sel_clk_binding
);
4575 int get_pll_limits(struct drm_device
*dev
, uint32_t limit_match
, struct pll_lims
*pll_lim
)
4580 * Version 0x10: NV30, NV31
4581 * One byte header (version), one record of 24 bytes
4582 * Version 0x11: NV36 - Not implemented
4583 * Seems to have same record style as 0x10, but 3 records rather than 1
4584 * Version 0x20: Found on Geforce 6 cards
4585 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
4586 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
4587 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
4588 * length in general, some (integrated) have an extra configuration byte
4589 * Version 0x30: Found on Geforce 8, separates the register mapping
4590 * from the limits tables.
4593 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
4594 struct nvbios
*bios
= &dev_priv
->vbios
;
4595 int cv
= bios
->chip_version
, pllindex
= 0;
4596 uint8_t pll_lim_ver
= 0, headerlen
= 0, recordlen
= 0, entries
= 0;
4597 uint32_t crystal_strap_mask
, crystal_straps
;
4599 if (!bios
->pll_limit_tbl_ptr
) {
4600 if (cv
== 0x30 || cv
== 0x31 || cv
== 0x35 || cv
== 0x36 ||
4602 NV_ERROR(dev
, "Pointer to PLL limits table invalid\n");
4606 pll_lim_ver
= bios
->data
[bios
->pll_limit_tbl_ptr
];
4608 crystal_strap_mask
= 1 << 6;
4609 /* open coded dev->twoHeads test */
4610 if (cv
> 0x10 && cv
!= 0x15 && cv
!= 0x1a && cv
!= 0x20)
4611 crystal_strap_mask
|= 1 << 22;
4612 crystal_straps
= nvReadEXTDEV(dev
, NV_PEXTDEV_BOOT_0
) &
4615 switch (pll_lim_ver
) {
4617 * We use version 0 to indicate a pre limit table bios (single stage
4618 * pll) and load the hard coded limits instead.
4625 * Strictly v0x11 has 3 entries, but the last two don't seem
4637 headerlen
= bios
->data
[bios
->pll_limit_tbl_ptr
+ 1];
4638 recordlen
= bios
->data
[bios
->pll_limit_tbl_ptr
+ 2];
4639 entries
= bios
->data
[bios
->pll_limit_tbl_ptr
+ 3];
4642 NV_ERROR(dev
, "PLL limits table revision 0x%X not currently "
4643 "supported\n", pll_lim_ver
);
4647 /* initialize all members to zero */
4648 memset(pll_lim
, 0, sizeof(struct pll_lims
));
4650 if (pll_lim_ver
== 0x10 || pll_lim_ver
== 0x11) {
4651 uint8_t *pll_rec
= &bios
->data
[bios
->pll_limit_tbl_ptr
+ headerlen
+ recordlen
* pllindex
];
4653 pll_lim
->vco1
.minfreq
= ROM32(pll_rec
[0]);
4654 pll_lim
->vco1
.maxfreq
= ROM32(pll_rec
[4]);
4655 pll_lim
->vco2
.minfreq
= ROM32(pll_rec
[8]);
4656 pll_lim
->vco2
.maxfreq
= ROM32(pll_rec
[12]);
4657 pll_lim
->vco1
.min_inputfreq
= ROM32(pll_rec
[16]);
4658 pll_lim
->vco2
.min_inputfreq
= ROM32(pll_rec
[20]);
4659 pll_lim
->vco1
.max_inputfreq
= pll_lim
->vco2
.max_inputfreq
= INT_MAX
;
4661 /* these values taken from nv30/31/36 */
4662 pll_lim
->vco1
.min_n
= 0x1;
4664 pll_lim
->vco1
.min_n
= 0x5;
4665 pll_lim
->vco1
.max_n
= 0xff;
4666 pll_lim
->vco1
.min_m
= 0x1;
4667 pll_lim
->vco1
.max_m
= 0xd;
4668 pll_lim
->vco2
.min_n
= 0x4;
4670 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
4671 * table version (apart from nv35)), N2 is compared to
4672 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
4675 pll_lim
->vco2
.max_n
= 0x28;
4676 if (cv
== 0x30 || cv
== 0x35)
4677 /* only 5 bits available for N2 on nv30/35 */
4678 pll_lim
->vco2
.max_n
= 0x1f;
4679 pll_lim
->vco2
.min_m
= 0x1;
4680 pll_lim
->vco2
.max_m
= 0x4;
4681 pll_lim
->max_log2p
= 0x7;
4682 pll_lim
->max_usable_log2p
= 0x6;
4683 } else if (pll_lim_ver
== 0x20 || pll_lim_ver
== 0x21) {
4684 uint16_t plloffs
= bios
->pll_limit_tbl_ptr
+ headerlen
;
4685 uint32_t reg
= 0; /* default match */
4690 * First entry is default match, if nothing better. warn if
4693 if (ROM32(bios
->data
[plloffs
]))
4694 NV_WARN(dev
, "Default PLL limit entry has non-zero "
4695 "register field\n");
4697 if (limit_match
> MAX_PLL_TYPES
)
4698 /* we've been passed a reg as the match */
4700 else /* limit match is a pll type */
4701 for (i
= 1; i
< entries
&& !reg
; i
++) {
4702 uint32_t cmpreg
= ROM32(bios
->data
[plloffs
+ recordlen
* i
]);
4704 if (limit_match
== NVPLL
&&
4705 (cmpreg
== NV_PRAMDAC_NVPLL_COEFF
|| cmpreg
== 0x4000))
4707 if (limit_match
== MPLL
&&
4708 (cmpreg
== NV_PRAMDAC_MPLL_COEFF
|| cmpreg
== 0x4020))
4710 if (limit_match
== VPLL1
&&
4711 (cmpreg
== NV_PRAMDAC_VPLL_COEFF
|| cmpreg
== 0x4010))
4713 if (limit_match
== VPLL2
&&
4714 (cmpreg
== NV_RAMDAC_VPLL2
|| cmpreg
== 0x4018))
4718 for (i
= 1; i
< entries
; i
++)
4719 if (ROM32(bios
->data
[plloffs
+ recordlen
* i
]) == reg
) {
4724 pll_rec
= &bios
->data
[plloffs
+ recordlen
* pllindex
];
4726 BIOSLOG(bios
, "Loading PLL limits for reg 0x%08x\n",
4727 pllindex
? reg
: 0);
4730 * Frequencies are stored in tables in MHz, kHz are more
4731 * useful, so we convert.
4734 /* What output frequencies can each VCO generate? */
4735 pll_lim
->vco1
.minfreq
= ROM16(pll_rec
[4]) * 1000;
4736 pll_lim
->vco1
.maxfreq
= ROM16(pll_rec
[6]) * 1000;
4737 pll_lim
->vco2
.minfreq
= ROM16(pll_rec
[8]) * 1000;
4738 pll_lim
->vco2
.maxfreq
= ROM16(pll_rec
[10]) * 1000;
4740 /* What input frequencies they accept (past the m-divider)? */
4741 pll_lim
->vco1
.min_inputfreq
= ROM16(pll_rec
[12]) * 1000;
4742 pll_lim
->vco2
.min_inputfreq
= ROM16(pll_rec
[14]) * 1000;
4743 pll_lim
->vco1
.max_inputfreq
= ROM16(pll_rec
[16]) * 1000;
4744 pll_lim
->vco2
.max_inputfreq
= ROM16(pll_rec
[18]) * 1000;
4746 /* What values are accepted as multiplier and divider? */
4747 pll_lim
->vco1
.min_n
= pll_rec
[20];
4748 pll_lim
->vco1
.max_n
= pll_rec
[21];
4749 pll_lim
->vco1
.min_m
= pll_rec
[22];
4750 pll_lim
->vco1
.max_m
= pll_rec
[23];
4751 pll_lim
->vco2
.min_n
= pll_rec
[24];
4752 pll_lim
->vco2
.max_n
= pll_rec
[25];
4753 pll_lim
->vco2
.min_m
= pll_rec
[26];
4754 pll_lim
->vco2
.max_m
= pll_rec
[27];
4756 pll_lim
->max_usable_log2p
= pll_lim
->max_log2p
= pll_rec
[29];
4757 if (pll_lim
->max_log2p
> 0x7)
4758 /* pll decoding in nv_hw.c assumes never > 7 */
4759 NV_WARN(dev
, "Max log2 P value greater than 7 (%d)\n",
4760 pll_lim
->max_log2p
);
4762 pll_lim
->max_usable_log2p
= 0x6;
4763 pll_lim
->log2p_bias
= pll_rec
[30];
4765 if (recordlen
> 0x22)
4766 pll_lim
->refclk
= ROM32(pll_rec
[31]);
4768 if (recordlen
> 0x23 && pll_rec
[35])
4770 "Bits set in PLL configuration byte (%x)\n",
4773 /* C51 special not seen elsewhere */
4774 if (cv
== 0x51 && !pll_lim
->refclk
) {
4775 uint32_t sel_clk
= bios_rd32(bios
, NV_PRAMDAC_SEL_CLK
);
4777 if (((limit_match
== NV_PRAMDAC_VPLL_COEFF
|| limit_match
== VPLL1
) && sel_clk
& 0x20) ||
4778 ((limit_match
== NV_RAMDAC_VPLL2
|| limit_match
== VPLL2
) && sel_clk
& 0x80)) {
4779 if (bios_idxprt_rd(bios
, NV_CIO_CRX__COLOR
, NV_CIO_CRE_CHIP_ID_INDEX
) < 0xa3)
4780 pll_lim
->refclk
= 200000;
4782 pll_lim
->refclk
= 25000;
4785 } else if (pll_lim_ver
== 0x30) { /* ver 0x30 */
4786 uint8_t *entry
= &bios
->data
[bios
->pll_limit_tbl_ptr
+ headerlen
];
4787 uint8_t *record
= NULL
;
4790 BIOSLOG(bios
, "Loading PLL limits for register 0x%08x\n",
4793 for (i
= 0; i
< entries
; i
++, entry
+= recordlen
) {
4794 if (ROM32(entry
[3]) == limit_match
) {
4795 record
= &bios
->data
[ROM16(entry
[1])];
4801 NV_ERROR(dev
, "Register 0x%08x not found in PLL "
4802 "limits table", limit_match
);
4806 pll_lim
->vco1
.minfreq
= ROM16(record
[0]) * 1000;
4807 pll_lim
->vco1
.maxfreq
= ROM16(record
[2]) * 1000;
4808 pll_lim
->vco2
.minfreq
= ROM16(record
[4]) * 1000;
4809 pll_lim
->vco2
.maxfreq
= ROM16(record
[6]) * 1000;
4810 pll_lim
->vco1
.min_inputfreq
= ROM16(record
[8]) * 1000;
4811 pll_lim
->vco2
.min_inputfreq
= ROM16(record
[10]) * 1000;
4812 pll_lim
->vco1
.max_inputfreq
= ROM16(record
[12]) * 1000;
4813 pll_lim
->vco2
.max_inputfreq
= ROM16(record
[14]) * 1000;
4814 pll_lim
->vco1
.min_n
= record
[16];
4815 pll_lim
->vco1
.max_n
= record
[17];
4816 pll_lim
->vco1
.min_m
= record
[18];
4817 pll_lim
->vco1
.max_m
= record
[19];
4818 pll_lim
->vco2
.min_n
= record
[20];
4819 pll_lim
->vco2
.max_n
= record
[21];
4820 pll_lim
->vco2
.min_m
= record
[22];
4821 pll_lim
->vco2
.max_m
= record
[23];
4822 pll_lim
->max_usable_log2p
= pll_lim
->max_log2p
= record
[25];
4823 pll_lim
->log2p_bias
= record
[27];
4824 pll_lim
->refclk
= ROM32(record
[28]);
4825 } else if (pll_lim_ver
) { /* ver 0x40 */
4826 uint8_t *entry
= &bios
->data
[bios
->pll_limit_tbl_ptr
+ headerlen
];
4827 uint8_t *record
= NULL
;
4830 BIOSLOG(bios
, "Loading PLL limits for register 0x%08x\n",
4833 for (i
= 0; i
< entries
; i
++, entry
+= recordlen
) {
4834 if (ROM32(entry
[3]) == limit_match
) {
4835 record
= &bios
->data
[ROM16(entry
[1])];
4841 NV_ERROR(dev
, "Register 0x%08x not found in PLL "
4842 "limits table", limit_match
);
4846 pll_lim
->vco1
.minfreq
= ROM16(record
[0]) * 1000;
4847 pll_lim
->vco1
.maxfreq
= ROM16(record
[2]) * 1000;
4848 pll_lim
->vco1
.min_inputfreq
= ROM16(record
[4]) * 1000;
4849 pll_lim
->vco1
.max_inputfreq
= ROM16(record
[6]) * 1000;
4850 pll_lim
->vco1
.min_m
= record
[8];
4851 pll_lim
->vco1
.max_m
= record
[9];
4852 pll_lim
->vco1
.min_n
= record
[10];
4853 pll_lim
->vco1
.max_n
= record
[11];
4854 pll_lim
->min_p
= record
[12];
4855 pll_lim
->max_p
= record
[13];
4856 /* where did this go to?? */
4857 if ((entry
[0] & 0xf0) == 0x80)
4858 pll_lim
->refclk
= 27000;
4860 pll_lim
->refclk
= 100000;
4864 * By now any valid limit table ought to have set a max frequency for
4865 * vco1, so if it's zero it's either a pre limit table bios, or one
4866 * with an empty limit table (seen on nv18)
4868 if (!pll_lim
->vco1
.maxfreq
) {
4869 pll_lim
->vco1
.minfreq
= bios
->fminvco
;
4870 pll_lim
->vco1
.maxfreq
= bios
->fmaxvco
;
4871 pll_lim
->vco1
.min_inputfreq
= 0;
4872 pll_lim
->vco1
.max_inputfreq
= INT_MAX
;
4873 pll_lim
->vco1
.min_n
= 0x1;
4874 pll_lim
->vco1
.max_n
= 0xff;
4875 pll_lim
->vco1
.min_m
= 0x1;
4876 if (crystal_straps
== 0) {
4877 /* nv05 does this, nv11 doesn't, nv10 unknown */
4879 pll_lim
->vco1
.min_m
= 0x7;
4880 pll_lim
->vco1
.max_m
= 0xd;
4883 pll_lim
->vco1
.min_m
= 0x8;
4884 pll_lim
->vco1
.max_m
= 0xe;
4886 if (cv
< 0x17 || cv
== 0x1a || cv
== 0x20)
4887 pll_lim
->max_log2p
= 4;
4889 pll_lim
->max_log2p
= 5;
4890 pll_lim
->max_usable_log2p
= pll_lim
->max_log2p
;
4893 if (!pll_lim
->refclk
)
4894 switch (crystal_straps
) {
4896 pll_lim
->refclk
= 13500;
4899 pll_lim
->refclk
= 14318;
4902 pll_lim
->refclk
= 27000;
4904 case (1 << 22 | 1 << 6):
4905 pll_lim
->refclk
= 25000;
4909 NV_DEBUG(dev
, "pll.vco1.minfreq: %d\n", pll_lim
->vco1
.minfreq
);
4910 NV_DEBUG(dev
, "pll.vco1.maxfreq: %d\n", pll_lim
->vco1
.maxfreq
);
4911 NV_DEBUG(dev
, "pll.vco1.min_inputfreq: %d\n", pll_lim
->vco1
.min_inputfreq
);
4912 NV_DEBUG(dev
, "pll.vco1.max_inputfreq: %d\n", pll_lim
->vco1
.max_inputfreq
);
4913 NV_DEBUG(dev
, "pll.vco1.min_n: %d\n", pll_lim
->vco1
.min_n
);
4914 NV_DEBUG(dev
, "pll.vco1.max_n: %d\n", pll_lim
->vco1
.max_n
);
4915 NV_DEBUG(dev
, "pll.vco1.min_m: %d\n", pll_lim
->vco1
.min_m
);
4916 NV_DEBUG(dev
, "pll.vco1.max_m: %d\n", pll_lim
->vco1
.max_m
);
4917 if (pll_lim
->vco2
.maxfreq
) {
4918 NV_DEBUG(dev
, "pll.vco2.minfreq: %d\n", pll_lim
->vco2
.minfreq
);
4919 NV_DEBUG(dev
, "pll.vco2.maxfreq: %d\n", pll_lim
->vco2
.maxfreq
);
4920 NV_DEBUG(dev
, "pll.vco2.min_inputfreq: %d\n", pll_lim
->vco2
.min_inputfreq
);
4921 NV_DEBUG(dev
, "pll.vco2.max_inputfreq: %d\n", pll_lim
->vco2
.max_inputfreq
);
4922 NV_DEBUG(dev
, "pll.vco2.min_n: %d\n", pll_lim
->vco2
.min_n
);
4923 NV_DEBUG(dev
, "pll.vco2.max_n: %d\n", pll_lim
->vco2
.max_n
);
4924 NV_DEBUG(dev
, "pll.vco2.min_m: %d\n", pll_lim
->vco2
.min_m
);
4925 NV_DEBUG(dev
, "pll.vco2.max_m: %d\n", pll_lim
->vco2
.max_m
);
4927 if (!pll_lim
->max_p
) {
4928 NV_DEBUG(dev
, "pll.max_log2p: %d\n", pll_lim
->max_log2p
);
4929 NV_DEBUG(dev
, "pll.log2p_bias: %d\n", pll_lim
->log2p_bias
);
4931 NV_DEBUG(dev
, "pll.min_p: %d\n", pll_lim
->min_p
);
4932 NV_DEBUG(dev
, "pll.max_p: %d\n", pll_lim
->max_p
);
4934 NV_DEBUG(dev
, "pll.refclk: %d\n", pll_lim
->refclk
);
4939 static void parse_bios_version(struct drm_device
*dev
, struct nvbios
*bios
, uint16_t offset
)
4942 * offset + 0 (8 bits): Micro version
4943 * offset + 1 (8 bits): Minor version
4944 * offset + 2 (8 bits): Chip version
4945 * offset + 3 (8 bits): Major version
4948 bios
->major_version
= bios
->data
[offset
+ 3];
4949 bios
->chip_version
= bios
->data
[offset
+ 2];
4950 NV_TRACE(dev
, "Bios version %02x.%02x.%02x.%02x\n",
4951 bios
->data
[offset
+ 3], bios
->data
[offset
+ 2],
4952 bios
->data
[offset
+ 1], bios
->data
[offset
]);
4955 static void parse_script_table_pointers(struct nvbios
*bios
, uint16_t offset
)
4958 * Parses the init table segment for pointers used in script execution.
4960 * offset + 0 (16 bits): init script tables pointer
4961 * offset + 2 (16 bits): macro index table pointer
4962 * offset + 4 (16 bits): macro table pointer
4963 * offset + 6 (16 bits): condition table pointer
4964 * offset + 8 (16 bits): io condition table pointer
4965 * offset + 10 (16 bits): io flag condition table pointer
4966 * offset + 12 (16 bits): init function table pointer
4969 bios
->init_script_tbls_ptr
= ROM16(bios
->data
[offset
]);
4970 bios
->macro_index_tbl_ptr
= ROM16(bios
->data
[offset
+ 2]);
4971 bios
->macro_tbl_ptr
= ROM16(bios
->data
[offset
+ 4]);
4972 bios
->condition_tbl_ptr
= ROM16(bios
->data
[offset
+ 6]);
4973 bios
->io_condition_tbl_ptr
= ROM16(bios
->data
[offset
+ 8]);
4974 bios
->io_flag_condition_tbl_ptr
= ROM16(bios
->data
[offset
+ 10]);
4975 bios
->init_function_tbl_ptr
= ROM16(bios
->data
[offset
+ 12]);
4978 static int parse_bit_A_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
4981 * Parses the load detect values for g80 cards.
4983 * offset + 0 (16 bits): loadval table pointer
4986 uint16_t load_table_ptr
;
4987 uint8_t version
, headerlen
, entrylen
, num_entries
;
4989 if (bitentry
->length
!= 3) {
4990 NV_ERROR(dev
, "Do not understand BIT A table\n");
4994 load_table_ptr
= ROM16(bios
->data
[bitentry
->offset
]);
4996 if (load_table_ptr
== 0x0) {
4997 NV_ERROR(dev
, "Pointer to BIT loadval table invalid\n");
5001 version
= bios
->data
[load_table_ptr
];
5003 if (version
!= 0x10) {
5004 NV_ERROR(dev
, "BIT loadval table version %d.%d not supported\n",
5005 version
>> 4, version
& 0xF);
5009 headerlen
= bios
->data
[load_table_ptr
+ 1];
5010 entrylen
= bios
->data
[load_table_ptr
+ 2];
5011 num_entries
= bios
->data
[load_table_ptr
+ 3];
5013 if (headerlen
!= 4 || entrylen
!= 4 || num_entries
!= 2) {
5014 NV_ERROR(dev
, "Do not understand BIT loadval table\n");
5018 /* First entry is normal dac, 2nd tv-out perhaps? */
5019 bios
->dactestval
= ROM32(bios
->data
[load_table_ptr
+ headerlen
]) & 0x3ff;
5024 static int parse_bit_C_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
5027 * offset + 8 (16 bits): PLL limits table pointer
5029 * There's more in here, but that's unknown.
5032 if (bitentry
->length
< 10) {
5033 NV_ERROR(dev
, "Do not understand BIT C table\n");
5037 bios
->pll_limit_tbl_ptr
= ROM16(bios
->data
[bitentry
->offset
+ 8]);
5042 static int parse_bit_display_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
5045 * Parses the flat panel table segment that the bit entry points to.
5046 * Starting at bitentry->offset:
5048 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
5049 * records beginning with a freq.
5050 * offset + 2 (16 bits): mode table pointer
5053 if (bitentry
->length
!= 4) {
5054 NV_ERROR(dev
, "Do not understand BIT display table\n");
5058 bios
->fp
.fptablepointer
= ROM16(bios
->data
[bitentry
->offset
+ 2]);
5063 static int parse_bit_init_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
5066 * Parses the init table segment that the bit entry points to.
5068 * See parse_script_table_pointers for layout
5071 if (bitentry
->length
< 14) {
5072 NV_ERROR(dev
, "Do not understand init table\n");
5076 parse_script_table_pointers(bios
, bitentry
->offset
);
5078 if (bitentry
->length
>= 16)
5079 bios
->some_script_ptr
= ROM16(bios
->data
[bitentry
->offset
+ 14]);
5080 if (bitentry
->length
>= 18)
5081 bios
->init96_tbl_ptr
= ROM16(bios
->data
[bitentry
->offset
+ 16]);
5086 static int parse_bit_i_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
5089 * BIT 'i' (info?) table
5091 * offset + 0 (32 bits): BIOS version dword (as in B table)
5092 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
5093 * offset + 13 (16 bits): pointer to table containing DAC load
5094 * detection comparison values
5096 * There's other things in the table, purpose unknown
5099 uint16_t daccmpoffset
;
5100 uint8_t dacver
, dacheaderlen
;
5102 if (bitentry
->length
< 6) {
5103 NV_ERROR(dev
, "BIT i table too short for needed information\n");
5107 parse_bios_version(dev
, bios
, bitentry
->offset
);
5110 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
5111 * Quadro identity crisis), other bits possibly as for BMP feature byte
5113 bios
->feature_byte
= bios
->data
[bitentry
->offset
+ 5];
5114 bios
->is_mobile
= bios
->feature_byte
& FEATURE_MOBILE
;
5116 if (bitentry
->length
< 15) {
5117 NV_WARN(dev
, "BIT i table not long enough for DAC load "
5118 "detection comparison table\n");
5122 daccmpoffset
= ROM16(bios
->data
[bitentry
->offset
+ 13]);
5124 /* doesn't exist on g80 */
5129 * The first value in the table, following the header, is the
5130 * comparison value, the second entry is a comparison value for
5131 * TV load detection.
5134 dacver
= bios
->data
[daccmpoffset
];
5135 dacheaderlen
= bios
->data
[daccmpoffset
+ 1];
5137 if (dacver
!= 0x00 && dacver
!= 0x10) {
5138 NV_WARN(dev
, "DAC load detection comparison table version "
5139 "%d.%d not known\n", dacver
>> 4, dacver
& 0xf);
5143 bios
->dactestval
= ROM32(bios
->data
[daccmpoffset
+ dacheaderlen
]);
5144 bios
->tvdactestval
= ROM32(bios
->data
[daccmpoffset
+ dacheaderlen
+ 4]);
5149 static int parse_bit_lvds_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
5152 * Parses the LVDS table segment that the bit entry points to.
5153 * Starting at bitentry->offset:
5155 * offset + 0 (16 bits): LVDS strap xlate table pointer
5158 if (bitentry
->length
!= 2) {
5159 NV_ERROR(dev
, "Do not understand BIT LVDS table\n");
5164 * No idea if it's still called the LVDS manufacturer table, but
5165 * the concept's close enough.
5167 bios
->fp
.lvdsmanufacturerpointer
= ROM16(bios
->data
[bitentry
->offset
]);
5173 parse_bit_M_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
,
5174 struct bit_entry
*bitentry
)
5177 * offset + 2 (8 bits): number of options in an
5178 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
5179 * offset + 3 (16 bits): pointer to strap xlate table for RAM
5180 * restrict option selection
5182 * There's a bunch of bits in this table other than the RAM restrict
5183 * stuff that we don't use - their use currently unknown
5187 * Older bios versions don't have a sufficiently long table for
5190 if (bitentry
->length
< 0x5)
5193 if (bitentry
->id
[1] < 2) {
5194 bios
->ram_restrict_group_count
= bios
->data
[bitentry
->offset
+ 2];
5195 bios
->ram_restrict_tbl_ptr
= ROM16(bios
->data
[bitentry
->offset
+ 3]);
5197 bios
->ram_restrict_group_count
= bios
->data
[bitentry
->offset
+ 0];
5198 bios
->ram_restrict_tbl_ptr
= ROM16(bios
->data
[bitentry
->offset
+ 1]);
5204 static int parse_bit_tmds_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
5207 * Parses the pointer to the TMDS table
5209 * Starting at bitentry->offset:
5211 * offset + 0 (16 bits): TMDS table pointer
5213 * The TMDS table is typically found just before the DCB table, with a
5214 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
5217 * At offset +7 is a pointer to a script, which I don't know how to
5219 * At offset +9 is a pointer to another script, likewise
5220 * Offset +11 has a pointer to a table where the first word is a pxclk
5221 * frequency and the second word a pointer to a script, which should be
5222 * run if the comparison pxclk frequency is less than the pxclk desired.
5223 * This repeats for decreasing comparison frequencies
5224 * Offset +13 has a pointer to a similar table
5225 * The selection of table (and possibly +7/+9 script) is dictated by
5226 * "or" from the DCB.
5229 uint16_t tmdstableptr
, script1
, script2
;
5231 if (bitentry
->length
!= 2) {
5232 NV_ERROR(dev
, "Do not understand BIT TMDS table\n");
5236 tmdstableptr
= ROM16(bios
->data
[bitentry
->offset
]);
5238 if (tmdstableptr
== 0x0) {
5239 NV_ERROR(dev
, "Pointer to TMDS table invalid\n");
5243 /* nv50+ has v2.0, but we don't parse it atm */
5244 if (bios
->data
[tmdstableptr
] != 0x11) {
5246 "TMDS table revision %d.%d not currently supported\n",
5247 bios
->data
[tmdstableptr
] >> 4, bios
->data
[tmdstableptr
] & 0xf);
5252 * These two scripts are odd: they don't seem to get run even when
5253 * they are not stubbed.
5255 script1
= ROM16(bios
->data
[tmdstableptr
+ 7]);
5256 script2
= ROM16(bios
->data
[tmdstableptr
+ 9]);
5257 if (bios
->data
[script1
] != 'q' || bios
->data
[script2
] != 'q')
5258 NV_WARN(dev
, "TMDS table script pointers not stubbed\n");
5260 bios
->tmds
.output0_script_ptr
= ROM16(bios
->data
[tmdstableptr
+ 11]);
5261 bios
->tmds
.output1_script_ptr
= ROM16(bios
->data
[tmdstableptr
+ 13]);
5267 parse_bit_U_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
,
5268 struct bit_entry
*bitentry
)
5271 * Parses the pointer to the G80 output script tables
5273 * Starting at bitentry->offset:
5275 * offset + 0 (16 bits): output script table pointer
5278 uint16_t outputscripttableptr
;
5280 if (bitentry
->length
!= 3) {
5281 NV_ERROR(dev
, "Do not understand BIT U table\n");
5285 outputscripttableptr
= ROM16(bios
->data
[bitentry
->offset
]);
5286 bios
->display
.script_table_ptr
= outputscripttableptr
;
5291 parse_bit_displayport_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
,
5292 struct bit_entry
*bitentry
)
5294 bios
->display
.dp_table_ptr
= ROM16(bios
->data
[bitentry
->offset
]);
5300 int (* const parse_fn
)(struct drm_device
*, struct nvbios
*, struct bit_entry
*);
5303 #define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
5306 parse_bit_table(struct nvbios
*bios
, const uint16_t bitoffset
,
5307 struct bit_table
*table
)
5309 struct drm_device
*dev
= bios
->dev
;
5310 uint8_t maxentries
= bios
->data
[bitoffset
+ 4];
5312 struct bit_entry bitentry
;
5314 for (i
= 0, offset
= bitoffset
+ 6; i
< maxentries
; i
++, offset
+= 6) {
5315 bitentry
.id
[0] = bios
->data
[offset
];
5317 if (bitentry
.id
[0] != table
->id
)
5320 bitentry
.id
[1] = bios
->data
[offset
+ 1];
5321 bitentry
.length
= ROM16(bios
->data
[offset
+ 2]);
5322 bitentry
.offset
= ROM16(bios
->data
[offset
+ 4]);
5324 return table
->parse_fn(dev
, bios
, &bitentry
);
5327 NV_INFO(dev
, "BIT table '%c' not found\n", table
->id
);
5332 parse_bit_structure(struct nvbios
*bios
, const uint16_t bitoffset
)
5337 * The only restriction on parsing order currently is having 'i' first
5338 * for use of bios->*_version or bios->feature_byte while parsing;
5339 * functions shouldn't be actually *doing* anything apart from pulling
5340 * data from the image into the bios struct, thus no interdependencies
5342 ret
= parse_bit_table(bios
, bitoffset
, &BIT_TABLE('i', i
));
5343 if (ret
) /* info? */
5345 if (bios
->major_version
>= 0x60) /* g80+ */
5346 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('A', A
));
5347 ret
= parse_bit_table(bios
, bitoffset
, &BIT_TABLE('C', C
));
5350 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('D', display
));
5351 ret
= parse_bit_table(bios
, bitoffset
, &BIT_TABLE('I', init
));
5354 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('M', M
)); /* memory? */
5355 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('L', lvds
));
5356 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('T', tmds
));
5357 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('U', U
));
5358 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('d', displayport
));
5363 static int parse_bmp_structure(struct drm_device
*dev
, struct nvbios
*bios
, unsigned int offset
)
5366 * Parses the BMP structure for useful things, but does not act on them
5368 * offset + 5: BMP major version
5369 * offset + 6: BMP minor version
5370 * offset + 9: BMP feature byte
5371 * offset + 10: BCD encoded BIOS version
5373 * offset + 18: init script table pointer (for bios versions < 5.10h)
5374 * offset + 20: extra init script table pointer (for bios
5377 * offset + 24: memory init table pointer (used on early bios versions)
5378 * offset + 26: SDR memory sequencing setup data table
5379 * offset + 28: DDR memory sequencing setup data table
5381 * offset + 54: index of I2C CRTC pair to use for CRT output
5382 * offset + 55: index of I2C CRTC pair to use for TV output
5383 * offset + 56: index of I2C CRTC pair to use for flat panel output
5384 * offset + 58: write CRTC index for I2C pair 0
5385 * offset + 59: read CRTC index for I2C pair 0
5386 * offset + 60: write CRTC index for I2C pair 1
5387 * offset + 61: read CRTC index for I2C pair 1
5389 * offset + 67: maximum internal PLL frequency (single stage PLL)
5390 * offset + 71: minimum internal PLL frequency (single stage PLL)
5392 * offset + 75: script table pointers, as described in
5393 * parse_script_table_pointers
5395 * offset + 89: TMDS single link output A table pointer
5396 * offset + 91: TMDS single link output B table pointer
5397 * offset + 95: LVDS single link output A table pointer
5398 * offset + 105: flat panel timings table pointer
5399 * offset + 107: flat panel strapping translation table pointer
5400 * offset + 117: LVDS manufacturer panel config table pointer
5401 * offset + 119: LVDS manufacturer strapping translation table pointer
5403 * offset + 142: PLL limits table pointer
5405 * offset + 156: minimum pixel clock for LVDS dual link
5408 uint8_t *bmp
= &bios
->data
[offset
], bmp_version_major
, bmp_version_minor
;
5410 uint16_t legacy_scripts_offset
, legacy_i2c_offset
;
5412 /* load needed defaults in case we can't parse this info */
5413 bios
->dcb
.i2c
[0].write
= NV_CIO_CRE_DDC_WR__INDEX
;
5414 bios
->dcb
.i2c
[0].read
= NV_CIO_CRE_DDC_STATUS__INDEX
;
5415 bios
->dcb
.i2c
[1].write
= NV_CIO_CRE_DDC0_WR__INDEX
;
5416 bios
->dcb
.i2c
[1].read
= NV_CIO_CRE_DDC0_STATUS__INDEX
;
5417 bios
->digital_min_front_porch
= 0x4b;
5418 bios
->fmaxvco
= 256000;
5419 bios
->fminvco
= 128000;
5420 bios
->fp
.duallink_transition_clk
= 90000;
5422 bmp_version_major
= bmp
[5];
5423 bmp_version_minor
= bmp
[6];
5425 NV_TRACE(dev
, "BMP version %d.%d\n",
5426 bmp_version_major
, bmp_version_minor
);
5429 * Make sure that 0x36 is blank and can't be mistaken for a DCB
5430 * pointer on early versions
5432 if (bmp_version_major
< 5)
5433 *(uint16_t *)&bios
->data
[0x36] = 0;
5436 * Seems that the minor version was 1 for all major versions prior
5437 * to 5. Version 6 could theoretically exist, but I suspect BIT
5440 if ((bmp_version_major
< 5 && bmp_version_minor
!= 1) || bmp_version_major
> 5) {
5441 NV_ERROR(dev
, "You have an unsupported BMP version. "
5442 "Please send in your bios\n");
5446 if (bmp_version_major
== 0)
5447 /* nothing that's currently useful in this version */
5449 else if (bmp_version_major
== 1)
5450 bmplength
= 44; /* exact for 1.01 */
5451 else if (bmp_version_major
== 2)
5452 bmplength
= 48; /* exact for 2.01 */
5453 else if (bmp_version_major
== 3)
5455 /* guessed - mem init tables added in this version */
5456 else if (bmp_version_major
== 4 || bmp_version_minor
< 0x1)
5457 /* don't know if 5.0 exists... */
5459 /* guessed - BMP I2C indices added in version 4*/
5460 else if (bmp_version_minor
< 0x6)
5461 bmplength
= 67; /* exact for 5.01 */
5462 else if (bmp_version_minor
< 0x10)
5463 bmplength
= 75; /* exact for 5.06 */
5464 else if (bmp_version_minor
== 0x10)
5465 bmplength
= 89; /* exact for 5.10h */
5466 else if (bmp_version_minor
< 0x14)
5467 bmplength
= 118; /* exact for 5.11h */
5468 else if (bmp_version_minor
< 0x24)
5470 * Not sure of version where pll limits came in;
5471 * certainly exist by 0x24 though.
5473 /* length not exact: this is long enough to get lvds members */
5475 else if (bmp_version_minor
< 0x27)
5477 * Length not exact: this is long enough to get pll limit
5483 * Length not exact: this is long enough to get dual link
5489 if (nv_cksum(bmp
, 8)) {
5490 NV_ERROR(dev
, "Bad BMP checksum\n");
5495 * Bit 4 seems to indicate either a mobile bios or a quadro card --
5496 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
5497 * (not nv10gl), bit 5 that the flat panel tables are present, and
5500 bios
->feature_byte
= bmp
[9];
5502 parse_bios_version(dev
, bios
, offset
+ 10);
5504 if (bmp_version_major
< 5 || bmp_version_minor
< 0x10)
5505 bios
->old_style_init
= true;
5506 legacy_scripts_offset
= 18;
5507 if (bmp_version_major
< 2)
5508 legacy_scripts_offset
-= 4;
5509 bios
->init_script_tbls_ptr
= ROM16(bmp
[legacy_scripts_offset
]);
5510 bios
->extra_init_script_tbl_ptr
= ROM16(bmp
[legacy_scripts_offset
+ 2]);
5512 if (bmp_version_major
> 2) { /* appears in BMP 3 */
5513 bios
->legacy
.mem_init_tbl_ptr
= ROM16(bmp
[24]);
5514 bios
->legacy
.sdr_seq_tbl_ptr
= ROM16(bmp
[26]);
5515 bios
->legacy
.ddr_seq_tbl_ptr
= ROM16(bmp
[28]);
5518 legacy_i2c_offset
= 0x48; /* BMP version 2 & 3 */
5520 legacy_i2c_offset
= offset
+ 54;
5521 bios
->legacy
.i2c_indices
.crt
= bios
->data
[legacy_i2c_offset
];
5522 bios
->legacy
.i2c_indices
.tv
= bios
->data
[legacy_i2c_offset
+ 1];
5523 bios
->legacy
.i2c_indices
.panel
= bios
->data
[legacy_i2c_offset
+ 2];
5524 if (bios
->data
[legacy_i2c_offset
+ 4])
5525 bios
->dcb
.i2c
[0].write
= bios
->data
[legacy_i2c_offset
+ 4];
5526 if (bios
->data
[legacy_i2c_offset
+ 5])
5527 bios
->dcb
.i2c
[0].read
= bios
->data
[legacy_i2c_offset
+ 5];
5528 if (bios
->data
[legacy_i2c_offset
+ 6])
5529 bios
->dcb
.i2c
[1].write
= bios
->data
[legacy_i2c_offset
+ 6];
5530 if (bios
->data
[legacy_i2c_offset
+ 7])
5531 bios
->dcb
.i2c
[1].read
= bios
->data
[legacy_i2c_offset
+ 7];
5533 if (bmplength
> 74) {
5534 bios
->fmaxvco
= ROM32(bmp
[67]);
5535 bios
->fminvco
= ROM32(bmp
[71]);
5538 parse_script_table_pointers(bios
, offset
+ 75);
5539 if (bmplength
> 94) {
5540 bios
->tmds
.output0_script_ptr
= ROM16(bmp
[89]);
5541 bios
->tmds
.output1_script_ptr
= ROM16(bmp
[91]);
5543 * Never observed in use with lvds scripts, but is reused for
5544 * 18/24 bit panel interface default for EDID equipped panels
5545 * (if_is_24bit not set directly to avoid any oscillation).
5547 bios
->legacy
.lvds_single_a_script_ptr
= ROM16(bmp
[95]);
5549 if (bmplength
> 108) {
5550 bios
->fp
.fptablepointer
= ROM16(bmp
[105]);
5551 bios
->fp
.fpxlatetableptr
= ROM16(bmp
[107]);
5552 bios
->fp
.xlatwidth
= 1;
5554 if (bmplength
> 120) {
5555 bios
->fp
.lvdsmanufacturerpointer
= ROM16(bmp
[117]);
5556 bios
->fp
.fpxlatemanufacturertableptr
= ROM16(bmp
[119]);
5558 if (bmplength
> 143)
5559 bios
->pll_limit_tbl_ptr
= ROM16(bmp
[142]);
5561 if (bmplength
> 157)
5562 bios
->fp
.duallink_transition_clk
= ROM16(bmp
[156]) * 10;
5567 static uint16_t findstr(uint8_t *data
, int n
, const uint8_t *str
, int len
)
5571 for (i
= 0; i
<= (n
- len
); i
++) {
5572 for (j
= 0; j
< len
; j
++)
5573 if (data
[i
+ j
] != str
[j
])
5582 static struct dcb_gpio_entry
*
5583 new_gpio_entry(struct nvbios
*bios
)
5585 struct dcb_gpio_table
*gpio
= &bios
->dcb
.gpio
;
5587 return &gpio
->entry
[gpio
->entries
++];
5590 struct dcb_gpio_entry
*
5591 nouveau_bios_gpio_entry(struct drm_device
*dev
, enum dcb_gpio_tag tag
)
5593 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
5594 struct nvbios
*bios
= &dev_priv
->vbios
;
5597 for (i
= 0; i
< bios
->dcb
.gpio
.entries
; i
++) {
5598 if (bios
->dcb
.gpio
.entry
[i
].tag
!= tag
)
5601 return &bios
->dcb
.gpio
.entry
[i
];
5608 parse_dcb30_gpio_entry(struct nvbios
*bios
, uint16_t offset
)
5610 struct dcb_gpio_entry
*gpio
;
5611 uint16_t ent
= ROM16(bios
->data
[offset
]);
5612 uint8_t line
= ent
& 0x1f,
5613 tag
= ent
>> 5 & 0x3f,
5614 flags
= ent
>> 11 & 0x1f;
5619 gpio
= new_gpio_entry(bios
);
5623 gpio
->invert
= flags
!= 4;
5628 parse_dcb40_gpio_entry(struct nvbios
*bios
, uint16_t offset
)
5630 uint32_t entry
= ROM32(bios
->data
[offset
]);
5631 struct dcb_gpio_entry
*gpio
;
5633 if ((entry
& 0x0000ff00) == 0x0000ff00)
5636 gpio
= new_gpio_entry(bios
);
5637 gpio
->tag
= (entry
& 0x0000ff00) >> 8;
5638 gpio
->line
= (entry
& 0x0000001f) >> 0;
5639 gpio
->state_default
= (entry
& 0x01000000) >> 24;
5640 gpio
->state
[0] = (entry
& 0x18000000) >> 27;
5641 gpio
->state
[1] = (entry
& 0x60000000) >> 29;
5642 gpio
->entry
= entry
;
5646 parse_dcb_gpio_table(struct nvbios
*bios
)
5648 struct drm_device
*dev
= bios
->dev
;
5649 uint16_t gpio_table_ptr
= bios
->dcb
.gpio_table_ptr
;
5650 uint8_t *gpio_table
= &bios
->data
[gpio_table_ptr
];
5651 int header_len
= gpio_table
[1],
5652 entries
= gpio_table
[2],
5653 entry_len
= gpio_table
[3];
5654 void (*parse_entry
)(struct nvbios
*, uint16_t) = NULL
;
5657 if (bios
->dcb
.version
>= 0x40) {
5658 if (gpio_table_ptr
&& entry_len
!= 4) {
5659 NV_WARN(dev
, "Invalid DCB GPIO table entry length.\n");
5663 parse_entry
= parse_dcb40_gpio_entry
;
5665 } else if (bios
->dcb
.version
>= 0x30) {
5666 if (gpio_table_ptr
&& entry_len
!= 2) {
5667 NV_WARN(dev
, "Invalid DCB GPIO table entry length.\n");
5671 parse_entry
= parse_dcb30_gpio_entry
;
5673 } else if (bios
->dcb
.version
>= 0x22) {
5675 * DCBs older than v3.0 don't really have a GPIO
5676 * table, instead they keep some GPIO info at fixed
5679 uint16_t dcbptr
= ROM16(bios
->data
[0x36]);
5680 uint8_t *tvdac_gpio
= &bios
->data
[dcbptr
- 5];
5682 if (tvdac_gpio
[0] & 1) {
5683 struct dcb_gpio_entry
*gpio
= new_gpio_entry(bios
);
5685 gpio
->tag
= DCB_GPIO_TVDAC0
;
5686 gpio
->line
= tvdac_gpio
[1] >> 4;
5687 gpio
->invert
= tvdac_gpio
[0] & 2;
5691 if (!gpio_table_ptr
)
5694 if (entries
> DCB_MAX_NUM_GPIO_ENTRIES
) {
5695 NV_WARN(dev
, "Too many entries in the DCB GPIO table.\n");
5696 entries
= DCB_MAX_NUM_GPIO_ENTRIES
;
5699 for (i
= 0; i
< entries
; i
++)
5700 parse_entry(bios
, gpio_table_ptr
+ header_len
+ entry_len
* i
);
5703 struct dcb_connector_table_entry
*
5704 nouveau_bios_connector_entry(struct drm_device
*dev
, int index
)
5706 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
5707 struct nvbios
*bios
= &dev_priv
->vbios
;
5708 struct dcb_connector_table_entry
*cte
;
5710 if (index
>= bios
->dcb
.connector
.entries
)
5713 cte
= &bios
->dcb
.connector
.entry
[index
];
5714 if (cte
->type
== 0xff)
5720 static enum dcb_connector_type
5721 divine_connector_type(struct nvbios
*bios
, int index
)
5723 struct dcb_table
*dcb
= &bios
->dcb
;
5724 unsigned encoders
= 0, type
= DCB_CONNECTOR_NONE
;
5727 for (i
= 0; i
< dcb
->entries
; i
++) {
5728 if (dcb
->entry
[i
].connector
== index
)
5729 encoders
|= (1 << dcb
->entry
[i
].type
);
5732 if (encoders
& (1 << OUTPUT_DP
)) {
5733 if (encoders
& (1 << OUTPUT_TMDS
))
5734 type
= DCB_CONNECTOR_DP
;
5736 type
= DCB_CONNECTOR_eDP
;
5738 if (encoders
& (1 << OUTPUT_TMDS
)) {
5739 if (encoders
& (1 << OUTPUT_ANALOG
))
5740 type
= DCB_CONNECTOR_DVI_I
;
5742 type
= DCB_CONNECTOR_DVI_D
;
5744 if (encoders
& (1 << OUTPUT_ANALOG
)) {
5745 type
= DCB_CONNECTOR_VGA
;
5747 if (encoders
& (1 << OUTPUT_LVDS
)) {
5748 type
= DCB_CONNECTOR_LVDS
;
5750 if (encoders
& (1 << OUTPUT_TV
)) {
5751 type
= DCB_CONNECTOR_TV_0
;
5758 apply_dcb_connector_quirks(struct nvbios
*bios
, int idx
)
5760 struct dcb_connector_table_entry
*cte
= &bios
->dcb
.connector
.entry
[idx
];
5761 struct drm_device
*dev
= bios
->dev
;
5763 /* Gigabyte NX85T */
5764 if ((dev
->pdev
->device
== 0x0421) &&
5765 (dev
->pdev
->subsystem_vendor
== 0x1458) &&
5766 (dev
->pdev
->subsystem_device
== 0x344c)) {
5767 if (cte
->type
== DCB_CONNECTOR_HDMI_1
)
5768 cte
->type
= DCB_CONNECTOR_DVI_I
;
5773 parse_dcb_connector_table(struct nvbios
*bios
)
5775 struct drm_device
*dev
= bios
->dev
;
5776 struct dcb_connector_table
*ct
= &bios
->dcb
.connector
;
5777 struct dcb_connector_table_entry
*cte
;
5778 uint8_t *conntab
= &bios
->data
[bios
->dcb
.connector_table_ptr
];
5782 if (!bios
->dcb
.connector_table_ptr
) {
5783 NV_DEBUG_KMS(dev
, "No DCB connector table present\n");
5787 NV_INFO(dev
, "DCB connector table: VHER 0x%02x %d %d %d\n",
5788 conntab
[0], conntab
[1], conntab
[2], conntab
[3]);
5789 if ((conntab
[0] != 0x30 && conntab
[0] != 0x40) ||
5790 (conntab
[3] != 2 && conntab
[3] != 4)) {
5791 NV_ERROR(dev
, " Unknown! Please report.\n");
5795 ct
->entries
= conntab
[2];
5797 entry
= conntab
+ conntab
[1];
5798 cte
= &ct
->entry
[0];
5799 for (i
= 0; i
< conntab
[2]; i
++, entry
+= conntab
[3], cte
++) {
5801 if (conntab
[3] == 2)
5802 cte
->entry
= ROM16(entry
[0]);
5804 cte
->entry
= ROM32(entry
[0]);
5806 cte
->type
= (cte
->entry
& 0x000000ff) >> 0;
5807 cte
->index2
= (cte
->entry
& 0x00000f00) >> 8;
5808 switch (cte
->entry
& 0x00033000) {
5810 cte
->gpio_tag
= 0x07;
5813 cte
->gpio_tag
= 0x08;
5816 cte
->gpio_tag
= 0x51;
5819 cte
->gpio_tag
= 0x52;
5822 cte
->gpio_tag
= 0xff;
5826 if (cte
->type
== 0xff)
5829 apply_dcb_connector_quirks(bios
, i
);
5831 NV_INFO(dev
, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n",
5832 i
, cte
->entry
, cte
->type
, cte
->index
, cte
->gpio_tag
);
5834 /* check for known types, fallback to guessing the type
5835 * from attached encoders if we hit an unknown.
5837 switch (cte
->type
) {
5838 case DCB_CONNECTOR_VGA
:
5839 case DCB_CONNECTOR_TV_0
:
5840 case DCB_CONNECTOR_TV_1
:
5841 case DCB_CONNECTOR_TV_3
:
5842 case DCB_CONNECTOR_DVI_I
:
5843 case DCB_CONNECTOR_DVI_D
:
5844 case DCB_CONNECTOR_LVDS
:
5845 case DCB_CONNECTOR_DP
:
5846 case DCB_CONNECTOR_eDP
:
5847 case DCB_CONNECTOR_HDMI_0
:
5848 case DCB_CONNECTOR_HDMI_1
:
5851 cte
->type
= divine_connector_type(bios
, cte
->index
);
5852 NV_WARN(dev
, "unknown type, using 0x%02x\n", cte
->type
);
5856 if (nouveau_override_conntype
) {
5857 int type
= divine_connector_type(bios
, cte
->index
);
5858 if (type
!= cte
->type
)
5859 NV_WARN(dev
, " -> type 0x%02x\n", cte
->type
);
5865 static struct dcb_entry
*new_dcb_entry(struct dcb_table
*dcb
)
5867 struct dcb_entry
*entry
= &dcb
->entry
[dcb
->entries
];
5869 memset(entry
, 0, sizeof(struct dcb_entry
));
5870 entry
->index
= dcb
->entries
++;
5875 static void fabricate_vga_output(struct dcb_table
*dcb
, int i2c
, int heads
)
5877 struct dcb_entry
*entry
= new_dcb_entry(dcb
);
5880 entry
->i2c_index
= i2c
;
5881 entry
->heads
= heads
;
5882 entry
->location
= DCB_LOC_ON_CHIP
;
5883 /* "or" mostly unused in early gen crt modesetting, 0 is fine */
5886 static void fabricate_dvi_i_output(struct dcb_table
*dcb
, bool twoHeads
)
5888 struct dcb_entry
*entry
= new_dcb_entry(dcb
);
5891 entry
->i2c_index
= LEGACY_I2C_PANEL
;
5892 entry
->heads
= twoHeads
? 3 : 1;
5893 entry
->location
= !DCB_LOC_ON_CHIP
; /* ie OFF CHIP */
5894 entry
->or = 1; /* means |0x10 gets set on CRE_LCD__INDEX */
5895 entry
->duallink_possible
= false; /* SiI164 and co. are single link */
5899 * For dvi-a either crtc probably works, but my card appears to only
5900 * support dvi-d. "nvidia" still attempts to program it for dvi-a,
5901 * doing the full fp output setup (program 0x6808.. fp dimension regs,
5902 * setting 0x680848 to 0x10000111 to enable, maybe setting 0x680880);
5903 * the monitor picks up the mode res ok and lights up, but no pixel
5904 * data appears, so the board manufacturer probably connected up the
5905 * sync lines, but missed the video traces / components
5907 * with this introduction, dvi-a left as an exercise for the reader.
5909 fabricate_vga_output(dcb
, LEGACY_I2C_PANEL
, entry
->heads
);
5913 static void fabricate_tv_output(struct dcb_table
*dcb
, bool twoHeads
)
5915 struct dcb_entry
*entry
= new_dcb_entry(dcb
);
5918 entry
->i2c_index
= LEGACY_I2C_TV
;
5919 entry
->heads
= twoHeads
? 3 : 1;
5920 entry
->location
= !DCB_LOC_ON_CHIP
; /* ie OFF CHIP */
5924 parse_dcb20_entry(struct drm_device
*dev
, struct dcb_table
*dcb
,
5925 uint32_t conn
, uint32_t conf
, struct dcb_entry
*entry
)
5927 entry
->type
= conn
& 0xf;
5928 entry
->i2c_index
= (conn
>> 4) & 0xf;
5929 entry
->heads
= (conn
>> 8) & 0xf;
5930 if (dcb
->version
>= 0x40)
5931 entry
->connector
= (conn
>> 12) & 0xf;
5932 entry
->bus
= (conn
>> 16) & 0xf;
5933 entry
->location
= (conn
>> 20) & 0x3;
5934 entry
->or = (conn
>> 24) & 0xf;
5936 switch (entry
->type
) {
5939 * Although the rest of a CRT conf dword is usually
5940 * zeros, mac biosen have stuff there so we must mask
5942 entry
->crtconf
.maxfreq
= (dcb
->version
< 0x30) ?
5943 (conf
& 0xffff) * 10 :
5944 (conf
& 0xff) * 10000;
5950 entry
->lvdsconf
.use_straps_for_mode
= true;
5951 if (dcb
->version
< 0x22) {
5954 * The laptop in bug 14567 lies and claims to not use
5955 * straps when it does, so assume all DCB 2.0 laptops
5956 * use straps, until a broken EDID using one is produced
5958 entry
->lvdsconf
.use_straps_for_mode
= true;
5960 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
5961 * mean the same thing (probably wrong, but might work)
5963 if (conf
& 0x4 || conf
& 0x8)
5964 entry
->lvdsconf
.use_power_scripts
= true;
5968 entry
->lvdsconf
.use_acpi_for_edid
= true;
5970 entry
->lvdsconf
.use_power_scripts
= true;
5971 entry
->lvdsconf
.sor
.link
= (conf
& 0x00000030) >> 4;
5975 * Until we even try to use these on G8x, it's
5976 * useless reporting unknown bits. They all are.
5978 if (dcb
->version
>= 0x40)
5981 NV_ERROR(dev
, "Unknown LVDS configuration bits, "
5988 if (dcb
->version
>= 0x30)
5989 entry
->tvconf
.has_component_output
= conf
& (0x8 << 4);
5991 entry
->tvconf
.has_component_output
= false;
5996 entry
->dpconf
.sor
.link
= (conf
& 0x00000030) >> 4;
5997 entry
->dpconf
.link_bw
= (conf
& 0x00e00000) >> 21;
5998 switch ((conf
& 0x0f000000) >> 24) {
6000 entry
->dpconf
.link_nr
= 4;
6003 entry
->dpconf
.link_nr
= 2;
6006 entry
->dpconf
.link_nr
= 1;
6011 if (dcb
->version
>= 0x22)
6012 entry
->tmdsconf
.slave_addr
= (conf
& 0x00000070) >> 4;
6013 else if (dcb
->version
>= 0x30)
6014 entry
->tmdsconf
.slave_addr
= (conf
& 0x00000700) >> 8;
6015 else if (dcb
->version
>= 0x40)
6016 entry
->tmdsconf
.sor
.link
= (conf
& 0x00000030) >> 4;
6020 /* weird g80 mobile type that "nv" treats as a terminator */
6027 if (dcb
->version
< 0x40) {
6028 /* Normal entries consist of a single bit, but dual link has
6029 * the next most significant bit set too
6031 entry
->duallink_possible
=
6032 ((1 << (ffs(entry
->or) - 1)) * 3 == entry
->or);
6034 entry
->duallink_possible
= (entry
->sorconf
.link
== 3);
6037 /* unsure what DCB version introduces this, 3.0? */
6038 if (conf
& 0x100000)
6039 entry
->i2c_upper_default
= true;
6045 parse_dcb15_entry(struct drm_device
*dev
, struct dcb_table
*dcb
,
6046 uint32_t conn
, uint32_t conf
, struct dcb_entry
*entry
)
6048 switch (conn
& 0x0000000f) {
6050 entry
->type
= OUTPUT_ANALOG
;
6053 entry
->type
= OUTPUT_TV
;
6057 entry
->type
= OUTPUT_LVDS
;
6060 switch ((conn
& 0x000000f0) >> 4) {
6062 entry
->type
= OUTPUT_TMDS
;
6065 entry
->type
= OUTPUT_LVDS
;
6068 NV_ERROR(dev
, "Unknown DCB subtype 4/%d\n",
6069 (conn
& 0x000000f0) >> 4);
6074 NV_ERROR(dev
, "Unknown DCB type %d\n", conn
& 0x0000000f);
6078 entry
->i2c_index
= (conn
& 0x0003c000) >> 14;
6079 entry
->heads
= ((conn
& 0x001c0000) >> 18) + 1;
6080 entry
->or = entry
->heads
; /* same as heads, hopefully safe enough */
6081 entry
->location
= (conn
& 0x01e00000) >> 21;
6082 entry
->bus
= (conn
& 0x0e000000) >> 25;
6083 entry
->duallink_possible
= false;
6085 switch (entry
->type
) {
6087 entry
->crtconf
.maxfreq
= (conf
& 0xffff) * 10;
6090 entry
->tvconf
.has_component_output
= false;
6093 if ((conn
& 0x00003f00) != 0x10)
6094 entry
->lvdsconf
.use_straps_for_mode
= true;
6095 entry
->lvdsconf
.use_power_scripts
= true;
6104 static bool parse_dcb_entry(struct drm_device
*dev
, struct dcb_table
*dcb
,
6105 uint32_t conn
, uint32_t conf
)
6107 struct dcb_entry
*entry
= new_dcb_entry(dcb
);
6110 if (dcb
->version
>= 0x20)
6111 ret
= parse_dcb20_entry(dev
, dcb
, conn
, conf
, entry
);
6113 ret
= parse_dcb15_entry(dev
, dcb
, conn
, conf
, entry
);
6117 read_dcb_i2c_entry(dev
, dcb
->version
, dcb
->i2c_table
,
6118 entry
->i2c_index
, &dcb
->i2c
[entry
->i2c_index
]);
6124 void merge_like_dcb_entries(struct drm_device
*dev
, struct dcb_table
*dcb
)
6127 * DCB v2.0 lists each output combination separately.
6128 * Here we merge compatible entries to have fewer outputs, with
6132 int i
, newentries
= 0;
6134 for (i
= 0; i
< dcb
->entries
; i
++) {
6135 struct dcb_entry
*ient
= &dcb
->entry
[i
];
6138 for (j
= i
+ 1; j
< dcb
->entries
; j
++) {
6139 struct dcb_entry
*jent
= &dcb
->entry
[j
];
6141 if (jent
->type
== 100) /* already merged entry */
6144 /* merge heads field when all other fields the same */
6145 if (jent
->i2c_index
== ient
->i2c_index
&&
6146 jent
->type
== ient
->type
&&
6147 jent
->location
== ient
->location
&&
6148 jent
->or == ient
->or) {
6149 NV_TRACE(dev
, "Merging DCB entries %d and %d\n",
6151 ient
->heads
|= jent
->heads
;
6152 jent
->type
= 100; /* dummy value */
6157 /* Compact entries merged into others out of dcb */
6158 for (i
= 0; i
< dcb
->entries
; i
++) {
6159 if (dcb
->entry
[i
].type
== 100)
6162 if (newentries
!= i
) {
6163 dcb
->entry
[newentries
] = dcb
->entry
[i
];
6164 dcb
->entry
[newentries
].index
= newentries
;
6169 dcb
->entries
= newentries
;
6173 apply_dcb_encoder_quirks(struct drm_device
*dev
, int idx
, u32
*conn
, u32
*conf
)
6175 /* Dell Precision M6300
6176 * DCB entry 2: 02025312 00000010
6177 * DCB entry 3: 02026312 00000020
6179 * Identical, except apparently a different connector on a
6180 * different SOR link. Not a clue how we're supposed to know
6181 * which one is in use if it even shares an i2c line...
6183 * Ignore the connector on the second SOR link to prevent
6184 * nasty problems until this is sorted (assuming it's not a
6187 if ((dev
->pdev
->device
== 0x040d) &&
6188 (dev
->pdev
->subsystem_vendor
== 0x1028) &&
6189 (dev
->pdev
->subsystem_device
== 0x019b)) {
6190 if (*conn
== 0x02026312 && *conf
== 0x00000020)
6198 parse_dcb_table(struct drm_device
*dev
, struct nvbios
*bios
, bool twoHeads
)
6200 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
6201 struct dcb_table
*dcb
= &bios
->dcb
;
6202 uint16_t dcbptr
= 0, i2ctabptr
= 0;
6204 uint8_t headerlen
= 0x4, entries
= DCB_MAX_NUM_ENTRIES
;
6205 bool configblock
= true;
6206 int recordlength
= 8, confofs
= 4;
6209 /* get the offset from 0x36 */
6210 if (dev_priv
->card_type
> NV_04
) {
6211 dcbptr
= ROM16(bios
->data
[0x36]);
6212 if (dcbptr
== 0x0000)
6213 NV_WARN(dev
, "No output data (DCB) found in BIOS\n");
6216 /* this situation likely means a really old card, pre DCB */
6217 if (dcbptr
== 0x0) {
6218 NV_INFO(dev
, "Assuming a CRT output exists\n");
6219 fabricate_vga_output(dcb
, LEGACY_I2C_CRT
, 1);
6221 if (nv04_tv_identify(dev
, bios
->legacy
.i2c_indices
.tv
) >= 0)
6222 fabricate_tv_output(dcb
, twoHeads
);
6227 dcbtable
= &bios
->data
[dcbptr
];
6229 /* get DCB version */
6230 dcb
->version
= dcbtable
[0];
6231 NV_TRACE(dev
, "Found Display Configuration Block version %d.%d\n",
6232 dcb
->version
>> 4, dcb
->version
& 0xf);
6234 if (dcb
->version
>= 0x20) { /* NV17+ */
6237 if (dcb
->version
>= 0x30) { /* NV40+ */
6238 headerlen
= dcbtable
[1];
6239 entries
= dcbtable
[2];
6240 recordlength
= dcbtable
[3];
6241 i2ctabptr
= ROM16(dcbtable
[4]);
6242 sig
= ROM32(dcbtable
[6]);
6243 dcb
->gpio_table_ptr
= ROM16(dcbtable
[10]);
6244 dcb
->connector_table_ptr
= ROM16(dcbtable
[20]);
6246 i2ctabptr
= ROM16(dcbtable
[2]);
6247 sig
= ROM32(dcbtable
[4]);
6251 if (sig
!= 0x4edcbdcb) {
6252 NV_ERROR(dev
, "Bad Display Configuration Block "
6253 "signature (%08X)\n", sig
);
6256 } else if (dcb
->version
>= 0x15) { /* some NV11 and NV20 */
6257 char sig
[8] = { 0 };
6259 strncpy(sig
, (char *)&dcbtable
[-7], 7);
6260 i2ctabptr
= ROM16(dcbtable
[2]);
6264 if (strcmp(sig
, "DEV_REC")) {
6265 NV_ERROR(dev
, "Bad Display Configuration Block "
6266 "signature (%s)\n", sig
);
6271 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always
6272 * has the same single (crt) entry, even when tv-out present, so
6273 * the conclusion is this version cannot really be used.
6274 * v1.2 tables (some NV6/10, and NV15+) normally have the same
6275 * 5 entries, which are not specific to the card and so no use.
6276 * v1.2 does have an I2C table that read_dcb_i2c_table can
6277 * handle, but cards exist (nv11 in #14821) with a bad i2c table
6278 * pointer, so use the indices parsed in parse_bmp_structure.
6279 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
6281 NV_TRACEWARN(dev
, "No useful information in BIOS output table; "
6282 "adding all possible outputs\n");
6283 fabricate_vga_output(dcb
, LEGACY_I2C_CRT
, 1);
6286 * Attempt to detect TV before DVI because the test
6287 * for the former is more accurate and it rules the
6290 if (nv04_tv_identify(dev
,
6291 bios
->legacy
.i2c_indices
.tv
) >= 0)
6292 fabricate_tv_output(dcb
, twoHeads
);
6294 else if (bios
->tmds
.output0_script_ptr
||
6295 bios
->tmds
.output1_script_ptr
)
6296 fabricate_dvi_i_output(dcb
, twoHeads
);
6302 NV_WARN(dev
, "No pointer to DCB I2C port table\n");
6304 dcb
->i2c_table
= &bios
->data
[i2ctabptr
];
6305 if (dcb
->version
>= 0x30)
6306 dcb
->i2c_default_indices
= dcb
->i2c_table
[4];
6309 * Parse the "management" I2C bus, used for hardware
6310 * monitoring and some external TMDS transmitters.
6312 if (dcb
->version
>= 0x22) {
6313 int idx
= (dcb
->version
>= 0x40 ?
6314 dcb
->i2c_default_indices
& 0xf :
6317 read_dcb_i2c_entry(dev
, dcb
->version
, dcb
->i2c_table
,
6318 idx
, &dcb
->i2c
[idx
]);
6322 if (entries
> DCB_MAX_NUM_ENTRIES
)
6323 entries
= DCB_MAX_NUM_ENTRIES
;
6325 for (i
= 0; i
< entries
; i
++) {
6326 uint32_t connection
, config
= 0;
6328 connection
= ROM32(dcbtable
[headerlen
+ recordlength
* i
]);
6330 config
= ROM32(dcbtable
[headerlen
+ confofs
+ recordlength
* i
]);
6332 /* seen on an NV11 with DCB v1.5 */
6333 if (connection
== 0x00000000)
6336 /* seen on an NV17 with DCB v2.0 */
6337 if (connection
== 0xffffffff)
6340 if ((connection
& 0x0000000f) == 0x0000000f)
6343 if (!apply_dcb_encoder_quirks(dev
, i
, &connection
, &config
))
6346 NV_TRACEWARN(dev
, "Raw DCB entry %d: %08x %08x\n",
6347 dcb
->entries
, connection
, config
);
6349 if (!parse_dcb_entry(dev
, dcb
, connection
, config
))
6354 * apart for v2.1+ not being known for requiring merging, this
6355 * guarantees dcbent->index is the index of the entry in the rom image
6357 if (dcb
->version
< 0x21)
6358 merge_like_dcb_entries(dev
, dcb
);
6363 parse_dcb_gpio_table(bios
);
6364 parse_dcb_connector_table(bios
);
6369 fixup_legacy_connector(struct nvbios
*bios
)
6371 struct dcb_table
*dcb
= &bios
->dcb
;
6372 int i
, i2c
, i2c_conn
[DCB_MAX_NUM_I2C_ENTRIES
] = { };
6375 * DCB 3.0 also has the table in most cases, but there are some cards
6376 * where the table is filled with stub entries, and the DCB entriy
6377 * indices are all 0. We don't need the connector indices on pre-G80
6378 * chips (yet?) so limit the use to DCB 4.0 and above.
6380 if (dcb
->version
>= 0x40)
6383 dcb
->connector
.entries
= 0;
6386 * No known connector info before v3.0, so make it up. the rule here
6387 * is: anything on the same i2c bus is considered to be on the same
6388 * connector. any output without an associated i2c bus is assigned
6389 * its own unique connector index.
6391 for (i
= 0; i
< dcb
->entries
; i
++) {
6393 * Ignore the I2C index for on-chip TV-out, as there
6394 * are cards with bogus values (nv31m in bug 23212),
6395 * and it's otherwise useless.
6397 if (dcb
->entry
[i
].type
== OUTPUT_TV
&&
6398 dcb
->entry
[i
].location
== DCB_LOC_ON_CHIP
)
6399 dcb
->entry
[i
].i2c_index
= 0xf;
6400 i2c
= dcb
->entry
[i
].i2c_index
;
6402 if (i2c_conn
[i2c
]) {
6403 dcb
->entry
[i
].connector
= i2c_conn
[i2c
] - 1;
6407 dcb
->entry
[i
].connector
= dcb
->connector
.entries
++;
6409 i2c_conn
[i2c
] = dcb
->connector
.entries
;
6412 /* Fake the connector table as well as just connector indices */
6413 for (i
= 0; i
< dcb
->connector
.entries
; i
++) {
6414 dcb
->connector
.entry
[i
].index
= i
;
6415 dcb
->connector
.entry
[i
].type
= divine_connector_type(bios
, i
);
6416 dcb
->connector
.entry
[i
].gpio_tag
= 0xff;
6421 fixup_legacy_i2c(struct nvbios
*bios
)
6423 struct dcb_table
*dcb
= &bios
->dcb
;
6426 for (i
= 0; i
< dcb
->entries
; i
++) {
6427 if (dcb
->entry
[i
].i2c_index
== LEGACY_I2C_CRT
)
6428 dcb
->entry
[i
].i2c_index
= bios
->legacy
.i2c_indices
.crt
;
6429 if (dcb
->entry
[i
].i2c_index
== LEGACY_I2C_PANEL
)
6430 dcb
->entry
[i
].i2c_index
= bios
->legacy
.i2c_indices
.panel
;
6431 if (dcb
->entry
[i
].i2c_index
== LEGACY_I2C_TV
)
6432 dcb
->entry
[i
].i2c_index
= bios
->legacy
.i2c_indices
.tv
;
6436 static int load_nv17_hwsq_ucode_entry(struct drm_device
*dev
, struct nvbios
*bios
, uint16_t hwsq_offset
, int entry
)
6439 * The header following the "HWSQ" signature has the number of entries,
6440 * and the entry size
6442 * An entry consists of a dword to write to the sequencer control reg
6443 * (0x00001304), followed by the ucode bytes, written sequentially,
6444 * starting at reg 0x00001400
6447 uint8_t bytes_to_write
;
6448 uint16_t hwsq_entry_offset
;
6451 if (bios
->data
[hwsq_offset
] <= entry
) {
6452 NV_ERROR(dev
, "Too few entries in HW sequencer table for "
6453 "requested entry\n");
6457 bytes_to_write
= bios
->data
[hwsq_offset
+ 1];
6459 if (bytes_to_write
!= 36) {
6460 NV_ERROR(dev
, "Unknown HW sequencer entry size\n");
6464 NV_TRACE(dev
, "Loading NV17 power sequencing microcode\n");
6466 hwsq_entry_offset
= hwsq_offset
+ 2 + entry
* bytes_to_write
;
6468 /* set sequencer control */
6469 bios_wr32(bios
, 0x00001304, ROM32(bios
->data
[hwsq_entry_offset
]));
6470 bytes_to_write
-= 4;
6473 for (i
= 0; i
< bytes_to_write
; i
+= 4)
6474 bios_wr32(bios
, 0x00001400 + i
, ROM32(bios
->data
[hwsq_entry_offset
+ i
+ 4]));
6476 /* twiddle NV_PBUS_DEBUG_4 */
6477 bios_wr32(bios
, NV_PBUS_DEBUG_4
, bios_rd32(bios
, NV_PBUS_DEBUG_4
) | 0x18);
6482 static int load_nv17_hw_sequencer_ucode(struct drm_device
*dev
,
6483 struct nvbios
*bios
)
6486 * BMP based cards, from NV17, need a microcode loading to correctly
6487 * control the GPIO etc for LVDS panels
6489 * BIT based cards seem to do this directly in the init scripts
6491 * The microcode entries are found by the "HWSQ" signature.
6494 const uint8_t hwsq_signature
[] = { 'H', 'W', 'S', 'Q' };
6495 const int sz
= sizeof(hwsq_signature
);
6498 hwsq_offset
= findstr(bios
->data
, bios
->length
, hwsq_signature
, sz
);
6502 /* always use entry 0? */
6503 return load_nv17_hwsq_ucode_entry(dev
, bios
, hwsq_offset
+ sz
, 0);
6506 uint8_t *nouveau_bios_embedded_edid(struct drm_device
*dev
)
6508 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
6509 struct nvbios
*bios
= &dev_priv
->vbios
;
6510 const uint8_t edid_sig
[] = {
6511 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
6512 uint16_t offset
= 0;
6514 int searchlen
= NV_PROM_SIZE
;
6517 return bios
->fp
.edid
;
6520 newoffset
= findstr(&bios
->data
[offset
], searchlen
,
6524 offset
+= newoffset
;
6525 if (!nv_cksum(&bios
->data
[offset
], EDID1_LEN
))
6528 searchlen
-= offset
;
6532 NV_TRACE(dev
, "Found EDID in BIOS\n");
6534 return bios
->fp
.edid
= &bios
->data
[offset
];
6538 nouveau_bios_run_init_table(struct drm_device
*dev
, uint16_t table
,
6539 struct dcb_entry
*dcbent
)
6541 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
6542 struct nvbios
*bios
= &dev_priv
->vbios
;
6543 struct init_exec iexec
= { true, false };
6545 mutex_lock(&bios
->lock
);
6546 bios
->display
.output
= dcbent
;
6547 parse_init_table(bios
, table
, &iexec
);
6548 bios
->display
.output
= NULL
;
6549 mutex_unlock(&bios
->lock
);
6552 static bool NVInitVBIOS(struct drm_device
*dev
)
6554 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
6555 struct nvbios
*bios
= &dev_priv
->vbios
;
6557 memset(bios
, 0, sizeof(struct nvbios
));
6558 mutex_init(&bios
->lock
);
6561 if (!NVShadowVBIOS(dev
, bios
->data
))
6564 bios
->length
= NV_PROM_SIZE
;
6568 static int nouveau_parse_vbios_struct(struct drm_device
*dev
)
6570 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
6571 struct nvbios
*bios
= &dev_priv
->vbios
;
6572 const uint8_t bit_signature
[] = { 0xff, 0xb8, 'B', 'I', 'T' };
6573 const uint8_t bmp_signature
[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
6576 offset
= findstr(bios
->data
, bios
->length
,
6577 bit_signature
, sizeof(bit_signature
));
6579 NV_TRACE(dev
, "BIT BIOS found\n");
6580 return parse_bit_structure(bios
, offset
+ 6);
6583 offset
= findstr(bios
->data
, bios
->length
,
6584 bmp_signature
, sizeof(bmp_signature
));
6586 NV_TRACE(dev
, "BMP BIOS found\n");
6587 return parse_bmp_structure(dev
, bios
, offset
);
6590 NV_ERROR(dev
, "No known BIOS signature found\n");
6595 nouveau_run_vbios_init(struct drm_device
*dev
)
6597 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
6598 struct nvbios
*bios
= &dev_priv
->vbios
;
6601 /* Reset the BIOS head to 0. */
6602 bios
->state
.crtchead
= 0;
6604 if (bios
->major_version
< 5) /* BMP only */
6605 load_nv17_hw_sequencer_ucode(dev
, bios
);
6607 if (bios
->execute
) {
6608 bios
->fp
.last_script_invoc
= 0;
6609 bios
->fp
.lvds_init_run
= false;
6612 parse_init_tables(bios
);
6615 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
6616 * parser will run this right after the init tables, the binary
6617 * driver appears to run it at some point later.
6619 if (bios
->some_script_ptr
) {
6620 struct init_exec iexec
= {true, false};
6622 NV_INFO(dev
, "Parsing VBIOS init table at offset 0x%04X\n",
6623 bios
->some_script_ptr
);
6624 parse_init_table(bios
, bios
->some_script_ptr
, &iexec
);
6627 if (dev_priv
->card_type
>= NV_50
) {
6628 for (i
= 0; i
< bios
->dcb
.entries
; i
++) {
6629 nouveau_bios_run_display_table(dev
,
6630 &bios
->dcb
.entry
[i
],
6639 nouveau_bios_i2c_devices_takedown(struct drm_device
*dev
)
6641 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
6642 struct nvbios
*bios
= &dev_priv
->vbios
;
6643 struct dcb_i2c_entry
*entry
;
6646 entry
= &bios
->dcb
.i2c
[0];
6647 for (i
= 0; i
< DCB_MAX_NUM_I2C_ENTRIES
; i
++, entry
++)
6648 nouveau_i2c_fini(dev
, entry
);
6652 nouveau_bios_posted(struct drm_device
*dev
)
6654 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
6657 if (dev_priv
->chipset
>= NV_50
) {
6658 if (NVReadVgaCrtc(dev
, 0, 0x00) == 0 &&
6659 NVReadVgaCrtc(dev
, 0, 0x1a) == 0)
6664 htotal
= NVReadVgaCrtc(dev
, 0, 0x06);
6665 htotal
|= (NVReadVgaCrtc(dev
, 0, 0x07) & 0x01) << 8;
6666 htotal
|= (NVReadVgaCrtc(dev
, 0, 0x07) & 0x20) << 4;
6667 htotal
|= (NVReadVgaCrtc(dev
, 0, 0x25) & 0x01) << 10;
6668 htotal
|= (NVReadVgaCrtc(dev
, 0, 0x41) & 0x01) << 11;
6670 return (htotal
!= 0);
6674 nouveau_bios_init(struct drm_device
*dev
)
6676 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
6677 struct nvbios
*bios
= &dev_priv
->vbios
;
6680 if (!NVInitVBIOS(dev
))
6683 ret
= nouveau_parse_vbios_struct(dev
);
6687 ret
= parse_dcb_table(dev
, bios
, nv_two_heads(dev
));
6691 fixup_legacy_i2c(bios
);
6692 fixup_legacy_connector(bios
);
6694 if (!bios
->major_version
) /* we don't run version 0 bios */
6697 /* init script execution disabled */
6698 bios
->execute
= false;
6700 /* ... unless card isn't POSTed already */
6701 if (!nouveau_bios_posted(dev
)) {
6702 NV_INFO(dev
, "Adaptor not initialised, "
6703 "running VBIOS init tables.\n");
6704 bios
->execute
= true;
6707 ret
= nouveau_run_vbios_init(dev
);
6711 /* feature_byte on BMP is poor, but init always sets CR4B */
6712 if (bios
->major_version
< 5)
6713 bios
->is_mobile
= NVReadVgaCrtc(dev
, 0, NV_CIO_CRE_4B
) & 0x40;
6715 /* all BIT systems need p_f_m_t for digital_min_front_porch */
6716 if (bios
->is_mobile
|| bios
->major_version
>= 5)
6717 ret
= parse_fp_mode_table(dev
, bios
);
6719 /* allow subsequent scripts to execute */
6720 bios
->execute
= true;
6726 nouveau_bios_takedown(struct drm_device
*dev
)
6728 nouveau_bios_i2c_devices_takedown(dev
);