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staging:iio:adc:ad7887 move to irqchip based trigger handling.
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / iio / adc / max1363_core.c
blob935914ed361b5e5082381a343b2e5bd5aeb98eed
1 /*
2 * iio/adc/max1363.c
3 * Copyright (C) 2008-2010 Jonathan Cameron
4 *
5 * based on linux/drivers/i2c/chips/max123x
6 * Copyright (C) 2002-2004 Stefan Eletzhofer
7 *
8 * based on linux/drivers/acron/char/pcf8583.c
9 * Copyright (C) 2000 Russell King
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * max1363.c
16 *
17 * Partial support for max1363 and similar chips.
18 *
19 * Not currently implemented.
20 *
21 * - Control of internal reference.
22 */
23
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/kernel.h>
27 #include <linux/sysfs.h>
28 #include <linux/list.h>
29 #include <linux/i2c.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/slab.h>
32 #include <linux/err.h>
33
34 #include "../iio.h"
35 #include "../sysfs.h"
36
37 #include "../ring_generic.h"
38 #include "adc.h"
39 #include "max1363.h"
40
41 /* Here we claim all are 16 bits. This currently does no harm and saves
42 * us a lot of scan element listings */
43
44 static const struct max1363_mode max1363_mode_table[] = {
45 /* All of the single channel options first */
46 MAX1363_MODE_SINGLE(0, 1 << 0),
47 MAX1363_MODE_SINGLE(1, 1 << 1),
48 MAX1363_MODE_SINGLE(2, 1 << 2),
49 MAX1363_MODE_SINGLE(3, 1 << 3),
50 MAX1363_MODE_SINGLE(4, 1 << 4),
51 MAX1363_MODE_SINGLE(5, 1 << 5),
52 MAX1363_MODE_SINGLE(6, 1 << 6),
53 MAX1363_MODE_SINGLE(7, 1 << 7),
54 MAX1363_MODE_SINGLE(8, 1 << 8),
55 MAX1363_MODE_SINGLE(9, 1 << 9),
56 MAX1363_MODE_SINGLE(10, 1 << 10),
57 MAX1363_MODE_SINGLE(11, 1 << 11),
58
59 MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12),
60 MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13),
61 MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14),
62 MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15),
63 MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16),
64 MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17),
65 MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18),
66 MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19),
67 MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20),
68 MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21),
69 MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22),
70 MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23),
71
72 /* The multichannel scans next */
73 MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003),
74 MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007),
75 MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C),
76 MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F),
77 MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F),
78 MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F),
79 MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F),
80 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0),
81 MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF),
82 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0),
83 MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF),
84 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0),
85 MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF),
86 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0),
87 MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF),
88 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0),
89 MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF),
90
91 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000),
92 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000),
93 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000),
94 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000),
95 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000),
96 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000),
97 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000),
98 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000),
99 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000),
100 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000),
101 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000),
102 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000),
103 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000),
104 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000),
105 };
106
107 const struct max1363_mode
108 *max1363_match_mode(u32 mask, const struct max1363_chip_info *ci)
109 {
110 int i;
111 if (mask)
112 for (i = 0; i < ci->num_modes; i++)
113 if (!((~max1363_mode_table[ci->mode_list[i]].modemask) &
114 mask))
115 return &max1363_mode_table[ci->mode_list[i]];
116 return NULL;
117 }
118
119 static int max1363_write_basic_config(struct i2c_client *client,
120 unsigned char d1,
121 unsigned char d2)
122 {
123 int ret;
124 u8 *tx_buf = kmalloc(2, GFP_KERNEL);
125
126 if (!tx_buf)
127 return -ENOMEM;
128 tx_buf[0] = d1;
129 tx_buf[1] = d2;
130
131 ret = i2c_master_send(client, tx_buf, 2);
132 kfree(tx_buf);
133
134 return (ret > 0) ? 0 : ret;
135 }
136
137 int max1363_set_scan_mode(struct max1363_state *st)
138 {
139 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
140 | MAX1363_SCAN_MASK
141 | MAX1363_SE_DE_MASK);
142 st->configbyte |= st->current_mode->conf;
143
144 return max1363_write_basic_config(st->client,
145 st->setupbyte,
146 st->configbyte);
147 }
148
149 static int max1363_read_single_chan(struct iio_dev *indio_dev,
150 struct iio_chan_spec const *chan,
151 int *val,
152 long m)
153 {
154 int ret = 0;
155 s32 data;
156 char rxbuf[2];
157 long mask;
158 struct max1363_state *st = iio_priv(indio_dev);
159 struct i2c_client *client = st->client;
160
161 mutex_lock(&indio_dev->mlock);
162 /*
163 * If monitor mode is enabled, the method for reading a single
164 * channel will have to be rather different and has not yet
165 * been implemented.
166 */
167 if (st->monitor_on) {
168 ret = -EBUSY;
169 goto error_ret;
170 }
171
172 /* If ring buffer capture is occurring, query the buffer */
173 if (iio_ring_enabled(indio_dev)) {
174 mask = max1363_mode_table[chan->address].modemask;
175 data = max1363_single_channel_from_ring(mask, st);
176 if (data < 0) {
177 ret = data;
178 goto error_ret;
179 }
180 } else {
181 /* Check to see if current scan mode is correct */
182 if (st->current_mode !=
183 &max1363_mode_table[chan->address]) {
184 /* Update scan mode if needed */
185 st->current_mode
186 = &max1363_mode_table[chan->address];
187 ret = max1363_set_scan_mode(st);
188 if (ret)
189 goto error_ret;
190 }
191 if (st->chip_info->bits != 8) {
192 /* Get reading */
193 data = i2c_master_recv(client, rxbuf, 2);
194 if (data < 0) {
195 ret = data;
196 goto error_ret;
197 }
198 data = (s32)(rxbuf[1]) | ((s32)(rxbuf[0] & 0x0F)) << 8;
199 } else {
200 /* Get reading */
201 data = i2c_master_recv(client, rxbuf, 1);
202 if (data < 0) {
203 ret = data;
204 goto error_ret;
205 }
206 data = rxbuf[0];
207 }
208 }
209 *val = data;
210 error_ret:
211 mutex_unlock(&indio_dev->mlock);
212 return ret;
213
214 }
215
216 static int max1363_read_raw(struct iio_dev *indio_dev,
217 struct iio_chan_spec const *chan,
218 int *val,
219 int *val2,
220 long m)
221 {
222 struct max1363_state *st = iio_priv(indio_dev);
223 int ret;
224 switch (m) {
225 case 0:
226 ret = max1363_read_single_chan(indio_dev, chan, val, m);
227 if (ret)
228 return ret;
229 return IIO_VAL_INT;
230 case (1 << IIO_CHAN_INFO_SCALE_SHARED):
231 if ((1 << (st->chip_info->bits + 1)) >
232 st->chip_info->int_vref_mv) {
233 *val = 0;
234 *val2 = 500000;
235 return IIO_VAL_INT_PLUS_MICRO;
236 } else {
237 *val = (st->chip_info->int_vref_mv)
238 >> st->chip_info->bits;
239 return IIO_VAL_INT;
240 }
241 default:
242 return -EINVAL;
243 }
244 return 0;
245 }
246
247 static ssize_t max1363_show_name(struct device *dev,
248 struct device_attribute *attr,
249 char *buf)
250 {
251 struct max1363_state *st = iio_priv(dev_get_drvdata(dev));
252 return sprintf(buf, "%s\n", st->client->name);
253 }
254
255 static IIO_DEVICE_ATTR(name, S_IRUGO, max1363_show_name, NULL, 0);
256
257 /* Applies to max1363 */
258 static const enum max1363_modes max1363_mode_list[] = {
259 _s0, _s1, _s2, _s3,
260 s0to1, s0to2, s0to3,
261 d0m1, d2m3, d1m0, d3m2,
262 d0m1to2m3, d1m0to3m2,
263 };
264
265 #define MAX1363_EV_M \
266 (IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) \
267 | IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING))
268 #define MAX1363_INFO_MASK (1 << IIO_CHAN_INFO_SCALE_SHARED)
269
270 static struct iio_chan_spec max1363_channels[] = {
271 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0, MAX1363_INFO_MASK,
272 _s0, 0, IIO_ST('u', 12, 16, 0), MAX1363_EV_M),
273 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK,
274 _s1, 1, IIO_ST('u', 12, 16, 0), MAX1363_EV_M),
275 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 2, 0, MAX1363_INFO_MASK,
276 _s2, 2, IIO_ST('u', 12, 16, 0), MAX1363_EV_M),
277 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 3, 0, MAX1363_INFO_MASK,
278 _s3, 3, IIO_ST('u', 12, 16, 0), MAX1363_EV_M),
279 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 0, 1, MAX1363_INFO_MASK,
280 d0m1, 4, IIO_ST('s', 12, 16, 0), MAX1363_EV_M),
281 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 2, 3, MAX1363_INFO_MASK,
282 d2m3, 5, IIO_ST('s', 12, 16, 0), MAX1363_EV_M),
283 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK,
284 d1m0, 6, IIO_ST('s', 12, 16, 0), MAX1363_EV_M),
285 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 3, 2, MAX1363_INFO_MASK,
286 d3m2, 7, IIO_ST('s', 12, 16, 0), MAX1363_EV_M),
287 IIO_CHAN_SOFT_TIMESTAMP(8)
288 };
289
290 static struct iio_chan_spec max1361_channels[] = {
291 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0, MAX1363_INFO_MASK,
292 _s0, 0, IIO_ST('u', 10, 16, 0), MAX1363_EV_M),
293 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK,
294 _s1, 1, IIO_ST('u', 10, 16, 0), MAX1363_EV_M),
295 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 2, 0, MAX1363_INFO_MASK,
296 _s2, 2, IIO_ST('u', 10, 16, 0), MAX1363_EV_M),
297 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 3, 0, MAX1363_INFO_MASK,
298 _s3, 3, IIO_ST('u', 10, 16, 0), MAX1363_EV_M),
299 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 0, 1, MAX1363_INFO_MASK,
300 d0m1, 4, IIO_ST('s', 10, 16, 0), MAX1363_EV_M),
301 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 2, 3, MAX1363_INFO_MASK,
302 d2m3, 5, IIO_ST('s', 10, 16, 0), MAX1363_EV_M),
303 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK,
304 d1m0, 6, IIO_ST('s', 10, 16, 0), MAX1363_EV_M),
305 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 3, 2, MAX1363_INFO_MASK,
306 d3m2, 7, IIO_ST('s', 10, 16, 0), MAX1363_EV_M),
307 IIO_CHAN_SOFT_TIMESTAMP(8)
308 };
309
310 #define MAX1363_CHAN_U(num, address, scan_index, bits) \
311 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, num, 0, MAX1363_INFO_MASK, \
312 address, scan_index, IIO_ST('u', bits, \
313 (bits == 8) ? 8 : 16, 0), 0)
314 /* bipolar channel */
315 #define MAX1363_CHAN_B(num, num2, address, scan_index, bits) \
316 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, num, num2, MAX1363_INFO_MASK,\
317 address, scan_index, IIO_ST('s', bits, \
318 (bits == 8) ? 8 : 16, 0), 0)
319
320 #define MAX1363_4X_CHANS(bits) { \
321 MAX1363_CHAN_U(0, _s0, 0, bits), \
322 MAX1363_CHAN_U(1, _s1, 1, bits), \
323 MAX1363_CHAN_U(2, _s2, 2, bits), \
324 MAX1363_CHAN_U(3, _s3, 3, bits), \
325 MAX1363_CHAN_B(0, 1, d0m1, 4, bits), \
326 MAX1363_CHAN_B(2, 3, d2m3, 5, bits), \
327 MAX1363_CHAN_B(1, 0, d1m0, 6, bits), \
328 MAX1363_CHAN_B(3, 2, d3m2, 7, bits), \
329 IIO_CHAN_SOFT_TIMESTAMP(8) \
330 }
331
332 static struct iio_chan_spec max1036_channels[] = MAX1363_4X_CHANS(8);
333 static struct iio_chan_spec max1136_channels[] = MAX1363_4X_CHANS(10);
334 static struct iio_chan_spec max1236_channels[] = MAX1363_4X_CHANS(12);
335
336 static struct attribute *max1363_device_attrs[] = {
337 &iio_dev_attr_name.dev_attr.attr,
338 NULL
339 };
340
341 static struct attribute_group max1363_dev_attr_group = {
342 .attrs = max1363_device_attrs,
343 };
344
345 /* Appies to max1236, max1237 */
346 static const enum max1363_modes max1236_mode_list[] = {
347 _s0, _s1, _s2, _s3,
348 s0to1, s0to2, s0to3,
349 d0m1, d2m3, d1m0, d3m2,
350 d0m1to2m3, d1m0to3m2,
351 s2to3,
352 };
353
354 /* Applies to max1238, max1239 */
355 static const enum max1363_modes max1238_mode_list[] = {
356 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
357 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6,
358 s0to7, s0to8, s0to9, s0to10, s0to11,
359 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
360 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
361 d0m1to2m3, d0m1to4m5, d0m1to6m7, d0m1to8m9, d0m1to10m11,
362 d1m0to3m2, d1m0to5m4, d1m0to7m6, d1m0to9m8, d1m0to11m10,
363 s6to7, s6to8, s6to9, s6to10, s6to11,
364 d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10,
365 };
366
367 #define MAX1363_12X_CHANS(bits) { \
368 MAX1363_CHAN_U(0, _s0, 0, bits), \
369 MAX1363_CHAN_U(1, _s1, 1, bits), \
370 MAX1363_CHAN_U(2, _s2, 2, bits), \
371 MAX1363_CHAN_U(3, _s3, 3, bits), \
372 MAX1363_CHAN_U(4, _s4, 4, bits), \
373 MAX1363_CHAN_U(5, _s5, 5, bits), \
374 MAX1363_CHAN_U(6, _s6, 6, bits), \
375 MAX1363_CHAN_U(7, _s7, 7, bits), \
376 MAX1363_CHAN_U(8, _s8, 8, bits), \
377 MAX1363_CHAN_U(9, _s9, 9, bits), \
378 MAX1363_CHAN_U(10, _s10, 10, bits), \
379 MAX1363_CHAN_U(11, _s11, 11, bits), \
380 MAX1363_CHAN_B(0, 1, d0m1, 12, bits), \
381 MAX1363_CHAN_B(2, 3, d2m3, 13, bits), \
382 MAX1363_CHAN_B(4, 5, d4m5, 14, bits), \
383 MAX1363_CHAN_B(6, 7, d6m7, 15, bits), \
384 MAX1363_CHAN_B(8, 9, d8m9, 16, bits), \
385 MAX1363_CHAN_B(10, 11, d10m11, 17, bits), \
386 MAX1363_CHAN_B(1, 0, d1m0, 18, bits), \
387 MAX1363_CHAN_B(3, 2, d3m2, 19, bits), \
388 MAX1363_CHAN_B(5, 4, d5m4, 20, bits), \
389 MAX1363_CHAN_B(7, 6, d7m6, 21, bits), \
390 MAX1363_CHAN_B(9, 8, d9m8, 22, bits), \
391 MAX1363_CHAN_B(11, 10, d11m10, 23, bits), \
392 IIO_CHAN_SOFT_TIMESTAMP(24) \
393 }
394 static struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
395 static struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
396 static struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
397
398 static const enum max1363_modes max11607_mode_list[] = {
399 _s0, _s1, _s2, _s3,
400 s0to1, s0to2, s0to3,
401 s2to3,
402 d0m1, d2m3, d1m0, d3m2,
403 d0m1to2m3, d1m0to3m2,
404 };
405
406 static const enum max1363_modes max11608_mode_list[] = {
407 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7,
408 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s0to7,
409 s6to7,
410 d0m1, d2m3, d4m5, d6m7,
411 d1m0, d3m2, d5m4, d7m6,
412 d0m1to2m3, d0m1to4m5, d0m1to6m7,
413 d1m0to3m2, d1m0to5m4, d1m0to7m6,
414 };
415
416 #define MAX1363_8X_CHANS(bits) { \
417 MAX1363_CHAN_U(0, _s0, 0, bits), \
418 MAX1363_CHAN_U(1, _s1, 1, bits), \
419 MAX1363_CHAN_U(2, _s2, 2, bits), \
420 MAX1363_CHAN_U(3, _s3, 3, bits), \
421 MAX1363_CHAN_U(4, _s4, 4, bits), \
422 MAX1363_CHAN_U(5, _s5, 5, bits), \
423 MAX1363_CHAN_U(6, _s6, 6, bits), \
424 MAX1363_CHAN_U(7, _s7, 7, bits), \
425 MAX1363_CHAN_B(0, 1, d0m1, 8, bits), \
426 MAX1363_CHAN_B(2, 3, d2m3, 9, bits), \
427 MAX1363_CHAN_B(4, 5, d4m5, 10, bits), \
428 MAX1363_CHAN_B(6, 7, d6m7, 11, bits), \
429 MAX1363_CHAN_B(1, 0, d1m0, 12, bits), \
430 MAX1363_CHAN_B(3, 2, d3m2, 13, bits), \
431 MAX1363_CHAN_B(5, 4, d5m4, 14, bits), \
432 MAX1363_CHAN_B(7, 6, d7m6, 15, bits), \
433 IIO_CHAN_SOFT_TIMESTAMP(16) \
434 }
435 static struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
436 static struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
437 static struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
438
439 enum { max1361,
440 max1362,
441 max1363,
442 max1364,
443 max1036,
444 max1037,
445 max1038,
446 max1039,
447 max1136,
448 max1137,
449 max1138,
450 max1139,
451 max1236,
452 max1237,
453 max1238,
454 max1239,
455 max11600,
456 max11601,
457 max11602,
458 max11603,
459 max11604,
460 max11605,
461 max11606,
462 max11607,
463 max11608,
464 max11609,
465 max11610,
466 max11611,
467 max11612,
468 max11613,
469 max11614,
470 max11615,
471 max11616,
472 max11617,
473 };
474
475 /* max1363 and max1368 tested - rest from data sheet */
476 static const struct max1363_chip_info max1363_chip_info_tbl[] = {
477 [max1361] = {
478 .bits = 10,
479 .int_vref_mv = 2048,
480 .monitor_mode = 1,
481 .mode_list = max1363_mode_list,
482 .num_modes = ARRAY_SIZE(max1363_mode_list),
483 .default_mode = s0to3,
484 .channels = max1361_channels,
485 .num_channels = ARRAY_SIZE(max1361_channels),
486 },
487 [max1362] = {
488 .bits = 10,
489 .int_vref_mv = 4096,
490 .monitor_mode = 1,
491 .mode_list = max1363_mode_list,
492 .num_modes = ARRAY_SIZE(max1363_mode_list),
493 .default_mode = s0to3,
494 .channels = max1361_channels,
495 .num_channels = ARRAY_SIZE(max1361_channels),
496 },
497 [max1363] = {
498 .bits = 12,
499 .int_vref_mv = 2048,
500 .monitor_mode = 1,
501 .mode_list = max1363_mode_list,
502 .num_modes = ARRAY_SIZE(max1363_mode_list),
503 .default_mode = s0to3,
504 .channels = max1363_channels,
505 .num_channels = ARRAY_SIZE(max1363_channels),
506 },
507 [max1364] = {
508 .bits = 12,
509 .int_vref_mv = 4096,
510 .monitor_mode = 1,
511 .mode_list = max1363_mode_list,
512 .num_modes = ARRAY_SIZE(max1363_mode_list),
513 .default_mode = s0to3,
514 .channels = max1363_channels,
515 .num_channels = ARRAY_SIZE(max1363_channels),
516 },
517 [max1036] = {
518 .bits = 8,
519 .int_vref_mv = 4096,
520 .mode_list = max1236_mode_list,
521 .num_modes = ARRAY_SIZE(max1236_mode_list),
522 .default_mode = s0to3,
523 .channels = max1036_channels,
524 .num_channels = ARRAY_SIZE(max1036_channels),
525 },
526 [max1037] = {
527 .bits = 8,
528 .int_vref_mv = 2048,
529 .mode_list = max1236_mode_list,
530 .num_modes = ARRAY_SIZE(max1236_mode_list),
531 .default_mode = s0to3,
532 .channels = max1036_channels,
533 .num_channels = ARRAY_SIZE(max1036_channels),
534 },
535 [max1038] = {
536 .bits = 8,
537 .int_vref_mv = 4096,
538 .mode_list = max1238_mode_list,
539 .num_modes = ARRAY_SIZE(max1238_mode_list),
540 .default_mode = s0to11,
541 .channels = max1038_channels,
542 .num_channels = ARRAY_SIZE(max1038_channels),
543 },
544 [max1039] = {
545 .bits = 8,
546 .int_vref_mv = 2048,
547 .mode_list = max1238_mode_list,
548 .num_modes = ARRAY_SIZE(max1238_mode_list),
549 .default_mode = s0to11,
550 .channels = max1038_channels,
551 .num_channels = ARRAY_SIZE(max1038_channels),
552 },
553 [max1136] = {
554 .bits = 10,
555 .int_vref_mv = 4096,
556 .mode_list = max1236_mode_list,
557 .num_modes = ARRAY_SIZE(max1236_mode_list),
558 .default_mode = s0to3,
559 .channels = max1136_channels,
560 .num_channels = ARRAY_SIZE(max1136_channels),
561 },
562 [max1137] = {
563 .bits = 10,
564 .int_vref_mv = 2048,
565 .mode_list = max1236_mode_list,
566 .num_modes = ARRAY_SIZE(max1236_mode_list),
567 .default_mode = s0to3,
568 .channels = max1136_channels,
569 .num_channels = ARRAY_SIZE(max1136_channels),
570 },
571 [max1138] = {
572 .bits = 10,
573 .int_vref_mv = 4096,
574 .mode_list = max1238_mode_list,
575 .num_modes = ARRAY_SIZE(max1238_mode_list),
576 .default_mode = s0to11,
577 .channels = max1138_channels,
578 .num_channels = ARRAY_SIZE(max1138_channels),
579 },
580 [max1139] = {
581 .bits = 10,
582 .int_vref_mv = 2048,
583 .mode_list = max1238_mode_list,
584 .num_modes = ARRAY_SIZE(max1238_mode_list),
585 .default_mode = s0to11,
586 .channels = max1138_channels,
587 .num_channels = ARRAY_SIZE(max1138_channels),
588 },
589 [max1236] = {
590 .bits = 12,
591 .int_vref_mv = 4096,
592 .mode_list = max1236_mode_list,
593 .num_modes = ARRAY_SIZE(max1236_mode_list),
594 .default_mode = s0to3,
595 .channels = max1236_channels,
596 .num_channels = ARRAY_SIZE(max1236_channels),
597 },
598 [max1237] = {
599 .bits = 12,
600 .int_vref_mv = 2048,
601 .mode_list = max1236_mode_list,
602 .num_modes = ARRAY_SIZE(max1236_mode_list),
603 .default_mode = s0to3,
604 .channels = max1236_channels,
605 .num_channels = ARRAY_SIZE(max1236_channels),
606 },
607 [max1238] = {
608 .bits = 12,
609 .int_vref_mv = 4096,
610 .mode_list = max1238_mode_list,
611 .num_modes = ARRAY_SIZE(max1238_mode_list),
612 .default_mode = s0to11,
613 .channels = max1238_channels,
614 .num_channels = ARRAY_SIZE(max1238_channels),
615 },
616 [max1239] = {
617 .bits = 12,
618 .int_vref_mv = 2048,
619 .mode_list = max1238_mode_list,
620 .num_modes = ARRAY_SIZE(max1238_mode_list),
621 .default_mode = s0to11,
622 .channels = max1238_channels,
623 .num_channels = ARRAY_SIZE(max1238_channels),
624 },
625 [max11600] = {
626 .bits = 8,
627 .int_vref_mv = 4096,
628 .mode_list = max11607_mode_list,
629 .num_modes = ARRAY_SIZE(max11607_mode_list),
630 .default_mode = s0to3,
631 .channels = max1036_channels,
632 .num_channels = ARRAY_SIZE(max1036_channels),
633 },
634 [max11601] = {
635 .bits = 8,
636 .int_vref_mv = 2048,
637 .mode_list = max11607_mode_list,
638 .num_modes = ARRAY_SIZE(max11607_mode_list),
639 .default_mode = s0to3,
640 .channels = max1036_channels,
641 .num_channels = ARRAY_SIZE(max1036_channels),
642 },
643 [max11602] = {
644 .bits = 8,
645 .int_vref_mv = 4096,
646 .mode_list = max11608_mode_list,
647 .num_modes = ARRAY_SIZE(max11608_mode_list),
648 .default_mode = s0to7,
649 .channels = max11602_channels,
650 .num_channels = ARRAY_SIZE(max11602_channels),
651 },
652 [max11603] = {
653 .bits = 8,
654 .int_vref_mv = 2048,
655 .mode_list = max11608_mode_list,
656 .num_modes = ARRAY_SIZE(max11608_mode_list),
657 .default_mode = s0to7,
658 .channels = max11602_channels,
659 .num_channels = ARRAY_SIZE(max11602_channels),
660 },
661 [max11604] = {
662 .bits = 8,
663 .int_vref_mv = 4098,
664 .mode_list = max1238_mode_list,
665 .num_modes = ARRAY_SIZE(max1238_mode_list),
666 .default_mode = s0to11,
667 .channels = max1238_channels,
668 .num_channels = ARRAY_SIZE(max1238_channels),
669 },
670 [max11605] = {
671 .bits = 8,
672 .int_vref_mv = 2048,
673 .mode_list = max1238_mode_list,
674 .num_modes = ARRAY_SIZE(max1238_mode_list),
675 .default_mode = s0to11,
676 .channels = max1238_channels,
677 .num_channels = ARRAY_SIZE(max1238_channels),
678 },
679 [max11606] = {
680 .bits = 10,
681 .int_vref_mv = 4096,
682 .mode_list = max11607_mode_list,
683 .num_modes = ARRAY_SIZE(max11607_mode_list),
684 .default_mode = s0to3,
685 .channels = max1136_channels,
686 .num_channels = ARRAY_SIZE(max1136_channels),
687 },
688 [max11607] = {
689 .bits = 10,
690 .int_vref_mv = 2048,
691 .mode_list = max11607_mode_list,
692 .num_modes = ARRAY_SIZE(max11607_mode_list),
693 .default_mode = s0to3,
694 .channels = max1136_channels,
695 .num_channels = ARRAY_SIZE(max1136_channels),
696 },
697 [max11608] = {
698 .bits = 10,
699 .int_vref_mv = 4096,
700 .mode_list = max11608_mode_list,
701 .num_modes = ARRAY_SIZE(max11608_mode_list),
702 .default_mode = s0to7,
703 .channels = max11608_channels,
704 .num_channels = ARRAY_SIZE(max11608_channels),
705 },
706 [max11609] = {
707 .bits = 10,
708 .int_vref_mv = 2048,
709 .mode_list = max11608_mode_list,
710 .num_modes = ARRAY_SIZE(max11608_mode_list),
711 .default_mode = s0to7,
712 .channels = max11608_channels,
713 .num_channels = ARRAY_SIZE(max11608_channels),
714 },
715 [max11610] = {
716 .bits = 10,
717 .int_vref_mv = 4098,
718 .mode_list = max1238_mode_list,
719 .num_modes = ARRAY_SIZE(max1238_mode_list),
720 .default_mode = s0to11,
721 .channels = max1238_channels,
722 .num_channels = ARRAY_SIZE(max1238_channels),
723 },
724 [max11611] = {
725 .bits = 10,
726 .int_vref_mv = 2048,
727 .mode_list = max1238_mode_list,
728 .num_modes = ARRAY_SIZE(max1238_mode_list),
729 .default_mode = s0to11,
730 .channels = max1238_channels,
731 .num_channels = ARRAY_SIZE(max1238_channels),
732 },
733 [max11612] = {
734 .bits = 12,
735 .int_vref_mv = 4096,
736 .mode_list = max11607_mode_list,
737 .num_modes = ARRAY_SIZE(max11607_mode_list),
738 .default_mode = s0to3,
739 .channels = max1363_channels,
740 .num_channels = ARRAY_SIZE(max1363_channels),
741 },
742 [max11613] = {
743 .bits = 12,
744 .int_vref_mv = 2048,
745 .mode_list = max11607_mode_list,
746 .num_modes = ARRAY_SIZE(max11607_mode_list),
747 .default_mode = s0to3,
748 .channels = max1363_channels,
749 .num_channels = ARRAY_SIZE(max1363_channels),
750 },
751 [max11614] = {
752 .bits = 12,
753 .int_vref_mv = 4096,
754 .mode_list = max11608_mode_list,
755 .num_modes = ARRAY_SIZE(max11608_mode_list),
756 .default_mode = s0to7,
757 .channels = max11614_channels,
758 .num_channels = ARRAY_SIZE(max11614_channels),
759 },
760 [max11615] = {
761 .bits = 12,
762 .int_vref_mv = 2048,
763 .mode_list = max11608_mode_list,
764 .num_modes = ARRAY_SIZE(max11608_mode_list),
765 .default_mode = s0to7,
766 .channels = max11614_channels,
767 .num_channels = ARRAY_SIZE(max11614_channels),
768 },
769 [max11616] = {
770 .bits = 12,
771 .int_vref_mv = 4098,
772 .mode_list = max1238_mode_list,
773 .num_modes = ARRAY_SIZE(max1238_mode_list),
774 .default_mode = s0to11,
775 .channels = max1238_channels,
776 .num_channels = ARRAY_SIZE(max1238_channels),
777 },
778 [max11617] = {
779 .bits = 12,
780 .int_vref_mv = 2048,
781 .mode_list = max1238_mode_list,
782 .num_modes = ARRAY_SIZE(max1238_mode_list),
783 .default_mode = s0to11,
784 .channels = max1238_channels,
785 .num_channels = ARRAY_SIZE(max1238_channels),
786 }
787 };
788
789 static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600,
790 8300, 4200, 2000, 1000 };
791
792 static ssize_t max1363_monitor_show_freq(struct device *dev,
793 struct device_attribute *attr,
794 char *buf)
795 {
796 struct max1363_state *st = iio_priv(dev_get_drvdata(dev));
797 return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]);
798 }
799
800 static ssize_t max1363_monitor_store_freq(struct device *dev,
801 struct device_attribute *attr,
802 const char *buf,
803 size_t len)
804 {
805 struct iio_dev *indio_dev = dev_get_drvdata(dev);
806 struct max1363_state *st = iio_priv(indio_dev);
807 int i, ret;
808 unsigned long val;
809 bool found = false;
810
811 ret = strict_strtoul(buf, 10, &val);
812 if (ret)
813 return -EINVAL;
814 for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++)
815 if (val == max1363_monitor_speeds[i]) {
816 found = true;
817 break;
818 }
819 if (!found)
820 return -EINVAL;
821
822 mutex_lock(&indio_dev->mlock);
823 st->monitor_speed = i;
824 mutex_unlock(&indio_dev->mlock);
825
826 return 0;
827 }
828
829 static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR,
830 max1363_monitor_show_freq,
831 max1363_monitor_store_freq);
832
833 static IIO_CONST_ATTR(sampling_frequency_available,
834 "133000 665000 33300 16600 8300 4200 2000 1000");
835
836 static int max1363_read_thresh(struct iio_dev *indio_dev,
837 int event_code,
838 int *val)
839 {
840 struct max1363_state *st = iio_priv(indio_dev);
841 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING)
842 *val = st->thresh_low[IIO_EVENT_CODE_EXTRACT_NUM(event_code)];
843 else
844 *val = st->thresh_high[IIO_EVENT_CODE_EXTRACT_NUM(event_code)];
845 return 0;
846 }
847
848 static int max1363_write_thresh(struct iio_dev *indio_dev,
849 int event_code,
850 int val)
851 {
852 struct max1363_state *st = iio_priv(indio_dev);
853 /* make it handle signed correctly as well */
854 switch (st->chip_info->bits) {
855 case 10:
856 if (val > 0x3FF)
857 return -EINVAL;
858 break;
859 case 12:
860 if (val > 0xFFF)
861 return -EINVAL;
862 break;
863 }
864
865 switch (IIO_EVENT_CODE_EXTRACT_DIR(event_code)) {
866 case IIO_EV_DIR_FALLING:
867 st->thresh_low[IIO_EVENT_CODE_EXTRACT_NUM(event_code)] = val;
868 break;
869 case IIO_EV_DIR_RISING:
870 st->thresh_high[IIO_EVENT_CODE_EXTRACT_NUM(event_code)] = val;
871 break;
872 }
873
874 return 0;
875 }
876
877 static irqreturn_t max1363_event_handler(int irq, void *private)
878 {
879 struct iio_dev *indio_dev = private;
880 struct max1363_state *st = iio_priv(indio_dev);
881 s64 timestamp = iio_get_time_ns();
882 u8 rx;
883 u8 tx[2] = { st->setupbyte,
884 MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 };
885
886 i2c_master_recv(st->client, &rx, 1);
887 /* todo - begging for use of for_each_set_bit */
888 if (rx & (1 << 0))
889 iio_push_event(indio_dev, 0,
890 IIO_EVENT_CODE_IN_LOW_THRESH(3),
891 timestamp);
892 if (rx & (1 << 1))
893 iio_push_event(indio_dev, 0,
894 IIO_EVENT_CODE_IN_HIGH_THRESH(3),
895 timestamp);
896 if (rx & (1 << 2))
897 iio_push_event(indio_dev, 0,
898 IIO_EVENT_CODE_IN_LOW_THRESH(2),
899 timestamp);
900 if (rx & (1 << 3))
901 iio_push_event(indio_dev, 0,
902 IIO_EVENT_CODE_IN_HIGH_THRESH(2),
903 timestamp);
904 if (rx & (1 << 4))
905 iio_push_event(indio_dev, 0,
906 IIO_EVENT_CODE_IN_LOW_THRESH(1),
907 timestamp);
908 if (rx & (1 << 5))
909 iio_push_event(indio_dev, 0,
910 IIO_EVENT_CODE_IN_HIGH_THRESH(1),
911 timestamp);
912 if (rx & (1 << 6))
913 iio_push_event(indio_dev, 0,
914 IIO_EVENT_CODE_IN_LOW_THRESH(0),
915 timestamp);
916 if (rx & (1 << 7))
917 iio_push_event(indio_dev, 0,
918 IIO_EVENT_CODE_IN_HIGH_THRESH(0),
919 timestamp);
920 i2c_master_send(st->client, tx, 2);
921
922 return IRQ_HANDLED;
923 }
924
925 static int max1363_read_event_config(struct iio_dev *indio_dev,
926 int event_code)
927 {
928 struct max1363_state *st = iio_priv(indio_dev);
929
930 int val;
931 int number = IIO_EVENT_CODE_EXTRACT_NUM(event_code);
932 mutex_lock(&indio_dev->mlock);
933 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING)
934 val = (1 << number) & st->mask_low;
935 else
936 val = (1 << number) & st->mask_high;
937 mutex_unlock(&indio_dev->mlock);
938
939 return val;
940 }
941
942 static int max1363_monitor_mode_update(struct max1363_state *st, int enabled)
943 {
944 u8 *tx_buf;
945 int ret, i = 3, j;
946 unsigned long numelements;
947 int len;
948 long modemask;
949
950 if (!enabled) {
951 /* transition to ring capture is not currently supported */
952 st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP;
953 st->configbyte &= ~MAX1363_SCAN_MASK;
954 st->monitor_on = false;
955 return max1363_write_basic_config(st->client,
956 st->setupbyte,
957 st->configbyte);
958 }
959
960 /* Ensure we are in the relevant mode */
961 st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP;
962 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
963 | MAX1363_SCAN_MASK
964 | MAX1363_SE_DE_MASK);
965 st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE;
966 if ((st->mask_low | st->mask_high) & 0x0F) {
967 st->configbyte |= max1363_mode_table[s0to3].conf;
968 modemask = max1363_mode_table[s0to3].modemask;
969 } else if ((st->mask_low | st->mask_high) & 0x30) {
970 st->configbyte |= max1363_mode_table[d0m1to2m3].conf;
971 modemask = max1363_mode_table[d0m1to2m3].modemask;
972 } else {
973 st->configbyte |= max1363_mode_table[d1m0to3m2].conf;
974 modemask = max1363_mode_table[d1m0to3m2].modemask;
975 }
976 numelements = hweight_long(modemask);
977 len = 3 * numelements + 3;
978 tx_buf = kmalloc(len, GFP_KERNEL);
979 if (!tx_buf) {
980 ret = -ENOMEM;
981 goto error_ret;
982 }
983 tx_buf[0] = st->configbyte;
984 tx_buf[1] = st->setupbyte;
985 tx_buf[2] = (st->monitor_speed << 1);
986
987 /*
988 * So we need to do yet another bit of nefarious scan mode
989 * setup to match what we need.
990 */
991 for (j = 0; j < 8; j++)
992 if (modemask & (1 << j)) {
993 /* Establish the mode is in the scan */
994 if (st->mask_low & (1 << j)) {
995 tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF;
996 tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0;
997 } else if (j < 4) {
998 tx_buf[i] = 0;
999 tx_buf[i + 1] = 0;
1000 } else {
1001 tx_buf[i] = 0x80;
1002 tx_buf[i + 1] = 0;
1003 }
1004 if (st->mask_high & (1 << j)) {
1005 tx_buf[i + 1] |=
1006 (st->thresh_high[j] >> 8) & 0x0F;
1007 tx_buf[i + 2] = st->thresh_high[j] & 0xFF;
1008 } else if (j < 4) {
1009 tx_buf[i + 1] |= 0x0F;
1010 tx_buf[i + 2] = 0xFF;
1011 } else {
1012 tx_buf[i + 1] |= 0x07;
1013 tx_buf[i + 2] = 0xFF;
1014 }
1015 i += 3;
1016 }
1017
1018
1019 ret = i2c_master_send(st->client, tx_buf, len);
1020 if (ret < 0)
1021 goto error_ret;
1022 if (ret != len) {
1023 ret = -EIO;
1024 goto error_ret;
1025 }
1026
1027 /*
1028 * Now that we hopefully have sensible thresholds in place it is
1029 * time to turn the interrupts on.
1030 * It is unclear from the data sheet if this should be necessary
1031 * (i.e. whether monitor mode setup is atomic) but it appears to
1032 * be in practice.
1033 */
1034 tx_buf[0] = st->setupbyte;
1035 tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0;
1036 ret = i2c_master_send(st->client, tx_buf, 2);
1037 if (ret < 0)
1038 goto error_ret;
1039 if (ret != 2) {
1040 ret = -EIO;
1041 goto error_ret;
1042 }
1043 ret = 0;
1044 st->monitor_on = true;
1045 error_ret:
1046
1047 kfree(tx_buf);
1048
1049 return ret;
1050 }
1051
1052 /*
1053 * To keep this manageable we always use one of 3 scan modes.
1054 * Scan 0...3, 0-1,2-3 and 1-0,3-2
1055 */
1056
1057 static inline int __max1363_check_event_mask(int thismask, int checkmask)
1058 {
1059 int ret = 0;
1060 /* Is it unipolar */
1061 if (thismask < 4) {
1062 if (checkmask & ~0x0F) {
1063 ret = -EBUSY;
1064 goto error_ret;
1065 }
1066 } else if (thismask < 6) {
1067 if (checkmask & ~0x30) {
1068 ret = -EBUSY;
1069 goto error_ret;
1070 }
1071 } else if (checkmask & ~0xC0)
1072 ret = -EBUSY;
1073 error_ret:
1074 return ret;
1075 }
1076
1077 static int max1363_write_event_config(struct iio_dev *indio_dev,
1078 int event_code,
1079 int state)
1080 {
1081 int ret = 0;
1082 struct max1363_state *st = iio_priv(indio_dev);
1083 u16 unifiedmask;
1084 int number = IIO_EVENT_CODE_EXTRACT_NUM(event_code);
1085
1086 mutex_lock(&indio_dev->mlock);
1087 unifiedmask = st->mask_low | st->mask_high;
1088 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING) {
1089
1090 if (state == 0)
1091 st->mask_low &= ~(1 << number);
1092 else {
1093 ret = __max1363_check_event_mask((1 << number),
1094 unifiedmask);
1095 if (ret)
1096 goto error_ret;
1097 st->mask_low |= (1 << number);
1098 }
1099 } else {
1100 if (state == 0)
1101 st->mask_high &= ~(1 << number);
1102 else {
1103 ret = __max1363_check_event_mask((1 << number),
1104 unifiedmask);
1105 if (ret)
1106 goto error_ret;
1107 st->mask_high |= (1 << number);
1108 }
1109 }
1110
1111 max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low));
1112 error_ret:
1113 mutex_unlock(&indio_dev->mlock);
1114
1115 return ret;
1116 }
1117
1118 /*
1119 * As with scan_elements, only certain sets of these can
1120 * be combined.
1121 */
1122 static struct attribute *max1363_event_attributes[] = {
1123 &iio_dev_attr_sampling_frequency.dev_attr.attr,
1124 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
1125 NULL,
1126 };
1127
1128 static struct attribute_group max1363_event_attribute_group = {
1129 .attrs = max1363_event_attributes,
1130 };
1131
1132 static int max1363_initial_setup(struct max1363_state *st)
1133 {
1134 st->setupbyte = MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD
1135 | MAX1363_SETUP_POWER_UP_INT_REF
1136 | MAX1363_SETUP_INT_CLOCK
1137 | MAX1363_SETUP_UNIPOLAR
1138 | MAX1363_SETUP_NORESET;
1139
1140 /* Set scan mode writes the config anyway so wait until then*/
1141 st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte);
1142 st->current_mode = &max1363_mode_table[st->chip_info->default_mode];
1143 st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte);
1144
1145 return max1363_set_scan_mode(st);
1146 }
1147
1148 static int __devinit max1363_probe(struct i2c_client *client,
1149 const struct i2c_device_id *id)
1150 {
1151 int ret, i, regdone = 0;
1152 struct max1363_state *st;
1153 struct iio_dev *indio_dev;
1154 struct regulator *reg;
1155
1156 reg = regulator_get(&client->dev, "vcc");
1157 if (!IS_ERR(reg)) {
1158 ret = regulator_enable(reg);
1159 if (ret)
1160 goto error_put_reg;
1161 }
1162
1163 indio_dev = iio_allocate_device(sizeof(struct max1363_state));
1164 if (indio_dev == NULL) {
1165 ret = -ENOMEM;
1166 goto error_disable_reg;
1167 }
1168 st = iio_priv(indio_dev);
1169 st->reg = reg;
1170 /* this is only used for device removal purposes */
1171 i2c_set_clientdata(client, indio_dev);
1172
1173 st->chip_info = &max1363_chip_info_tbl[id->driver_data];
1174 st->client = client;
1175
1176 indio_dev->available_scan_masks
1177 = kzalloc(sizeof(*indio_dev->available_scan_masks)*
1178 (st->chip_info->num_modes + 1), GFP_KERNEL);
1179 if (!indio_dev->available_scan_masks) {
1180 ret = -ENOMEM;
1181 goto error_free_device;
1182 }
1183
1184 for (i = 0; i < st->chip_info->num_modes; i++)
1185 indio_dev->available_scan_masks[i] =
1186 max1363_mode_table[st->chip_info->mode_list[i]]
1187 .modemask;
1188 /* Estabilish that the iio_dev is a child of the i2c device */
1189 indio_dev->dev.parent = &client->dev;
1190 indio_dev->attrs = &max1363_dev_attr_group;
1191 indio_dev->read_event_value = &max1363_read_thresh;
1192 indio_dev->write_event_value = &max1363_write_thresh;
1193 indio_dev->read_event_config = &max1363_read_event_config;
1194 indio_dev->write_event_config = &max1363_write_event_config;
1195 indio_dev->channels = st->chip_info->channels;
1196 indio_dev->num_channels = st->chip_info->num_channels;
1197 indio_dev->read_raw = &max1363_read_raw;
1198 /* Todo: this shouldn't be here. */
1199 indio_dev->driver_module = THIS_MODULE;
1200 indio_dev->modes = INDIO_DIRECT_MODE;
1201 if (st->chip_info->monitor_mode && client->irq) {
1202 indio_dev->num_interrupt_lines = 1;
1203 indio_dev->event_attrs
1204 = &max1363_event_attribute_group;
1205 }
1206
1207 ret = max1363_initial_setup(st);
1208 if (ret)
1209 goto error_free_available_scan_masks;
1210
1211 ret = max1363_register_ring_funcs_and_init(indio_dev);
1212 if (ret)
1213 goto error_free_available_scan_masks;
1214
1215 ret = iio_device_register(indio_dev);
1216 if (ret)
1217 goto error_cleanup_ring;
1218 regdone = 1;
1219 ret = iio_ring_buffer_register_ex(indio_dev->ring, 0,
1220 st->chip_info->channels,
1221 st->chip_info->num_channels);
1222 if (ret)
1223 goto error_cleanup_ring;
1224
1225 if (st->chip_info->monitor_mode && client->irq) {
1226 ret = request_threaded_irq(st->client->irq,
1227 NULL,
1228 &max1363_event_handler,
1229 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1230 "max1363_event",
1231 indio_dev);
1232
1233 if (ret)
1234 goto error_uninit_ring;
1235 }
1236
1237 return 0;
1238 error_uninit_ring:
1239 iio_ring_buffer_unregister(indio_dev->ring);
1240 error_cleanup_ring:
1241 max1363_ring_cleanup(indio_dev);
1242 error_free_available_scan_masks:
1243 kfree(indio_dev->available_scan_masks);
1244 error_free_device:
1245 if (!regdone)
1246 iio_free_device(indio_dev);
1247 else
1248 iio_device_unregister(indio_dev);
1249 error_disable_reg:
1250 if (!IS_ERR(st->reg))
1251 regulator_disable(st->reg);
1252 error_put_reg:
1253 if (!IS_ERR(st->reg))
1254 regulator_put(st->reg);
1255
1256 return ret;
1257 }
1258
1259 static int max1363_remove(struct i2c_client *client)
1260 {
1261 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1262 struct max1363_state *st = iio_priv(indio_dev);
1263 struct regulator *reg = st->reg;
1264
1265 if (st->chip_info->monitor_mode && client->irq)
1266 free_irq(st->client->irq, indio_dev);
1267 iio_ring_buffer_unregister(indio_dev->ring);
1268 max1363_ring_cleanup(indio_dev);
1269 kfree(indio_dev->available_scan_masks);
1270 if (!IS_ERR(reg)) {
1271 regulator_disable(reg);
1272 regulator_put(reg);
1273 }
1274 iio_device_unregister(indio_dev);
1275
1276 return 0;
1277 }
1278
1279 static const struct i2c_device_id max1363_id[] = {
1280 { "max1361", max1361 },
1281 { "max1362", max1362 },
1282 { "max1363", max1363 },
1283 { "max1364", max1364 },
1284 { "max1036", max1036 },
1285 { "max1037", max1037 },
1286 { "max1038", max1038 },
1287 { "max1039", max1039 },
1288 { "max1136", max1136 },
1289 { "max1137", max1137 },
1290 { "max1138", max1138 },
1291 { "max1139", max1139 },
1292 { "max1236", max1236 },
1293 { "max1237", max1237 },
1294 { "max1238", max1238 },
1295 { "max1239", max1239 },
1296 { "max11600", max11600 },
1297 { "max11601", max11601 },
1298 { "max11602", max11602 },
1299 { "max11603", max11603 },
1300 { "max11604", max11604 },
1301 { "max11605", max11605 },
1302 { "max11606", max11606 },
1303 { "max11607", max11607 },
1304 { "max11608", max11608 },
1305 { "max11609", max11609 },
1306 { "max11610", max11610 },
1307 { "max11611", max11611 },
1308 { "max11612", max11612 },
1309 { "max11613", max11613 },
1310 { "max11614", max11614 },
1311 { "max11615", max11615 },
1312 { "max11616", max11616 },
1313 { "max11617", max11617 },
1314 {}
1315 };
1316
1317 MODULE_DEVICE_TABLE(i2c, max1363_id);
1318
1319 static struct i2c_driver max1363_driver = {
1320 .driver = {
1321 .name = "max1363",
1322 },
1323 .probe = max1363_probe,
1324 .remove = max1363_remove,
1325 .id_table = max1363_id,
1326 };
1327
1328 static __init int max1363_init(void)
1329 {
1330 return i2c_add_driver(&max1363_driver);
1331 }
1332
1333 static __exit void max1363_exit(void)
1334 {
1335 i2c_del_driver(&max1363_driver);
1336 }
1337
1338 MODULE_AUTHOR("Jonathan Cameron <jic23@cam.ac.uk>");
1339 MODULE_DESCRIPTION("Maxim 1363 ADC");
1340 MODULE_LICENSE("GPL v2");
1341
1342 module_init(max1363_init);
1343 module_exit(max1363_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree