drivers/net/wireless/b43/b43.h

   1 #ifndef B43_H_
   2 #define B43_H_
   3
   4 #include <linux/kernel.h>
   5 #include <linux/spinlock.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/hw_random.h>
   8 #include <linux/ssb/ssb.h>
   9 #include <net/mac80211.h>
  10
  11 #include "debugfs.h"
  12 #include "leds.h"
  13 #include "rfkill.h"
  14 #include "lo.h"
  15 #include "phy_common.h"
  16
  17
  18 /* The unique identifier of the firmware that's officially supported by
  19  * this driver version. */
  20 #define B43_SUPPORTED_FIRMWARE_ID       "FW13"
  21
  22
  23 #ifdef CONFIG_B43_DEBUG
  24 # define B43_DEBUG      1
  25 #else
  26 # define B43_DEBUG      0
  27 #endif
  28
  29 #define B43_RX_MAX_SSI                  60
  30
  31 /* MMIO offsets */
  32 #define B43_MMIO_DMA0_REASON            0x20
  33 #define B43_MMIO_DMA0_IRQ_MASK          0x24
  34 #define B43_MMIO_DMA1_REASON            0x28
  35 #define B43_MMIO_DMA1_IRQ_MASK          0x2C
  36 #define B43_MMIO_DMA2_REASON            0x30
  37 #define B43_MMIO_DMA2_IRQ_MASK          0x34
  38 #define B43_MMIO_DMA3_REASON            0x38
  39 #define B43_MMIO_DMA3_IRQ_MASK          0x3C
  40 #define B43_MMIO_DMA4_REASON            0x40
  41 #define B43_MMIO_DMA4_IRQ_MASK          0x44
  42 #define B43_MMIO_DMA5_REASON            0x48
  43 #define B43_MMIO_DMA5_IRQ_MASK          0x4C
  44 #define B43_MMIO_MACCTL                 0x120   /* MAC control */
  45 #define B43_MMIO_MACCMD                 0x124   /* MAC command */
  46 #define B43_MMIO_GEN_IRQ_REASON         0x128
  47 #define B43_MMIO_GEN_IRQ_MASK           0x12C
  48 #define B43_MMIO_RAM_CONTROL            0x130
  49 #define B43_MMIO_RAM_DATA               0x134
  50 #define B43_MMIO_PS_STATUS              0x140
  51 #define B43_MMIO_RADIO_HWENABLED_HI     0x158
  52 #define B43_MMIO_SHM_CONTROL            0x160
  53 #define B43_MMIO_SHM_DATA               0x164
  54 #define B43_MMIO_SHM_DATA_UNALIGNED     0x166
  55 #define B43_MMIO_XMITSTAT_0             0x170
  56 #define B43_MMIO_XMITSTAT_1             0x174
  57 #define B43_MMIO_REV3PLUS_TSF_LOW       0x180   /* core rev >= 3 only */
  58 #define B43_MMIO_REV3PLUS_TSF_HIGH      0x184   /* core rev >= 3 only */
  59 #define B43_MMIO_TSF_CFP_REP            0x188
  60 #define B43_MMIO_TSF_CFP_START          0x18C
  61 #define B43_MMIO_TSF_CFP_MAXDUR         0x190
  62
  63 /* 32-bit DMA */
  64 #define B43_MMIO_DMA32_BASE0            0x200
  65 #define B43_MMIO_DMA32_BASE1            0x220
  66 #define B43_MMIO_DMA32_BASE2            0x240
  67 #define B43_MMIO_DMA32_BASE3            0x260
  68 #define B43_MMIO_DMA32_BASE4            0x280
  69 #define B43_MMIO_DMA32_BASE5            0x2A0
  70 /* 64-bit DMA */
  71 #define B43_MMIO_DMA64_BASE0            0x200
  72 #define B43_MMIO_DMA64_BASE1            0x240
  73 #define B43_MMIO_DMA64_BASE2            0x280
  74 #define B43_MMIO_DMA64_BASE3            0x2C0
  75 #define B43_MMIO_DMA64_BASE4            0x300
  76 #define B43_MMIO_DMA64_BASE5            0x340
  77
  78 /* PIO on core rev < 11 */
  79 #define B43_MMIO_PIO_BASE0              0x300
  80 #define B43_MMIO_PIO_BASE1              0x310
  81 #define B43_MMIO_PIO_BASE2              0x320
  82 #define B43_MMIO_PIO_BASE3              0x330
  83 #define B43_MMIO_PIO_BASE4              0x340
  84 #define B43_MMIO_PIO_BASE5              0x350
  85 #define B43_MMIO_PIO_BASE6              0x360
  86 #define B43_MMIO_PIO_BASE7              0x370
  87 /* PIO on core rev >= 11 */
  88 #define B43_MMIO_PIO11_BASE0            0x200
  89 #define B43_MMIO_PIO11_BASE1            0x240
  90 #define B43_MMIO_PIO11_BASE2            0x280
  91 #define B43_MMIO_PIO11_BASE3            0x2C0
  92 #define B43_MMIO_PIO11_BASE4            0x300
  93 #define B43_MMIO_PIO11_BASE5            0x340
  94
  95 #define B43_MMIO_PHY_VER                0x3E0
  96 #define B43_MMIO_PHY_RADIO              0x3E2
  97 #define B43_MMIO_PHY0                   0x3E6
  98 #define B43_MMIO_ANTENNA                0x3E8
  99 #define B43_MMIO_CHANNEL                0x3F0
 100 #define B43_MMIO_CHANNEL_EXT            0x3F4
 101 #define B43_MMIO_RADIO_CONTROL          0x3F6
 102 #define B43_MMIO_RADIO_DATA_HIGH        0x3F8
 103 #define B43_MMIO_RADIO_DATA_LOW         0x3FA
 104 #define B43_MMIO_PHY_CONTROL            0x3FC
 105 #define B43_MMIO_PHY_DATA               0x3FE
 106 #define B43_MMIO_MACFILTER_CONTROL      0x420
 107 #define B43_MMIO_MACFILTER_DATA         0x422
 108 #define B43_MMIO_RCMTA_COUNT            0x43C
 109 #define B43_MMIO_RADIO_HWENABLED_LO     0x49A
 110 #define B43_MMIO_GPIO_CONTROL           0x49C
 111 #define B43_MMIO_GPIO_MASK              0x49E
 112 #define B43_MMIO_TSF_CFP_START_LOW      0x604
 113 #define B43_MMIO_TSF_CFP_START_HIGH     0x606
 114 #define B43_MMIO_TSF_CFP_PRETBTT        0x612
 115 #define B43_MMIO_TSF_0                  0x632   /* core rev < 3 only */
 116 #define B43_MMIO_TSF_1                  0x634   /* core rev < 3 only */
 117 #define B43_MMIO_TSF_2                  0x636   /* core rev < 3 only */
 118 #define B43_MMIO_TSF_3                  0x638   /* core rev < 3 only */
 119 #define B43_MMIO_RNG                    0x65A
 120 #define B43_MMIO_IFSCTL                 0x688 /* Interframe space control */
 121 #define  B43_MMIO_IFSCTL_USE_EDCF       0x0004
 122 #define B43_MMIO_POWERUP_DELAY          0x6A8
 123
 124 /* SPROM boardflags_lo values */
 125 #define B43_BFL_BTCOEXIST               0x0001  /* implements Bluetooth coexistance */
 126 #define B43_BFL_PACTRL                  0x0002  /* GPIO 9 controlling the PA */
 127 #define B43_BFL_AIRLINEMODE             0x0004  /* implements GPIO 13 radio disable indication */
 128 #define B43_BFL_RSSI                    0x0008  /* software calculates nrssi slope. */
 129 #define B43_BFL_ENETSPI                 0x0010  /* has ephy roboswitch spi */
 130 #define B43_BFL_XTAL_NOSLOW             0x0020  /* no slow clock available */
 131 #define B43_BFL_CCKHIPWR                0x0040  /* can do high power CCK transmission */
 132 #define B43_BFL_ENETADM                 0x0080  /* has ADMtek switch */
 133 #define B43_BFL_ENETVLAN                0x0100  /* can do vlan */
 134 #define B43_BFL_AFTERBURNER             0x0200  /* supports Afterburner mode */
 135 #define B43_BFL_NOPCI                   0x0400  /* leaves PCI floating */
 136 #define B43_BFL_FEM                     0x0800  /* supports the Front End Module */
 137 #define B43_BFL_EXTLNA                  0x1000  /* has an external LNA */
 138 #define B43_BFL_HGPA                    0x2000  /* had high gain PA */
 139 #define B43_BFL_BTCMOD                  0x4000  /* BFL_BTCOEXIST is given in alternate GPIOs */
 140 #define B43_BFL_ALTIQ                   0x8000  /* alternate I/Q settings */
 141
 142 /* GPIO register offset, in both ChipCommon and PCI core. */
 143 #define B43_GPIO_CONTROL                0x6c
 144
 145 /* SHM Routing */
 146 enum {
 147         B43_SHM_UCODE,          /* Microcode memory */
 148         B43_SHM_SHARED,         /* Shared memory */
 149         B43_SHM_SCRATCH,        /* Scratch memory */
 150         B43_SHM_HW,             /* Internal hardware register */
 151         B43_SHM_RCMTA,          /* Receive match transmitter address (rev >= 5 only) */
 152 };
 153 /* SHM Routing modifiers */
 154 #define B43_SHM_AUTOINC_R               0x0200  /* Auto-increment address on read */
 155 #define B43_SHM_AUTOINC_W               0x0100  /* Auto-increment address on write */
 156 #define B43_SHM_AUTOINC_RW              (B43_SHM_AUTOINC_R | \
 157                                          B43_SHM_AUTOINC_W)
 158
 159 /* Misc SHM_SHARED offsets */
 160 #define B43_SHM_SH_WLCOREREV            0x0016  /* 802.11 core revision */
 161 #define B43_SHM_SH_PCTLWDPOS            0x0008
 162 #define B43_SHM_SH_RXPADOFF             0x0034  /* RX Padding data offset (PIO only) */
 163 #define B43_SHM_SH_PHYVER               0x0050  /* PHY version */
 164 #define B43_SHM_SH_PHYTYPE              0x0052  /* PHY type */
 165 #define B43_SHM_SH_ANTSWAP              0x005C  /* Antenna swap threshold */
 166 #define B43_SHM_SH_HOSTFLO              0x005E  /* Hostflags for ucode options (low) */
 167 #define B43_SHM_SH_HOSTFMI              0x0060  /* Hostflags for ucode options (middle) */
 168 #define B43_SHM_SH_HOSTFHI              0x0062  /* Hostflags for ucode options (high) */
 169 #define B43_SHM_SH_RFATT                0x0064  /* Current radio attenuation value */
 170 #define B43_SHM_SH_RADAR                0x0066  /* Radar register */
 171 #define B43_SHM_SH_PHYTXNOI             0x006E  /* PHY noise directly after TX (lower 8bit only) */
 172 #define B43_SHM_SH_RFRXSP1              0x0072  /* RF RX SP Register 1 */
 173 #define B43_SHM_SH_CHAN                 0x00A0  /* Current channel (low 8bit only) */
 174 #define  B43_SHM_SH_CHAN_5GHZ           0x0100  /* Bit set, if 5Ghz channel */
 175 #define B43_SHM_SH_BCMCFIFOID           0x0108  /* Last posted cookie to the bcast/mcast FIFO */
 176 /* TSSI information */
 177 #define B43_SHM_SH_TSSI_CCK             0x0058  /* TSSI for last 4 CCK frames (32bit) */
 178 #define B43_SHM_SH_TSSI_OFDM_A          0x0068  /* TSSI for last 4 OFDM frames (32bit) */
 179 #define B43_SHM_SH_TSSI_OFDM_G          0x0070  /* TSSI for last 4 OFDM frames (32bit) */
 180 #define  B43_TSSI_MAX                   0x7F    /* Max value for one TSSI value */
 181 /* SHM_SHARED TX FIFO variables */
 182 #define B43_SHM_SH_SIZE01               0x0098  /* TX FIFO size for FIFO 0 (low) and 1 (high) */
 183 #define B43_SHM_SH_SIZE23               0x009A  /* TX FIFO size for FIFO 2 and 3 */
 184 #define B43_SHM_SH_SIZE45               0x009C  /* TX FIFO size for FIFO 4 and 5 */
 185 #define B43_SHM_SH_SIZE67               0x009E  /* TX FIFO size for FIFO 6 and 7 */
 186 /* SHM_SHARED background noise */
 187 #define B43_SHM_SH_JSSI0                0x0088  /* Measure JSSI 0 */
 188 #define B43_SHM_SH_JSSI1                0x008A  /* Measure JSSI 1 */
 189 #define B43_SHM_SH_JSSIAUX              0x008C  /* Measure JSSI AUX */
 190 /* SHM_SHARED crypto engine */
 191 #define B43_SHM_SH_DEFAULTIV            0x003C  /* Default IV location */
 192 #define B43_SHM_SH_NRRXTRANS            0x003E  /* # of soft RX transmitter addresses (max 8) */
 193 #define B43_SHM_SH_KTP                  0x0056  /* Key table pointer */
 194 #define B43_SHM_SH_TKIPTSCTTAK          0x0318
 195 #define B43_SHM_SH_KEYIDXBLOCK          0x05D4  /* Key index/algorithm block (v4 firmware) */
 196 #define B43_SHM_SH_PSM                  0x05F4  /* PSM transmitter address match block (rev < 5) */
 197 /* SHM_SHARED WME variables */
 198 #define B43_SHM_SH_EDCFSTAT             0x000E  /* EDCF status */
 199 #define B43_SHM_SH_TXFCUR               0x0030  /* TXF current index */
 200 #define B43_SHM_SH_EDCFQ                0x0240  /* EDCF Q info */
 201 /* SHM_SHARED powersave mode related */
 202 #define B43_SHM_SH_SLOTT                0x0010  /* Slot time */
 203 #define B43_SHM_SH_DTIMPER              0x0012  /* DTIM period */
 204 #define B43_SHM_SH_NOSLPZNATDTIM        0x004C  /* NOSLPZNAT DTIM */
 205 /* SHM_SHARED beacon/AP variables */
 206 #define B43_SHM_SH_BTL0                 0x0018  /* Beacon template length 0 */
 207 #define B43_SHM_SH_BTL1                 0x001A  /* Beacon template length 1 */
 208 #define B43_SHM_SH_BTSFOFF              0x001C  /* Beacon TSF offset */
 209 #define B43_SHM_SH_TIMBPOS              0x001E  /* TIM B position in beacon */
 210 #define B43_SHM_SH_DTIMP                0x0012  /* DTIP period */
 211 #define B43_SHM_SH_MCASTCOOKIE          0x00A8  /* Last bcast/mcast frame ID */
 212 #define B43_SHM_SH_SFFBLIM              0x0044  /* Short frame fallback retry limit */
 213 #define B43_SHM_SH_LFFBLIM              0x0046  /* Long frame fallback retry limit */
 214 #define B43_SHM_SH_BEACPHYCTL           0x0054  /* Beacon PHY TX control word (see PHY TX control) */
 215 #define B43_SHM_SH_EXTNPHYCTL           0x00B0  /* Extended bytes for beacon PHY control (N) */
 216 /* SHM_SHARED ACK/CTS control */
 217 #define B43_SHM_SH_ACKCTSPHYCTL         0x0022  /* ACK/CTS PHY control word (see PHY TX control) */
 218 /* SHM_SHARED probe response variables */
 219 #define B43_SHM_SH_PRSSID               0x0160  /* Probe Response SSID */
 220 #define B43_SHM_SH_PRSSIDLEN            0x0048  /* Probe Response SSID length */
 221 #define B43_SHM_SH_PRTLEN               0x004A  /* Probe Response template length */
 222 #define B43_SHM_SH_PRMAXTIME            0x0074  /* Probe Response max time */
 223 #define B43_SHM_SH_PRPHYCTL             0x0188  /* Probe Response PHY TX control word */
 224 /* SHM_SHARED rate tables */
 225 #define B43_SHM_SH_OFDMDIRECT           0x01C0  /* Pointer to OFDM direct map */
 226 #define B43_SHM_SH_OFDMBASIC            0x01E0  /* Pointer to OFDM basic rate map */
 227 #define B43_SHM_SH_CCKDIRECT            0x0200  /* Pointer to CCK direct map */
 228 #define B43_SHM_SH_CCKBASIC             0x0220  /* Pointer to CCK basic rate map */
 229 /* SHM_SHARED microcode soft registers */
 230 #define B43_SHM_SH_UCODEREV             0x0000  /* Microcode revision */
 231 #define B43_SHM_SH_UCODEPATCH           0x0002  /* Microcode patchlevel */
 232 #define B43_SHM_SH_UCODEDATE            0x0004  /* Microcode date */
 233 #define B43_SHM_SH_UCODETIME            0x0006  /* Microcode time */
 234 #define B43_SHM_SH_UCODESTAT            0x0040  /* Microcode debug status code */
 235 #define  B43_SHM_SH_UCODESTAT_INVALID   0
 236 #define  B43_SHM_SH_UCODESTAT_INIT      1
 237 #define  B43_SHM_SH_UCODESTAT_ACTIVE    2
 238 #define  B43_SHM_SH_UCODESTAT_SUSP      3       /* suspended */
 239 #define  B43_SHM_SH_UCODESTAT_SLEEP     4       /* asleep (PS) */
 240 #define B43_SHM_SH_MAXBFRAMES           0x0080  /* Maximum number of frames in a burst */
 241 #define B43_SHM_SH_SPUWKUP              0x0094  /* pre-wakeup for synth PU in us */
 242 #define B43_SHM_SH_PRETBTT              0x0096  /* pre-TBTT in us */
 243
 244 /* SHM_SCRATCH offsets */
 245 #define B43_SHM_SC_MINCONT              0x0003  /* Minimum contention window */
 246 #define B43_SHM_SC_MAXCONT              0x0004  /* Maximum contention window */
 247 #define B43_SHM_SC_CURCONT              0x0005  /* Current contention window */
 248 #define B43_SHM_SC_SRLIMIT              0x0006  /* Short retry count limit */
 249 #define B43_SHM_SC_LRLIMIT              0x0007  /* Long retry count limit */
 250 #define B43_SHM_SC_DTIMC                0x0008  /* Current DTIM count */
 251 #define B43_SHM_SC_BTL0LEN              0x0015  /* Beacon 0 template length */
 252 #define B43_SHM_SC_BTL1LEN              0x0016  /* Beacon 1 template length */
 253 #define B43_SHM_SC_SCFB                 0x0017  /* Short frame transmit count threshold for rate fallback */
 254 #define B43_SHM_SC_LCFB                 0x0018  /* Long frame transmit count threshold for rate fallback */
 255
 256 /* Hardware Radio Enable masks */
 257 #define B43_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
 258 #define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
 259
 260 /* HostFlags. See b43_hf_read/write() */
 261 #define B43_HF_ANTDIVHELP       0x000000000001ULL /* ucode antenna div helper */
 262 #define B43_HF_SYMW             0x000000000002ULL /* G-PHY SYM workaround */
 263 #define B43_HF_RXPULLW          0x000000000004ULL /* RX pullup workaround */
 264 #define B43_HF_CCKBOOST         0x000000000008ULL /* 4dB CCK power boost (exclusive with OFDM boost) */
 265 #define B43_HF_BTCOEX           0x000000000010ULL /* Bluetooth coexistance */
 266 #define B43_HF_GDCW             0x000000000020ULL /* G-PHY DC canceller filter bw workaround */
 267 #define B43_HF_OFDMPABOOST      0x000000000040ULL /* Enable PA gain boost for OFDM */
 268 #define B43_HF_ACPR             0x000000000080ULL /* Disable for Japan, channel 14 */
 269 #define B43_HF_EDCF             0x000000000100ULL /* on if WME and MAC suspended */
 270 #define B43_HF_TSSIRPSMW        0x000000000200ULL /* TSSI reset PSM ucode workaround */
 271 #define B43_HF_20IN40IQW        0x000000000200ULL /* 20 in 40 MHz I/Q workaround (rev >= 13 only) */
 272 #define B43_HF_DSCRQ            0x000000000400ULL /* Disable slow clock request in ucode */
 273 #define B43_HF_ACIW             0x000000000800ULL /* ACI workaround: shift bits by 2 on PHY CRS */
 274 #define B43_HF_2060W            0x000000001000ULL /* 2060 radio workaround */
 275 #define B43_HF_RADARW           0x000000002000ULL /* Radar workaround */
 276 #define B43_HF_USEDEFKEYS       0x000000004000ULL /* Enable use of default keys */
 277 #define B43_HF_AFTERBURNER      0x000000008000ULL /* Afterburner enabled */
 278 #define B43_HF_BT4PRIOCOEX      0x000000010000ULL /* Bluetooth 4-priority coexistance */
 279 #define B43_HF_FWKUP            0x000000020000ULL /* Fast wake-up ucode */
 280 #define B43_HF_VCORECALC        0x000000040000ULL /* Force VCO recalculation when powering up synthpu */
 281 #define B43_HF_PCISCW           0x000000080000ULL /* PCI slow clock workaround */
 282 #define B43_HF_4318TSSI         0x000000200000ULL /* 4318 TSSI */
 283 #define B43_HF_FBCMCFIFO        0x000000400000ULL /* Flush bcast/mcast FIFO immediately */
 284 #define B43_HF_HWPCTL           0x000000800000ULL /* Enable hardwarre power control */
 285 #define B43_HF_BTCOEXALT        0x000001000000ULL /* Bluetooth coexistance in alternate pins */
 286 #define B43_HF_TXBTCHECK        0x000002000000ULL /* Bluetooth check during transmission */
 287 #define B43_HF_SKCFPUP          0x000004000000ULL /* Skip CFP update */
 288 #define B43_HF_N40W             0x000008000000ULL /* N PHY 40 MHz workaround (rev >= 13 only) */
 289 #define B43_HF_ANTSEL           0x000020000000ULL /* Antenna selection (for testing antenna div.) */
 290 #define B43_HF_BT3COEXT         0x000020000000ULL /* Bluetooth 3-wire coexistence (rev >= 13 only) */
 291 #define B43_HF_BTCANT           0x000040000000ULL /* Bluetooth coexistence (antenna mode) (rev >= 13 only) */
 292 #define B43_HF_ANTSELEN         0x000100000000ULL /* Antenna selection enabled (rev >= 13 only) */
 293 #define B43_HF_ANTSELMODE       0x000200000000ULL /* Antenna selection mode (rev >= 13 only) */
 294 #define B43_HF_MLADVW           0x001000000000ULL /* N PHY ML ADV workaround (rev >= 13 only) */
 295 #define B43_HF_PR45960W         0x080000000000ULL /* PR 45960 workaround (rev >= 13 only) */
 296
 297 /* MacFilter offsets. */
 298 #define B43_MACFILTER_SELF              0x0000
 299 #define B43_MACFILTER_BSSID             0x0003
 300
 301 /* PowerControl */
 302 #define B43_PCTL_IN                     0xB0
 303 #define B43_PCTL_OUT                    0xB4
 304 #define B43_PCTL_OUTENABLE              0xB8
 305 #define B43_PCTL_XTAL_POWERUP           0x40
 306 #define B43_PCTL_PLL_POWERDOWN          0x80
 307
 308 /* PowerControl Clock Modes */
 309 #define B43_PCTL_CLK_FAST               0x00
 310 #define B43_PCTL_CLK_SLOW               0x01
 311 #define B43_PCTL_CLK_DYNAMIC            0x02
 312
 313 #define B43_PCTL_FORCE_SLOW             0x0800
 314 #define B43_PCTL_FORCE_PLL              0x1000
 315 #define B43_PCTL_DYN_XTAL               0x2000
 316
 317 /* PHYVersioning */
 318 #define B43_PHYTYPE_A                   0x00
 319 #define B43_PHYTYPE_B                   0x01
 320 #define B43_PHYTYPE_G                   0x02
 321 #define B43_PHYTYPE_N                   0x04
 322 #define B43_PHYTYPE_LP                  0x05
 323
 324 /* PHYRegisters */
 325 #define B43_PHY_ILT_A_CTRL              0x0072
 326 #define B43_PHY_ILT_A_DATA1             0x0073
 327 #define B43_PHY_ILT_A_DATA2             0x0074
 328 #define B43_PHY_G_LO_CONTROL            0x0810
 329 #define B43_PHY_ILT_G_CTRL              0x0472
 330 #define B43_PHY_ILT_G_DATA1             0x0473
 331 #define B43_PHY_ILT_G_DATA2             0x0474
 332 #define B43_PHY_A_PCTL                  0x007B
 333 #define B43_PHY_G_PCTL                  0x0029
 334 #define B43_PHY_A_CRS                   0x0029
 335 #define B43_PHY_RADIO_BITFIELD          0x0401
 336 #define B43_PHY_G_CRS                   0x0429
 337 #define B43_PHY_NRSSILT_CTRL            0x0803
 338 #define B43_PHY_NRSSILT_DATA            0x0804
 339
 340 /* RadioRegisters */
 341 #define B43_RADIOCTL_ID                 0x01
 342
 343 /* MAC Control bitfield */
 344 #define B43_MACCTL_ENABLED              0x00000001      /* MAC Enabled */
 345 #define B43_MACCTL_PSM_RUN              0x00000002      /* Run Microcode */
 346 #define B43_MACCTL_PSM_JMP0             0x00000004      /* Microcode jump to 0 */
 347 #define B43_MACCTL_SHM_ENABLED          0x00000100      /* SHM Enabled */
 348 #define B43_MACCTL_SHM_UPPER            0x00000200      /* SHM Upper */
 349 #define B43_MACCTL_IHR_ENABLED          0x00000400      /* IHR Region Enabled */
 350 #define B43_MACCTL_PSM_DBG              0x00002000      /* Microcode debugging enabled */
 351 #define B43_MACCTL_GPOUTSMSK            0x0000C000      /* GPOUT Select Mask */
 352 #define B43_MACCTL_BE                   0x00010000      /* Big Endian mode */
 353 #define B43_MACCTL_INFRA                0x00020000      /* Infrastructure mode */
 354 #define B43_MACCTL_AP                   0x00040000      /* AccessPoint mode */
 355 #define B43_MACCTL_RADIOLOCK            0x00080000      /* Radio lock */
 356 #define B43_MACCTL_BEACPROMISC          0x00100000      /* Beacon Promiscuous */
 357 #define B43_MACCTL_KEEP_BADPLCP         0x00200000      /* Keep frames with bad PLCP */
 358 #define B43_MACCTL_KEEP_CTL             0x00400000      /* Keep control frames */
 359 #define B43_MACCTL_KEEP_BAD             0x00800000      /* Keep bad frames (FCS) */
 360 #define B43_MACCTL_PROMISC              0x01000000      /* Promiscuous mode */
 361 #define B43_MACCTL_HWPS                 0x02000000      /* Hardware Power Saving */
 362 #define B43_MACCTL_AWAKE                0x04000000      /* Device is awake */
 363 #define B43_MACCTL_CLOSEDNET            0x08000000      /* Closed net (no SSID bcast) */
 364 #define B43_MACCTL_TBTTHOLD             0x10000000      /* TBTT Hold */
 365 #define B43_MACCTL_DISCTXSTAT           0x20000000      /* Discard TX status */
 366 #define B43_MACCTL_DISCPMQ              0x40000000      /* Discard Power Management Queue */
 367 #define B43_MACCTL_GMODE                0x80000000      /* G Mode */
 368
 369 /* MAC Command bitfield */
 370 #define B43_MACCMD_BEACON0_VALID        0x00000001      /* Beacon 0 in template RAM is busy/valid */
 371 #define B43_MACCMD_BEACON1_VALID        0x00000002      /* Beacon 1 in template RAM is busy/valid */
 372 #define B43_MACCMD_DFQ_VALID            0x00000004      /* Directed frame queue valid (IBSS PS mode, ATIM) */
 373 #define B43_MACCMD_CCA                  0x00000008      /* Clear channel assessment */
 374 #define B43_MACCMD_BGNOISE              0x00000010      /* Background noise */
 375
 376 /* 802.11 core specific TM State Low (SSB_TMSLOW) flags */
 377 #define B43_TMSLOW_GMODE                0x20000000      /* G Mode Enable */
 378 #define B43_TMSLOW_PHYCLKSPEED          0x00C00000      /* PHY clock speed mask (N-PHY only) */
 379 #define  B43_TMSLOW_PHYCLKSPEED_40MHZ   0x00000000      /* 40 MHz PHY */
 380 #define  B43_TMSLOW_PHYCLKSPEED_80MHZ   0x00400000      /* 80 MHz PHY */
 381 #define  B43_TMSLOW_PHYCLKSPEED_160MHZ  0x00800000      /* 160 MHz PHY */
 382 #define B43_TMSLOW_PLLREFSEL            0x00200000      /* PLL Frequency Reference Select (rev >= 5) */
 383 #define B43_TMSLOW_MACPHYCLKEN          0x00100000      /* MAC PHY Clock Control Enable (rev >= 5) */
 384 #define B43_TMSLOW_PHYRESET             0x00080000      /* PHY Reset */
 385 #define B43_TMSLOW_PHYCLKEN             0x00040000      /* PHY Clock Enable */
 386
 387 /* 802.11 core specific TM State High (SSB_TMSHIGH) flags */
 388 #define B43_TMSHIGH_DUALBAND_PHY        0x00080000      /* Dualband PHY available */
 389 #define B43_TMSHIGH_FCLOCK              0x00040000      /* Fast Clock Available (rev >= 5) */
 390 #define B43_TMSHIGH_HAVE_5GHZ_PHY       0x00020000      /* 5 GHz PHY available (rev >= 5) */
 391 #define B43_TMSHIGH_HAVE_2GHZ_PHY       0x00010000      /* 2.4 GHz PHY available (rev >= 5) */
 392
 393 /* Generic-Interrupt reasons. */
 394 #define B43_IRQ_MAC_SUSPENDED           0x00000001
 395 #define B43_IRQ_BEACON                  0x00000002
 396 #define B43_IRQ_TBTT_INDI               0x00000004
 397 #define B43_IRQ_BEACON_TX_OK            0x00000008
 398 #define B43_IRQ_BEACON_CANCEL           0x00000010
 399 #define B43_IRQ_ATIM_END                0x00000020
 400 #define B43_IRQ_PMQ                     0x00000040
 401 #define B43_IRQ_PIO_WORKAROUND          0x00000100
 402 #define B43_IRQ_MAC_TXERR               0x00000200
 403 #define B43_IRQ_PHY_TXERR               0x00000800
 404 #define B43_IRQ_PMEVENT                 0x00001000
 405 #define B43_IRQ_TIMER0                  0x00002000
 406 #define B43_IRQ_TIMER1                  0x00004000
 407 #define B43_IRQ_DMA                     0x00008000
 408 #define B43_IRQ_TXFIFO_FLUSH_OK         0x00010000
 409 #define B43_IRQ_CCA_MEASURE_OK          0x00020000
 410 #define B43_IRQ_NOISESAMPLE_OK          0x00040000
 411 #define B43_IRQ_UCODE_DEBUG             0x08000000
 412 #define B43_IRQ_RFKILL                  0x10000000
 413 #define B43_IRQ_TX_OK                   0x20000000
 414 #define B43_IRQ_PHY_G_CHANGED           0x40000000
 415 #define B43_IRQ_TIMEOUT                 0x80000000
 416
 417 #define B43_IRQ_ALL                     0xFFFFFFFF
 418 #define B43_IRQ_MASKTEMPLATE            (B43_IRQ_TBTT_INDI | \
 419                                          B43_IRQ_ATIM_END | \
 420                                          B43_IRQ_PMQ | \
 421                                          B43_IRQ_MAC_TXERR | \
 422                                          B43_IRQ_PHY_TXERR | \
 423                                          B43_IRQ_DMA | \
 424                                          B43_IRQ_TXFIFO_FLUSH_OK | \
 425                                          B43_IRQ_NOISESAMPLE_OK | \
 426                                          B43_IRQ_UCODE_DEBUG | \
 427                                          B43_IRQ_RFKILL | \
 428                                          B43_IRQ_TX_OK)
 429
 430 /* The firmware register to fetch the debug-IRQ reason from. */
 431 #define B43_DEBUGIRQ_REASON_REG         63
 432 /* Debug-IRQ reasons. */
 433 #define B43_DEBUGIRQ_PANIC              0       /* The firmware panic'ed */
 434 #define B43_DEBUGIRQ_DUMP_SHM           1       /* Dump shared SHM */
 435 #define B43_DEBUGIRQ_DUMP_REGS          2       /* Dump the microcode registers */
 436 #define B43_DEBUGIRQ_MARKER             3       /* A "marker" was thrown by the firmware. */
 437 #define B43_DEBUGIRQ_ACK                0xFFFF  /* The host writes that to ACK the IRQ */
 438
 439 /* The firmware register that contains the "marker" line. */
 440 #define B43_MARKER_ID_REG               2
 441 #define B43_MARKER_LINE_REG             3
 442
 443 /* The firmware register to fetch the panic reason from. */
 444 #define B43_FWPANIC_REASON_REG          3
 445 /* Firmware panic reason codes */
 446 #define B43_FWPANIC_DIE                 0 /* Firmware died. Don't auto-restart it. */
 447 #define B43_FWPANIC_RESTART             1 /* Firmware died. Schedule a controller reset. */
 448
 449 /* The firmware register that contains the watchdog counter. */
 450 #define B43_WATCHDOG_REG                1
 451
 452 /* Device specific rate values.
 453  * The actual values defined here are (rate_in_mbps * 2).
 454  * Some code depends on this. Don't change it. */
 455 #define B43_CCK_RATE_1MB                0x02
 456 #define B43_CCK_RATE_2MB                0x04
 457 #define B43_CCK_RATE_5MB                0x0B
 458 #define B43_CCK_RATE_11MB               0x16
 459 #define B43_OFDM_RATE_6MB               0x0C
 460 #define B43_OFDM_RATE_9MB               0x12
 461 #define B43_OFDM_RATE_12MB              0x18
 462 #define B43_OFDM_RATE_18MB              0x24
 463 #define B43_OFDM_RATE_24MB              0x30
 464 #define B43_OFDM_RATE_36MB              0x48
 465 #define B43_OFDM_RATE_48MB              0x60
 466 #define B43_OFDM_RATE_54MB              0x6C
 467 /* Convert a b43 rate value to a rate in 100kbps */
 468 #define B43_RATE_TO_BASE100KBPS(rate)   (((rate) * 10) / 2)
 469
 470 #define B43_DEFAULT_SHORT_RETRY_LIMIT   7
 471 #define B43_DEFAULT_LONG_RETRY_LIMIT    4
 472
 473 #define B43_PHY_TX_BADNESS_LIMIT        1000
 474
 475 /* Max size of a security key */
 476 #define B43_SEC_KEYSIZE                 16
 477 /* Security algorithms. */
 478 enum {
 479         B43_SEC_ALGO_NONE = 0,  /* unencrypted, as of TX header. */
 480         B43_SEC_ALGO_WEP40,
 481         B43_SEC_ALGO_TKIP,
 482         B43_SEC_ALGO_AES,
 483         B43_SEC_ALGO_WEP104,
 484         B43_SEC_ALGO_AES_LEGACY,
 485 };
 486
 487 struct b43_dmaring;
 488
 489 /* The firmware file header */
 490 #define B43_FW_TYPE_UCODE       'u'
 491 #define B43_FW_TYPE_PCM         'p'
 492 #define B43_FW_TYPE_IV          'i'
 493 struct b43_fw_header {
 494         /* File type */
 495         u8 type;
 496         /* File format version */
 497         u8 ver;
 498         u8 __padding[2];
 499         /* Size of the data. For ucode and PCM this is in bytes.
 500          * For IV this is number-of-ivs. */
 501         __be32 size;
 502 } __attribute__((__packed__));
 503
 504 /* Initial Value file format */
 505 #define B43_IV_OFFSET_MASK      0x7FFF
 506 #define B43_IV_32BIT            0x8000
 507 struct b43_iv {
 508         __be16 offset_size;
 509         union {
 510                 __be16 d16;
 511                 __be32 d32;
 512         } data __attribute__((__packed__));
 513 } __attribute__((__packed__));
 514
 515
 516 /* Data structures for DMA transmission, per 80211 core. */
 517 struct b43_dma {
 518         struct b43_dmaring *tx_ring_AC_BK; /* Background */
 519         struct b43_dmaring *tx_ring_AC_BE; /* Best Effort */
 520         struct b43_dmaring *tx_ring_AC_VI; /* Video */
 521         struct b43_dmaring *tx_ring_AC_VO; /* Voice */
 522         struct b43_dmaring *tx_ring_mcast; /* Multicast */
 523
 524         struct b43_dmaring *rx_ring;
 525 };
 526
 527 struct b43_pio_txqueue;
 528 struct b43_pio_rxqueue;
 529
 530 /* Data structures for PIO transmission, per 80211 core. */
 531 struct b43_pio {
 532         struct b43_pio_txqueue *tx_queue_AC_BK; /* Background */
 533         struct b43_pio_txqueue *tx_queue_AC_BE; /* Best Effort */
 534         struct b43_pio_txqueue *tx_queue_AC_VI; /* Video */
 535         struct b43_pio_txqueue *tx_queue_AC_VO; /* Voice */
 536         struct b43_pio_txqueue *tx_queue_mcast; /* Multicast */
 537
 538         struct b43_pio_rxqueue *rx_queue;
 539 };
 540
 541 /* Context information for a noise calculation (Link Quality). */
 542 struct b43_noise_calculation {
 543         bool calculation_running;
 544         u8 nr_samples;
 545         s8 samples[8][4];
 546 };
 547
 548 struct b43_stats {
 549         u8 link_noise;
 550         /* Store the last TX/RX times here for updating the leds. */
 551         unsigned long last_tx;
 552         unsigned long last_rx;
 553 };
 554
 555 struct b43_key {
 556         /* If keyconf is NULL, this key is disabled.
 557          * keyconf is a cookie. Don't derefenrence it outside of the set_key
 558          * path, because b43 doesn't own it. */
 559         struct ieee80211_key_conf *keyconf;
 560         u8 algorithm;
 561 };
 562
 563 /* SHM offsets to the QOS data structures for the 4 different queues. */
 564 #define B43_QOS_PARAMS(queue)   (B43_SHM_SH_EDCFQ + \
 565                                  (B43_NR_QOSPARAMS * sizeof(u16) * (queue)))
 566 #define B43_QOS_BACKGROUND      B43_QOS_PARAMS(0)
 567 #define B43_QOS_BESTEFFORT      B43_QOS_PARAMS(1)
 568 #define B43_QOS_VIDEO           B43_QOS_PARAMS(2)
 569 #define B43_QOS_VOICE           B43_QOS_PARAMS(3)
 570
 571 /* QOS parameter hardware data structure offsets. */
 572 #define B43_NR_QOSPARAMS        16
 573 enum {
 574         B43_QOSPARAM_TXOP = 0,
 575         B43_QOSPARAM_CWMIN,
 576         B43_QOSPARAM_CWMAX,
 577         B43_QOSPARAM_CWCUR,
 578         B43_QOSPARAM_AIFS,
 579         B43_QOSPARAM_BSLOTS,
 580         B43_QOSPARAM_REGGAP,
 581         B43_QOSPARAM_STATUS,
 582 };
 583
 584 /* QOS parameters for a queue. */
 585 struct b43_qos_params {
 586         /* The QOS parameters */
 587         struct ieee80211_tx_queue_params p;
 588 };
 589
 590 struct b43_wldev;
 591
 592 /* Data structure for the WLAN parts (802.11 cores) of the b43 chip. */
 593 struct b43_wl {
 594         /* Pointer to the active wireless device on this chip */
 595         struct b43_wldev *current_dev;
 596         /* Pointer to the ieee80211 hardware data structure */
 597         struct ieee80211_hw *hw;
 598
 599         struct mutex mutex;
 600         spinlock_t irq_lock;
 601         /* R/W lock for data transmission.
 602          * Transmissions on 2+ queues can run concurrently, but somebody else
 603          * might sync with TX by write_lock_irqsave()'ing. */
 604         rwlock_t tx_lock;
 605         /* Lock for LEDs access. */
 606         spinlock_t leds_lock;
 607         /* Lock for SHM access. */
 608         spinlock_t shm_lock;
 609
 610         /* We can only have one operating interface (802.11 core)
 611          * at a time. General information about this interface follows.
 612          */
 613
 614         struct ieee80211_vif *vif;
 615         /* The MAC address of the operating interface. */
 616         u8 mac_addr[ETH_ALEN];
 617         /* Current BSSID */
 618         u8 bssid[ETH_ALEN];
 619         /* Interface type. (IEEE80211_IF_TYPE_XXX) */
 620         int if_type;
 621         /* Is the card operating in AP, STA or IBSS mode? */
 622         bool operating;
 623         /* filter flags */
 624         unsigned int filter_flags;
 625         /* Stats about the wireless interface */
 626         struct ieee80211_low_level_stats ieee_stats;
 627
 628         struct hwrng rng;
 629         u8 rng_initialized;
 630         char rng_name[30 + 1];
 631
 632         /* The RF-kill button */
 633         struct b43_rfkill rfkill;
 634
 635         /* List of all wireless devices on this chip */
 636         struct list_head devlist;
 637         u8 nr_devs;
 638
 639         bool radiotap_enabled;
 640
 641         /* The beacon we are currently using (AP or IBSS mode).
 642          * This beacon stuff is protected by the irq_lock. */
 643         struct sk_buff *current_beacon;
 644         bool beacon0_uploaded;
 645         bool beacon1_uploaded;
 646         bool beacon_templates_virgin; /* Never wrote the templates? */
 647         struct work_struct beacon_update_trigger;
 648
 649         /* The current QOS parameters for the 4 queues. */
 650         struct b43_qos_params qos_params[4];
 651
 652         /* Work for adjustment of the transmission power.
 653          * This is scheduled when we determine that the actual TX output
 654          * power doesn't match what we want. */
 655         struct work_struct txpower_adjust_work;
 656 };
 657
 658 /* In-memory representation of a cached microcode file. */
 659 struct b43_firmware_file {
 660         const char *filename;
 661         const struct firmware *data;
 662 };
 663
 664 /* Pointers to the firmware data and meta information about it. */
 665 struct b43_firmware {
 666         /* Microcode */
 667         struct b43_firmware_file ucode;
 668         /* PCM code */
 669         struct b43_firmware_file pcm;
 670         /* Initial MMIO values for the firmware */
 671         struct b43_firmware_file initvals;
 672         /* Initial MMIO values for the firmware, band-specific */
 673         struct b43_firmware_file initvals_band;
 674
 675         /* Firmware revision */
 676         u16 rev;
 677         /* Firmware patchlevel */
 678         u16 patch;
 679
 680         /* Set to true, if we are using an opensource firmware. */
 681         bool opensource;
 682         /* Set to true, if the core needs a PCM firmware, but
 683          * we failed to load one. This is always false for
 684          * core rev > 10, as these don't need PCM firmware. */
 685         bool pcm_request_failed;
 686 };
 687
 688 /* Device (802.11 core) initialization status. */
 689 enum {
 690         B43_STAT_UNINIT = 0,    /* Uninitialized. */
 691         B43_STAT_INITIALIZED = 1,       /* Initialized, but not started, yet. */
 692         B43_STAT_STARTED = 2,   /* Up and running. */
 693 };
 694 #define b43_status(wldev)               atomic_read(&(wldev)->__init_status)
 695 #define b43_set_status(wldev, stat)     do {                    \
 696                 atomic_set(&(wldev)->__init_status, (stat));    \
 697                 smp_wmb();                                      \
 698                                         } while (0)
 699
 700 /* XXX---   HOW LOCKING WORKS IN B43   ---XXX
 701  *
 702  * You should always acquire both, wl->mutex and wl->irq_lock unless:
 703  * - You don't need to acquire wl->irq_lock, if the interface is stopped.
 704  * - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet
 705  *   and packet TX path (and _ONLY_ there.)
 706  */
 707
 708 /* Data structure for one wireless device (802.11 core) */
 709 struct b43_wldev {
 710         struct ssb_device *dev;
 711         struct b43_wl *wl;
 712
 713         /* The device initialization status.
 714          * Use b43_status() to query. */
 715         atomic_t __init_status;
 716         /* Saved init status for handling suspend. */
 717         int suspend_init_status;
 718
 719         bool bad_frames_preempt;        /* Use "Bad Frames Preemption" (default off) */
 720         bool dfq_valid;         /* Directed frame queue valid (IBSS PS mode, ATIM) */
 721         bool short_slot;        /* TRUE, if short slot timing is enabled. */
 722         bool radio_hw_enable;   /* saved state of radio hardware enabled state */
 723         bool suspend_in_progress;       /* TRUE, if we are in a suspend/resume cycle */
 724
 725         /* PHY/Radio device. */
 726         struct b43_phy phy;
 727
 728         union {
 729                 /* DMA engines. */
 730                 struct b43_dma dma;
 731                 /* PIO engines. */
 732                 struct b43_pio pio;
 733         };
 734         /* Use b43_using_pio_transfers() to check whether we are using
 735          * DMA or PIO data transfers. */
 736         bool __using_pio_transfers;
 737
 738         /* Various statistics about the physical device. */
 739         struct b43_stats stats;
 740
 741         /* The device LEDs. */
 742         struct b43_led led_tx;
 743         struct b43_led led_rx;
 744         struct b43_led led_assoc;
 745         struct b43_led led_radio;
 746
 747         /* Reason code of the last interrupt. */
 748         u32 irq_reason;
 749         u32 dma_reason[6];
 750         /* saved irq enable/disable state bitfield. */
 751         u32 irq_savedstate;
 752         /* Link Quality calculation context. */
 753         struct b43_noise_calculation noisecalc;
 754         /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
 755         int mac_suspended;
 756
 757         /* Interrupt Service Routine tasklet (bottom-half) */
 758         struct tasklet_struct isr_tasklet;
 759
 760         /* Periodic tasks */
 761         struct delayed_work periodic_work;
 762         unsigned int periodic_state;
 763
 764         struct work_struct restart_work;
 765
 766         /* encryption/decryption */
 767         u16 ktp;                /* Key table pointer */
 768         u8 max_nr_keys;
 769         struct b43_key key[58];
 770
 771         /* Firmware data */
 772         struct b43_firmware fw;
 773
 774         /* Devicelist in struct b43_wl (all 802.11 cores) */
 775         struct list_head list;
 776
 777         /* Debugging stuff follows. */
 778 #ifdef CONFIG_B43_DEBUG
 779         struct b43_dfsentry *dfsentry;
 780 #endif
 781 };
 782
 783 static inline struct b43_wl *hw_to_b43_wl(struct ieee80211_hw *hw)
 784 {
 785         return hw->priv;
 786 }
 787
 788 static inline struct b43_wldev *dev_to_b43_wldev(struct device *dev)
 789 {
 790         struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
 791         return ssb_get_drvdata(ssb_dev);
 792 }
 793
 794 /* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */
 795 static inline int b43_is_mode(struct b43_wl *wl, int type)
 796 {
 797         return (wl->operating && wl->if_type == type);
 798 }
 799
 800 /**
 801  * b43_current_band - Returns the currently used band.
 802  * Returns one of IEEE80211_BAND_2GHZ and IEEE80211_BAND_5GHZ.
 803  */
 804 static inline enum ieee80211_band b43_current_band(struct b43_wl *wl)
 805 {
 806         return wl->hw->conf.channel->band;
 807 }
 808
 809 static inline u16 b43_read16(struct b43_wldev *dev, u16 offset)
 810 {
 811         return ssb_read16(dev->dev, offset);
 812 }
 813
 814 static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value)
 815 {
 816         ssb_write16(dev->dev, offset, value);
 817 }
 818
 819 static inline u32 b43_read32(struct b43_wldev *dev, u16 offset)
 820 {
 821         return ssb_read32(dev->dev, offset);
 822 }
 823
 824 static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value)
 825 {
 826         ssb_write32(dev->dev, offset, value);
 827 }
 828
 829 static inline bool b43_using_pio_transfers(struct b43_wldev *dev)
 830 {
 831 #ifdef CONFIG_B43_PIO
 832         return dev->__using_pio_transfers;
 833 #else
 834         return 0;
 835 #endif
 836 }
 837
 838 #ifdef CONFIG_B43_FORCE_PIO
 839 # define B43_FORCE_PIO  1
 840 #else
 841 # define B43_FORCE_PIO  0
 842 #endif
 843
 844
 845 /* Message printing */
 846 void b43info(struct b43_wl *wl, const char *fmt, ...)
 847     __attribute__ ((format(printf, 2, 3)));
 848 void b43err(struct b43_wl *wl, const char *fmt, ...)
 849     __attribute__ ((format(printf, 2, 3)));
 850 void b43warn(struct b43_wl *wl, const char *fmt, ...)
 851     __attribute__ ((format(printf, 2, 3)));
 852 #if B43_DEBUG
 853 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
 854     __attribute__ ((format(printf, 2, 3)));
 855 #else /* DEBUG */
 856 # define b43dbg(wl, fmt...) do { /* nothing */ } while (0)
 857 #endif /* DEBUG */
 858
 859 /* A WARN_ON variant that vanishes when b43 debugging is disabled.
 860  * This _also_ evaluates the arg with debugging disabled. */
 861 #if B43_DEBUG
 862 # define B43_WARN_ON(x) WARN_ON(x)
 863 #else
 864 static inline bool __b43_warn_on_dummy(bool x) { return x; }
 865 # define B43_WARN_ON(x) __b43_warn_on_dummy(unlikely(!!(x)))
 866 #endif
 867
 868 /* Convert an integer to a Q5.2 value */
 869 #define INT_TO_Q52(i)   ((i) << 2)
 870 /* Convert a Q5.2 value to an integer (precision loss!) */
 871 #define Q52_TO_INT(q52) ((q52) >> 2)
 872 /* Macros for printing a value in Q5.2 format */
 873 #define Q52_FMT         "%u.%u"
 874 #define Q52_ARG(q52)    Q52_TO_INT(q52), ((((q52) & 0x3) * 100) / 4)
 875
 876 #endif /* B43_H_ */